Signal processing method, driving chip, backlight unit and display device

Abstract

The invention discloses a signal processing method, a driving chip, a backlight unit and a display device, and the method comprises the steps: receiving a first analog signal, and converting the first analog signal into a first digital signal; performing compensation operation based on the first digital signal and a compensation parameter to generate a second analog signal; and outputting the second analog signal to a next-stage driving chip. And before the driving chip outputs the signal to the next-stage driving chip, the output signal is compensated, so that the quality of the output signal is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a signal processing method, a driving chip, a backlight unit and a display device. Background Art

[0002] Mini Light Emitting Diode (Mini-LED) backlight unit (BLU) is used in liquid crystal display (LCD) devices to achieve local dimming, which is beneficial to improve the contrast of the display image and reduce energy consumption.

[0003] In Local Dimming technology, the Mini-LED BLU is divided into multiple dimming areas. The Mini-LED in each dimming area is controlled by the same driver chip, and multiple dimming areas are controlled by multiple driver chips respectively. In Local Dimming technology, multiple driver chips used to control multiple dimming areas are usually connected in series through a single line. Signals are lost during transmission, causing the signal quality to gradually deteriorate during the stage-by-stage transmission process, affecting the display effect. Summary of the invention

[0004] The invention provides a signal processing method, a driving chip, a backlight unit and a display device, which are used to improve the signal transmission quality.

[0005] A first aspect of the present invention provides a signal processing method, comprising:

[0006] receiving a first analog signal, and converting the first analog signal into a first digital signal;

[0007] Perform a compensation operation based on the first digital signal and the compensation parameter to generate a second analog signal;

[0008] The second analog signal is output to the next-stage driver chip.

[0009] In some embodiments, within a signal cycle, the duration that the amplitude of the second analog signal is above the analog / digital conversion reference value is greater than the duration of the high level of the first digital signal.

[0010] In some embodiments, the compensation parameter is a time compensation parameter; the time compensation parameter is used to adjust the high level duration of the first digital signal;

[0011] Performing a compensation operation based on the first digital signal and the compensation parameter to generate a second analog signal specifically includes:

[0012] Based on the time compensation parameter, a compensation operation is performed on the high level duration of the first digital signal to obtain a second digital signal;

[0013] The second digital signal is converted into a second analog signal.

[0014] In some embodiments, the compensation parameter is an amplitude compensation parameter; the second analog signal includes a rising phase and a steady-state phase, and the amplitude compensation parameter is used to adjust the target voltage amplitude corresponding to the rising phase;

[0015] Performing a compensation operation based on the first digital signal and the compensation parameter to generate a second analog signal specifically includes:

[0016] Based on the amplitude compensation parameter, the target voltage amplitude corresponding to the second analog signal in the rising phase is adjusted during the digital-to-analog conversion process to convert the first digital signal into the second analog signal.

[0017] In some embodiments, before performing the compensation operation based on the first digital signal and the compensation parameter, the method further includes:

[0018] Acquire current rate information corresponding to the first digital signal; the rate information is a transmission rate of the first analog signal or a transmission rate of the first digital signal;

[0019] Confirm the compensation parameters based on the rate information.

[0020] In some embodiments, the first analog signal carries rate information;

[0021] Obtaining rate information corresponding to the first digital signal, specifically including:

[0022] The rate information is extracted directly from the first analog signal.

[0023] In some embodiments, obtaining rate information corresponding to the first digital signal specifically includes:

[0024] Calculating the transmission rate of the first analog signal to obtain rate information; or,

[0025] The transmission rate of the first digital signal is calculated to obtain rate information.

[0026] In some embodiments, the compensation parameter is determined according to the rate information, specifically including:

[0027] According to the rate information and compensation parameter comparison table, confirm the compensation parameters corresponding to the rate information.

[0028] In some embodiments, the rate information and compensation parameter comparison table is established according to the inherent loss of the target driver chip at the set transmission rate;

[0029] Alternatively, the rate information and compensation parameter comparison table is established according to the inherent loss of the target driver chip at the set transmission rate and the line loss between the target driver chip and the next-level driver chip.

[0030] A second aspect of the present invention provides a driver chip, comprising:

[0031] A first conversion module, used to receive a first analog signal; and also used to convert the first analog signal into a first digital signal;

[0032] The second conversion module is used to perform a compensation operation based on the first digital signal and the compensation parameter to generate a second analog signal; and is also used to output the second analog signal to the next-level driver chip.

[0033] In some embodiments, the second conversion module is further used to obtain current rate information corresponding to the first digital signal; and is further used to confirm the compensation parameter according to the rate information.

[0034] In some embodiments, the driver chip further includes:

[0035] The counting compensation module is used to store a rate information and compensation parameter comparison table recording the comparison relationship between the rate information and the compensation parameter.

[0036] A third aspect of the present invention provides a backlight unit, comprising a plurality of driver chips connected in series; one driver chip is used to control one dimming area; wherein at least one driver chip executes any one of the above signal processing methods.

[0037] A fourth aspect of the present invention provides a display device comprising any one of the above backlight units.

[0038] The beneficial effects of the present invention are as follows:

[0039] The present invention provides a signal processing method, a driver chip, a backlight unit and a display device. The signal processing method includes: receiving a first analog signal and converting the first analog signal into a first digital signal; performing a compensation operation based on the first digital signal and a compensation parameter to generate a second analog signal; and outputting the second analog signal to a next-level driver chip. Before the driver chip outputs the signal to the next-level driver chip, the driver chip performs a compensation operation on the output signal, which is beneficial to improving the quality of the output signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings introduced below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0041] Figure 1 A schematic diagram of a connection structure of a driver chip and Mini-LED in a backlight unit provided by an embodiment of the present invention;

[0042] Figure 2A It is a schematic diagram of the structure of a single driver chip in the related art;

[0043] Figure 2B A schematic diagram of a signal conversion process of a single driver chip in the related art;

[0044] Figure 3 One of the flowcharts of the signal processing method provided by the embodiment of the present invention;

[0045] Figure 4 A second flowchart of a signal processing method provided by an embodiment of the present invention;

[0046] Figure 5 One of the schematic diagrams of the signal conversion process of a single driver chip provided by an embodiment of the present invention;

[0047] Figure 6 The second schematic diagram of the signal conversion process of a single driver chip provided by an embodiment of the present invention;

[0048] Figure 7 Flowchart 3 of the signal processing method provided by an embodiment of the present invention;

[0049] Figure 8 A schematic diagram of driver chip connection provided by an embodiment of the present invention;

[0050] Fig. 9 One of the structural schematic diagrams of the driver chip provided by the embodiment of the present invention;

[0051] Fig.10 The second structural schematic diagram of the driver chip provided in the embodiment of the present invention. DETAILED DESCRIPTION

[0052] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and understandable, the present invention will be further described below with reference to the accompanying drawings and examples. However, the exemplary embodiments can be implemented in various forms and should not be understood as being limited to the embodiments described herein; on the contrary, these embodiments are provided to make the present invention more comprehensive and complete, and to fully convey the concepts of the exemplary embodiments to those skilled in the art. The same figure marks in the figures represent the same or similar structures, and thus their repeated descriptions will be omitted. The words expressing position and direction described in the present invention are all explained using the accompanying drawings as examples, but changes can be made as needed, and the changes made are all included in the scope of protection of the present invention. The drawings of the present invention are only used to illustrate the relative position relationship and do not represent the true proportions.

[0053] Mini Light Emitting Diode (Mini-LED) backlight unit (BLU) is used in liquid crystal display (LCD) devices to achieve local dimming, which is beneficial to improve the contrast of the display image and reduce energy consumption.

[0054] In Local Dimming technology, the Mini-LED BLU is divided into multiple dimming areas. The Mini-LED in each dimming area is controlled by the same driver chip, and multiple dimming areas are controlled by multiple driver chips respectively. In Local Dimming technology, multiple driver chips used to control multiple dimming areas are usually connected in series through a single line. Signals are lost during transmission, causing the signal quality to gradually deteriorate during the stage-by-stage transmission process, affecting the display effect.

[0055] Figure 1 A schematic diagram of a connection structure of a driver chip and Mini-LED in a backlight unit provided by an embodiment of the present invention; Figure 2A It is a schematic diagram of the structure of a single driver chip in the related art; Figure 2B Schematic diagram of the signal conversion process of a single driver chip in the related art.

[0056] For example, if Figure 1 As shown in FIG. 1 , in the Local Dimming technology, the backlight unit includes a plurality of driver chips connected in series, such as the first-level driver chip IC1, the second-level driver chip IC2, and the third-level driver chip IC3, etc. The output of the previous-level driver chip is used as the input of the next-level driver chip, and each driver chip is connected to at least one light-emitting diode LED. Each driver chip processes the driving signal input therein and extracts effective information, thereby controlling the light-emitting diode LED connected thereto to light up or turn off.

[0057] In related technologies, such as Figure 2AAs shown, a single driver chip generally includes an input pin 1, an input module 2, a digital logic module 3, an output module 4 and an output pin 5. The input pin 1 is used to connect to the controller or the output pin 5 of the previous driver chip for signal input. For example, the input pin of the first-level driver chip IC1 is generally connected to the controller, and the controller is used as a signal source device to provide an initial drive signal. The input pin of the second-level driver chip IC2 is connected to the output pin 5 of the first driver chip IC1, and the input pin of the third-level driver chip IC3 is connected to the output pin 5 of the second-level driver chip IC2. When the backlight unit includes more partitions and driver chips, the connection method of the driver chip is similar, and it is not repeated here. The input module 2 is used to perform preliminary processing on the input signal. For example, the input signal is generally an analog signal, and the input module can be used to convert the analog signal into a digital signal, thereby facilitating the transmission and identification of the signal inside the driver chip. The digital logic module 3 can further process the converted digital signal, extract effective information from the drive signal, and perform corresponding operations, such as controlling the light-emitting diode LED to light up or turn off, controlling the brightness of the light-emitting diode LED, etc. The output module 4 can be used to convert the digital signal into an analog signal again, and output it as an output signal to the next-level driver chip through the output pin.

[0058] In related technologies, such as Figure 2B As shown, the transmission process of the driving signal inside a single driving chip requires converting the first input signal into a digital signal, wherein the input signal is a first analog signal. In the process of converting the first analog signal into a digital signal, a reference value of the analog / digital conversion needs to be referred to. For example, when the amplitude of the first analog signal is greater than the reference value, the digital signal is at a high level, and when the amplitude of the first analog signal is less than the reference value, the digital signal is at a low level.

[0059] For example, if Figure 2BAs shown, in a rise-fall cycle of the first analog signal, the first analog signal first rises from the minimum amplitude to the steady-state amplitude H, stably maintains the first time length t1 at the steady-state amplitude H, and then drops to the minimum amplitude again, wherein the reference value of analog / digital conversion can be set to 0.8H. Since the first analog signal is a continuously changing signal and the digital signal is a discrete signal, when the input module detects that the amplitude of the first analog signal rises to greater than or equal to 0.8H, the digital signal jumps from a low level to a high level; when the input module detects that the amplitude of the first analog signal drops to less than or equal to 0.8H, the digital signal jumps from a high level to a low level. For example, the voltage range of the first analog signal can be 0 to 3.3V, the steady-state amplitude H of the first analog signal is 3.3V, and the minimum amplitude is 0, wherein the reference value of analog / digital conversion can be set to 0.8H=0.8×3.3V=2.64V. When the amplitude of the first analog signal rises to greater than or equal to 2.64V in the rising stage, the digital signal jumps from a low level to a high level; when the amplitude of the first analog signal drops to less than or equal to 2.64V in the falling stage, the digital signal jumps from a high level to a low level. Within the second time length t2 when the amplitude of the first analog signal is greater than or equal to 0.8H, the digital signal maintains a high level state, that is, the high level duration of the digital signal is the second time length t2.

[0060] like Figure 2BAs shown, the output signal output by the driver chip of this level to the driver chip of the next level is the second analog signal. Before the driver chip of this level outputs the signal to the driver chip of the next level, it is necessary to convert the digital signal into the second analog signal. Specifically, the output module starts to output voltage to the driver chip of the next level at the moment when the digital signal jumps from low level to high level, and the amplitude of the second analog signal gradually rises from 0 to the steady-state amplitude H; the output module stops outputting voltage to the driver chip of the next level at the moment when the digital signal jumps from high level to low level, and the amplitude of the second analog signal gradually decreases from the steady-state amplitude H to 0. Since the second analog signal is a continuous signal, the rise and fall of the signal amplitude are both continuous processes and cannot be completed instantly. Therefore, the amplitude of the second analog signal increases from 0 to 0.8H, and the rise time required is t11, and the amplitude of the second analog signal decreases from 0.8H to 0, and the fall time required is t22. For the next-level driver chip, after receiving the second analog signal, it converts the second analog signal into a digital signal, and the duration of the high level of the digital signal is the duration when the amplitude of the second analog signal is greater than or equal to 0.8H, that is, the third time length t3, t3 = t2-t11 + t12. Because under normal circumstances, the rising process of the amplitude of the output voltage of the output module from 0 to the steady-state amplitude H is slower than the process of the amplitude of the output voltage falling from the steady-state amplitude H to 0, the rising time t11 required for the amplitude of the second analog signal to rise from 0 to 0.8H is greater than the falling time t12 for the amplitude of the second analog signal to fall from the steady-state amplitude H to 0.8H, that is, t11>t12, so the third time length t3 = t2-t11 + t12 is less than the second time length t2. That is to say, the high-level duration of the digital signal obtained by the next-level driver chip based on the second analog signal conversion is shorter than the high-level duration of the digital signal obtained by the current-level driver chip based on the first analog signal conversion, which results in that among the multiple driver chips connected in series, the higher the driver chip is, the shorter the high-level duration of the digital signal obtained by converting the input signal is, and the worse the signal quality is. As the number of driver chips connected in series increases, the latter driver chips may be completely unable to recognize the correct driving signal, which seriously limits the number of driver chips that can be connected in series and the number of partitions of the backlight unit.

[0061] In view of this, a first aspect of an embodiment of the present invention provides a signal processing method for solving the above-mentioned problem.

[0062] Figure 3 This is one of the flowcharts of the signal processing method provided by the embodiment of the present invention.

[0063] The signal processing method provided in the embodiment of the present invention can be applied to a driver chip, specifically to any one or more of a plurality of driver chips connected in series, to solve the problem that the signal quality of the plurality of driver chips connected in series gradually deteriorates. Figure 3 As shown, the signal processing method provided by the embodiment of the present invention includes the following steps:

[0064] S301: Receive a first analog signal, and convert the first analog signal into a first digital signal.

[0065] In this step, the driver chip at this level can receive the first analog signal from the controller or receive the first analog signal from the driver chip at the previous level. For example, the driver chip at this level can be a first-level driver chip, which can be directly connected to the controller and receive the first analog signal output by the controller. For another example, the driver chip at this level can be an N-level driver chip, where N is an integer greater than 1, and the N-level driver chip can receive the first analog signal output by the driver chip at the previous level. This is not limited here.

[0066] When the driver chip at this level converts the first analog signal into the first digital signal, it can refer to the preset analog / digital conversion reference value for conversion. For example, when the amplitude of the first analog signal is greater than the reference value, the corresponding first digital signal is a high level, and when the amplitude of the first analog signal is less than the reference value, the corresponding first digital signal is a low level. When it is specifically implemented, you can refer to the above-mentioned related content, which will not be described in detail here.

[0067] S302: Perform a compensation operation based on the first digital signal and the compensation parameter to generate a second analog signal.

[0068] In this step, a second analog signal is generated by performing a compensation operation based on the first digital signal and compensation parameters, so that within a rise-fall cycle, the time length during which the voltage amplitude in the second analog signal is greater than the analog / digital conversion reference value can be extended, thereby improving the quality of the second analog signal.

[0069] Specifically, by extending the time length that the voltage amplitude of the second analog signal is greater than the analog / digital conversion reference value within a rise-fall cycle, the time length that the amplitude of the second analog signal is above the analog / digital conversion reference value can be made greater than the high level time length of the first digital signal within a signal cycle, and ultimately the time length that the amplitude of the second analog signal is above the analog / digital conversion reference value is equal to or close to the time length that the amplitude of the first analog signal is above the analog / digital conversion reference value, that is, the second time length t2 is equal to or close to the third time length t3, thereby ensuring the signal quality during transmission between serial chips.

[0070] In a specific implementation, the compensation operation is performed based on the first digital signal and the compensation signal to generate the second analog signal, which can be performed in at least the following two feasible ways:

[0071] Method 1

[0072] In this embodiment, the compensation parameter may be a time compensation parameter, which is used to adjust the high level duration of the first digital signal. Figure 4 The second flowchart of the signal processing method provided by the embodiment of the present invention. Figure 4 As shown, performing a compensation operation based on the first digital signal and the compensation parameter to generate a second analog signal specifically includes the following steps:

[0073] S401: Based on a time compensation parameter, a compensation operation is performed on a high level duration of a first digital signal to obtain a second digital signal;

[0074] S402: Convert the second digital signal into a second analog signal.

[0075] Figure 5 This is one of the schematic diagrams of the signal conversion process of a single driver chip provided by an embodiment of the present invention. Specifically, Figure 5 As shown, the driver chip at this level first converts the first analog signal into a first digital signal, and then, based on the first digital signal, compensates the high level duration of the first digital signal through the time compensation parameter to obtain a second digital signal. Figure 5 As shown, the duration of the high level of the first digital signal is the second time length t2. After compensating the high level duration of the first digital signal based on the time compensation parameter t4, the duration of the high level of the second digital signal is the fourth time length t5, where t5=t2+t4. In the related art, in a rising-falling cycle, due to the inherent time loss of the driving signal when it is transmitted inside the driving chip, the time length of the voltage amplitude in the second analog signal is greater than or equal to the reference value is usually shorter than the time length of the voltage amplitude in the first analog signal is greater than or equal to the reference value. Therefore, in a specific implementation, the value of the time compensation parameter t4 is usually a positive value, so that t5>t2, and then when the second analog signal is obtained based on the second digital signal, in a rising-falling cycle, the time length of the voltage amplitude in the second analog signal is greater than or equal to the reference value can be equal to or close to the second time length t2, that is, the third time length t3 is equal to or close to the second time length t2, so as to ensure the signal quality of the input signal received by the next-level driving chip.

[0076] Method 2

[0077] In this embodiment, the compensation parameter may be an amplitude compensation parameter. Since the amplitude of the analog signal changes continuously, in a rise-fall cycle, the second analog signal includes a rising phase in which the amplitude gradually rises, a steady-state phase in which the amplitude remains stable, and a falling phase in which the amplitude gradually decreases, wherein the amplitude compensation parameter is used to increase the target voltage amplitude corresponding to the rising phase. Performing a compensation operation based on the first digital signal and the compensation parameter to generate the second analog signal specifically includes the following steps:

[0078] Based on the amplitude compensation parameter, the target voltage amplitude corresponding to the second analog signal in the rising phase is increased during the digital-to-analog conversion process to convert the first digital signal into the second analog signal.

[0079] Figure 6 The second schematic diagram of the signal conversion process of a single driver chip provided by an embodiment of the present invention. Specifically, Figure 6 As shown, the driver chip first converts the first analog signal into a first digital signal, and then, based on the first digital signal and the amplitude compensation parameter, increases the target voltage amplitude corresponding to the second analog signal in the rising phase during the digital-to-analog conversion process to convert the first digital signal into a second analog signal. Figure 6 As shown, in a rising-falling cycle, the voltage output by the current driver chip in the steady-state stage is a steady-state amplitude H, the reference value of the analog / digital conversion is 0.8H, and the amplitude compensation parameter is a. In specific implementation, the target voltage amplitude H' corresponding to the second analog signal in the rising stage can be adjusted upward relative to the steady-state amplitude H based on the amplitude compensation parameter a, so that H'=H+a. Since the driver chip cannot output the target voltage instantly, the voltage needs a certain amount of time to gradually increase to the target voltage, which is reflected in the waveform of the second analog signal in the rising stage. The larger the target voltage output by the driver chip, the faster the voltage changes, and the larger the corresponding driving signal climbing slope in the rising stage, which means that the rising time t11 for the amplitude of the driving signal to rise to the reference value of the analog / digital conversion is shorter. According to the third time length t3=t2-t11+t12, it can be known that the longer the third time length t3 is, the longer the time length of the voltage amplitude in the second analog signal is greater than or equal to the reference value. Compared with the related art, the embodiment of the present invention can increase the target voltage amplitude corresponding to the second analog signal in the rising stage through the amplitude compensation parameter, so that the target voltage amplitude is greater than the steady-state amplitude, thereby shortening the time for the amplitude of the second analog signal to reach the reference value of the analog / digital conversion, making the third time length t3 equal to or close to the second time length t2, thereby ensuring the signal quality of the input signal received by the next-level driver chip.

[0080] S303: Output the second analog signal to the next-stage driver chip.

[0081] In this step, the driver chip outputs the second analog signal to the next-stage driver chip connected thereto. Since after the aforementioned compensation operation, in a rising-falling cycle, the time length during which the voltage amplitude in the second analog signal is greater than the analog / digital conversion reference value is the same as or close to the second analog signal, the signal quality of the input signal received by the next-stage driver chip can be ensured.

[0082] Figure 7 The third flowchart of the signal processing method provided by the embodiment of the present invention.

[0083] In some embodiments, Figure 7 As shown, before performing the compensation operation based on the first digital signal and the compensation parameter, the following steps are also included:

[0084] S701: Obtain current rate information corresponding to a first digital signal;

[0085] S702: Confirm compensation parameters according to the rate information.

[0086] In the related art, the maximum number of driver chips that can be connected in series in the backlight unit is also affected by the signal transmission rate. Figure 2B As shown, for a digital signal, a greater rate of the digital signal means a faster switching frequency of high and low levels, and a shorter duration of the high level, i.e., the second time length t2. Therefore, when converting the digital signal into a second analog signal, a greater proportion of the time loss caused by the rise time t11 of the second analog signal in the second time length t2 occurs, resulting in an increase in the proportion of the third time length t3 being reduced compared to the second time length t2, a faster rate of deterioration of the drive signal quality, and ultimately a reduction in the number of drive chips that can be connected in series in the backlight unit.

[0087] In this embodiment, before performing the compensation operation based on the first digital signal and the compensation parameter, the compensation parameter is first confirmed according to the current rate information corresponding to the first digital signal. The rate information may specifically be the transmission rate of the first analog signal or the transmission rate of the first digital signal. It should be noted that since the first digital signal is converted from the first analog signal, there is no substantial difference between the rate information represented by the transmission rate of the first analog signal and the rate information represented by the transmission rate of the first digital signal.

[0088] Different compensation parameters can be set for different rate information. The corresponding relationship between the compensation parameter and the rate information satisfies that, under the set transmission rate (which can be the transmission rate of the first analog signal or the transmission rate of the first digital signal), after the compensation operation is performed using the compensation parameter corresponding to the transmission rate, the second time length t2 in the input signal received by the next-level driver chip can be made the same or similar to the second time length t2 in the input signal received by the current-level driver chip. Thus, for signals with different transmission rates, the second time length t2 in the input signal received by the next-level driver chip can be compensated accordingly, reducing the difference between the signal received by the current-level driver chip and the signal received by the next-level driver chip, and ensuring the quality of transmission of signals with different transmission rates between multiple driver chips connected in series.

[0089] In specific implementation, the current rate information corresponding to the first digital signal can be obtained in at least the following two ways:

[0090] Method 1

[0091] The rate information may be carried in the first analog signal, wherein the rate information carried in the first analog signal may be the transmission rate of the first analog signal, or the rate information of the first digital signal converted from the first analog signal. Specifically, when the controller outputs a driving signal, the driving signal input by the controller to the first-level driving chip carries the rate information, so that in the process of the driving signal being transmitted step by step in the driving chips at each level, the driving chips at each level can receive and identify the rate information. In a specific implementation, the driving chip can directly read the rate information from the first analog signal, and the process of confirming the rate information is relatively simple.

[0092] Method 2

[0093] The first analog signal may not carry rate information. The process of the driver chip acquiring the rate information corresponding to the first digital signal specifically includes: calculating the transmission rate of the first analog signal to obtain the rate information; or calculating the transmission rate of the first digital signal to obtain the rate information.

[0094] Specifically, for example, the signal input module may have a transmission rate calculation function, so that the transmission rate of the first analog signal may be calculated by the signal input module, thereby reducing the amount of information carried in the driving signal sent by the controller and improving transmission efficiency.

[0095] For example, the digital logic module may have a transmission rate calculation function, so that the transmission rate of the first digital signal may be calculated by the digital logic module, thereby reducing the amount of information carried in the driving signal sent by the controller and improving transmission efficiency.

[0096] For example, a functional module specifically used for calculating the signal transmission rate may be provided in the driver chip, which is not limited here.

[0097] In some embodiments, in the step of confirming the compensation parameter according to the rate information, the compensation parameter corresponding to the rate information may be confirmed according to a pre-established rate information and compensation parameter comparison table.

[0098] For example, the rate information and compensation parameter comparison table can be stored in the driver chip, so that the driver chip can directly call the rate information and compensation parameter comparison table after obtaining the rate information, and confirm the corresponding compensation parameters according to the rate information and compensation parameter comparison table. In specific implementation, the rate information and compensation parameter comparison table can be stored in the digital logic module. In some embodiments, the driver chip may also include a counting compensation module, and the rate information and compensation parameter comparison table may be stored in the counting compensation module, thereby improving data stability and reducing the working pressure of the digital logic module. The rate information and compensation parameter comparison table may also be stored in other modules, which is not limited here.

[0099] In specific implementation, the rate information and compensation parameter comparison table of the target chip can be constructed by at least the following two methods, wherein the target chip is the chip for which the rate information and compensation parameter comparison table is to be constructed:

[0100] Method 1

[0101] Based on the inherent loss of the target driver chip at the set transmission rate, the compensation parameters corresponding to the transmission rate are determined and recorded to form a comparison table of rate information and compensation parameters.

[0102] The transmission rate setting may be the transmission rate of the first analog signal, that is, the transmission rate of the input signal received by the target driver chip. The transmission rate setting may also be the transmission rate of the first digital signal converted from the first analog signal, which is not limited here. In specific implementation, in order to refine the correspondence between the transmission rate and the compensation parameter, the compensation parameters corresponding to multiple different transmission rates may be measured and recorded respectively.

[0103] The inherent losses of the target driver chip, such as Figure 2B As shown, it specifically refers to the difference between the second time length t2 and the third time length t3 when the target driver chip does not perform compensation operation and directly converts the digital signal into the second analog signal. The fixed loss is mainly caused by the inability to offset the rise time t11 and the fall time t12. In this embodiment, only the inherent loss of the target driver chip can be considered to reduce the difficulty of constructing the rate information and compensation parameter comparison table.

[0104] In some embodiments, when the compensation parameter is a duration compensation parameter, the inherent loss of the target driver chip at a set transmission rate can be directly determined as the duration compensation parameter corresponding to the transmission rate.

[0105] In some embodiments, when the compensation parameter is a duration compensation parameter or an amplitude compensation parameter, the compensation parameter corresponding to the set transmission rate can also be determined by the following process: at the set transmission rate, the size of the compensation parameter is adjusted, and for compensation parameters of different sizes, the length of the third time length t3 corresponding to the second analog signal and the length of the second time length t2 corresponding to the first analog signal are compared. When the length of the third time length t3 corresponding to the second analog signal and the length of the second time length t2 corresponding to the first analog signal meet the preset requirements, the compensation parameter at this time is recorded as the compensation parameter corresponding to the set transmission rate. For example, when the length of the third time length t3 corresponding to the second analog signal is the same as the length of the second time length t2 corresponding to the first analog signal, or when the difference between the length of the third time length t3 corresponding to the second analog signal and the length of the second time length t2 corresponding to the first analog signal is less than the set value, the compensation parameter at this time is recorded as the compensation parameter corresponding to the target chip at the transmission rate.

[0106] Method 2

[0107] Based on the inherent loss of the target driver chip at the set transmission rate and the line loss between the target driver chip and the next-level driver chip, the compensation parameter corresponding to the transmission rate is determined and recorded.

[0108] Figure 8 A schematic diagram of driver chip connections provided by an embodiment of the present invention.

[0109] like Figure 8 As shown, in the process of transmission of the driving signal between the serially connected driving chips, in addition to the inherent loss during transmission inside the driving chip, there may also be loss on the connection line between the previous level driving chip and the next level driving chip. For example, during the transmission of the output signal of the previous level driving chip on the connection line, the line loss caused by the voltage drop caused by the resistance of the connection line and other reasons may cause the time length of the voltage amplitude in the input signal of the next level driving chip to be greater than or equal to the analog / digital conversion reference value to be further shortened. Therefore, when determining the compensation parameters corresponding to the set transmission rate, the inherent loss of the target driving chip and the line loss between the target driving chip and the next level driving chip can be considered at the same time to further ensure the signal quality received by the next level driving chip.

[0110] In specific implementation, the compensation parameter corresponding to the set transmission rate can also be determined by the following process: under the set transmission rate, the size of the compensation parameter is adjusted, and for compensation parameters of different sizes, the time length of the voltage amplitude in the input signal of the next level driver chip of the target driver chip is greater than or equal to the analog / digital conversion reference value and the length of the second time length t2 corresponding to the first analog signal received by the target driver chip are compared, and when the preset requirements are met, the compensation parameter at this time is recorded as the compensation parameter corresponding to the set transmission rate. For example, when the time length of the voltage amplitude in the input signal of the next level driver chip of the target driver chip is greater than or equal to the analog / digital conversion reference value is the same as the length of the second time length t2 corresponding to the first analog signal received by the target driver chip, or when the difference between the time length of the voltage amplitude in the input signal of the next level driver chip of the target driver chip is greater than or equal to the analog / digital conversion reference value and the length of the second time length t2 corresponding to the first analog signal received by the target driver chip is less than a specific value, the compensation parameter at this time is recorded as the compensation parameter corresponding to the set transmission rate, thereby further ensuring the quality of the drive signal received by the next level driver chip of the target driver chip.

[0111] Fig. 9 This is one of the structural schematic diagrams of the driver chip provided by an embodiment of the present invention.

[0112] According to a second aspect of the embodiment of the present invention, a driver chip is also provided. Fig. 9 As shown, the driving chip includes a first conversion module 11 and a second conversion module 12 .

[0113] The first conversion module 11 is used to receive a first analog signal. The first conversion module 11 is also used to convert the first analog signal into a first digital signal. In specific implementation, the first conversion module 11 may include an input module 11, which is not limited here.

[0114] The second conversion module 12 is used to perform a compensation operation based on the first digital signal and the compensation parameter to generate a second analog signal. The second conversion module 12 is also used to output the second analog signal to the next-level driver chip. In specific implementation, the second conversion module 12 may include a digital logic module 3 and an output module 4, and the digital logic module 3 and the output module 4 cooperate to complete the compensation operation and the digital / analog conversion process.

[0115] In some embodiments, the compensation parameter is a time compensation parameter. The time compensation parameter is used to adjust the high level duration of the first digital signal. In specific implementation, the digital logic module 3 is specifically used to perform a compensation operation on the high level duration of the first digital signal based on the time compensation parameter to obtain a second digital signal. The output module 4 is specifically used to convert the second digital signal into a second analog signal.

[0116] In some embodiments, the compensation parameter is an amplitude compensation parameter. The second analog signal includes a rising phase and a steady-state phase, and the amplitude compensation parameter is used to adjust the target voltage amplitude corresponding to the rising phase. The output module 4 is specifically used to adjust the target voltage amplitude corresponding to the second analog signal in the rising phase during the digital-to-analog conversion process based on the amplitude compensation parameter, and convert the first digital signal into the second analog signal.

[0117] In some embodiments, the second conversion module 12 is further configured to obtain current rate information corresponding to the first digital signal before performing a compensation operation based on the first digital signal and the compensation parameter, and to confirm the compensation parameter according to the rate information.

[0118] The rate information may be the transmission rate of the first analog signal or the transmission rate of the first digital signal, which is not limited here. In some embodiments, the rate information may be directly carried in the first analog signal, and after the rate information is read by the input module, the rate information and the converted first digital signal may be sent to the second conversion module 12 together; or the rate information may be read from the first digital signal by the digital logic module 3, which is not limited here. In some embodiments, the first analog signal does not directly carry the rate information, and the signal input module may have a transmission rate calculation function, so that the transmission rate of the first analog signal may be calculated by the signal input module, and the transmission rate of the first analog signal may be sent to the second conversion module 12; or the digital logic module may have a transmission rate calculation function, so that the transmission rate of the first digital signal may be calculated by the digital logic module, thereby obtaining the rate information, which may reduce the amount of information carried in the drive signal sent by the controller and improve the transmission efficiency.

[0119] Fig.10 The second structural schematic diagram of the driver chip provided in the embodiment of the present invention.

[0120] When the second conversion module 12 confirms the compensation parameter according to the rate information, it can specifically confirm the compensation parameter corresponding to the rate information according to the rate information and compensation parameter comparison table. In some embodiments, the rate information and compensation parameter comparison table can be stored in the digital logic module 3. After obtaining the rate information, the digital logic module 3 can call the rate information and compensation parameter comparison table to confirm the compensation parameter corresponding to the rate information, and use the compensation parameter for subsequent compensation operations.

[0121] In some embodiments, Fig.10As shown, the driver chip also includes a counting compensation module 6. The counting compensation module 6 is connected to the second conversion module 12. Specifically, the counting compensation module 6 can be connected to the digital logic module 3. The rate information and compensation parameter comparison table can be stored in the counting compensation module 6. After obtaining the rate information, the digital logic module 3 can obtain the compensation parameters corresponding to the rate information from the counting compensation module 6, and use the compensation parameters for subsequent compensation operations. This is not limited here.

[0122] The driver chip provided by the embodiment of the present invention can also refer to the relevant contents of the signal processing method of the aforementioned driver chip when it is specifically applied, and will not be elaborated here. Because the driver chip provided by the embodiment of the present invention performs a compensation operation on the output signal before outputting the signal to the next-level driver chip, it is beneficial to improve the quality of the output signal, thereby improving the quality of the signal transmission between multiple series-connected driver chips in the scenario where multiple driver chips are connected in series, thereby increasing the number of series-connected chips. When applied to a backlight unit, the number of partitions can be increased.

[0123] According to a third aspect of the embodiments of the present invention, a backlight unit is provided. Figure 1 As shown, the backlight unit includes a plurality of driver chips connected in series. One driver chip is used to control a dimming area. One dimming area includes at least one light-emitting unit. In specific implementation, the light-emitting unit may be a Mini LED or other light-emitting device, which is not limited here. Among them, at least one driver chip can execute the signal processing method provided in any of the foregoing embodiments. The backlight unit provided in an embodiment of the present invention has the same or similar technical effect as the signal processing method provided in any of the foregoing embodiments in specific implementation, which is not repeated here.

[0124] According to a fourth aspect of the embodiments of the present invention, a display device is provided, which includes the backlight unit provided by any one of the above embodiments.

[0125] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0126] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A signal processing method, characterized in that: include: receiving a first analog signal, and converting the first analog signal into a first digital signal; Perform a compensation operation based on the first digital signal and a compensation parameter to generate a second analog signal; The second analog signal is output to the next-stage driver chip.

2. The method according to claim 1, characterized in that In a signal cycle, the duration that the amplitude of the second analog signal is above the analog / digital conversion reference value is greater than the duration of the high level of the first digital signal.

3. The method according to claim 1 or 2, characterized in that The compensation parameter is a time compensation parameter; the time compensation parameter is used to adjust the high level duration of the first digital signal; The performing a compensation operation based on the first digital signal and the compensation parameter to generate a second analog signal specifically includes: Based on the time compensation parameter, a compensation operation is performed on the high level duration of the first digital signal to obtain a second digital signal; The second digital signal is converted into the second analog signal.

4. The method according to claim 1 or 2, characterized in that: The compensation parameter is an amplitude compensation parameter; the second analog signal includes a rising phase and a steady-state phase, and the amplitude compensation parameter is used to adjust the target voltage amplitude corresponding to the rising phase; The performing a compensation operation based on the first digital signal and the compensation parameter to generate a second analog signal specifically includes: Based on the amplitude compensation parameter, the target voltage amplitude corresponding to the second analog signal in the rising phase is adjusted during the digital-to-analog conversion process, and the first digital signal is converted into the second analog signal.

5. The method according to claim 1 or 2, characterized in that: Before performing a compensation operation based on the first digital signal and the compensation parameter, the method further includes: Acquire current rate information corresponding to the first digital signal; the rate information is a transmission rate of the first analog signal or a transmission rate of the first digital signal; The compensation parameter is determined according to the rate information.

6. The method according to claim 5, characterized in that The first analog signal carries the rate information; Acquiring rate information corresponding to the first digital signal specifically includes: The rate information is extracted directly from the first analog signal.

7. The method according to claim 5, characterized in that Acquiring rate information corresponding to the first digital signal specifically includes: calculating the transmission rate of the first analog signal to obtain the rate information; or, The transmission rate of the first digital signal is calculated to obtain the rate information.

8. The method according to claim 5, characterized in that The confirming the compensation parameter according to the rate information specifically includes: According to the rate information and compensation parameter comparison table, the compensation parameter corresponding to the rate information is confirmed.

9. The method according to claim 8, characterized in that The rate information and compensation parameter comparison table is established according to the inherent loss of the target driver chip at the set transmission rate; Alternatively, the rate information and compensation parameter comparison table is established according to the inherent loss of the target driver chip at the set transmission rate and the line loss between the target driver chip and the next-level driver chip.

10. A driver chip, characterized in that: include: A first conversion module, configured to receive a first analog signal; Also used for converting the first analog signal into a first digital signal; The second conversion module is used to perform a compensation operation based on the first digital signal and the compensation parameter to generate a second analog signal; and is also used to output the second analog signal to the next-level driver chip.

11. The driver chip according to claim 10, characterized in that: The second conversion module is further used to obtain current rate information corresponding to the first digital signal; and is further used to confirm the compensation parameter according to the rate information.

12. The driver chip according to claim 11, characterized in that: Also includes: The counting compensation module is used to store a rate information and compensation parameter comparison table recording the comparison relationship between the rate information and the compensation parameter.

13. A backlight unit, characterized in that: It comprises a plurality of driver chips connected in series; one of the driver chips is used to control a dimming area; wherein at least one of the driver chips executes the signal processing method according to any one of claims 1 to 9.

14. A display device, characterized in that: Comprising the backlight unit as claimed in claim 13.

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