Semiconductor structure and manufacturing method thereof

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof, and the manufacturing method comprises the steps: firstly, etching a substrate to obtain sunken parts located at two sides of a channel region before a gate structure is formed, enabling the top surface of the substrate in a source-drain region to be lower than the top surface of the substrate in the channel region, and enabling the top surface of the substrate to be lower than the top surface of the channel region in the subsequently formed gate structure; the gate dielectric layer conformally covers the top surface and the side surface of the substrate in the channel region; the gate electrode layer is positioned on the surface of the gate dielectric layer, and the lowest point of the gate electrode layer is higher than the top surface of the substrate in the source-drain region. The top surface of the substrate in the channel region is higher than the top surface of the substrate in the source-drain region, so that the gate dielectric layer not only covers the top surface of the substrate in the channel region, but also can cover the side surface of the substrate in the channel region, thereby increasing the length of the gate channel under the same device area, and improving the reliability of the device. The density of the transistors is improved (the number of the transistors in the same area is larger), the short-channel effect is improved, and the performance of the device is improved. In addition, the manufacturing method of the semiconductor structure is simple in process, and the manufacturing cost can be reduced.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor technology and relates to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] The planar transistor structure is mainly composed of a gate, a source, and a drain. The gate is located above the channel region, isolated from the semiconductor substrate by an insulating oxide layer, and controls the flow of current. The source and drain are located on both sides of the channel region, respectively, and are the input and output ends of the current. In a metal-oxide-semiconductor field-effect transistor (MOSFET), changes in the gate voltage control the conductive channel formed between the source and the drain, thereby controlling the current passing through the transistor.

[0003] As the size of transistors continues to shrink, the gate width is also getting smaller and smaller. However, a gate width that is too small will lead to the short channel effect. This effect includes phenomena such as reduced threshold voltage, drain-induced barrier lowering (DIBL), carrier velocity saturation, and mobility degradation. Specifically: (1) As the channel length decreases, the proportion of the source-drain junction depletion region in the entire channel increases, resulting in a decrease in the amount of charge required to form an inversion layer, thereby reducing the threshold voltage; (2) When a high voltage is applied to the drain, since the channel is very short, the source is also affected by the drain electric field, resulting in a lower source junction barrier, an expansion of the drain depletion layer, and even connecting to the depletion region of the source junction, causing the device to be unable to turn off; (3) Under high electric fields, the carrier velocity reaches saturation and no longer increases with the increase in electric field, which leads to drain current saturation, affecting the performance of the transistor; (4) Due to the influence of high electric fields, the carrier mobility decreases, resulting in a decrease in drain current.

[0004] In order to control the short channel effect and improve the performance and reliability of transistors, the industry generally considers fin transistors (FinFET) or gate-all-around transistors (GAA) below the 40 nm process. Among them, FinFET transistors are a three-dimensional complementary metal oxide semiconductor (CMOS) transistor, which is characterized by a gate wrapped around a tall and thin fin-shaped channel to form a shape similar to a fish fin. This design enhances the gate's control over the channel, effectively alleviates the short channel effect, reduces leakage current, and allows the size of the transistor to be further reduced; and the characteristic of GAA transistors is that the gate wraps the source and drain in all directions. Compared with traditional FinFET transistors, the gate control surface of the gate-all-around transistor is changed from 3 sides to 4 sides, which can achieve comprehensive control of the channel. While reducing the size of the transistor, it can better control the flow of current, reduce leakage current, and increase the switching speed.

[0005] However, the manufacturing process of fin transistors and ring-gate transistors is more complicated. For example, the fine geometry and spacing of fin transistors require high-precision lithography technology and precisely controlled etching technology to ensure the accurate formation of fins, while the manufacturing process of ring-gate transistors requires precise control of channel length and device spacing, as well as the process from gate self-alignment to precise control of channel length. In other words, compared with planar transistors, the manufacturing methods of fin transistors and ring-gate transistors are more complicated and the manufacturing cost is higher.

[0006] Therefore, how to improve the structure and manufacturing process of planar transistors, improve the short channel effect while increasing the transistor density, and reduce the manufacturing cost has become an important technical problem that technical personnel in this field need to solve urgently.

[0007] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0008] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a semiconductor structure and a manufacturing method thereof, so as to solve the problem that the existing planar transistor structure is difficult to further miniaturize and has a high manufacturing cost.

[0009] To achieve the above object and other related objects, the present invention provides a method for manufacturing a semiconductor structure, comprising the following steps: Providing a substrate, the substrate comprising a channel region and source and drain regions located on both sides of the channel region; Etching the substrate to obtain recessed portions located at both sides of the channel region, so that the top surface of the substrate in the source and drain regions is lower than the top surface of the substrate in the channel region; Forming a gate structure, the gate structure comprising a gate dielectric layer and a gate electrode layer, the gate dielectric layer conformally covers the substrate top surface and substrate side surface of the channel region, the gate electrode layer is located on the surface of the gate dielectric layer, and the lowest point of the gate electrode layer is higher than the substrate top surface of the source and drain region; A gate sidewall and a source-drain doped region are formed, wherein the gate sidewall is located at both sides of the gate structure, and the source-drain doped region is located in the substrate of the source-drain region.

[0010] Optionally, the depth of the recessed portion ranges from 1 to 50 nm.

[0011] Optionally, etching the substrate to obtain recessed portions located on both sides of the channel region comprises the following steps: forming a barrier layer on the surface of the substrate; forming a hard mask layer on the surface of the barrier layer; Patterning the hard mask layer to obtain a hard mask opening, wherein the surface of the barrier layer in the channel region is still covered by the hard mask layer; Etching the substrate based on the patterned hard mask layer to obtain the recessed portion; The hard mask layer and the barrier layer are removed.

[0012] Optionally, the barrier layer includes a silicon oxide layer, and the method of removing the barrier layer includes wet etching.

[0013] Optionally, before forming the gate structure, the following steps are also included: forming a pad oxide layer on the surface of the substrate; The pad oxide layer is removed.

[0014] Optionally, forming the gate structure comprises the following steps: Depositing a gate dielectric material layer on the surface of the substrate; Depositing a gate electrode material layer on the surface of the gate dielectric material layer; The gate electrode material layer and the gate dielectric material layer are patterned to obtain the gate electrode layer and the gate dielectric layer.

[0015] Optionally, a vertical distance between the lowest point of the gate electrode layer and the substrate top surface of the source and drain regions is smaller than a height difference between the substrate top surface of the source and drain regions and the substrate top surface of the channel region.

[0016] The present invention also provides a semiconductor structure, comprising: A substrate, the substrate comprising a channel region and source and drain regions located at both sides of the channel region, wherein a top surface of the substrate in the source and drain regions is lower than a top surface of the substrate in the channel region; A gate structure, comprising a gate dielectric layer and a gate electrode layer, wherein the gate dielectric layer conformally covers the top surface and side surfaces of the substrate in the channel region, and the gate electrode layer is located on the surface of the gate dielectric layer and is spaced a preset distance from the top surface of the substrate in the source and drain region; Gate sidewalls, located on both sides of the gate structure; The source-drain doping region is located in the substrate of the source-drain region.

[0017] Optionally, a height difference between a top surface of the substrate of the source and drain regions and a top surface of the substrate of the channel region is in a range of 1 to 50 nm.

[0018] Optionally, a vertical distance between the lowest point of the gate electrode layer and the substrate top surface of the source and drain regions is smaller than a height difference between the substrate top surface of the source and drain regions and the substrate top surface of the channel region.

[0019] As described above, the present invention provides a semiconductor structure and a manufacturing method thereof. Before forming a gate structure, the manufacturing method first etches the substrate to obtain recessed portions located on both sides of the channel region, so that the substrate top surface of the source and drain regions is lower than the substrate top surface of the channel region. In the gate structure formed subsequently, the gate dielectric layer conformally covers the substrate top surface and the substrate side surface of the channel region, and the gate electrode layer is located on the surface of the gate dielectric layer and the lowest point of the gate electrode layer is higher than the substrate top surface of the source and drain regions. Since the substrate top surface of the channel region is higher than the substrate top surface of the source and drain regions, the gate dielectric layer not only covers the substrate top surface of the channel region, but also covers the substrate side surface of the channel region, thereby increasing the length of the gate channel under the same device area, which helps to improve the short channel effect while increasing the transistor density (more transistors under the same area), and improves the device performance. In addition, the manufacturing method of the semiconductor structure of the present invention has a simple process and helps to reduce manufacturing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 The process flow diagram of the method for manufacturing the semiconductor structure of the present invention is shown.

[0021] Figure 2 A schematic structural diagram showing a substrate provided for the method for manufacturing a semiconductor structure of the present invention.

[0022] Figure 3 It is a schematic diagram showing the structure obtained after forming a barrier layer on the surface of a substrate according to the manufacturing method of the semiconductor structure of the present invention.

[0023] Figure 4 It is a schematic diagram showing the structure obtained after forming a hard mask layer on the surface of the blocking layer according to the manufacturing method of the semiconductor structure of the present invention.

[0024] Figure 5 It is a schematic diagram showing the structure obtained after the hard mask layer is patterned in the manufacturing method of the semiconductor structure of the present invention to obtain a hard mask opening.

[0025] Figure 6 The schematic diagram of the structure obtained after etching the substrate to obtain the recessed portion based on the patterned hard mask layer is shown in the manufacturing method of the semiconductor structure of the present invention.

[0026] Figure 7 It is a schematic diagram showing the structure obtained after removing the hard mask layer and the barrier layer in the manufacturing method of the semiconductor structure of the present invention.

[0027] Figure 8 It is a schematic diagram showing the structure obtained after forming a liner oxide layer on the surface of a substrate according to the manufacturing method of the semiconductor structure of the present invention.

[0028] Fig. 9It is a schematic diagram showing the structure obtained after removing the pad oxide layer according to the manufacturing method of the semiconductor structure of the present invention.

[0029] Fig.10 It is a schematic diagram showing the structure obtained after the gate dielectric material layer is deposited on the surface of the substrate according to the manufacturing method of the semiconductor structure of the present invention.

[0030] Fig.11 It is a schematic diagram showing the structure obtained after the gate electrode material layer is deposited on the surface of the gate dielectric material layer according to the manufacturing method of the semiconductor structure of the present invention.

[0031] Fig.12 It is a schematic diagram showing the structure obtained after the gate electrode material layer and the gate dielectric material layer are patterned to obtain the gate electrode layer and the gate dielectric layer according to the manufacturing method of the semiconductor structure of the present invention.

[0032] Fig.13 It is a schematic diagram showing the structure obtained after the gate sidewall and source / drain doping regions are formed according to the manufacturing method of the semiconductor structure of the present invention.

[0033] Fig.14 Shown is a conventional planar transistor and its carrier paths when it is on.

[0034] Fig.15 Shown is the carrier path when the transistor in the semiconductor structure of the present invention is turned on.

[0035] Description of the accompanying drawings: S1~S4 steps, 1 substrate, 2 recessed portion, 3 barrier layer, 4 hard mask layer, 5 gate dielectric layer, 5a gate dielectric material layer, 6 gate electrode layer, 6a gate electrode material layer, 7 pad oxide layer, 8 gate sidewall, 9 source and drain doping region, I channel region, II source and drain region, D depth. DETAILED DESCRIPTION

[0036] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0037] It should be emphasized that the term “include / comprises” when used herein refers to the presence of features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps or components.

[0038] Features described and / or illustrated with respect to one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0039] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the schematic diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0040] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0041] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0042] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0043] The present invention provides a method for manufacturing a semiconductor structure. Figure 1 , shown as a process flow chart of the manufacturing method, comprising the following steps: S1: providing a substrate, wherein the substrate comprises a channel region and source and drain regions located on both sides of the channel region; S2: etching the substrate to obtain recessed portions located at both sides of the channel region, so that the top surface of the substrate in the source and drain regions is lower than the top surface of the substrate in the channel region; S3: forming a gate structure, wherein the gate structure comprises a gate dielectric layer and a gate electrode layer, wherein the gate dielectric layer conformally covers the substrate top surface and substrate side surface of the channel region, the gate electrode layer is located on the surface of the gate dielectric layer, and the lowest point of the gate electrode layer is higher than the substrate top surface of the source and drain region; S4: forming gate sidewalls and source-drain doped regions, wherein the gate sidewalls are located at two sides of the gate structure, and the source-drain doped regions are located in the substrate of the source-drain regions.

[0044] The above steps will be described in detail below with reference to the structure diagram.

[0045] First see Figure 2 , perform the step S1: provide a substrate 1, the substrate 1 includes a channel region I and source and drain regions II located on both sides of the channel region I.

[0046] As an example, the substrate 1 may be a silicon substrate, a silicon-on-insulator substrate, a silicon-germanium substrate, a silicon carbide substrate, a III-V compound substrate or other suitable semiconductor substrates.

[0047] In some embodiments, the substrate 1 may be a substrate without an epitaxial layer.

[0048] In other embodiments, the substrate 1 may also be a substrate with an epitaxial layer, that is, the substrate 1 includes a base layer and an epitaxial layer located on one side of the base layer. The thickness of the epitaxial layer is usually several microns, and its lattice structure is the same as that of the base layer, but the resistivity and thickness may be different. The subsequent device structure is carried out on the epitaxial layer, which helps to improve the stability and reliability of the product.

[0049] As an example, the epitaxial layer may be made of the same material as the base layer (homoepitaxy), or may be made of a different material from the base layer (heteroepitaxy).

[0050] As an example, the substrate 1 may be a doped substrate, such as a P-type doped substrate or an N-type doped substrate. The specific doping type and doping concentration may be selected according to the required electrical parameters and are not specifically limited here.

[0051] Please see again Figures 3 to 7 , performing the step S2: etching the substrate 1 to obtain recessed portions 2 located on both sides of the channel region I, so that the top surface of the substrate of the source and drain region II is lower than the top surface of the substrate of the channel region I.

[0052] In some embodiments, etching the substrate 1 to obtain the recessed portions 2 located on both sides of the channel region 1 comprises the following steps: (1) If Figure 3 As shown, a barrier layer 3 is formed on the surface of the substrate 1; (2) If Figure 4 As shown, a hard mask layer 4 is formed on the surface of the barrier layer 3; (3) If Figure 5As shown, the hard mask layer 4 is patterned by semiconductor processes such as photolithography and etching to obtain a hard mask opening, wherein the hard mask opening at least exposes the barrier layer surface of the source and drain regions II, while the barrier layer surface of the channel region I is still covered by the hard mask layer 4; (4) If Figure 6 As shown, the substrate 1 is etched based on the patterned hard mask layer 4 to obtain the recessed portion 2; (5) If Figure 7 As shown, the hard mask layer 4 and the barrier layer 3 are removed.

[0053] Specifically, the barrier layer 3 is used to protect the surface of the substrate 1. In some embodiments, the barrier layer 3 includes a silicon oxide layer, which can be formed on the surface of the substrate 1 by thermal oxidation or other suitable methods.

[0054] As an example, the hard mask layer 4 may be made of a silicon nitride layer or other suitable hard mask materials, and may be formed by low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD) or other suitable methods.

[0055] As an example, the method of etching the substrate 1 based on the patterned hard mask layer 4 to obtain the recessed portion 2 may be dry etching, wet etching or a combination of the two.

[0056] As an example, the desired depth of the recessed portion may be achieved by controlling the etching time or other etching parameters, wherein the deeper the depth of the recessed portion 2 is, the longer the increased channel length is.

[0057] As an example, the depth D of the recessed portion 2 is in the range of 1 to 50 nm, for example, 5 nm, 10 nm, 20 nm, 25 nm, 30 nm, etc., and can be specifically set according to the required electrical parameters of the device.

[0058] As an example, after the recessed portion 2 is obtained by etching, the hard mask layer 4 and the barrier layer 3 need to be removed to expose the top surface of the substrate in the channel region I.

[0059] In some embodiments, the method for removing the hard mask layer 4 includes wet etching. For example, for the silicon nitride hard mask layer, a hot phosphoric acid (H3PO4) solution may be used for removal. The temperature of the hot phosphoric acid solution may be, for example, about 160° C. The method of removing the silicon nitride hard mask layer using a hot phosphoric acid solution has good selectivity, and the etching process can be controlled to avoid damage to other materials.

[0060] In some embodiments, the method for removing the barrier layer 3 includes wet etching. For example, for the silicon oxide barrier layer, DHF can be used for removal. The full name of DHF in English is Diluted Hydrofluoric Acid, which is a diluted hydrofluoric acid solution, which is made by diluting hydrofluoric acid and water in a certain proportion. Its typical ratio is HF:H2O=1:20 or 1:50. It can effectively remove the silicon oxide layer, as well as remove metal ions attached to the silicon oxide layer during the cleaning process, such as aluminum, iron, zinc, nickel, etc., while having less corrosion effect on the substrate itself, which helps to maintain the surface characteristics and electrical characteristics of the substrate.

[0061] Please see again Figures 8 to 11 , perform the step S3: form a gate structure, the gate structure includes a gate dielectric layer 5 and a gate electrode layer 6, the gate dielectric layer 5 conformally covers the substrate top surface and substrate side surface of the channel region I, and the gate electrode layer 6 is located on the surface of the gate dielectric layer 5.

[0062] Specifically, the lowest point of the gate electrode layer 5 is higher than the top surface of the substrate of the source and drain region II, so as to avoid direct contact between the gate electrode layer 5 and the substrate of the source and drain region II.

[0063] In some embodiments, in order to round the corners of the substrate in the channel region I and repair the etched damaged substrate (for example, repair the etched damaged Si substrate), the following steps may be performed before forming the gate structure: (1) If Figure 8 As shown, a pad oxide layer 7 is formed on the surface of the substrate 1 by thermal oxidation or other suitable methods; (2) If Fig. 9 As shown, the pad oxide layer 7 is removed by wet etching or other suitable methods.

[0064] Specifically, since the corners of the substrate in the channel region I are rounded, the thickness uniformity of the gate dielectric layer 5 formed subsequently can be improved, that is, the thickness consistency of the gate dielectric layer in the corner areas, top surface and side surfaces of the substrate in the channel region I is improved.

[0065] In some embodiments, forming the gate structure comprises the following steps: (1) If Fig.10 As shown, a gate dielectric material layer 5a is deposited on the surface of the substrate 1 by thermal oxidation, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD) or other suitable methods; (2) If Fig.11 As shown, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD) or other suitable methods are used to deposit a gate electrode material layer 6a on the surface of the gate dielectric material layer 5a; (3) If Fig.12 As shown, the gate electrode material layer 6 a and the gate dielectric material layer 5 a are patterned by semiconductor processes such as photolithography and etching to obtain the gate electrode layer 6 and the gate dielectric layer 5 .

[0066] In some embodiments, the gate dielectric layer 5 includes a silicon oxide layer, and the gate electrode layer 6 includes a polysilicon layer.

[0067] In other embodiments, the gate structure may also adopt a high-K metal gate structure, wherein the gate dielectric layer 5 adopts a high-K material (High-k material) with a dielectric constant (K value) higher than that of traditional silicon dioxide (SiO2, K value is about 3.9), and the gate electrode layer 6 adopts a metal material. The use of high-K material as the gate dielectric layer can obtain a gate dielectric layer with a larger physical thickness under the condition of the same equivalent gate oxide layer thickness, thereby improving the gate leakage current, and using a metal gate instead of a polysilicon gate can improve the Fermi level pinning effect. At the same time, the metal gate has an extremely high electron density, which can effectively solve the polysilicon gate depletion problem.

[0068] As an example, the high-K material can be hafnium oxide (HfO2), silicon oxynitride (SiON), aluminum oxide (Al2O3), doped rare earth oxides (such as La2O3, Gd2O3, Er2O3, etc.), Hf-based high-K materials (such as HfSiON) or other suitable high-K materials, and the metal material can be titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum nitride (TaAlN), etc.

[0069] As an example, the vertical distance between the lowest point of the gate electrode layer 5 and the substrate top surface of the source and drain region II is smaller than the height difference between the substrate top surface of the source and drain region and the substrate top surface of the channel region. Please see again Fig.13 , perform the step S4: form a gate sidewall 8 and a source-drain doped region 9, the gate sidewall 8 is located on both sides of the gate structure, and the source-drain doped region 9 is located in the substrate of the source-drain region II.

[0070] As an example, the source-drain doping region 9 includes a lightly doped source-drain region (Lightly Doped Drain, LDD for short) formed before the gate spacer 8 and a heavily doped source-drain region (Heavily Doped Drain, HDD for short) formed after the gate spacer 8 .

[0071] In some embodiments, in order to suppress the drain induced barrier lowering (DIBL) effect of short channel devices, the source and drain doping regions 9 also include a halo (Halo, or pocket) ion implantation region formed before the gate sidewall 8, wherein the type of halo ion implantation is the same as that of the substrate, for example, the type of halo ion implantation of the NMOS transistor is P type, while the type of halo ion implantation of the PMOS transistor is N type. Since the depth of the halo ion implantation is deeper than that of the LDD ion implantation, the lateral expansion of the depletion regions of the source and drain can be effectively reduced to prevent source-drain punch-through.

[0072] In some embodiments, the gate spacer 8 includes a silicon nitride layer-silicon oxide layer-silicon nitride layer composite layer, ie, a NON composite layer.

[0073] In some other embodiments, the gate spacer may also include a silicon oxide layer-silicon nitride layer-silicon nitride layer composite layer, that is, an ONO composite layer.

[0074] At this point, a semiconductor structure is obtained by using a simple semiconductor process, in which the top surface of the substrate in the source and drain regions is lower than the top surface of the substrate in the channel region, wherein the gate dielectric layer not only covers the top surface of the substrate in the channel region, but also covers the side surface of the substrate in the channel region, thereby increasing the length of the gate channel under the same device area, which helps to improve the short channel effect while increasing the transistor density (more transistors under the same area) and improving the device performance.

[0075] The present invention also provides a semiconductor structure, which can be manufactured by the above manufacturing method or other suitable methods, see Fig.13 , showing a schematic diagram of the semiconductor structure, including a substrate 1, a gate structure and a source-drain doped region 9, wherein the substrate 1 includes a channel region I and a source-drain region II located on both sides of the channel region I, the substrate top surface of the source-drain region II is lower than the substrate top surface of the channel region I, the gate structure includes a gate dielectric layer 5 and a gate electrode layer 6, the gate dielectric layer 5 conformally covers the substrate top surface and substrate side surface of the channel region I, the gate electrode layer 6 is located on the surface of the gate dielectric layer 5 and is spaced a preset distance from the substrate top surface of the source-drain region II, the gate sidewalls 8 are located on both sides of the gate structure, and the source-drain doped region 9 is located in the substrate of the source-drain region II.

[0076] As an example, the height difference between the substrate top surface of the source and drain region II and the substrate top surface of the channel region I is in the range of 1 to 50 nm, for example, 5 nm, 10 nm, 20 nm, 25 nm, 30 nm, etc., and can be set specifically according to the required device electrical parameters.

[0077] As an example, the vertical distance between the lowest point of the gate electrode layer 6 and the top surface of the substrate of the source and drain region II is smaller than the height difference between the top surface of the substrate of the source and drain region II and the top surface of the substrate of the channel region I, that is, the gate electrode layer 5 surrounds the top surface of the substrate and a portion of the side surface of the source and drain region II (with the gate dielectric layer 5 in between), thereby increasing the control range of the gate electrode layer 5.

[0078] As an example, the substrate 1 can be a silicon substrate, a silicon-on-insulator substrate, a silicon-germanium substrate, a silicon carbide substrate, a III-V compound substrate or other suitable semiconductor substrates, and the doping type of the substrate 1 can be P-type or N-type.

[0079] As an example, the substrate 1 may be a substrate without an epitaxial layer or a substrate with an epitaxial layer, and the epitaxial layer may be homoepitaxial or heteroepitaxial.

[0080] As an example, the substrate of the channel region I has rounded corners (vertex angles), so that the gate dielectric layer 5 has a higher thickness uniformity, that is, the gate dielectric layer thickness consistency of the corner areas, top surface and side surfaces of the substrate of the channel region I is good.

[0081] As an example, in the gate structure, the gate dielectric layer 5 includes a silicon oxide layer, the gate electrode layer 6 includes a polysilicon layer, or the gate structure may also adopt a high-K metal gate structure, wherein the gate dielectric layer 5 adopts a high-K material (High-k material) having a dielectric constant (K value) higher than that of conventional silicon dioxide (SiO2, K value is about 3.9), and the gate electrode layer 6 adopts a metal material. The high-K material may be, for example, hafnium oxide (HfO2), silicon oxynitride (SiON), aluminum oxide (Al2O3), doped rare earth oxides (such as La2O3, Gd2O3, Er2O3, etc.), Hf-based high-K materials (such as HfSiON) or other suitable high-K materials, and the metal material may be, for example, titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum nitride (TaAlN), etc.

[0082] As an example, the gate sidewall 8 may be made of a NON composite layer or an ONO composite layer, and the source and drain doping region 9 includes a lightly doped source and drain region (Lightly Doped Drain, LDD for short) and a heavily doped source and drain region (Heavily Doped Drain, HDD for short). In some embodiments, the source and drain doping region 9 may further include a halo (Halo, or pocket) ion implantation region as needed.

[0083] For comparison, see Fig.14 and Fig.15 ,in, Fig.14 Shown is a conventional planar transistor and its carrier path when it is on. Fig.15 It shows the carrier path when the transistor in the semiconductor structure of the present invention is turned on. It can be seen that under the same area, the carrier path when the transistor in the semiconductor structure of the present invention is longer when it is turned on, which helps to improve the short channel effect and enhance the device performance.

[0084] In summary, the present invention provides a semiconductor structure and a manufacturing method thereof. Before forming a gate structure, the manufacturing method first etches the substrate to obtain recessed portions located on both sides of the channel region, so that the substrate top surface of the source and drain region is lower than the substrate top surface of the channel region. In the gate structure formed subsequently, the gate dielectric layer conformally covers the substrate top surface and the substrate side surface of the channel region, and the gate electrode layer is located on the surface of the gate dielectric layer and the lowest point of the gate electrode layer is higher than the substrate top surface of the source and drain region. Since the substrate top surface of the channel region is higher than the substrate top surface of the source and drain region, the gate dielectric layer not only covers the substrate top surface of the channel region, but also covers the substrate side surface of the channel region, thereby increasing the length of the gate channel under the same device area, which helps to improve the short channel effect while increasing the transistor density (more transistors under the same area) and improve the device performance. In addition, the manufacturing method of the semiconductor structure of the present invention has a simple process and helps to reduce the manufacturing cost. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0085] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: The following steps are involved: Providing a substrate, the substrate comprising a channel region and source and drain regions located on both sides of the channel region; Etching the substrate to obtain recessed portions located at both sides of the channel region, so that the top surface of the substrate in the source and drain regions is lower than the top surface of the substrate in the channel region; Forming a gate structure, the gate structure comprising a gate dielectric layer and a gate electrode layer, the gate dielectric layer conformally covers the substrate top surface and substrate side surface of the channel region, the gate electrode layer is located on the surface of the gate dielectric layer, and the lowest point of the gate electrode layer is higher than the substrate top surface of the source and drain region; A gate sidewall and a source-drain doped region are formed, wherein the gate sidewall is located at both sides of the gate structure, and the source-drain doped region is located in the substrate of the source-drain region.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein: The depth of the depression is in the range of 1 to 50 nm.

3. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: Etching the substrate to obtain recessed portions located on both sides of the channel region comprises the following steps: forming a barrier layer on the surface of the substrate; forming a hard mask layer on the surface of the barrier layer; Patterning the hard mask layer to obtain a hard mask opening, wherein the surface of the barrier layer in the channel region is still covered by the hard mask layer; Etching the substrate based on the patterned hard mask layer to obtain the recessed portion; The hard mask layer and the barrier layer are removed.

4. The method for manufacturing a semiconductor structure according to claim 3, wherein: The barrier layer comprises a silicon oxide layer, and the method of removing the barrier layer comprises wet etching.

5. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: Before forming the gate structure, the method further includes the following steps: forming a pad oxide layer on the surface of the substrate; The pad oxide layer is removed.

6. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: Forming the gate structure comprises the following steps: Depositing a gate dielectric material layer on the surface of the substrate; Depositing a gate electrode material layer on the surface of the gate dielectric material layer; The gate electrode material layer and the gate dielectric material layer are patterned to obtain the gate electrode layer and the gate dielectric layer.

7. The method for manufacturing a semiconductor structure according to claim 1, wherein: A vertical distance between the lowest point of the gate electrode layer and the substrate top surface of the source and drain regions is smaller than a height difference between the substrate top surface of the source and drain regions and the substrate top surface of the channel region.

8. A semiconductor structure, characterized in that: include: A substrate, the substrate comprising a channel region and source and drain regions located at both sides of the channel region, wherein a top surface of the substrate in the source and drain regions is lower than a top surface of the substrate in the channel region; A gate structure, comprising a gate dielectric layer and a gate electrode layer, wherein the gate dielectric layer conformally covers the top surface and side surfaces of the substrate in the channel region, and the gate electrode layer is located on the surface of the gate dielectric layer and is spaced a preset distance from the top surface of the substrate in the source and drain region; Gate sidewalls, located on both sides of the gate structure; The source-drain doping region is located in the substrate of the source-drain region.

9. The semiconductor structure according to claim 8, characterized in that: The height difference between the substrate top surface of the source and drain regions and the substrate top surface of the channel region is in the range of 1 to 50 nm.

10. The semiconductor structure according to claim 8, characterized in that: A vertical distance between the lowest point of the gate electrode layer and the substrate top surface of the source and drain regions is smaller than a height difference between the substrate top surface of the source and drain regions and the substrate top surface of the channel region.

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