Wafer packaging method and chip

Abstract

The invention provides a wafer packaging method and a chip, and the method comprises the steps: obtaining a support plate mold which comprises a first mold and a second mold; a wafer is obtained, the wafer comprises a plurality of to-be-packaged chips, and conductive bumps are prepared on the to-be-packaged chips; arranging at least two wafers on a first mold at intervals, wherein the first mold and a second mold are enclosed to form an injection molding space; injection molding and filling are carried out on the carrier plate mold from the surface of the first mold to the second mold to form a plastic package body, the plastic package body comprises a plastic package layer and at least two wafers plastically packaged in the plastic package layer, and the height of the plastic package body is larger than the sum of the heights of the conductive bumps and the wafers; after injection molding filling is completed, the side, away from the first mold, of the plastic package body is ground and polished, and the conductive protruding blocks are exposed out of the surface of the plastic package body; and rewiring is manufactured on the surface of the plastic package body where the conductive bumps are exposed, a next circuit layer is formed, the wafer and the plastic package material on the side, away from the solder balls, of the plastic package body are ground and thinned, and the plastic package body is cut. The wafer processing efficiency can be improved, and the cost can be reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to a wafer packaging method and a chip. Background Art

[0002] The existing wafer-level packaging method is to package multiple chips first and then cut them to obtain independent chips, or to obtain independent chips first and then package them separately. No matter which method is based on processing multiple chips on a single wafer, it is mainly in the form of dry film and yellow light process. Through the superposition of yellow light, sputtering, electroplating process, etc., according to the design requirements, multi-layer circuit layers are made. The biggest technical feature of these two solutions is that they can only realize the manufacture of multi-layer circuits by single-wafer processing, and the method based on single-wafer processing has low wafer processing efficiency and low production efficiency. Summary of the invention

[0003] In order to overcome the defects in the prior art, the embodiments of the present invention provide a wafer packaging method and a chip, which can improve the efficiency of wafer processing and reduce costs.

[0004] In order to achieve the above object, the technical solution adopted by the present invention is:

[0005] A first aspect of the present invention discloses a wafer packaging method, comprising:

[0006] S1, obtaining a carrier mold, wherein the carrier mold includes a first mold and a second mold;

[0007] S2, obtaining a wafer, wherein the wafer includes a plurality of chips to be packaged, and conductive bumps are prepared on the chips to be packaged;

[0008] S3, placing at least two of the wafers on the first mold with a spacing therebetween, and the first mold and the second mold are enclosed to form an injection molding space;

[0009] S4, injecting the carrier mold from the surface of the first mold into the second mold to form a plastic package body, wherein the plastic package body includes a plastic package layer and at least two wafers plastic packaged in the plastic package layer, and the height of the plastic package body is greater than the sum of the heights of the conductive bumps and the wafers;

[0010] S5, after the injection molding is completed, grinding and polishing the side of the plastic package body away from the first mold, so that the conductive bump is exposed on the surface of the plastic package body;

[0011] S6, making a rewiring on the surface of the plastic package body where the conductive bumps are exposed to form a next circuit layer, forming solder balls on the surface of the next circuit layer or repeating steps S4-S6 after the next circuit layer is completed, until the circuit layer reaches a preset number of layers, and planting solder balls on the surface of the preset number of circuit layers;

[0012] S7, grinding and thinning the wafer and the plastic sealing layer on the side of the plastic sealing body away from the solder balls separately or simultaneously, and after the thinning is completed, cutting the plastic sealing body to obtain a single wafer;

[0013] S8, cutting is performed along the cutting paths inside the single wafer to obtain the cut chips.

[0014] According to the size of the carrier mold, the above technical scheme sets at least two wafers in one carrier mold, and performs plastic sealing and subsequent process on at least two wafers at the same time. At least two wafers can be processed at one time. After the packaging is completed, the at least two wafers are separated by cutting, and then the chips on the single wafer are obtained. The wafer packaging method is simple. The rewiring process is performed on at least two wafers on a carrier mold at the same time, including metal layer sputtering, photolithography, electroplating, corrosion and other processes. At least two wafers can be packaged at the same time without performing other complicated process operations. Compared with the single wafer processing in the prior art, the efficiency of wafer processing is greatly improved, and the production efficiency is improved.

[0015] Furthermore, the material of the plastic encapsulation layer is EMC. The EMC is an epoxy resin molding compound, and the epoxy resin molding compound is used as a filling injection molding compound. When manufacturing a multi-layer circuit layer, each layer is filled with the epoxy resin molding compound, so that the epoxy resin molding compound completely covers the conductive bumps of the wafer chip, and replaces the PI material as the dielectric layer and the insulating layer of the subsequent manufacturing of the redistribution layer, which can reduce the cost.

[0016] Furthermore, the conductive bumps extend out of the packaged chip, forming a height difference with the chip to be packaged, the height difference being 10um to 100um. The conductive bumps are used to realize circuit layer interconnection between chips, and the height of the conductive bumps is 10um to 100um higher than the chip to be packaged to meet the requirements.

[0017] Furthermore, an adhesive layer is provided between the wafer and the first mold, and the wafer is bonded to the first mold through the adhesive layer. The wafer can be fixed to the carrier mold by the adhesive, and the fixing method is simple and low in cost.

[0018] Furthermore, the preset number of layers is 1 to 10. Based on the requirements of the circuit layer, the cyclic plastic packaging and wiring process can produce multi-layer circuits.

[0019] Furthermore, the step S6 also includes: after the circuit layer reaches a preset number of layers, making metal solder joints on the pads of the circuit layer.

[0020] Furthermore, the step S7 further includes:

[0021] After the solder balls are implanted, the substrate mold is removed, and after the plastic package body is turned over, the wafer and the plastic package layer on the side of the plastic package body away from the solder balls are ground and thinned;

[0022] During cutting, the plastic sealing layer on the plastic sealing body is cut according to the size of any wafer to obtain a single wafer.

[0023] The plastic sealing layer in the present application starts to be sealed from the surface of the first mold, and completely seals at least two wafers during the sealing process, so that at least two wafers and the plastic sealing layer form a whole. After the plastic sealing is completed, the thickness of the entire plastic sealing body is relatively thick. During grinding and thinning, the wafer substrate and the plastic sealing material on the side of the plastic sealing body away from the solder ball are thinned together. This is different from the method of thinning the plastic sealing material or the wafer substrate separately in the prior art, and can improve the efficiency of wafer processing.

[0024] Furthermore, the wafer includes at least one of a silicon wafer, a silicon carbide wafer, a gallium arsenide wafer, and a gallium nitride wafer.

[0025] Furthermore, the conductive bump is a copper bump.

[0026] The second aspect of the present invention discloses a chip, wherein the chip is manufactured by any method disclosed in the first aspect.

[0027] Due to the application of the above technical solution, the present invention has the following advantages compared with the prior art:

[0028] 1. According to the size of the carrier mold, the present application sets at least two wafers in one carrier mold, and performs plastic sealing and subsequent process on at least two wafers at the same time. At least two wafers can be processed at one time. After the packaging is completed, the at least two wafers are separated by cutting to obtain the chips on the single wafer. The wafer packaging method is simple. At least two wafers are subjected to a rewiring process on a carrier mold at the same time, including metal layer sputtering, photolithography, electroplating, corrosion and other processes. At least two wafers can be packaged at the same time without performing other complicated process operations. Compared with the single wafer processing in the prior art, the efficiency of wafer processing is greatly improved, and the production efficiency is improved.

[0029] 2. The present application reduces the difficulty of obtaining materials and reduces the cost of wafer packaging by setting epoxy resin molding compound as the filler of the plastic package and using the epoxy resin molding compound as the insulating layer and the dielectric layer in the multi-layer circuit layer.

[0030] In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0032] Figure 1 is a top view of a wafer packaging structure provided by an embodiment of the present invention;

[0033] Figure 2 It is a structural schematic diagram of a carrier plate mold provided by an embodiment of the present invention;

[0034] Figure 3 It is a schematic flow chart of a wafer packaging method provided by an embodiment of the present invention;

[0035] Figures 4 to 12 Based on Figure 3 The process shown is a schematic diagram of the process of preparing a wafer packaging structure.

[0036] The figure markings of the above drawings are: 1. carrier mold; 2. wafer; 3. chip; 4. conductive bump; 5. plastic packaging material; 6. solder ball; 7. substrate; 8. pad; 9. first mold; 10. second mold. DETAILED DESCRIPTION

[0037] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. In addition, the drawings of the present invention are only simple schematic illustrations and are not depicted according to actual sizes. Please note in advance.

[0038] In the present invention, it should be noted that the terms "upper", "lower", "inside", "outside", "forward", "backward", "between", "close to", "far away" and the like indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present invention. It should also be noted that, unless otherwise clearly specified and limited, the terms "installation" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances.

[0039] It should be understood that, although the terms "first", "second", "third", etc. may be used herein to describe various components or signals, these components or signals should not be limited by these terms. These terms are mainly used to distinguish one component from another component, or one signal from another signal. In addition, the term "or" used herein may include any one or more combinations of the associated listed items depending on the actual situation.

[0040] Reference Figure 1 The embodiment of the present application provides a top view of wafer packaging. During packaging, at least two wafers 2 are set on a carrier mold 1, and plastic sealing and subsequent processes are performed on at least two wafers 2 at the same time. According to the size of the carrier mold 1, the embodiment of the present application sets at least two wafers 2 on the carrier mold 1 for plastic sealing, and plastic sealing and subsequent processes are performed on at least two wafers 2 at the same time. At least two wafers 2 can be processed at one time. After the packaging is completed, the at least two wafers 2 are separated by cutting, and then the chips on the single wafer are obtained. The present application can process at least two wafers at one time based on the size of the carrier mold. Compared with the single wafer processing in the prior art, the efficiency of wafer processing is greatly improved, and the production efficiency is improved.

[0041] It should be noted that due to the different sizes of wafers and carrier molds, there must be unusable areas between at least two wafers. These unusable areas will cause obvious warping in the actual wafer packaging process in this embodiment because of the obvious difference in CTE shrinkage between the wafer material and the plastic packaging material itself. During actual packaging, another auxiliary material with CTE shrinkage and completely opposite properties of EMC plastic packaging material is placed in the gap between wafers, such as a metal block or block silicon. In a possible embodiment, the metal block is a copper block or an iron block, and the size and shape of the copper block and the iron block are set according to the size and shape of the gap between wafers.

[0042] Reference Figure 3 , an embodiment of the present application provides a wafer packaging method, comprising the following steps:

[0043] S1 , obtaining a carrier mold 1 , wherein the carrier mold includes a first mold 9 and a second mold 10 .

[0044] Reference Figure 2 An embodiment of the present application provides a structural diagram of a carrier mold 1, including a first mold 9 and a second mold 10, wherein the first mold 9 is arranged below the second mold 10, the first mold 9 is used to place multiple wafers 2, and the second mold 10 is used to enclose the first mold 9 to form an injection space during injection molding to apply pressure to the plastic packaging material 5.

[0045] During plastic encapsulation, at least two wafers 2 are first placed on the first mold 9. After the second mold 10 is enclosed with the first mold 9, the plastic encapsulation space is filled with plastic encapsulation material 5. The first mold 9 and the second mold 10 apply pressure to the plastic encapsulation material 5 to extend from the surface of the first mold 9 to the second mold 10 to form a plastic encapsulation body, which includes a plastic encapsulation layer and at least two wafers 2 encapsulated in the plastic encapsulation layer.

[0046] S2, obtaining a wafer 2, wherein the wafer 2 includes a plurality of chips 3 to be packaged, and conductive bumps 4 are prepared on the chips 3 to be packaged.

[0047] like Figure 4 As shown, based on the incoming wafer 2, the wafer 2 is pre-processed, and the conductive bumps 4 are processed on the pads 8 of the wafer 2, wherein the height of the conductive bumps 4 is higher than the surface of the chip 3 to be packaged on the wafer 2.

[0048] It should be noted that the above-mentioned step of setting the conductive bump 4 is a conventionally known technique for setting the bump, and the pad of the wafer 2 is a metal pad.

[0049] In a possible embodiment, the conductive bump 4 is a copper bump, the pad 8 is an aluminum pad, and the conductive bump 4 is used to form a good electrical connection with an external circuit.

[0050] Since the conductive bump 4 is used to connect different circuit layers, the height of the conductive bump 4 does not need to be set too high. In a possible embodiment, the height of the conductive bump 4 is 10um to 100um higher than the chip to be packaged 3. If the height of the conductive bump 4 is too high, the manufacturing cost will increase, and the conductive bump 4 will be easily broken. If the height is too low, the wafer will be easily damaged in the subsequent process, such as the grinding process. The height of the conductive bump 4 higher than the chip to be packaged 3 is set within this range, which can meet the process requirements.

[0051] Optionally, the wafer 2 has a variety of sizes, including 6 inches, 8 inches, 12 inches, etc., and the manufacturing process of the wafer 2 includes a variety of processes, and it can be a silicon wafer, a silicon carbide wafer, a gallium arsenide wafer, a gallium nitride wafer, etc.

[0052] Optionally, the shape and structure of the wafer 2 can be set to be circular or have at least one side that is flat or has a notch or has at least one side that is flat after cutting, etc.

[0053] Optionally, when the wafer 2 is set to be circular, its diameter size includes multiple types, such as 150 mm, 200 mm, 300 mm, etc.

[0054] S3, at least two wafers 2 are spaced apart and arranged on the first mold 9, and the first mold 9 and the second mold 10 are enclosed to form an injection molding space.

[0055] like Figure 5 As shown, at least two wafers 2 are arranged in the carrier mold 1.

[0056] In a possible embodiment, an adhesive layer is provided on the first mold 9 , and the at least two wafers 2 are fixed in the carrier mold 1 by the adhesive.

[0057] The substrate mold 1 and the wafer 2 have various sizes, such as Figure 1 As shown, the embodiment of the present application is described by taking an 8-inch wafer as an example in which a carrier mold 1 with a size of 515 mm x 510 mm is provided. Figure 1 Four 8-inch wafers 2 are arranged in the carrier mold 1, and all subsequent process processing of the wafers 2 is performed on the four wafers at the same time, which can greatly improve production efficiency and reduce costs.

[0058] In other possible embodiments, two 12-inch wafers 2 or nine 6-inch wafers 2 may be placed in the carrier mold 1 .

[0059] It should be noted that, based on the size of the carrier mold 1 and the size of the wafer 2 placed thereon, different wafers 2 can be placed in different carrier molds 1 , and at least two wafers 2 can be placed on one carrier mold 1 .

[0060] S4, injecting the carrier mold 1 from the surface of the first mold 9 into the second mold 10 to form a plastic package body, wherein the plastic package body includes a plastic package layer and at least two wafers 2 plastic packaged in the plastic package layer, and the height of the plastic package body is greater than the sum of the heights of the conductive bumps 4 and the wafers 2.

[0061] like Figure 6 As shown, the carrier mold 1 on which four wafers 2 are placed is injection molded and filled. During filling, the molding compound 5 is injected from the surface of the first mold 9 to the second mold 10, and the molding compound completely fills the gap between at least two wafers 2. The height of the molding compound 5 at least covers the conductive bumps 4 on the surface of the wafer 2. At least two wafers 2 are connected by the molding compound 5. In the subsequent wiring and continued filling of the molding compound 5 process, at least two wafers 2 are processed simultaneously.

[0062] The filled plastic packaging material 5 is EMC.

[0063] S5, after the injection molding is completed, the side of the plastic package body away from the first mold 9 is polished to expose the conductive bump 4 on the surface of the plastic package body.

[0064] like Figure 7 As shown, after filling the EMC molding compound, the surface of the EMC facing away from the first mold 9 is ground and polished to expose the manufactured conductive bumps 4, in preparation for forming the next layer of circuits.

[0065] S6, making rewiring on the surface of the plastic package body where the conductive bumps 4 are exposed to form the next circuit layer, forming solder balls 6 on the surface of the next circuit layer, or repeating steps S4-S6 after the next circuit layer is completed, until the circuit layer reaches a preset number of layers, and implanting solder balls 6 on the surface of the preset number of circuit layers.

[0066] like Figure 8-Figure 9 As shown, a rewiring process is performed on the exposed conductive bump 4, and the rewiring process includes making a metal pad on the conductive bump 4, performing metal layer sputtering, photolithography, electroplating, corrosion and other processes to make the next circuit layer.

[0067] After the next circuit layer is completed, conductive bumps 4 are made again on the surface of the circuit layer, and the carrier mold 1 is plastic-sealed and filled again. The plastic sealing material 5 used for plastic sealing is epoxy plastic sealing material. After the plastic sealing and filling is completed, it is polished until the conductive bumps 4 of the second layer of circuit are exposed.

[0068] The above steps are repeated until the required one or more circuit layers are completed, and finally solder balls 6 are made on the surface of the circuit layer.

[0069] In a possible embodiment, the preset number of layers is 1 to 10 layers, the circuit layer is a metal layer, and the metal may be copper.

[0070] After the circuit layer reaches a preset number of layers, metal solder joints are made on the circuit layer pads for subsequent SMT chip placement operations.

[0071] In the above embodiment, EMC is used as a dielectric layer and an insulating layer for filling plastic packaging and for the subsequent manufacture of a redistribution layer. When performing plastic packaging and manufacturing a circuit layer, the EMC will completely cover the conductive bumps 4 of the wafer chip. Subsequently, part of the EMC is removed by grinding and polishing until the conductive bumps 4 are exposed for the next layer of circuit manufacturing. Compared with the prior art that uses PI material as the dielectric layer and insulating layer of the redistribution layer, the difficulty of obtaining dielectric layer and insulating layer materials is reduced, and the cost of wafer packaging is reduced.

[0072] S7, grinding and thinning the wafer 2 and the plastic packaging layer on the side of the plastic packaging body away from the solder ball 6 separately or simultaneously. After the thinning is completed, the plastic packaging body is cut to obtain a single wafer 2.

[0073] The above steps also include:

[0074] After the solder balls 6 are implanted, the carrier mold 1 is removed, and after the plastic package body is turned over, the wafer 2 and the plastic package layer on the side of the plastic package body away from the solder balls 6 are ground and thinned;

[0075] During cutting, the plastic sealing layer on the plastic sealing body is cut according to the size of any wafer 2 to obtain a single wafer 2.

[0076] like Fig.10 As shown, after the multi-layer circuit layer processing in steps S4-S6, the thickness of the plastic package body and the circuit layer formed on the plastic package body can reach hundreds of microns, and the overall rigid thickness can support subsequent processing. At this time, the carrier mold 1 is removed, the plastic package body is turned over, and the substrate 7 and the plastic package material 5 of the wafer 2 are ground and thinned at the same time to make the plastic package body reach the required thickness. Compared with the method of thinning the plastic package material 5 or the wafer substrate 7 separately in the prior art, after many experiments, the method of grinding and thinning the substrate 7 and the plastic package material 5 of the wafer 2 at the same time in the present application can improve the efficiency of wafer processing.

[0077] like Fig.11 As shown, after the thinning is completed, the formed plastic package of multiple wafers 2 is cut and separated according to the size of each wafer 2 to obtain a single wafer 2 processed with a circuit layer.

[0078] S8, cutting is performed along the cutting paths inside the single wafer 2 to obtain the cut chips.

[0079] like Fig.12 As shown, the wafer is cut along the cutting paths inside the single wafer 2 to obtain independent chips.

[0080] The embodiment of the present application also provides a chip, which is manufactured by the method in the above embodiment.

[0081] The wafer packaging method and chip in the above-mentioned embodiment are to simultaneously package and rewire at least two wafers in a carrier mold, separate the at least two wafers after the processing is completed, and cut the separated single wafers to obtain chips.

[0082] The present invention uses specific embodiments to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A wafer packaging method, characterized in that: include: S1, obtaining a carrier mold, wherein the carrier mold includes a first mold and a second mold; S2, obtaining a wafer, wherein the wafer includes a plurality of chips to be packaged, and conductive bumps are prepared on the chips to be packaged; S3, placing at least two of the wafers on the first mold with a spacing therebetween, and the first mold and the second mold are enclosed to form an injection molding space; S4, injecting the carrier mold from the surface of the first mold into the second mold to form a plastic package body, wherein the plastic package body includes a plastic package layer and at least two wafers plastic packaged in the plastic package layer, and the height of the plastic package body is greater than the sum of the heights of the conductive bumps and the wafers; S5, after the injection molding is completed, grinding and polishing the side of the plastic package body away from the first mold, so that the conductive bump is exposed on the surface of the plastic package body; S6, making a rewiring on the surface of the plastic package body where the conductive bumps are exposed to form a next circuit layer, forming solder balls on the surface of the next circuit layer or repeating steps S4-S6 after the next circuit layer is completed, until the circuit layer reaches a preset number of layers, and planting solder balls on the surface of the preset number of circuit layers; S7, grinding and thinning the wafer and the plastic sealing layer on the side of the plastic sealing body away from the solder balls separately or simultaneously, and after the thinning is completed, cutting the plastic sealing body to obtain a single wafer; S8, cutting is performed along the cutting paths inside the single wafer to obtain the cut chips.

2. A wafer packaging method according to claim 1, characterized in that: The material of the plastic sealing layer is EMC.

3. The wafer packaging method according to claim 1, characterized in that: The conductive bumps extend out of the chip to be packaged, forming a height difference with the chip to be packaged, and the height difference is 10um to 100um.

4. The wafer packaging method according to claim 1, characterized in that: An adhesive layer is provided between the wafer and the first mold, and the wafer is bonded to the first mold through the adhesive layer.

5. The wafer packaging method according to claim 1, characterized in that: The preset number of layers is 1 to 10 layers.

6. The wafer packaging method according to claim 1, characterized in that: The step S6 also includes: after the circuit layer reaches a preset number of layers, making metal solder joints on the pads of the circuit layer.

7. The wafer packaging method according to claim 1, characterized in that: The step S7 further comprises: After the solder balls are implanted, the substrate mold is removed, and after the plastic package body is turned over, the wafer and the plastic package layer on the side of the plastic package body away from the solder balls are ground and thinned; During cutting, the plastic sealing layer on the plastic sealing body is cut according to the size of any wafer to obtain a single wafer.

8. The wafer packaging method according to claim 1, characterized in that: The wafer includes at least one of a silicon wafer, a silicon carbide wafer, a gallium arsenide wafer, and a gallium nitride wafer.

9. The wafer packaging method according to claim 1, characterized in that: The conductive bumps are copper bumps.

10. A chip, characterized in that: The chip is prepared by the method according to any one of claims 1 to 9.

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