Transistor, manufacturing method thereof and electronic equipment
By forming side by side channel layers, source and drain terminals on the substrate, and increasing the thickness with the structure of the crystallized layer, the problems of increasing parasitic resistance and channel layer damage in microtransistors are solved, and performance improvement is achieved.
Patent Information
- Application Number
- CN202310672775.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-07
- Publication Date
- 2024-12-10
AI Technical Summary
In microtransistors, increased parasitic resistance at the source and drain terminals leads to a degradation of performance, and the prior art tends to overetch damage the channel layer when making a lifting structure, resulting in uncertain thickness.
By forming a channel layer on the substrate and providing at least a source and drain ends of the crystallization layer on both sides thereof, the third surface of the crystallization layer is further away from the substrate than the second surface of the channel layer, This increases the thickness of the source and drain ends while avoiding damage to the channel layer.
It effectively reduces the parasitic resistance at the source and drain terminals, improves the transistor's miniaturization potential, and improves performance while avoiding damage to the channel layer.
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Figure CN119108409A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a transistor, a manufacturing method thereof, and an electronic device. Background Art
[0002] With the continuous development of CMOS (Complementary Metal Oxide Semiconductor) integrated circuit manufacturing process, the size of transistors continues to shrink, which makes the size of source and drain terminals also continue to decrease, which leads to an increase in parasitic resistance of the source and drain terminals, resulting in a decrease in device performance. In order to solve this problem, a lifting structure can be used above the source terminal to raise the source terminal, and a lifting structure can be used above the drain terminal to raise the drain terminal. In this way, the thickness of the source and drain terminals can be increased without affecting gate control and leakage, thereby reducing the parasitic resistance of the source and drain terminals and improving the miniaturization potential of the device.
[0003] In the current technology, when making a raised source terminal and a raised drain terminal, an amorphous IGZO (full name in English: Indium Gallium Zinc Oxide, Chinese meaning: Indium Gallium Zinc Oxide) film can be first deposited on the substrate, and part of the amorphous IGZO film can be used as a channel layer. Then, a crystallized IGZO film is deposited on the amorphous IGZO film, and the position corresponding to the channel layer in the crystallized IGZO film is etched to expose the channel layer, thereby facilitating the production of a gate structure on the channel layer, and the remaining portion of the crystallized IGZO film can be used as a raised source terminal and a raised drain terminal. However, in the above process, since it is necessary to etch the position corresponding to the channel layer in the crystallized IGZO film, part of the channel layer may be etched away due to over-etching, resulting in an uncertain thickness of the channel layer. This phenomenon is particularly significant when the thickness of the channel layer is thin, thereby affecting the performance of the transistor. Summary of the invention
[0004] The present application provides a transistor, a manufacturing method thereof, and an electronic device, which can not only increase the thickness of the source and drain terminals to reduce the parasitic resistance of the source and drain terminals, but also avoid adverse effects on the channel layer, thereby improving the performance of the transistor.
[0005] In the first aspect, an embodiment of the present application provides a transistor, which may include: a substrate, and a channel layer, a source terminal and a drain terminal arranged on the substrate, wherein the source terminal and the drain terminal are respectively arranged on opposite sides of the channel layer, so that the source terminal, the drain terminal, and the channel layer can be arranged side by side on the substrate, and the source terminal and the drain terminal each include at least a crystallization layer. Among them, the surface of the crystallization layer facing the substrate is the first surface, the surface of the channel layer facing away from the substrate is the second surface, and the surface of the crystallization layer facing away from the substrate is the third surface. The distance between the first surface and the substrate is recorded as the first distance, the distance between the second surface and the substrate is recorded as the second distance, and the distance between the third surface and the substrate is recorded as the third distance. The third distance is greater than the second distance, indicating that the third surface of the crystallization layer is farther away from the substrate than the second surface of the channel layer, and further indicating that the thickness of the source terminal and the drain terminal is greater than the thickness of the channel layer, achieving an increase in the thickness of the source terminal and the drain terminal, reducing the parasitic resistance of the source terminal and the drain terminal, and improving the miniaturization potential of the device. Furthermore, the first distance is smaller than the second distance, indicating that the first surface of the crystallized layer is closer to the substrate than the second surface of the channel layer. This structure can avoid damage to the channel layer when increasing the thickness of the source and drain terminals, thereby improving the performance of the transistor.
[0006] It should be emphasized that in the current technology, a film layer (referred to as the first film layer) for making a raised source terminal and a raised drain terminal is deposited on the channel layer, and the corresponding position of the channel layer in the first film layer is etched to make the raised source terminal and the raised drain terminal. Due to over-etching, part of the channel layer may be etched away, which will cause the first surface of the crystallized layer to be further away from the substrate than the second surface of the channel layer. In the embodiment of the present application, if the entire crystallized layer in the source terminal is regarded as a raised source terminal, and the entire crystallized layer in the drain terminal is regarded as a raised drain terminal, then the opposite is true, that is, the first surface of the crystallized layer is closer to the substrate than the second surface of the channel layer, which means that when the thickness of the source terminal and the drain terminal is increased by raising the source terminal and the drain terminal, the channel is not etched, thereby avoiding damage to the channel layer due to over-etching, thereby improving the performance of the transistor. Alternatively, if the partially crystallized layer in the source terminal is regarded as a raised source terminal, and the partially crystallized layer in the drain terminal is regarded as a raised drain terminal, when the crystallized layer in the source terminal is produced by a single process, and the crystallized layer in the drain terminal is also produced by a single process, the raised source terminal and the raised drain terminal are also produced when the crystallized layer is produced. Therefore, when the first surface of the crystallized layer is closer to the substrate than the second surface of the channel layer, it can also be explained that when the raised source terminal and the raised drain terminal are formed to increase the thickness of the source terminal and the drain terminal, the channel layer is not damaged, thereby improving the performance of the transistor.
[0007] Exemplarily, the channel layer can be made of amorphous materials, which can reduce the difference in the number of grain boundaries in the channel layers of each transistor, thereby improving the uniformity of each transistor produced; of course, the channel layer can also be made of crystallized materials, which can improve the electron mobility and stability of the transistor. In addition, the material for making the channel layer includes a first oxide semiconductor material, and the first oxide semiconductor material can be crystallized or amorphous. The material for making the crystallized layer includes a crystallized second oxide semiconductor material, so the crystallized layer is obviously crystallized.
[0008] Among them, the first oxide semiconductor material and the second oxide semiconductor material can meet the following conditions: the first oxide semiconductor material and the second oxide semiconductor material both include oxygen and other elements, and the other elements corresponding to the first oxide semiconductor material and the second oxide semiconductor material include the same elements. Among them, when the elements included in the other elements corresponding to the first oxide semiconductor material and the second oxide semiconductor material are exactly the same, it means that the first oxide semiconductor material and the second oxide semiconductor material are the same material; when the elements included in the other elements corresponding to the first oxide semiconductor material and the second oxide semiconductor material are partially the same, it means that the first oxide semiconductor material and the second oxide semiconductor material are different materials, but belong to a similar material system or the same material system, which is conducive to the production of thickened source and drain terminals. Exemplarily, the oxide semiconductor material can include but is not limited to: indium oxide, indium gallium oxide, indium tin oxide, indium gallium zinc oxide and other oxide semiconductors, which can be selected according to actual conditions and are not limited here.
[0009] Of course, the materials used to make the channel layer and the crystallization layer are not limited to oxide semiconductor materials, but may also include other semiconductor materials. As long as the semiconductor materials can realize the functions of the channel layer and the crystallization layer, they belong to the protection scope of the embodiments of the present application.
[0010] Exemplarily, the crystallization layer in the source terminal and the crystallization layer in the drain terminal may be made of the same material, which can facilitate the simultaneous production of the crystallization layer in the source terminal and the crystallization layer in the drain terminal, thereby simplifying the production steps of the transistor and reducing the difficulty of producing the transistor. Of course, the crystallization layer in the source terminal and the crystallization layer in the drain terminal may also be made of different materials, so that the crystallization layer in the source terminal and the crystallization layer in the drain terminal need to be produced separately through different production steps to meet the needs of different application scenarios and improve the flexibility of the design.
[0011] Exemplarily, the source terminal and the drain terminal may only include a crystallized layer, and correspondingly, the first distance between the first surface of the crystallized layer facing the substrate side and the substrate is zero, in which case part of the crystal layer in the source terminal can be used as a raised source terminal, and part of the crystallized layer in the drain terminal can be used as a raised drain terminal. Alternatively, in addition to both including a crystallized layer, the source terminal and the drain terminal may also include an amorphous layer, and correspondingly, the first distance between the first surface of the crystallized layer facing the substrate side and the substrate is greater than zero. For the source terminal: the corresponding amorphous layer is arranged between the crystallized layer and the substrate, and the entire crystallized layer in the source terminal serves as a raised source terminal; for the drain terminal: the corresponding amorphous layer is arranged between the crystallized layer and the substrate, and the entire crystallized layer in the drain terminal serves as a raised drain terminal. In this way, the thickness of the source terminal and the drain terminal is increased by superposition of the amorphous layer and the crystallized layer. Among them, the materials used to make the amorphous layer in the source end and the amorphous layer in the drain end can be the same as the materials used to make the channel layer, such as both can include a first oxide semiconductor material, and the amorphous layer in the source end and the amorphous layer in the drain end can be made of the same material, or made of different materials but belonging to a similar material system or the same material system. The specific selection can be made based on actual conditions and is not limited here.
[0012] Exemplarily, the transistor may further include: a gate structure disposed on the substrate, the gate structure overlapping the orthographic projection of the channel layer on the substrate, so that the gate voltage provided by the gate structure can act on the channel layer to realize the function of the transistor. Based on the setting position of the gate structure, the transistor can be divided into a top-gate transistor and a bottom-gate transistor, which are introduced below.
[0013] For top-gate transistors: the gate structure is arranged on the side of the channel layer away from the substrate, so that when the substrate is arranged below the channel layer, the gate structure is arranged above the channel layer, thereby obtaining a top-gate structure, at which time the source terminal and the drain terminal can be spaced apart by the gate structure and the channel layer to avoid short-circuiting between the source terminal and the drain terminal. Based on this, the gate structure may include: a gate, a gate insulating layer and an insulating structure, the gate and the channel layer are spaced apart by the gate insulating layer to avoid short-circuiting between the gate and the channel layer, and multiple insulating structures may be arranged, for example but not limited to two, three or more, and may be arranged specifically according to actual conditions, wherein part of the insulating structure is arranged between the gate and the source terminal, and the remaining insulating structure is arranged between the gate and the drain terminal, and the insulating structure may avoid short-circuiting between the gate and the source terminal, and avoid short-circuiting between the gate and the drain terminal, thereby improving the reliability of the transistor.
[0014] For bottom-gate transistors: the gate structure is arranged on the side of the channel layer facing the substrate, that is, the gate structure is arranged between the substrate and the channel layer, so that the gate structure is arranged below the channel layer, thereby obtaining a bottom-gate structure. Among them, a groove may be arranged on the surface of the side of the substrate facing the channel layer, and the gate structure may be arranged in the groove of the substrate. The depth of the groove may be less than, greater than or equal to the height of the gate structure, which can be beneficial to reduce the thickness of the transistor; or, a groove for accommodating the gate structure is not arranged on the surface of the side of the substrate facing the channel layer, and the gate structure is arranged on the surface of the side of the substrate facing the channel layer, and the entire gate structure protrudes from the surface; therefore, the arrangement of the gate structure and the substrate can be arranged according to actual needs and is not limited here. In addition, the gate structure may include a stacked gate and a gate insulating layer, and the gate insulating layer is arranged between the gate and the channel layer to avoid short circuit between the gate and the channel layer. In addition, the transistor may further include: an insulating barrier wall disposed on the side of the channel layer facing away from the substrate, wherein the insulating barrier wall may overlap with the positive projection of the channel layer on the substrate, and at this time, the source terminal and the drain terminal may be spaced apart by the channel layer and the insulating barrier wall to avoid short circuit between the source terminal and the drain terminal, thereby improving the reliability of the transistor.
[0015] It should be understood that the gate insulation layer, insulation structure and insulation barrier mentioned above can be made of any material that can achieve insulation function, and is not limited here.
[0016] In the second aspect, the embodiment of the present application also provides a method for manufacturing a transistor, which may include: forming a channel layer on a substrate; forming a source terminal and a drain terminal on both sides of the channel layer, wherein the source terminal and the drain terminal both include at least a crystallized layer; wherein, in the first surface of the crystallized layer facing the substrate side and the second surface of the channel layer facing away from the substrate side, the distance between the first surface and the substrate is less than the distance between the second surface and the substrate; the distance between the third surface of the crystallized layer facing away from the substrate side and the substrate is greater than the distance between the second surface and the substrate. In this way, the third surface of the crystallized layer is further away from the substrate than the second surface of the channel layer, which further indicates that the thickness of the source terminal and the drain terminal is greater than the thickness of the channel layer, thereby achieving an increase in the thickness of the source terminal and the drain terminal, reducing the parasitic resistance of the source terminal and the drain terminal, and improving the miniaturization potential of the device. In addition, the first surface of the crystallized layer is closer to the substrate than the second surface of the channel layer. This structure can avoid damage to the channel layer when increasing the thickness of the source terminal and the drain terminal, thereby improving the performance of the transistor.
[0017] Illustratively, while forming the channel layer, it may also include: forming a first end and a second end on the substrate, and the first end and the second end are arranged side by side on opposite sides of the channel layer, wherein the materials used to make the first end and the second end may include an amorphous first oxide semiconductor material.
[0018] Based on this, the following steps can be included when forming the source terminal and the drain terminal: forming a spacing structure on the channel layer, and forming openings on the first terminal and the second terminal, the openings exposing the first terminal and the second terminal; forming an amorphous second oxide semiconductor layer on the substrate formed with the spacing structure and the opening, and processing the amorphous second oxide semiconductor layer to crystallize the amorphous second oxide semiconductor layer in contact with the first terminal and the second terminal, and to keep the second oxide semiconductor layer not in contact with the first terminal and the second terminal amorphous; etching the amorphous portion of the second oxide semiconductor layer so that: the crystallized second oxide semiconductor layer located above the first terminal and the crystallized portion in the first terminal form a crystallized layer in the source terminal, the crystallized layer in the source terminal and the amorphous portion in the first terminal form the source terminal, and the crystallized second oxide semiconductor layer located above the second terminal and the crystallized portion in the second terminal form a crystallized layer in the drain terminal, and the crystallized layer in the drain terminal and the amorphous portion in the second terminal form the drain terminal.
[0019] It should be understood that when the Gibbs free energy of the material that decreases due to crystallization is greater than the Gibbs free energy of the interface and the surface that increases due to crystallization, the crystallization reaction of the material can proceed spontaneously in thermodynamics, so the material has a minimum thickness required for crystallization (also referred to as a preset thickness). Only when the thickness of the material is greater than the preset thickness will the material change from an amorphous state to a crystallized state. The effect of this thickness on crystallization can be referred to as a thickness effect. Therefore, based on the thickness effect, the amorphous second oxide semiconductor layer can be processed to crystallize the amorphous second oxide semiconductor layer in contact with the first end and the second end, and to keep the second oxide semiconductor layer that is not in contact with the first end and the second end amorphous. When the amorphous second oxide semiconductor layer in contact with the first end has a first thickness, the amorphous second oxide semiconductor layer in contact with the second end has a second thickness, and the amorphous second oxide semiconductor layer that is not in contact with the first end and the second end has a third thickness, it can specifically include:
[0020] The first thickness, the second thickness and the third thickness are all less than the preset thickness, and the first thickness, the second thickness and the third thickness can be the same or different. In this way, since the thickness of the amorphous second oxide semiconductor layer that is not in contact with the first end and the second end does not reach the preset thickness, under the condition of heating, the amorphous second oxide semiconductor layer that is not in contact with the first end and the second end still maintains the amorphous state. If the first end and the second end are made of amorphous first oxide semiconductor materials, when the first oxide semiconductor material and the second oxide semiconductor material belong to the same material system or a similar material system or the same material, under the condition of heating, the first oxide semiconductor material can promote the crystallization process of the second oxide semiconductor material. Even if the thickness of the amorphous second oxide semiconductor layer in contact with the first end and the second end does not reach the preset thickness, the first oxide semiconductor material in the first end and the second end will contribute a part of the thickness, so that the second oxide semiconductor reaches the thickness requirement of crystallization, so the second oxide semiconductor layer in contact with the first end and the second end can be transformed from the amorphous state to the crystallized state. In addition, in the first end and the second end, the partially amorphous first oxide semiconductor material in contact with the second oxide semiconductor layer will also be transformed from the amorphous state to the crystallized state. The heating method may include but is not limited to at least one of annealing and laser irradiation.
[0021] Alternatively, the first thickness and the second thickness are both greater than or equal to the preset thickness, the first thickness and the second thickness may be the same or different, and the third thickness is less than the preset thickness. In this way, since the thickness of the amorphous second oxide semiconductor layer in contact with the first end and the second end exceeds the preset thickness, and the thickness of the amorphous second oxide semiconductor layer not in contact with the first end and the second end does not exceed the preset thickness, under heating conditions, the amorphous second oxide semiconductor layer in contact with the first end and the second end can be transformed from an amorphous state to a crystallized state, while the amorphous second oxide semiconductor layer not in contact with the first end and the second end remains in an amorphous state because it does not reach the preset thickness. In addition, when the manufacturing materials of the first end and the second end belong to the same material system or a similar material system or the same material as the second oxide semiconductor material, at least part of the first oxide semiconductor material in the first end and the second end may also be transformed from an amorphous state to a crystallized state.
[0022] Of course, in order to process the amorphous second oxide semiconductor layer, crystallize the amorphous second oxide semiconductor layer in contact with the first end and the second end, and keep the second oxide semiconductor layer not in contact with the first end and the second end amorphous, in addition to being realized based on the thickness effect (which can be regarded as a crystallization mechanism), it can also be realized based on other crystallization mechanisms or special processing means, and the thickness of the amorphous second oxide semiconductor layer at each position will not be limited by the preset thickness, so that the needs of different application scenarios can be met and the flexibility of design can be improved. Exemplarily, other crystallization mechanisms can specifically include but are not limited to: based on the different interface energy changes caused by different substances when the material changes from the amorphous state to the crystallized state, by selecting a suitable substance, part of the amorphous second oxide semiconductor layer can be crystallized and part can remain amorphous, and the effect of this substance on the interface energy and then on the crystallization can be called the substrate effect. Exemplarily, the special processing means can specifically include but are not limited to: injecting electrons into part of the amorphous second oxide semiconductor layer, so that the part injected with electrons can be transformed into a crystallized state, while the part without electrons remains amorphous. The method of injecting electrons may be any method known to those skilled in the art that can achieve electron injection, and is not limited here. Therefore, as long as the amorphous second oxide semiconductor layer in contact with the first end and the second end can be crystallized, the method of keeping the second oxide semiconductor layer not in contact with the first end and the second end amorphous is within the protection scope of the embodiments of the present application.
[0023] Based on this, the crystallized portion of the first end and the second oxide semiconductor layer that is in contact with the first end and crystallized together constitute the crystallized layer in the source end, and the crystallized portion of the second end and the second oxide semiconductor layer that is in contact with the second end and crystallized together constitute the crystallized layer in the drain end. Wherein, if the first oxide semiconductor material in the first end and the second end is partially crystallized, then the amorphous portion of the first end and the crystallized layer in the source end constitute the source end, and the amorphous portion of the second end and the crystallized layer in the drain end constitute the drain end. Alternatively, if the first oxide semiconductor material in the first end and the second end is completely transformed from an amorphous state to a crystallized state, then the entire first end and the second oxide semiconductor layer that is in contact with the first end and crystallized together constitute the crystallized layer in the source end, and the entire second end and the second oxide semiconductor layer that is in contact with the second end and crystallized together constitute the crystallized layer in the drain end, and therefore the source end only includes the crystallized layer, and the drain end also only includes the crystallized layer.
[0024] In this way, the source and drain terminals can be produced by depositing an amorphous second oxide semiconductor layer, processing the amorphous second oxide semiconductor layer so that part of the second oxide semiconductor layer is transformed from an amorphous state to a crystallized state, and etching the amorphous part of the second oxide semiconductor layer. In addition, during these processes, the spacing structure always covers the channel layer, which protects the channel layer and avoids damaging the channel layer during the etching process, thereby improving the performance of the transistor. In addition, even if over-etching occurs when making the source and drain terminals, such over-etching may etch away part of the spacing structure and part of the crystallized second oxide semiconductor layer, but will not damage the channel layer. Therefore, even if over-etching occurs, the channel layer will not be damaged, thereby effectively improving the reliability and performance of the transistor.
[0025] Exemplarily, when forming the spacing structure and the opening, it may include: depositing a first film layer structure on a substrate having a channel layer, a first end, and a second end, etching a portion of the first film layer structure using an etching technique, the portion of the first film layer structure that is retained forms a spacing structure, and the portion of the first film layer structure that is etched away forms an opening, so that the opening exposes the first end and the second end, and the spacing structure covers the channel layer. Exemplarily, when the transistor is a bottom-gate transistor, the spacing structure may be the insulating barrier wall in the first aspect above, and the first film layer structure may include a single insulating film layer or multiple stacked insulating film layers. When the transistor is a top-gate transistor, the spacer structure can be the gate structure in the first aspect mentioned above. In this case, the first film layer structure may include: an insulating film layer and a conductive layer stacked in sequence along a direction from the substrate to the channel layer; and after etching the first film layer structure to form an opening, it may also include: forming an insulating structure on the side wall of the opening, so that two adjacent insulating structures in two adjacent openings and the portion retained and sandwiched between the two insulating structures form a gate structure, wherein in the portion between the two insulating structures, the insulating film layer serves as a gate insulating layer, the conductive layer serves as a gate, and the gate structure serves as a spacer structure.
[0026] In this way, when the transistor is a top-gate transistor, the gate structure can be manufactured simultaneously during the process of manufacturing the source and drain terminals, and the gate structure and the channel layer can be completely overlapped in their orthographic projections on the substrate, thereby realizing self-calibration of the source, drain, channel layer, and gate structure, thereby reducing the number of layouts used, reducing etching steps, and reducing the manufacturing cost of transistors. It can also avoid degradation of transistor performance due to calibration errors.
[0027] Illustratively, when forming the amorphous second oxide semiconductor layer, any method capable of realizing film deposition may be used, such as but not limited to atomic layer deposition, physical vapor deposition, etc., which is not limited here.
[0028] Exemplarily, when etching the amorphous portion of the second oxide semiconductor layer, a suitable etchant can be used to etch away the amorphous portion of the second oxide semiconductor layer based on the etching selectivity of the amorphous portion and the crystallized portion of the second oxide semiconductor material, and the crystallized portion of the second oxide semiconductor layer is retained. Therefore, when performing this step, patterning is not required, the operation is easy, and it is also conducive to achieving self-calibration of the source end, the drain end, and the gate structure, simplifying the difficulty of manufacturing the transistor and improving the manufacturing efficiency of the transistor.
[0029] Exemplarily, the above process of making the source terminal and the drain terminal can be repeated to increase the thickness of the source terminal and the drain terminal, so as to meet the performance requirements of the transistor. In addition, the above process of forming the source terminal and the drain terminal can be applied to the scene where the crystallization temperature of the second oxide semiconductor material is within a preset temperature range, wherein the preset temperature range can be set according to the temperature used in the manufacturing process of the semiconductor device, and is not limited here.
[0030] Exemplarily, before the amorphous second oxide semiconductor layer is processed and after the amorphous second oxide semiconductor layer is formed, the method for manufacturing the transistor may further include: forming an induced crystallization layer on the amorphous second oxide semiconductor layer. That is, on a substrate formed with a spacing structure and an opening, an amorphous second oxide semiconductor layer is first formed, and then an induced crystallization layer is formed, and then the processing and etching are performed. Since the induced crystallization layer has the effect of catalyzing crystallization and reducing the crystallization temperature for the second oxide semiconductor layer to change from an amorphous state to a crystallized state, the presence of the induced crystallization layer can promote the change of the second oxide semiconductor layer from an amorphous state to a crystallized state; and, under the effect of the thickness effect, when the third thickness of the amorphous second oxide semiconductor is less than the preset thickness, the induced crystallization layer does not cause the amorphous second oxide semiconductor layer that is not in contact with the first end and the second end to change to a crystallized state.
[0031] Furthermore, when the crystallization temperature of the amorphized second oxide semiconductor layer exceeds the preset temperature range, since the induced crystallization layer has the function of lowering the crystallization temperature, the induced crystallization layer can lower the crystallization temperature of the amorphized second oxide semiconductor layer. Even if the crystallization temperature of the amorphized second oxide semiconductor layer itself is high and exceeds the preset temperature range, the crystallization temperature is lowered under the action of the induced crystallization layer, so that the amorphized second oxide semiconductor layer in contact with the first end and the second end is crystallized, and under the support of the thickness effect, the amorphized second oxide semiconductor layer not in contact with the first end and the second end still maintains the amorphized state. Of course, when the crystallization temperature of the amorphized second oxide semiconductor layer does not exceed the preset temperature range, the induced crystallization layer can still be set to further lower the crystallization temperature of the second oxide semiconductor material, reduce the thermal budget, and thus reduce the manufacturing cost and difficulty of the transistor.
[0032] In the third aspect, an embodiment of the present application provides an electronic device, which may include: a circuit board and a transistor as described in the first aspect above, and the transistor may be arranged on the circuit board. In this way, by setting the source terminal and the drain terminal, not only the thickness of the source terminal and the drain terminal can be increased, the parasitic resistance of the source terminal and the drain terminal can be reduced, and the miniaturization potential of the device can be improved, but also damage to the channel layer can be avoided, thereby improving the performance of the transistor and even the electronic device. Since the implementation principle of the electronic device is similar to the implementation principle of the above-mentioned transistor, the specific implementation method and technical effects of the electronic device can refer to the specific implementation method and technical effects of the above-mentioned transistor, and the repeated parts will not be repeated. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] Figure 1 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;
[0034] Figure 2 A schematic diagram of the structure of a transistor provided in an embodiment of the present application;
[0035] Figure 3 A schematic diagram of the structure of another transistor provided in an embodiment of the present application;
[0036] Figure 4 A schematic diagram of the structure of another transistor provided in an embodiment of the present application;
[0037] Figure 5 A schematic diagram of the structure of another transistor provided in an embodiment of the present application;
[0038] Figure 6 A schematic diagram of the structure of another transistor provided in an embodiment of the present application;
[0039] Figure 7A schematic diagram of a transistor manufacturing process provided in an embodiment of the present application;
[0040] Figure 8 A schematic diagram of another transistor manufacturing process provided in an embodiment of the present application;
[0041] Fig. 9 A schematic diagram of a manufacturing process of another transistor provided in an embodiment of the present application;
[0042] Fig.10 A schematic diagram of a manufacturing process of another transistor provided in an embodiment of the present application;
[0043] Fig.11 A schematic diagram of a manufacturing process of another transistor provided in an embodiment of the present application.
[0044] Reference numerals:
[0045] 10-substrate, 20-channel layer, 31-source terminal, 32-drain terminal, 40-gate structure, 41-gate, 42-gate insulating layer, 43-insulating structure, 50-insulating barrier wall, 100-housing, 200-circuit board, 300-transistor, m1-crystallized layer, m2-amorphized layer, m3-groove, b1-first surface, b2-second surface, b3-third surface, d1-first distance, d2-second distance, d3-third distance, k0-spacer structure, k1-first end, k2-second end, k3-opening, k4-second oxide semiconductor layer, k5-induced crystallization layer, x1-first thickness, x2-second thickness, x3-third thickness. DETAILED DESCRIPTION
[0046] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings.
[0047] It should be noted that the same reference numerals in the drawings of this application represent the same or similar structures, and thus their repeated description will be omitted. The words expressing positions and directions described in this application are all explained using the drawings as examples, but they can be changed as needed, and the changes are included in the protection scope of this application. The drawings of this application are only used to illustrate the relative position relationship and do not represent the true proportion.
[0048] In order to facilitate understanding of the technical solution provided by the embodiments of the present application, the application scenario of the embodiments of the present application is first explained below.
[0049] The transistor provided in the embodiment of the present application can be widely used in various electronic devices, and the electronic devices may include various terminal devices and electronic devices. Among them, the terminal devices may include but are not limited to: smart phones, smart TVs, smart TV set-top boxes, smart watches, personal computers (PCs), wearable devices, smart broadband and other devices. Electronic devices may include but are not limited to: wireless networks, fixed networks, servers and other telecommunication equipment, as well as chip modules, memory and other devices, which are not listed here one by one.
[0050] Figure 1 The schematic diagram of the structure of a transistor when it is used in an electronic device is shown as an example. Figure 1 As shown, the electronic device includes a housing 100 and a circuit board 200 disposed in the housing 100, and a transistor 300 is disposed on the circuit board 200. With the continuous development of CMOS integrated circuit manufacturing processes, the size of the transistor 300 is continuously miniaturized, so that the size of the source terminal and the drain terminal is also continuously reduced, which leads to an increase in the parasitic resistance of the source terminal and the drain terminal, resulting in a decrease in the performance of the device. In order to solve this problem, a lifting structure can be used above the source terminal to raise the source terminal, and a lifting structure can be used above the drain terminal to raise the drain terminal. In this way, the thickness of the source terminal and the drain terminal can be increased without affecting the gate control and leakage, thereby reducing the parasitic resistance of the source terminal and the drain terminal and improving the miniaturization potential of the device.
[0051] In the current technology, when making a raised source terminal and a raised drain terminal, an amorphous IGZO film can be first deposited on the substrate, and part of the amorphous IGZO film can be used as a channel layer. Then, a crystallized IGZO film is deposited on the amorphous IGZO film, and the position corresponding to the channel layer in the crystallized IGZO film is etched to expose the channel layer, thereby facilitating the production of a gate structure on the channel layer, and the remaining part of the crystallized IGZO film can be used as a raised source terminal and a raised drain terminal. However, in the above process, since it is necessary to etch the position corresponding to the channel layer in the crystallized IGZO film, part of the channel layer may be etched away due to over-etching, resulting in an uncertain thickness of the channel layer. This phenomenon is particularly significant when the thickness of the channel layer is thin, thereby affecting the performance of the transistor.
[0052] Based on this, an embodiment of the present application provides a transistor, which can not only increase the thickness of the source and drain terminals to reduce the parasitic resistance of the source and drain terminals, but also avoid adverse effects on the channel layer, thereby improving the performance of the transistor.
[0053] Figure 2 The schematic diagram of the structure of the transistor in the first embodiment of the present application is shown as an example. Figure 2As shown, the transistor may include: a substrate 10, and a channel layer 20, a source terminal 31 and a drain terminal 32 arranged on the substrate 10, wherein the source terminal 31 and the drain terminal 32 are respectively arranged on opposite sides of the channel layer 20, so that the source terminal 31, the drain terminal 32, and the channel layer 20 can be arranged side by side on the substrate 10; the source terminal 31 and the drain terminal 32 each include at least a crystallization layer m1. Among them, the surface of the crystallization layer m1 facing the substrate 10 is a first surface b1, and the distance between the first surface b1 and the substrate 10 is recorded as a first distance d1, the surface of the channel layer 20 facing away from the substrate 10 is a second surface b2, and the distance between the second surface b2 and the substrate 10 is recorded as a second distance d2, and the surface of the crystallization layer m1 facing away from the substrate 10 is a third surface b3, and the distance between the third surface b3 and the substrate 10 is recorded as a third distance d3. The third distance d3 is greater than the second distance d2, indicating that the third surface b3 of the crystallized layer m1 is further away from the substrate 10 than the second surface b2 of the channel layer 20, and further indicating that the thickness of the source terminal 31 and the drain terminal 32 is greater than the thickness of the channel layer 20, achieving an increase in the thickness of the source terminal 31 and the drain terminal 32, reducing the parasitic resistance of the source terminal 31 and the drain terminal 32, and improving the miniaturization potential of the device. In addition, the first distance d1 is less than the second distance d2, indicating that the first surface b1 of the crystallized layer m1 is closer to the substrate 10 than the second surface b2 of the channel layer 20. This structure can avoid damage to the channel layer 20 when increasing the thickness of the source terminal 31 and the drain terminal 32, thereby improving the performance of the transistor.
[0054] Among them, the material of the channel layer 20 may include a first oxide semiconductor material, and the first oxide semiconductor material may be crystallized or amorphous. The material of the crystallized layer m1 includes a crystallized second oxide semiconductor material, so the crystallized layer m1 is obviously crystallized. In addition, the first oxide semiconductor material and the second oxide semiconductor material may meet the following conditions: the first oxide semiconductor material and the second oxide semiconductor material both include oxygen and other elements, and the first oxide semiconductor material and the second oxide semiconductor material include the same elements in the other elements corresponding to the first oxide semiconductor material and the second oxide semiconductor material. Among them, when the elements included in the other elements corresponding to the first oxide semiconductor material and the second oxide semiconductor material are exactly the same, it means that the first oxide semiconductor material and the second oxide semiconductor material are the same material; when the elements included in the other elements corresponding to the first oxide semiconductor material and the second oxide semiconductor material are partially the same, it means that the first oxide semiconductor material and the second oxide semiconductor material are different materials, but belong to a similar material system or the same material system, which is conducive to the production of thickened source terminals 31 and drain terminals 32. Exemplarily, the oxide semiconductor material may include, but is not limited to, oxide semiconductors such as indium oxide, indium gallium oxide, indium tin oxide, indium gallium zinc oxide, etc., which can be selected according to actual conditions and are not limited here.
[0055] The crystallization layer m1 in the source terminal 31 and the crystallization layer m1 in the drain terminal 32 may be made of the same material, which is conducive to realizing the simultaneous production of the crystallization layer m1 in the source terminal 31 and the crystallization layer m1 in the drain terminal 32, thereby simplifying the production steps of the transistor and reducing the difficulty of producing the transistor. Of course, the crystallization layer m1 in the source terminal 31 and the crystallization layer m1 in the drain terminal 32 may also be made of different materials, so that the crystallization layer m1 in the source terminal 31 and the crystallization layer m1 in the drain terminal 32 need to be produced respectively through different production steps to meet the needs of different application scenarios and improve the flexibility of design.
[0056] Continue to refer to Figure 2 As shown, in addition to the crystallized layer m1, the source terminal 31 and the drain terminal 32 may also include an amorphous layer m2, and the amorphous layer m2 in the source terminal 31 is arranged between the corresponding crystallized layer m1 and the substrate 10, and the amorphous layer m2 in the drain terminal 32 is arranged between the corresponding crystallized layer m1 and the substrate 10, so that the source terminal 31 is composed of the amorphous layer m2 and the crystallized layer m1, and the drain terminal 32 is also composed of the amorphous layer m2 and the crystallized layer m1. The amorphous layer m2 and the channel layer 20 may be made of the same material, or different materials but belonging to the same material system or a similar material system. Therefore, in the source terminal 31, the crystallized layer m1 can be regarded as a raised source terminal; in the drain terminal 32, the crystallized layer m1 can be regarded as a raised drain terminal.
[0057] Reference Figure 3 As shown, the transistor may further include a gate structure 40, and the gate structure 40 overlaps with the positive projection of the channel layer 20 on the substrate 10, so that the gate voltage provided by the gate structure 40 can act on the channel layer 20 to realize the function of the transistor. Exemplarily, the transistor may be a top-gate transistor. The gate structure 40 is arranged on the side of the channel layer 20 away from the substrate 10, so that when the substrate 10 is arranged below the channel layer 20, the gate structure 40 is arranged above the channel layer 20, thereby obtaining a top-gate structure, and at this time, the source terminal 31 and the drain terminal 32 can be arranged at intervals through the gate structure 40 and the channel layer 20 to avoid short-circuiting the source terminal 31 and the drain terminal 32. Based on this, the gate structure 40 may include: a gate 41, a gate insulating layer 42 and an insulating structure 43. The gate 41 and the channel layer 20 are separated by the gate insulating layer 42 to avoid short circuit between the gate 41 and the channel layer 20. There may be multiple insulating structures 43, for example but not limited to two, and three, four or more, which may be arranged according to actual conditions. Some insulating structures 43 are arranged between the gate 41 and the source terminal 31, and the remaining insulating structures 43 are arranged between the gate 41 and the drain terminal 32. The insulating structure 43 can avoid short circuit between the gate 41 and the source terminal 31, and avoid short circuit between the gate 41 and the drain terminal 32, thereby improving the reliability of the transistor.
[0058] Figure 4The schematic diagram of the structure of the transistor in the second embodiment of the present application is exemplarily shown. The structure of the transistor in this embodiment is similar to that of the transistor in the first embodiment, except that: Figure 4 As shown, the transistor is a bottom-gate transistor. The gate structure 40 is disposed on the side of the channel layer 20 facing the substrate 10, that is, the gate structure 40 is disposed between the substrate 10 and the channel layer 20, so that the gate structure 40 is disposed below the channel layer 20, thereby obtaining a bottom-gate structure. Figure 4 The upper surface of the substrate 10 shown in the figure may be provided with a groove m3, and the gate structure 40 may be provided in the groove m3 of the substrate 10. The depth of the groove m3 may be less than, greater than or equal to the height of the gate structure 40, which may be beneficial to reducing the thickness of the transistor; or, the surface of the substrate 10 facing the channel layer 20 is not provided with a groove m3 for accommodating the gate structure 40, and the gate structure 40 is provided on the surface of the substrate 10 facing the channel layer 20, and the entire gate structure 40 protrudes from the surface; therefore, the arrangement of the gate structure 40 and the substrate 10 may be arranged according to actual needs, and is not limited here. In addition, the gate structure 40 may include a gate 41 and a gate insulating layer 42 arranged in a stacked manner, and the gate insulating layer 42 is arranged between the gate 41 and the channel layer 20 to avoid short circuit between the gate 41 and the channel layer 20. In addition, the transistor may further include: an insulating barrier 50 disposed on the side of the channel layer 20 away from the substrate 10, the insulating barrier 50 and the positive projection of the channel layer 20 on the substrate 10 may overlap, at which time the source terminal 31 and the drain terminal 32 may be spaced apart by the channel layer 20 and the insulating barrier 50 to avoid short circuit between the source terminal 31 and the drain terminal 32, thereby improving the reliability of the transistor; and, the alignment of the source terminal 31, the drain terminal 32, the channel layer 20 and the gate 41 may also be achieved to improve the performance of the transistor. For the parts of this embodiment that are the same as those of the first embodiment, reference may be made to the description of the first embodiment, and the repeated parts will not be repeated.
[0059] Figure 5 The schematic diagram of the structure of the transistor in the third embodiment of the present application is exemplarily shown. The structure of the transistor in this embodiment is similar to that of the transistor in the first embodiment, except that: Figure 5 As shown, the source terminal 31 and the drain terminal 32 only include the crystallized layer m1, and correspondingly, the first distance d1 between the first surface b1 of the crystallized layer m1 facing the substrate 10 and the substrate 10 is zero, and at this time, part of the crystal layer m1 in the source terminal 31 can be used as a raised source terminal, and part of the crystallized layer m1 in the drain terminal 32 can be used as a raised drain terminal. For the same parts of this embodiment as the first embodiment, please refer to the description of the first embodiment, and the repeated parts will not be repeated.
[0060] Figure 6The schematic diagram of the structure of the transistor in the fourth embodiment of the present application is exemplarily shown. The structure of the transistor in this embodiment is similar to that of the transistor in the first embodiment, except that: Figure 6 As shown, on the one hand, the transistor is a bottom-gate transistor. On the other hand, the source terminal 31 and the drain terminal 32 only include the crystallized layer m1. Correspondingly, the first distance d1 between the first surface b1 of the crystallized layer m1 facing the substrate 10 and the substrate 10 is zero. At this time, part of the crystal layer m1 in the source terminal 31 can be used as a raised source terminal, and part of the crystal layer m1 in the drain terminal 32 can be used as a raised drain terminal. Among them, for the parts of this embodiment that are the same as those in the first embodiment, refer to the description of the first embodiment, and for the structure of the bottom-gate transistor, refer to the description in the second embodiment, and the repeated parts will not be repeated.
[0061] Figure 7 The flowchart of the method for manufacturing a transistor in the fifth embodiment of the present application is exemplarily shown, referring to Figure 7 As shown, the following steps may be included:
[0062] Step 1: Figure 7 As shown in (a), a channel layer 20, a first end k1 and a second end k2 are formed on a substrate 10, the channel layer 20, the first end k1 and the second end k2 are all made of a first oxide semiconductor material, and the first end k1 and the second end k2 are arranged side by side on opposite sides of the channel layer 20.
[0063] The channel layer 20 , the first end k1 and the second end k2 can be manufactured through a single manufacturing process, so as to simplify the manufacturing process of the transistor.
[0064] Step 2: Figure 7 As shown in (a), a spacing structure k0 is formed on the channel layer 20, and an opening k3 is formed on the first end k1 and the second end k2, and the opening k3 exposes the first end k1 and the second end k2. Exemplarily, the spacing structure k0 can be a gate structure to form a top-gate transistor.
[0065] Step 3: Figure 7 As shown in (b) of FIG. 1 , an amorphized second oxide semiconductor layer k4 is formed on the substrate 10 having the spacer structure k0 and the opening k3 formed thereon.
[0066] Among them, assuming that the amorphous second oxide semiconductor layer k4 in contact with the first end k1 has a first thickness x1, the amorphous second oxide semiconductor layer k4 in contact with the second end k2 has a second thickness x2, and the amorphous second oxide semiconductor layer k4 not in contact with the first end k1 and the second end k2 has a third thickness x3, then the first thickness x1, the second thickness x2 and the third thickness x3 can all be less than the preset thickness, and the first thickness x1, the second thickness x2 and the third thickness x3 can all be the same or different.
[0067] Furthermore, the first oxide semiconductor material and the second oxide semiconductor material may be the same material, or different materials but belonging to the same material system or a similar material system.
[0068] Step 4: Figure 7 As shown in (c), when it is determined that the crystallization temperature of the amorphous second oxide semiconductor layer k4 does not exceed the preset temperature range, the amorphous second oxide semiconductor layer k4 is heat-treated so that the amorphous second oxide semiconductor layer k4 in contact with the first end k1 and the second end k2 (such as the portion shown by Q3) and the second oxide semiconductor layer k4 not in contact with the first end k1 and the second end k2 remain amorphous.
[0069] Exemplarily, the heat treatment method may include but is not limited to at least one of annealing and laser irradiation, etc. The preset temperature range may be set according to the temperature used in the manufacturing process of the semiconductor device, for example, the preset temperature range may be set to no more than 500°C.
[0070] Furthermore, if the first oxide semiconductor material in the channel layer 20, the first end k1, and the second end k2 is amorphized, when the amorphized second oxide semiconductor layer k4 (the portion shown as Q3) in contact with the first end k1 and the second end k2 is crystallized, the first oxide semiconductor in at least a portion of the first end k1 and at least a portion of the second end k2 will also be crystallized (the portion shown as Q1). If the first oxide semiconductor material in the channel layer 20, the first end k1, and the second end k2 is crystallized, when the amorphized second oxide semiconductor layer k4 (the portion shown as Q3) in contact with the first end k1 and the second end k2 is crystallized, the first oxide semiconductor in the first end k1 and the second end k2 can continue to remain crystallized, and promote the crystallization process of the amorphized second oxide semiconductor layer k4 in contact with the first end k1 and the second end k2.
[0071] Step 5: Figure 7As shown in (d) in the figure, the amorphous portion of the second oxide semiconductor layer k4 is etched so that the crystallized second oxide semiconductor layer k4 located above the first end k1 (the portion shown by Q3) and the crystallized first end k1 (the portion shown by Q1) form the crystallized layer m1 in the source end 31, and then the crystallized layer m1 in the source end 31 and the amorphous portion of the first end k1 (the portion shown by Q2, that is, the structure indicated by m2) form the source end 31; the crystallized second oxide semiconductor layer k4 located above the second end k2 and the crystallized second end k2 form the crystallized layer in the drain end 32, and then the crystallized layer in the drain end 32 and the amorphous portion of the second end k2 form the drain end 32.
[0072] If the first oxide semiconductor material in the first terminal k1 is partially crystallized and the first oxide semiconductor material in the second terminal k2 is partially crystallized, the crystallized layer m1 in the source terminal 31 can be regarded as a raised source terminal, and the crystallized layer in the drain terminal 32 can be regarded as a raised drain terminal. Alternatively, if the first oxide semiconductor material in the first terminal k1 is completely crystallized and the first oxide semiconductor material in the second terminal k2 is completely crystallized, the partially crystallized layer m1 in the source terminal 31 can be regarded as a raised source terminal, and the partially crystallized layer in the drain terminal 32 can be regarded as a raised drain terminal.
[0073] In addition, when performing the etching process, it can be achieved based on the difference in etching selectivity between crystallization and amorphization.
[0074] In this way, when the thickness of the source terminal 31 and the drain terminal 32 is increased, damage to the channel layer 20 can be avoided, thereby improving the performance of the transistor; and, since the thickness of the source terminal 31 and the drain terminal 32 is increased, the parasitic resistance of the source terminal 31 and the drain terminal 32 can also be reduced, thereby improving the miniaturization potential of the device.
[0075] Figure 8 The flowchart of the manufacturing method of the transistor in the sixth embodiment of the present application is exemplarily shown. The manufacturing method is basically similar to the fifth manufacturing method mentioned above, and the differences include the following points:
[0076] First point: adding step s1 between step 3 in the fifth embodiment and step 4 in the fifth embodiment: Figure 8As shown in (c) in FIG. 1 , an induced crystallization layer k5 is formed on the amorphous second oxide semiconductor layer k4. The presence of the induced crystallization layer k5 can accelerate the crystallization process of the amorphous second oxide semiconductor layer k4 in contact with the first end k1 and the second end k2, and can also reduce the crystallization temperature, thereby reducing the heat treatment temperature, reducing the thermal budget, and reducing the manufacturing cost of the transistor. It should be emphasized that when the third thickness x3 of the amorphous second oxide semiconductor is less than the preset thickness, under the action of the thickness effect, even if the induced crystallization layer k5 is provided, the amorphous second oxide semiconductor layer k4 that is not in contact with the first end k1 and the second end k2 still remains in an amorphous state; regardless of whether the thickness of the amorphous second oxide semiconductor layer k4 in contact with the first end k1 and the second end k2 is greater than or equal to the preset thickness, because the first oxide semiconductor material in the first end k1 and the second end k2 promotes the crystallization of the second oxide semiconductor layer k4, the amorphous second oxide semiconductor layer k4 in contact with the first end k1 and the second end k2 can be transformed from an amorphous state to a crystallized state, and under the action of the induced crystallization layer k5, the crystallization temperature of the amorphous second oxide semiconductor layer k4 in contact with the first end k1 and the second end k2 can be reduced, thereby accelerating the crystallization process.
[0077] Second point: Step 4 in the fifth embodiment should be adjusted to: Figure 8 As shown in (d), when it is determined that the crystallization temperature of the amorphized second oxide semiconductor layer k4 exceeds the preset temperature range, the amorphized second oxide semiconductor layer k4 is heat-treated to make the amorphized second oxide semiconductor layer k4 in contact with the first end k1 and the second end k2, and the second oxide semiconductor layer k4 not in contact with the first end k1 and the second end k2 remain amorphized. Since the induced crystallization layer k5 has the function of lowering the crystallization temperature, the induced crystallization layer k5 can lower the crystallization temperature of the amorphized second oxide semiconductor layer k4. Even if the crystallization temperature of the amorphized second oxide semiconductor layer k4 itself is high and exceeds the preset temperature range, the amorphized second oxide semiconductor layer k4 in contact with the first end k1 and the second end k2 can still be crystallized through the function of the induced crystallization layer k5, thereby lowering the heat treatment temperature, reducing the thermal budget, and reducing the manufacturing cost of the transistor.
[0078] Of course, when the crystallization temperature of the amorphous second oxide semiconductor layer k4 does not exceed the preset temperature range, the above step s1 can also be performed, so that the crystallization temperature, which is not high to begin with, can be further reduced, thereby reducing the manufacturing difficulty and manufacturing cost of the transistor.
[0079] Third point: before step 5 in the fifth embodiment and after step 4 in this embodiment, step s2 is added: etching the induced crystallization layer k5, so as to remove the induced crystallization layer k5 and expose the second oxide semiconductor layer k4, thereby facilitating etching the exposed second oxide semiconductor layer k4.
[0080] The similarities between this embodiment and the fifth embodiment mentioned above can be found in the description of the fifth embodiment mentioned above, and the repeated parts will not be repeated here.
[0081] Fig. 9 The flowchart of the manufacturing method of the transistor in the seventh embodiment of the present application is exemplarily shown. The manufacturing method is basically similar to the fifth manufacturing method mentioned above, except that step s3 is added between step 3 in the fifth embodiment and step 4 in the fifth embodiment: Fig. 9 As shown in (c), the thickness of the amorphized second oxide semiconductor layer k4 in contact with the first end k1 and the second end k2 is increased, so that the first thickness x1 of the amorphized second oxide semiconductor layer k4 in contact with the first end k1 and the second thickness x2 of the amorphized second oxide semiconductor layer k4 in contact with the second end k2 are greater than or equal to the preset thickness, and the third thickness x3 of the amorphized second oxide semiconductor layer k4 not in contact with the first end k1 and the second end k2 is less than the preset thickness. In this way, under the action of the thickness effect, the amorphized second oxide semiconductor layer k4 in contact with the first end k1 and the second end k2 can be transformed from an amorphized state to a crystallized state, while the amorphized second oxide semiconductor layer k4 not in contact with the first end k1 and the second end k2 remains in an amorphized state. The similarities between this embodiment and the fifth embodiment described above can be found in the description of the fifth embodiment described above, and the repeated parts will not be repeated.
[0082] Fig.10 The flowchart of the manufacturing method of the transistor in the eighth embodiment of the present application is exemplarily shown. The manufacturing method is basically similar to the fifth manufacturing method described above, except that: step S4 is added after step 3 in the fifth embodiment and before step 4 in the fifth embodiment: Fig.10 As shown in (c) in FIG. 1 , electrons are injected into the amorphized second oxide semiconductor layer k4 in contact with the first end k1 and the second end k2; wherein the thickness of any part of the amorphized second oxide semiconductor layer k4 may be greater than the preset thickness, or may be less than or equal to the preset thickness. Thus, after executing step 4, the position where the electrons are injected in the second oxide semiconductor layer k4 changes from the amorphized state to the crystallized state, while the position where the electrons are not injected remains in the amorphized state, thereby realizing selective crystallization in the second oxide semiconductor layer k4 by using special processing means without relying on the thickness effect.
[0083] Fig.11 The flowchart of the manufacturing method of the transistor in the ninth embodiment of the present application is exemplarily shown. The manufacturing method is basically similar to the fifth manufacturing method mentioned above, except that: step S5 is added before step 1 in the fifth embodiment: Fig.11 As shown in (a) of FIG. 1 , a gate structure 40 is formed in the substrate 10 to form a bottom-gate transistor. The same points between this embodiment and the fifth embodiment can be found in the description of the fifth embodiment, and the repeated points will not be repeated.
[0084] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.
Claims
1. A transistor, characterized in that: include: A substrate, and a channel layer, a source terminal and a drain terminal arranged on the substrate, wherein the source terminal and the drain terminal are arranged on both sides of the channel layer, and each of the source terminal and the drain terminal at least comprises a crystallized layer; The surface of the crystallized layer facing the substrate is a first surface, the surface of the channel layer facing away from the substrate is a second surface, the surface of the crystallized layer facing away from the substrate is a third surface, and the distance between the first surface and the substrate is smaller than the distance between the second surface and the substrate; A distance between the third surface and the substrate is greater than a distance between the second surface and the substrate.
2. The transistor according to claim 1, wherein The crystallized layer in the source terminal and the crystallized layer in the drain terminal include the same manufacturing material.
3. The transistor according to claim 1, wherein The channel layer is made of a material including a first oxide semiconductor material; The crystallization layer is made of a material including a crystallized second oxide semiconductor material.
4. The transistor according to claim 3, characterized in that The first oxide semiconductor material and the second oxide semiconductor material both include oxygen and other elements, and the other elements corresponding to the first oxide semiconductor material and the second oxide semiconductor material include the same element.
5. The transistor according to any one of claims 1 to 4, characterized in that: At least one of the source terminal and the drain terminal further includes an amorphous layer disposed between the crystallized layer and the substrate, and the amorphous layer is made of the same material as the channel layer.
6. The transistor according to any one of claims 1 to 5, characterized in that: The transistor further comprises a gate structure, wherein the gate structure is arranged on a side of the channel layer away from the substrate; The source terminal and the drain terminal are spaced apart by the gate structure and the channel layer.
7. The transistor according to claim 6, characterized in that The gate structure includes: a gate, a gate insulating layer disposed between the gate and the channel layer, and insulating structures disposed between the gate and the source terminal and between the gate and the drain terminal respectively.
8. The transistor according to any one of claims 1 to 5, characterized in that: The transistor further comprises a gate structure, wherein the gate structure is arranged on a side of the channel layer facing the substrate, and the transistor further comprises: an insulating barrier wall arranged on a side of the channel layer facing away from the substrate and corresponding to the channel layer; The source terminal and the drain terminal are spaced apart by the insulating barrier wall and the channel layer.
9. A method for manufacturing a transistor, characterized in that: include: forming a channel layer over the substrate; forming a source terminal and a drain terminal on both sides of the channel layer, wherein the source terminal and the drain terminal both include at least a crystallized layer; The surface of the crystallized layer facing the substrate is a first surface, the surface of the channel layer facing away from the substrate is a second surface, the surface of the crystallized layer facing away from the substrate is a third surface, and the distance between the first surface and the substrate is smaller than the distance between the second surface and the substrate; A distance between the third surface and the substrate is greater than a distance between the second surface and the substrate.
10. The manufacturing method according to claim 9, characterized in that: Forming the source and drain terminals, including: When the channel layer is formed, a first end and a second end are also formed, the first end and the second end are arranged side by side and on opposite sides of the channel layer, the first end and the second end are both made of a first oxide semiconductor material, and when the crystallized layer is made of a crystallized second oxide semiconductor material, a spacing structure is formed on the channel layer, and openings are formed on the first end and the second end, and the openings expose the first end and the second end; forming an amorphized second oxide semiconductor layer on the substrate having the spacer structure and the opening, and processing the amorphized second oxide semiconductor layer to crystallize the amorphized second oxide semiconductor layer in contact with the first end and the second end, and to keep the second oxide semiconductor layer not in contact with the first end and the second end amorphized; The amorphous portion of the second oxide semiconductor layer is etched so that: the crystallized second oxide semiconductor layer located above the first end and the crystallized portion in the first end form a crystallized layer in the source end, the crystallized layer in the source end and the amorphous portion in the first end form the source end, and the crystallized second oxide semiconductor layer located above the second end and the crystallized portion in the second end form a crystallized layer in the drain end, the crystallized layer in the drain end and the amorphous portion in the second end form the drain end.
11. The method according to claim 10, characterized in that: Also includes: Before processing the amorphized second oxide semiconductor layer and after forming the amorphized second oxide semiconductor layer, a crystallization-inducing layer is formed over the amorphized second oxide semiconductor layer.
12. The method according to claim 11, characterized in that: Also includes: Before forming the inducing crystallization layer, it is determined that the crystallization temperature of the amorphized second oxide semiconductor layer exceeds a preset temperature range.
13. The production method according to any one of claims 10 to 12, characterized in that: Also includes: Before processing the substrate on which the amorphized second oxide semiconductor layer is formed, it is determined that a crystallization temperature of the amorphized second oxide semiconductor layer does not exceed a preset temperature range.
14. An electronic device, characterized in that: include: A circuit board and a transistor as claimed in any one of claims 1 to 8, wherein the transistor is arranged on the circuit board.