Low-side driving overvoltage protection circuit and electronic equipment

Abstract

The invention provides a low-side driving overvoltage protection circuit and electronic equipment, and a voltage sampling module in the circuit carries out the first processing of the voltage of the first end of a low-side driving power tube through a high voltage, outputs a first sampling voltage, carries out the second processing of the voltage of the second end of the low-side driving power tube, and outputs a second sampling voltage. The wide common-ground input range is guaranteed, the comparison module is located in the voltage domain where the suspension voltage is located, the first sampling voltage and the second sampling voltage are compared through high-voltage bias current, a first comparison signal is output, and the comparison accuracy is guaranteed; and the level conversion module is used for converting the first comparison signal into a second voltage domain from a voltage domain where the suspension voltage is located, and outputting a second comparison signal, so that a subsequent logic module can simply control the on-off of the low-side driving power tube based on the second comparison signal. Therefore, the low-side driving overvoltage protection circuit provided by the invention is wide in common-ground input range and simple in structure.

Description

Technical Field

[0001] The present invention relates to the technical field of power electronics, and in particular to a low-side drive overvoltage protection circuit and electronic equipment. Background Art

[0002] The low-side drive overvoltage protection circuit is widely used in the drive circuit, so that the circuit can immediately shut down the low-side drive power tube when overvoltage occurs, so as to avoid the low-side drive power tube from burning out.

[0003] At present, the commonly used method of the low-side drive overvoltage protection circuit is: sampling the voltage difference between the two ends of the low-side drive power tube, when the sampled voltage is greater than the first reference voltage, the PWM control chip prohibits the output of pulses to the low-side drive power tube, and when the sampled voltage drops to the second reference voltage, the control chip allows the output of pulses to the low-side drive power tube. The first reference voltage is greater than the second reference voltage.

[0004] However, this method can only handle a narrow common ground voltage range and has poor anti-interference ability to the ground. In the case of large fluctuations in the power ground, an erroneous sampling voltage may be output.

[0005] Therefore, how to make the low-side drive overvoltage protection circuit have a wide common ground input range while keeping the structure simple has become a technical problem that urgently needs to be solved in the industry. Summary of the invention

[0006] The technical problem solved by the present invention is to provide a low-side drive overvoltage protection circuit and an electronic device, which solves the problem of how to make the low-side drive overvoltage protection circuit have a wide common ground input range while keeping the structure simple.

[0007] To solve the above technical problems, according to a first aspect of the present invention, an embodiment of the present invention provides a low-side drive overvoltage protection circuit, comprising:

[0008] A low-side driving power tube, a first end of which receives a first voltage and a second end of which is coupled to a power ground;

[0009] A voltage sampling module, wherein a first input terminal and a second input terminal are respectively coupled to the first terminal and the second terminal of the low-side driving power tube, and a third input terminal receives a high voltage. The voltage sampling module is used to perform a first process on the voltage of the first terminal of the low-side driving power tube using the high voltage to output a first sampled voltage, and to perform a second process on the voltage of the second terminal of the low-side driving power tube to output a second sampled voltage, wherein the first process includes a sampling process, and the second process includes a sampling process and a voltage adjustment process, and the second sampled voltage corresponds to an overvoltage threshold voltage of the first voltage;

[0010] A comparison module, wherein the first end receives a suspension voltage, the second end receives a high-voltage bias current, the first input end receives the first sampling voltage, and the second input end receives the second sampling voltage, the voltage value of the suspension voltage is higher than the voltage value of the power ground, and the difference between the voltage value of the suspension voltage and the voltage value of the power ground is a set voltage value, and the comparison module is used to compare the first sampling voltage and the second sampling voltage using the high-voltage bias current, and output a first comparison signal;

[0011] a level conversion module, configured to perform level conversion processing on the first comparison signal, so as to convert the first comparison signal from a voltage domain where the floating voltage is located to a second voltage domain, and output a second comparison signal;

[0012] A logic module is used to control the on and off of the low-side driving power tube based on the second comparison signal.

[0013] Optionally, the voltage sampling module includes:

[0014] A first sampling unit includes a first cascode current mirror, a first NMOS transistor, a first current source, a second NMOS transistor and a first resistor;

[0015] The first input terminal of the first cascode current mirror receives the high voltage, the first output terminal thereof is coupled to the drain of the first NMOS tube, the gate of the first NMOS tube receives an enable signal, the source of the first NMOS tube is coupled to the first terminal of the first current source, the second terminal of the first current source is connected to the signal ground, the second output terminal of the first cascode current mirror is coupled to the drain of the second NMOS tube, the gate of the second NMOS tube receives the floating voltage, the source of the second NMOS tube is coupled to the first terminal of the low-side driving power tube through the first resistor, and the second output terminal of the first cascode current mirror is also used to output the first sampling voltage;

[0016] The second sampling unit includes a second cascode current mirror, a third NMOS transistor, a second current source, a fourth NMOS transistor and a second resistor;

[0017] The first input terminal of the second cascode current mirror receives the high voltage, the first output terminal thereof is coupled to the drain of the third NMOS tube, the gate of the third NMOS tube receives the enable signal, the source of the third NMOS tube is coupled to the first terminal of the second current source, the second terminal of the second current source is connected to the signal ground, the second output terminal of the second cascode current mirror is coupled to the drain of the fourth NMOS tube, the gate of the fourth NMOS tube receives the floating voltage, the source of the fourth NMOS tube is coupled to the second terminal of the low-side drive power tube through the second resistor, and the second output terminal of the second cascode current mirror is also used to output the second sampling voltage;

[0018] The current value of the current provided by the second current source is greater than the current value of the current provided by the first current source.

[0019] Optionally, the second current source includes a first sub-current source and a second sub-current source;

[0020] The first end of the first sub-current source and the first end of the second sub-current source are both coupled to the source of the third NMOS tube, the second end of the first sub-current source and the second end of the second sub-current source are both connected to the signal ground, and the current value of the current provided by the first sub-current source is equal to the current value of the current provided by the first current source.

[0021] Optionally, the voltage sampling module further includes a threshold voltage adjustment unit;

[0022] The threshold voltage adjustment unit is coupled to the control terminal of the second sub-current source and is used to control the current value output by the second sub-current source.

[0023] Optionally, the first process further includes a clamping process, and the first sampling unit further includes a fifth NMOS tube;

[0024] The drain of the fifth NMOS tube is coupled to the second output terminal of the first cascode current mirror, the gate of the fifth NMOS tube is coupled to the source of the fifth NMOS tube, and the source of the fifth NMOS tube is connected to the power ground.

[0025] Optionally, the comparison module includes:

[0026] A high-voltage bias isolation unit, used to output a high-voltage bias current using the high-voltage voltage, comprising a third cascode current mirror, a sixth NMOS tube and a third current source;

[0027] The first input terminal of the third cascode current mirror receives the high voltage, the first output terminal of the third cascode current mirror is coupled to the drain of the third NMOS tube, the gate of the third NMOS tube receives the enable signal, the source of the third NMOS tube is coupled to the first terminal of the third current source, the second terminal of the third current source is connected to the signal ground, and the second output terminal of the third cascode current mirror outputs the high voltage bias current;

[0028] A comparison unit, including a current mirror unit and an open-loop comparator;

[0029] The input end of the current mirror unit receives the high voltage bias current, the output end thereof is coupled to the first end of the open loop comparator, the ground end of the current mirror unit is connected to the power ground, and the power supply end of the current mirror unit is connected to the floating voltage;

[0030] The power supply terminal of the open-loop comparator is connected to the floating voltage, the first input terminal thereof receives the first sampling voltage, the second input terminal thereof receives the second sampling voltage, the ground terminal thereof is connected to the power ground, and the output terminal thereof outputs the first comparison signal.

[0031] Optionally, the current mirror unit includes a seventh NMOS tube, an eighth NMOS tube and a ninth PMOS tube;

[0032] The drain of the seventh NMOS tube receives the high-voltage bias current, the gate of the seventh NMOS tube is respectively coupled to the drain of the seventh NMOS tube and the gate of the eighth NMOS tube, the source of the seventh NMOS tube and the source of the eighth NMOS tube are both connected to the power ground, the drain of the eighth NMOS tube is respectively coupled to the drain and the gate of the ninth PMOS tube, and the source of the ninth PMOS tube is connected to the floating voltage.

[0033] Optionally, the open-loop comparator includes a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube, a sixteenth NMOS tube and an inverter;

[0034] The source of the tenth PMOS tube is connected to the floating voltage, and the gate thereof is coupled to the gate of the ninth PMOS tube. The drain of the tenth PMOS tube is respectively coupled to the source of the twelfth PMOS tube and the source of the thirteenth PMOS tube. The gate of the twelfth PMOS tube receives the first sampling voltage. The drain of the twelfth PMOS tube is respectively coupled to the drain and the gate of the fourteenth NMOS tube. The source of the fourteenth NMOS tube is connected to the power ground. The gate of the thirteenth PMOS tube receives the second sampling voltage. The drain of the thirteenth PMOS tube is connected to the drain of the fifteenth NMOS tube. The gate of the fifteenth NMOS tube is coupled to the gate of the fourteenth NMOS tube. The source of the fifteenth NMOS tube is connected to the power ground.

[0035] The source of the eleventh PMOS tube is connected to the floating voltage, the gate thereof is coupled to the gate of the ninth PMOS tube, the drain of the eleventh PMOS tube is respectively coupled to the input end of the inverter and the drain of the sixteenth NMOS tube, the gate of the sixteenth NMOS tube is coupled to the drain of the fifteenth NMOS tube, the source of the sixteenth NMOS tube is connected to the power ground, the power supply end of the inverter receives the floating voltage, the ground end thereof is connected to the power ground, and the output end thereof outputs the first comparison signal.

[0036] Optionally, the comparison module further includes a limiting unit, including a seventeenth PMOS tube, an eighteenth PMOS tube and a third resistor;

[0037] The source of the seventeenth PMOS tube is connected to the floating voltage, the gate of the seventeenth PMOS tube is coupled to the gate of the ninth PMOS tube, the drain of the seventeenth PMOS tube is connected to the power ground through the third resistor, the source of the eighteenth PMOS tube is coupled to the gate of the twelfth PMOS tube, the gate of the eighteenth PMOS tube is coupled to the drain of the seventeenth PMOS tube, and the drain of the eighteenth PMOS tube is connected to the power ground.

[0038] Optionally, the second voltage domain includes a second power supply voltage and a second power ground voltage; and the level conversion module includes:

[0039] a signal processing unit, configured to output a first pulse signal and a second pulse signal respectively according to the first comparison signal, wherein the first pulse signal is used to indicate that the first comparison signal is in a first level state, and the second pulse signal is used to indicate that the first comparison signal is in a second level state, and the first pulse signal and the second pulse signal are differential signals;

[0040] a first level conversion unit, wherein a first output end thereof receives the first pulse signal through a first driving unit, a second input end thereof receives the first pulse signal through a first inverter, a power supply end thereof receives the second power supply voltage, and a ground end thereof is connected to the power ground, and is used for performing voltage domain isolation processing and XOR processing on the differential first pulse signal, and outputting a first control signal;

[0041] A second level conversion unit, wherein a first output end thereof receives the second pulse signal through a second driving unit, a second input end thereof receives the second pulse signal through a second inverter, a power supply end thereof receives the second power supply voltage, a ground end thereof is connected to the power ground, a voltage domain isolation process and an XOR process are performed on the differential second pulse signal, and a second control signal is output;

[0042] The latch has a set terminal receiving the first control signal, a reset terminal receiving the second control signal, an output terminal outputting the second comparison signal, a power supply terminal receiving the second power supply voltage, and a ground terminal connected to the second power supply ground voltage.

[0043] Optionally, the first level conversion unit includes a fourth resistor, a fifth resistor, a first capacitor, a second capacitor, a nineteenth NMOS tube, a twentieth NMOS tube, and a first XOR sub-unit; the second level conversion unit includes a sixth resistor, a seventh resistor, a third capacitor, a fourth capacitor, a twenty-first NMOS tube, a twenty-second NMOS tube, and a second XOR sub-unit;

[0044] The first end of the fourth resistor and the first end of the fifth resistor are both connected to the second power supply voltage, the second end of the fourth resistor is coupled to the drain of the nineteenth NMOS tube through the first capacitor, the gate of the nineteenth NMOS tube receives the first pulse signal through the first driving unit, the source of the nineteenth NMOS tube is connected to the power ground, and the second end of the fourth resistor is also coupled to the first input end of the first XOR subunit to output a first output signal;

[0045] The second end of the fifth resistor is coupled to the drain of the 20th NMOS transistor through the second capacitor, the gate of the 20th NMOS transistor receives the first pulse signal through the first inverter and the first driving unit in sequence, the source of the 20th NMOS transistor is connected to the power ground, and the second end of the fifth resistor is also coupled to the second input end of the first XOR subunit to output a second output signal;

[0046] The output end of the first XOR subunit outputs the first control signal;

[0047] The first end of the sixth resistor and the first end of the seventh resistor are both connected to the second power supply voltage, the second end of the sixth resistor is coupled to the drain of the twenty-first NMOS tube through the third capacitor, the gate of the twenty-first NMOS tube receives the second pulse signal through the second driving unit, the source of the twenty-first NMOS tube is connected to the power ground, and the second end of the sixth resistor is also coupled to the first input end of the second XOR subunit to output a third output signal;

[0048] The second end of the seventh resistor is coupled to the drain of the twenty-second NMOS transistor through the fourth capacitor, the gate of the twenty-second NMOS transistor receives the second pulse signal through the second inverter and the second driving unit in sequence, the source of the twenty-second NMOS transistor is connected to the power ground, and the second end of the seventh resistor is also coupled to the second input end of the second XOR subunit to output a fourth output signal;

[0049] The output terminal of the second XOR subunit outputs the second control signal.

[0050] According to a second aspect of the present invention, an electronic device is provided, comprising the low-side drive overvoltage protection circuit provided by any one of the first aspects.

[0051] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0052] In the low-side drive overvoltage protection circuit and electronic device of the technical solution of the present invention, the first end of the low-side drive power tube receives the first voltage, and the second end thereof is coupled to the power ground. The voltage sampling module performs a first process on the voltage of the first end of the low-side drive power tube using the high voltage, outputs the first sampling voltage, and performs a second process on the voltage of the second end of the low-side drive power tube, outputs the second sampling voltage, and ensures a wide common ground input range. The comparison module is located in the voltage domain where the floating voltage is located, and compares the first sampling voltage and the second sampling voltage using the high voltage bias current, and outputs the first comparison signal, ensuring the accuracy of the comparison; the level conversion module is used to convert the first comparison signal from the voltage domain where the floating voltage is located to the second voltage domain, and outputs the second comparison signal, so that the subsequent logic module can simply control the on and off of the low-side drive power tube based on the second comparison signal. Therefore, the common ground input range of the low-side drive overvoltage protection circuit provided by the present invention is wide, and the structure is also relatively simple.

[0053] Furthermore, the first processing also includes a clamping processing, the first sampling unit also includes a fifth NMOS tube, the drain of the fifth NMOS tube is coupled to the second output end of the first common-source common-gate current mirror, the gate of the fifth NMOS tube is coupled to the source of the fifth NMOS tube, and the source of the fifth NMOS tube is connected to the power ground. Therefore, when the present invention is applied to an inductive load, in the case where the first voltage is transiently lower than the power, the fifth NMOS tube can clamp the first sampling voltage through its own parasitic body diode to protect subsequent circuits.

[0054] Furthermore, the voltage sampling module also includes a threshold voltage adjustment unit, which is coupled to the control end of the second sub-current source and is used to control the current value output by the second sub-current source. Therefore, the present invention can also change the overvoltage threshold of the low-side driving power tube as needed.

[0055] Furthermore, the comparison module also includes a limiting unit, including a seventeenth PMOS tube, an eighteenth PMOS tube and a third resistor; the source of the seventeenth PMOS tube is connected to the floating voltage, the gate thereof is coupled to the gate of the ninth PMOS tube, the drain of the seventeenth PMOS tube is connected to the power ground through the third resistor, the source of the eighteenth PMOS tube is coupled to the gate of the twelfth PMOS tube, the gate of the eighteenth PMOS tube is coupled to the drain of the seventeenth PMOS tube, and the drain of the eighteenth PMOS tube is connected to the power ground. Thus, the present invention can also limit the maximum voltage value of the positive terminal of the open-loop comparator to counteract the NBTI phenomenon of the PMOS.

[0056] Furthermore, the level conversion module of the present invention converts the single-ended input into a differential input, and inputs the generated first pulse signal and the second pulse signal into the first level conversion unit and the second level conversion unit respectively. The first level conversion unit performs voltage domain isolation processing and XOR processing on the differential first pulse signal, and outputs a first control signal. The second level conversion unit performs voltage domain isolation processing and XOR processing on the differential second pulse signal, and outputs a second control signal. That is, the common-mode suppression capability of the circuit is improved by using differential input and XOR logic judgment, and the voltage domain conversion of the first comparison signal is completed by receiving the first control signal through the set end of the latch, receiving the second control signal through its reset end, and outputting the second comparison signal through its output end. Therefore, in the level conversion module of the present invention, the common-mode operating range is only limited by the device withstand voltage, and is not affected by the wide range of power ground voltage changes.

[0057] Furthermore, the level conversion module of the present invention performs voltage domain isolation processing through capacitors, and does not use high-voltage devices with huge areas, so the area can be greatly reduced and the speed can be correspondingly improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0059] Figure 1 1 is a schematic diagram of the structure of a low-side drive overvoltage protection circuit provided by an embodiment of the present invention;

[0060] Figure 2 The structure of the voltage sampling module provided by an embodiment of the present invention is shown in FIG. Figure 1 ;

[0061] Figure 3 The structure of the voltage sampling module provided by an embodiment of the present invention is shown in FIG. Figure 2 ;

[0062] Figure 4 is a schematic diagram of the structure of a comparison module provided by an embodiment of the present invention Figure 1 ;

[0063] Figure 5 is a schematic diagram of the structure of a comparison module provided by an embodiment of the present invention Figure 2 ;

[0064] Figure 6 is a schematic diagram of the structure of a level conversion module provided by an embodiment of the present invention;

[0065] Description of reference numerals:

[0066] 10- low side driver power tube;

[0067] 20- voltage sampling module;

[0068] 30-Comparison module;

[0069] 40-level conversion module;

[0070] 50-Logic module;

[0071] 201-a first cascode current mirror;

[0072] 202-a first current source;

[0073] 203-a second cascode current mirror;

[0074] 204- a second current source;

[0075] 2041 - a first sub-current source;

[0076] 2042- a second sub-current source;

[0077] 205-threshold voltage adjustment unit;

[0078] 301- a third cascode current mirror;

[0079] 302- a third current source;

[0080] 303-current mirror unit;

[0081] 304- open loop comparator;

[0082] 401- signal processing unit;

[0083] 4021-first driving unit;

[0084] 4022-first inverter;

[0085] 4023-first XOR subunit;

[0086] 4031- second driving unit;

[0087] 4032 - second inverter;

[0088] 4033 - second XOR subunit;

[0089] 404-Latch;

[0090] Vbus-first voltage;

[0091] PGND-power ground;

[0092] PVDD-suspension voltage;

[0093] VS-high voltage;

[0094] VH-second supply voltage;

[0095] VL-second power supply ground voltage;

[0096] DGND-signal ground;

[0097] EN-enable signal;

[0098] Vbus_sns-first sampling voltage;

[0099] PGND_sns-second sampling voltage;

[0100] INP-first pulse signal;

[0101] INN-second pulse signal;

[0102] SET-first control signal;

[0103] RESET-second control signal;

[0104] OUT1-first comparison signal;

[0105] OUT2 - second comparison signal. DETAILED DESCRIPTION

[0106] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0107] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0108] The technical solution of the present invention is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0109] As described in the background art, it is difficult in the prior art to make the low-side drive overvoltage protection circuit have a wide common ground input range while keeping the structure simple.

[0110] In view of this, the present invention provides a low-side drive overvoltage protection circuit, which receives a first voltage through the first end of the low-side drive power tube, and its second end is coupled to the power ground. The voltage sampling module uses the high voltage to perform a first process on the voltage of the first end of the low-side drive power tube, outputs the first sampling voltage, and performs a second process on the voltage of the second end of the low-side drive power tube, outputs the second sampling voltage, and ensures a wide common ground input range. The comparison module is located in the voltage domain where the floating voltage is located, and uses a high voltage bias current to compare the first sampling voltage and the second sampling voltage, and outputs a first comparison signal, ensuring the accuracy of the comparison; the level conversion module is used to convert the first comparison signal from the voltage domain where the floating voltage is located to the second voltage domain, and outputs the second comparison signal, so that the subsequent logic module can simply control the on and off of the low-side drive power tube based on the second comparison signal. Therefore, the common ground input range of the low-side drive overvoltage protection circuit provided by the present invention is wide, and the structure is also relatively simple.

[0111] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0112] Please refer to Figure 1 The present invention proposes a low-side drive overvoltage protection circuit, comprising:

[0113] The low-side driving power tube 10 has a first terminal receiving a first voltage Vbus and a second terminal coupled to a power ground PGND;

[0114] A voltage sampling module 20, wherein the first input terminal and the second input terminal are respectively coupled to the first terminal and the second terminal of the low-side driving power tube 10, and the third input terminal receives the high voltage voltage VS. The voltage sampling module 20 is used to perform a first process on the voltage of the first terminal of the low-side driving power tube 10 using the high voltage voltage VS, and output a first sampled voltage, and to perform a second process on the voltage of the second terminal of the low-side driving power tube 10, and output a second sampled voltage, wherein the first process includes a sampling process, and the second process includes a sampling process and a voltage adjustment process, and the second sampled voltage corresponds to an overvoltage threshold voltage of the first voltage Vbus;

[0115] A comparison module 30, wherein the first end receives a floating voltage PVDD, the second end receives a high-voltage bias current, the first input end receives the first sampling voltage, and the second input end receives the second sampling voltage, the voltage value of the floating voltage PVDD is higher than the voltage value of the power ground PGND, and the difference between the voltage value of the floating voltage PVDD and the voltage value of the power ground PGND is a set voltage value, and the comparison module 30 is used to compare the first sampling voltage and the second sampling voltage using the high-voltage bias current, and output a first comparison signal;

[0116] The level conversion module 40 is used to perform level conversion processing on the first comparison signal to convert the first comparison signal from the voltage domain where the floating voltage PVDD is located to the second voltage domain, and output a second comparison signal;

[0117] The logic module 50 is used to control the on / off of the low-side driving power tube 10 based on the second comparison signal.

[0118] exist Figure 1 In the example, the logic module 50 controls the on and off of the low-side driving power tube 10 by outputting a gate control signal Vg.

[0119] The voltage sampling module 20 of the present invention ensures a wide common ground input range by sampling the voltage of the first end and the voltage of the second end of the low-side driving power tube 10. The comparison module 30 compares the first sampling voltage and the second sampling voltage using a high-voltage bias current, outputs a first comparison signal, and ensures the accuracy of the comparison; the level conversion module 40 converts the first comparison signal from the voltage domain where the floating voltage PVDD is located to the second voltage domain, so that when the drain-source overvoltage of the low-side driving power tube 10 occurs, the logic module 50 can accurately control the low-side driving power tube 10 to shut down. It can be seen that the circuit provided by the embodiment of the present invention not only has a simple structure, but also can effectively suppress the common-mode interference of the driving ground voltage.

[0120] In one implementation, please refer to Figure 2 , the voltage sampling module 20 includes:

[0121] The first sampling unit includes a first cascode current mirror 201, a first NMOS transistor MN1, a first current source 202, a second NMOS transistor MN2 and a first resistor R1;

[0122] The first input terminal of the first cascode current mirror 201 receives the high voltage VS, the first output terminal thereof is coupled to the drain of the first NMOS transistor MN1, the gate of the first NMOS transistor MN1 receives the enable signal EN, the source of the first NMOS transistor MN1 is coupled to the first terminal of the first current source 202, the second terminal of the first current source 202 is connected to the signal ground DGND, the second output terminal of the first cascode current mirror 201 is coupled to the drain of the second NMOS transistor MN2, the gate of the second NMOS transistor MN2 receives the floating voltage PVDD, the source of the second NMOS transistor MN2 is coupled to the first terminal of the low-side driving power transistor 10 through the first resistor R1, and the second output terminal of the first cascode current mirror 201 is also used to output the first sampling voltage Vbus_sns;

[0123] The second sampling unit includes a second cascode current mirror 203, a third NMOS transistor MN3, a second current source 204, a fourth NMOS transistor MN4 and a second resistor R2;

[0124] The first input terminal of the second cascode current mirror 203 receives the high voltage VS, the first output terminal of the second cascode current mirror 203 is coupled to the drain of the third NMOS transistor MN3, the gate of the third NMOS transistor MN3 receives the enable signal EN, the source of the third NMOS transistor MN3 is coupled to the first terminal of the second current source 204, the second terminal of the second current source 204 is connected to the signal ground DGND, the second output terminal of the second cascode current mirror 203 is coupled to the drain of the fourth NMOS transistor MN4, the gate of the fourth NMOS transistor MN4 receives the floating voltage PVDD, the source of the fourth NMOS transistor MN4 is coupled to the second terminal of the low-side driving power transistor 10 through the second resistor R2, and the second output terminal of the second cascode current mirror 203 is also used to output the second sampling voltage PGND_sns;

[0125] The current value of the current Ifref2 provided by the second current source 204 is greater than the current value of the current Ifref1 provided by the first current source 202 .

[0126] In the embodiment of the present invention, the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, and the fourth NMOS transistor MN4 are all high-voltage LDMOS devices;

[0127] The signal ground can be understood as 0V.

[0128] exist Figure 2 In the example, the first cascode current mirror 201 includes a first power tube M1, a second power tube M2, a third power tube M3 and a fourth power tube M4;

[0129] The first end of the first power tube M1 receives the high voltage VS, and the second end thereof is respectively coupled to the first end of the third power tube M3 and the control end of the first power tube M1, and the second end of the third power tube M3 is respectively coupled to the drain of the first NMOS tube MN1 and the control end of the third power tube M3;

[0130] The first end of the second power tube M2 receives the high voltage VS, the second end thereof is coupled to the first end of the fourth power tube M4, the control end thereof is coupled to the control end of the first power tube M1, the second end of the fourth power tube M4 is coupled to the drain of the second NMOS tube MN2, and the control end thereof is coupled to the control end of the third power tube M3.

[0131] The first power tube M1 , the second power tube M2 , the third power tube M3 , and the fourth power tube M4 are all PMOS tubes.

[0132] The second cascode current mirror 203 includes a fifth power tube M5, a sixth power tube M6, a seventh power tube M7 and an eighth power tube M8;

[0133] The first end of the fifth power tube M5 receives the high voltage VS, and the second end thereof is respectively coupled to the first end of the seventh power tube M7 and the control end of the fifth power tube M5, and the second end of the seventh power tube M7 is respectively coupled to the drain of the third NMOS tube MN3 and the control end of the seventh power tube M7;

[0134] The first end of the sixth power tube M6 receives the high voltage VS, the second end thereof is coupled to the first end of the eighth power tube M8, the control end thereof is coupled to the control end of the sixth power tube M6, the second end of the eighth power tube M8 is coupled to the drain of the fourth NMOS tube MN4, and the control end thereof is coupled to the control end of the sixth power tube M6.

[0135] The fifth power tube M5, the sixth power tube M6, the seventh power tube M7 and the eighth power tube M8 are all PMOS tubes.

[0136] In one implementation, the fourth power tube M4 and the eighth power tube M8 are both high-voltage LDMOS devices.

[0137] Now combined Figure 2 The example shown further illustrates the working principle of the voltage sampling module 20:

[0138] The second sampling voltage PGND_sns in the embodiment of the present invention can be understood as the overvoltage threshold of the low-side driving power tube 10 .

[0139] In an embodiment of the present invention, the first resistor R1 and the second resistor R2 have the same resistance value and shape. Furthermore, in this case, in the first sampling unit, the voltage Vbus at the first end of the low-side driving power tube 10 is sampled through the first resistor R1 and the first current source 202, and the obtained first sampling voltage Vbus_sns=Vbus+Iref1×R1;

[0140] Wherein, Iref1 is the current value of the current provided by the first current source 202 .

[0141] In the second sampling unit, the voltage of the second end of the low-side driving power tube 10 (ie, the power ground PGND) is sampled and processed through the second resistor R2 and the second current source 204, and the obtained second sampling voltage PGND_sns=PGND+IrefR2;

[0142] Wherein, Iref2 is the current value of the current provided by the second current source 204 .

[0143] In order to conveniently change the overvoltage threshold of the low-side driving power tube 10, in a preferred embodiment, please refer to Figure 2 , the second current source 204 includes a first sub-current source 2041 and a second sub-current source 2042;

[0144] The first end of the first sub-current source 2041 and the first end of the second sub-current source 2042 are both coupled to the source of the third NMOS tube MN3, the second end of the first sub-current source 2041 and the second end of the second sub-current source 2042 are both connected to the signal ground DGND, and the current value of the current provided by the first sub-current source 2041 is equal to the current value of the current provided by the first current source 202.

[0145] In this case, in the second sampling unit, the voltage of the second end of the low-side driving power tube 10 (ie, the power ground PGND) is sampled and processed through the second resistor R2 and the second current source 204 (Iref2+Idac);

[0146] The obtained second sampling voltage PGND_sns=PGND+(Iref2+Idac)R2;

[0147] Wherein, Iref2 is the current value of the current provided by the second sub-current source 2042 .

[0148] In practical applications, please refer to Figure 3 , the voltage sampling module 20 further includes a threshold voltage adjustment unit 205;

[0149] The threshold voltage adjustment unit 205 is coupled to the control terminal of the second sub-current source 2042 and is used to control the current value output by the second sub-current source 2042 .

[0150] Therefore, the present invention can also change the overvoltage threshold of the low-side driving power tube 10 as needed.

[0151] In a specific implementation manner, the present invention can control the magnitude of the current Idac of the second sub-current source 2042 by digital bits to change the overvoltage threshold of the low-side driving power tube 10 .

[0152] Theoretically, in the circuit provided by the present invention, the maximum input voltage of the power ground PGND can reach VS-2Vod-(Iref2+Idac)R2.

[0153] Wherein, Vod is the over-driving voltage of the sixth power tube M6 and the eighth power tube M8. In actual implementation, the minimum input voltage of the power ground PGND also depends in part on the design of the process and layout, which will not be elaborated in the present invention.

[0154] When the low-side driving power tube 10 is used in an inductive load application, the voltage Vbus at the first end of the low-side driving power tube 10 may be transiently lower than the voltage of the power ground PGND by a large margin. Therefore, in a preferred embodiment, please refer to Figure 3 , the first process further includes a clamping process, and the first sampling unit further includes a fifth NMOS tube MN5;

[0155] The drain of the fifth NMOS transistor MN5 is coupled to the second output terminal of the first cascode current mirror 201 , the gate of the fifth NMOS transistor MN5 is coupled to the source of the fifth NMOS transistor MN5 , and the source of the fifth NMOS transistor MN5 is connected to the power ground PGND.

[0156] It can be seen that when the present invention is applied to an inductive load, when the first voltage Vbus is transiently lower than the power, the fifth NMOS tube MN5 can clamp the voltage of the first end of the low-side driving power tube 10 through its own parasitic body diode to protect subsequent circuits.

[0157] Regarding the comparison module 30, in one implementation, please refer to Figure 4 , the comparison module 30 comprises:

[0158] A high-voltage bias isolation unit, used to output a high-voltage bias current using the high-voltage voltage VS, comprising a third cascode current mirror 301, a sixth NMOS transistor MN6 and a third current source 302;

[0159] The first input terminal of the third cascode current mirror 301 receives the high voltage VS, the first output terminal thereof is coupled to the drain of the third NMOS transistor MN3, the gate of the third NMOS transistor MN3 receives the enable signal EN, the source of the third NMOS transistor MN3 is coupled to the first terminal of the third current source 302, the second terminal of the third current source 302 is connected to the signal ground DGND, and the second output terminal of the third cascode current mirror 301 outputs the high voltage bias current;

[0160] A comparison unit, comprising a current mirror unit 303 and an open-loop comparator 304;

[0161] The input end of the current mirror unit 303 receives the high voltage bias current, and the output end thereof is coupled to the first end of the open loop comparator 304, the ground end of the current mirror unit 303 is connected to the power ground PGND, and the power supply end of the current mirror unit 303 is connected to the floating voltage PVDD;

[0162] The open-loop comparator 304 has a power supply terminal connected to the floating voltage PVDD, a first input terminal receiving the first sampling voltage Vbus_sns, a second input terminal receiving the second sampling voltage PGND_sns, a ground terminal connected to the power ground PGND, and an output terminal outputting the first comparison signal OUT1.

[0163] For a specific implementation, please refer to Figure 5 , the third cascode current mirror 301 includes a ninth power tube M9, a tenth power tube M10, an eleventh power tube M11 and a twelfth power tube M12;

[0164] The first end of the ninth power tube M9 receives the high voltage VS, and the second end thereof is respectively coupled to the first end of the eleventh power tube M11 and the control end of the ninth power tube M9, and the second end of the eleventh power tube M11 is respectively coupled to the drain of the sixth NMOS tube MN6 and the control end of the eleventh power tube M11;

[0165] The first end of the tenth power tube M10 receives the high voltage VS, the second end of the tenth power tube M10 is coupled to the first end of the twelfth power tube M12, the control end of the tenth power tube M10 is coupled to the control end of the ninth power tube M9, the second end of the twelfth power tube M12 is coupled to the input end of the current mirror unit 303, and the control end of the twelfth power tube M11 is coupled to the control end.

[0166] The ninth power tube M9 , the tenth power tube M10 , the eleventh power tube M11 , and the twelfth power tube M12 are all PMOS tubes.

[0167] In the case where the high voltage bias isolation unit receives the high voltage VS, in one implementation, the sixth NMOS transistor MN6 and the twelfth power transistor M12 are both high voltage LDMOS devices, thereby isolating the high voltage domain from the low voltage domain.

[0168] For a specific implementation, please refer to Figure 5 , the current mirror unit 303 includes a seventh NMOS tube MN7, an eighth NMOS tube MN8 and a ninth PMOS tube MP9;

[0169] The drain of the seventh NMOS tube MN7 receives the high-voltage bias current, the gate of the seventh NMOS tube MN7 is respectively coupled to the drain of the seventh NMOS tube MN7 and the gate of the eighth NMOS tube MN8, the source of the seventh NMOS tube MN7 and the source of the eighth NMOS tube MN8 are both connected to the power ground PGND, the drain of the eighth NMOS tube MN8 is respectively coupled to the drain and the gate of the ninth PMOS tube MP9, and the source of the ninth PMOS tube MP9 is connected to the floating voltage PVDD.

[0170] For a specific implementation, please refer to Figure 5 , the open-loop comparator 304 includes a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, a twelfth PMOS transistor MP12, a thirteenth PMOS transistor MP13, a fourteenth NMOS transistor MN14, a fifteenth NMOS transistor MN15, a sixteenth NMOS transistor MN16 and an inverter INV1;

[0171] The source of the tenth PMOS transistor MP10 is connected to the floating voltage PVDD, and the gate thereof is coupled to the gate of the ninth PMOS transistor MP9. The drain of the tenth PMOS transistor MP10 is respectively coupled to the source of the twelfth PMOS transistor MP12 and the source of the thirteenth PMOS transistor MP13. The gate of the twelfth PMOS transistor MP12 receives the first sampling voltage Vbus_sns. The drain of the twelfth PMOS transistor MP12 is respectively coupled to the drain and the gate of the fourteenth NMOS transistor MN14. The source of the fourteenth NMOS transistor MN14 is connected to the power ground PGND. The gate of the thirteenth PMOS transistor MP13 receives the second sampling voltage PGND_sns. The drain of the thirteenth PMOS transistor MP13 is connected to the drain of the fifteenth NMOS transistor MN15. The gate of the fifteenth NMOS transistor MN15 is coupled to the gate of the fourteenth NMOS transistor MN14. The source of the fifteenth NMOS transistor MN15 is connected to the power ground PGND.

[0172] The source of the eleventh PMOS tube MP11 is connected to the floating voltage PVDD, and the gate thereof is coupled to the gate of the ninth PMOS tube MP9. The drain of the eleventh PMOS tube MP11 is respectively coupled to the input end of the inverter INV1 and the drain of the sixteenth NMOS tube MN16. The gate of the sixteenth NMOS tube MN16 is coupled to the drain of the fifteenth NMOS tube MN15. The source of the sixteenth NMOS tube is connected to the power ground PGND. The power supply end of the inverter INV1 receives the floating voltage PVDD, the ground end thereof is connected to the power ground PGND, and the output end thereof outputs the first comparison signal OUT1.

[0173] Since the open-loop comparator 304 is used to detect the voltage of the low-side driving power tube 10, Figure 5 In the example, a PMOS tube is used as the input pair tube. Since the PMOS tube has NBTI phenomenon, in a preferred implementation, please refer to Figure 5 , the comparison module 30 further includes a limiting unit, including a seventeenth PMOS tube MP17, an eighteenth PMOS tube MP18 and a third resistor R3;

[0174] The source of the seventeenth PMOS tube MP17 is connected to the floating voltage PVDD, the gate of the seventeenth PMOS tube MP17 is coupled to the gate of the ninth PMOS tube MP9, the drain of the seventeenth PMOS tube MP17 is connected to the power ground PGND through the third resistor R3, the source of the eighteenth PMOS tube MP18 is coupled to the gate of the twelfth PMOS tube MP12, the gate of the eighteenth PMOS tube MP18 is coupled to the drain of the seventeenth PMOS tube MP17, and the drain of the eighteenth PMOS tube MP18 is connected to the power ground PGND.

[0175] The limiting unit mentioned above can limit the maximum voltage value of the non-inverting input terminal of the open-loop comparator 304 to resist the NBTI phenomenon of the PMOS tube.

[0176] In summary, Figure 5 In the comparison module 30 of the example, M9-M12, MN7, MN8, MP9, and MP17 form three pairs of current mirrors, and MP10-MN16 form a seven-tube open-loop comparator 304, and the output is obtained through the inverter INV1. It can be seen that in theory, in the comparison module 30 provided by the present invention, the maximum voltage value of the power ground PGND can reach VS-2Vod-Vgs7;

[0177] Wherein, Vod is the over-driving voltage of M10 and M12, and Vgs7 is the gate-source voltage of the seventh NMOS transistor MN7.

[0178] In practical applications, the minimum input voltage of the power ground PGND of the comparison module 30 provided by the present invention and the minimum input voltage of the power ground PGND of the voltage sampling module 20 described above can be set to be the same.

[0179] The level conversion module 40 is now further described:

[0180] In one implementation, the second voltage domain includes a second power supply voltage VH and a second power ground voltage VL;

[0181] In this case, please refer to Figure 6 , the level conversion module 40 includes:

[0182] The signal processing unit 401 is used to output a first pulse signal INP and a second pulse signal INN according to the first comparison signal OUT1, wherein the first pulse signal INP is used to indicate that the first comparison signal OUT1 is in a first level state, and the second pulse signal INN is used to indicate that the first comparison signal OUT1 is in a second level state, and the first pulse signal INP and the second pulse signal INN are differential signals;

[0183] a first level conversion unit, wherein a first output end thereof receives the first pulse signal INP through a first driving unit 4021, a second input end thereof receives the first pulse signal INP through a first inverter 4022, a power supply end thereof receives the second power supply voltage VH, and a ground end thereof is connected to the power ground PGND, and is used for performing voltage domain isolation processing and exclusive OR processing (i.e., XOR processing) on ​​the differential first pulse signal INP, and outputting a first control signal SET;

[0184] a second level conversion unit, wherein a first output end thereof receives the second pulse signal INN through a second driving unit 4031, a second input end thereof receives the second pulse signal INN through a second inverter 4032, a power supply end thereof receives the second power supply voltage VH, a ground end thereof is connected to the power ground PGND, a voltage domain isolation process and an exclusive OR process (i.e., an XOR process) are performed on the differential second pulse signal INN, and a second control signal RESET is output;

[0185] The latch 404 has a set terminal receiving the first control signal SET, a reset terminal receiving the second control signal RESET, an output terminal outputting the second comparison signal OUT2, a power supply terminal receiving the second power supply voltage VH, and a ground terminal connected to the second power ground voltage VL.

[0186] It can be seen that the level conversion module 40 of the present invention converts the single-ended input into a differential input, and inputs the generated first pulse signal INP and the second pulse signal INN into the first level conversion unit and the second level conversion unit respectively. The first level conversion unit performs voltage domain isolation processing and XOR processing on the differential first pulse signal INP, and outputs the first control signal SET. The second level conversion unit performs voltage domain isolation processing and XOR processing on the differential second pulse signal INN, and outputs the second control signal RESET, that is, the differential input and XOR logic judgment are used to improve the common mode suppression capability of the circuit, and the voltage domain conversion of the first comparison signal OUT1 is completed by receiving the first control signal SET at the set end of the latch 404, receiving the second control signal RESET at the reset end, and outputting the second comparison signal OUT2 at the output end. Therefore, in the level conversion module 40 of the present invention, the common mode operating range is only limited by the device withstand voltage, and is not affected by the wide range change of the power ground PGND voltage.

[0187] In one implementation, the second power supply voltage VH and the second power ground voltage VL correspond to a signal high level (DVDD) and a signal ground DGND, respectively. For example, the signal high level may be 5V, and the signal ground DGND may be 0V.

[0188] For example, please refer to the signal processing unit 401. Figure 6 The input end of the signal processing unit 401 receives the first comparison signal OUT1, and uses a driver to output the first pulse signal INP, and uses an inverter to output the second pulse signal INN.

[0189] In a specific implementation, please refer to Figure 6 , the first level conversion unit includes a fourth resistor R4, a fifth resistor R5, a first capacitor C1, a second capacitor C2, a nineteenth NMOS transistor MN19, a twentieth NMOS transistor MN20, and a first XOR subunit 4023; the second level conversion unit includes a sixth resistor R6, a seventh resistor R7, a third capacitor C3, a fourth capacitor C4, a twenty-first NMOS transistor MN21, a twenty-second NMOS transistor MN22, and a second XOR subunit 4033;

[0190] The first end of the fourth resistor R4 and the first end of the fifth resistor R5 are both connected to the second power supply voltage VH, the second end of the fourth resistor R4 is coupled to the drain of the nineteenth NMOS transistor MN19 through the first capacitor C1, the gate of the nineteenth NMOS transistor receives the first pulse signal INP through the first driving unit 4021, the source of the nineteenth NMOS transistor is connected to the second power supply ground voltage VL, and the second end of the fourth resistor R4 is also coupled to the first input end of the first XOR subunit 4023 to output a first output signal;

[0191] The second end of the fifth resistor R5 is coupled to the drain of the 20th NMOS transistor MN20 through the second capacitor C2, the gate of the 20th NMOS transistor receives the first pulse signal INP through the first inverter INV1 and the first driving unit 4021 in sequence, the source of the 20th NMOS transistor is connected to the second power supply ground voltage VL, and the second end of the fifth resistor R5 is also coupled to the second input end of the first XOR subunit 4023 to output a second output signal;

[0192] The output end of the first XOR subunit 4023 outputs the first control signal SET;

[0193] The first end of the sixth resistor R6 and the first end of the seventh resistor R7 are both connected to the second power supply voltage VH, the second end of the sixth resistor R6 is coupled to the drain of the twenty-first NMOS transistor MN21 through the third capacitor C3, the gate of the twenty-first NMOS transistor receives the second pulse signal INN through the second driving unit 4031, the source of the twenty-first NMOS transistor is connected to the second power ground voltage VL, and the second end of the sixth resistor R6 is also coupled to the first input end of the second XOR subunit 4033 to output a third output signal;

[0194] The second end of the seventh resistor R7 is coupled to the drain of the twenty-second NMOS transistor MN22 through the fourth capacitor C4, the gate of the twenty-second NMOS transistor receives the second pulse signal INN through the second inverter INV1 and the second driving unit 4031 in sequence, the source of the twenty-second NMOS transistor is connected to the second power ground voltage VL, and the second end of the seventh resistor R7 is also coupled to the second input end of the second XOR subunit 4033 to output a fourth output signal;

[0195] The output terminal of the second XOR sub-unit 4033 outputs the second control signal RESET.

[0196] exist Figure 6In the example, the power supply ends of the first XOR subunit 4023 and the second XOR subunit 4033 both receive the second power supply voltage VH, and the ground ends thereof are both connected to the second power ground voltage VL.

[0197] exist Figure 6 In the example, the static bias points of the inputs A1, B1, A2, and B2 of the first XOR subunit 4023 and the second XOR subunit 4033 in the output voltage domain of the present invention are high. The level conversion module 40 performs voltage domain isolation processing through capacitors, and the common mode operating range is only limited by the device withstand voltage, so it is not affected by the wide range of changes in the power ground PGND voltage. In addition, Figure 6 The exemplary level conversion circuit does not use a high-voltage device with a huge area, so the area can be greatly reduced and the speed can be correspondingly improved.

[0198] In summary, the low-side drive overvoltage protection circuit provided by the present invention has a wider common ground input range and a simpler structure.

[0199] In addition, the present invention also provides an electronic device, including the above-mentioned low-side drive overvoltage protection circuit. As an example, the device can be a power supply, etc., and the present invention is not limited to this, and can also be other power devices that require overvoltage protection.

[0200] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A low-side drive overvoltage protection circuit, It is characterized in that include: A low-side driving power tube, a first end of which receives a first voltage and a second end of which is coupled to a power ground; A voltage sampling module, wherein a first input terminal and a second input terminal are respectively coupled to the first terminal and the second terminal of the low-side driving power tube, and a third input terminal receives a high voltage. The voltage sampling module is used to perform a first process on the voltage of the first terminal of the low-side driving power tube using the high voltage to output a first sampled voltage, and to perform a second process on the voltage of the second terminal of the low-side driving power tube to output a second sampled voltage, wherein the first process includes a sampling process, and the second process includes a sampling process and a voltage adjustment process, and the second sampled voltage corresponds to an overvoltage threshold voltage of the first voltage; A comparison module, wherein the first end receives a suspension voltage, the second end receives a high-voltage bias current, the first input end receives the first sampling voltage, and the second input end receives the second sampling voltage, the voltage value of the suspension voltage is higher than the voltage value of the power ground, and the difference between the voltage value of the suspension voltage and the voltage value of the power ground is a set voltage value, and the comparison module is used to compare the first sampling voltage and the second sampling voltage using the high-voltage bias current, and output a first comparison signal; a level conversion module, configured to perform level conversion processing on the first comparison signal, so as to convert the first comparison signal from a voltage domain where the floating voltage is located to a second voltage domain, and output a second comparison signal; A logic module is used to control the on and off of the low-side driving power tube based on the second comparison signal.

2. The low-side drive overvoltage protection circuit according to claim 1, It is characterized in that The voltage sampling module comprises: The first sampling unit includes a first cascode current mirror, a first NMOS transistor, a first current source, a second NMOS transistor and a first resistor; The first input terminal of the first cascode current mirror receives the high voltage, the first output terminal thereof is coupled to the drain of the first NMOS tube, the gate of the first NMOS tube receives an enable signal, the source of the first NMOS tube is coupled to the first terminal of the first current source, the second terminal of the first current source is connected to the signal ground, the second output terminal of the first cascode current mirror is coupled to the drain of the second NMOS tube, the gate of the second NMOS tube receives the floating voltage, the source of the second NMOS tube is coupled to the first terminal of the low-side driving power tube through the first resistor, and the second output terminal of the first cascode current mirror is also used to output the first sampling voltage; The second sampling unit includes a second cascode current mirror, a third NMOS transistor, a second current source, a fourth NMOS transistor and a second resistor; The first input terminal of the second cascode current mirror receives the high voltage, the first output terminal thereof is coupled to the drain of the third NMOS tube, the gate of the third NMOS tube receives the enable signal, the source of the third NMOS tube is coupled to the first terminal of the second current source, the second terminal of the second current source is connected to the signal ground, the second output terminal of the second cascode current mirror is coupled to the drain of the fourth NMOS tube, the gate of the fourth NMOS tube receives the floating voltage, the source of the fourth NMOS tube is coupled to the second terminal of the low-side drive power tube through the second resistor, and the second output terminal of the second cascode current mirror is also used to output the second sampling voltage; The current value of the current provided by the second current source is greater than the current value of the current provided by the first current source.

3. The low-side drive overvoltage protection circuit according to claim 2, It is characterized in that The second current source includes a first sub-current source and a second sub-current source; The first end of the first sub-current source and the first end of the second sub-current source are both coupled to the source of the third NMOS tube, the second end of the first sub-current source and the second end of the second sub-current source are both connected to the signal ground, and the current value of the current provided by the first sub-current source is equal to the current value of the current provided by the first current source.

4. The low-side drive overvoltage protection circuit according to claim 3, It is characterized in that The voltage sampling module also includes a threshold voltage adjustment unit; The threshold voltage adjustment unit is coupled to the control terminal of the second sub-current source and is used to control the current value output by the second sub-current source.

5. The low-side drive overvoltage protection circuit according to claim 2, It is characterized in that The first process further includes a clamping process, and the first sampling unit further includes a fifth NMOS tube; The drain of the fifth NMOS tube is coupled to the second output terminal of the first cascode current mirror, the gate of the fifth NMOS tube is coupled to the source of the fifth NMOS tube, and the source of the fifth NMOS tube is connected to the power ground.

6. The low-side drive overvoltage protection circuit according to claim 2, It is characterized in that The comparison module comprises: A high-voltage bias isolation unit, used to output a high-voltage bias current using the high-voltage voltage, comprising a third cascode current mirror, a sixth NMOS tube and a third current source; The first input terminal of the third cascode current mirror receives the high voltage, the first output terminal of the third cascode current mirror is coupled to the drain of the third NMOS tube, the gate of the third NMOS tube receives the enable signal, the source of the third NMOS tube is coupled to the first terminal of the third current source, the second terminal of the third current source is connected to the signal ground, and the second output terminal of the third cascode current mirror outputs the high voltage bias current; A comparison unit, including a current mirror unit and an open-loop comparator; The input end of the current mirror unit receives the high voltage bias current, the output end thereof is coupled to the first end of the open loop comparator, the ground end of the current mirror unit is connected to the power ground, and the power supply end of the current mirror unit is connected to the floating voltage; The power supply terminal of the open-loop comparator is connected to the floating voltage, the first input terminal thereof receives the first sampling voltage, the second input terminal thereof receives the second sampling voltage, the ground terminal thereof is connected to the power ground, and the output terminal thereof outputs the first comparison signal.

7. The low-side drive overvoltage protection circuit according to claim 6, It is characterized in that The current mirror unit includes a seventh NMOS tube, an eighth NMOS tube and a ninth PMOS tube; The drain of the seventh NMOS tube receives the high-voltage bias current, the gate of the seventh NMOS tube is respectively coupled to the drain of the seventh NMOS tube and the gate of the eighth NMOS tube, the source of the seventh NMOS tube and the source of the eighth NMOS tube are both connected to the power ground, the drain of the eighth NMOS tube is respectively coupled to the drain and the gate of the ninth PMOS tube, and the source of the ninth PMOS tube is connected to the floating voltage.

8. The low-side drive overvoltage protection circuit according to claim 7, It is characterized in that The open-loop comparator includes a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube, a sixteenth NMOS tube and an inverter; The source of the tenth PMOS tube is connected to the floating voltage, and the gate thereof is coupled to the gate of the ninth PMOS tube. The drain of the tenth PMOS tube is respectively coupled to the source of the twelfth PMOS tube and the source of the thirteenth PMOS tube. The gate of the twelfth PMOS tube receives the first sampling voltage. The drain of the twelfth PMOS tube is respectively coupled to the drain and the gate of the fourteenth NMOS tube. The source of the fourteenth NMOS tube is connected to the power ground. The gate of the thirteenth PMOS tube receives the second sampling voltage. The drain of the thirteenth PMOS tube is connected to the drain of the fifteenth NMOS tube. The gate of the fifteenth NMOS tube is coupled to the gate of the fourteenth NMOS tube. The source of the fifteenth NMOS tube is connected to the power ground. The source of the eleventh PMOS tube is connected to the floating voltage, the gate thereof is coupled to the gate of the ninth PMOS tube, the drain of the eleventh PMOS tube is respectively coupled to the input end of the inverter and the drain of the sixteenth NMOS tube, the gate of the sixteenth NMOS tube is coupled to the drain of the fifteenth NMOS tube, the source of the sixteenth NMOS tube is connected to the power ground, the power supply end of the inverter receives the floating voltage, the ground end thereof is connected to the power ground, and the output end thereof outputs the first comparison signal.

9. The low-side drive overvoltage protection circuit according to claim 8, It is characterized in that The comparison module further includes a limiting unit, including a seventeenth PMOS tube, an eighteenth PMOS tube and a third resistor; The source of the seventeenth PMOS tube is connected to the floating voltage, the gate of the seventeenth PMOS tube is coupled to the gate of the ninth PMOS tube, the drain of the seventeenth PMOS tube is connected to the power ground through the third resistor, the source of the eighteenth PMOS tube is coupled to the gate of the twelfth PMOS tube, the gate of the eighteenth PMOS tube is coupled to the drain of the seventeenth PMOS tube, and the drain of the eighteenth PMOS tube is connected to the power ground.

10. The low-side drive overvoltage protection circuit according to claim 1, It is characterized in that The second voltage domain includes a second supply voltage and a second power ground voltage; The level conversion module comprises: a signal processing unit, configured to output a first pulse signal and a second pulse signal respectively according to the first comparison signal, wherein the first pulse signal is used to indicate that the first comparison signal is in a first level state, and the second pulse signal is used to indicate that the first comparison signal is in a second level state, and the first pulse signal and the second pulse signal are differential signals; a first level conversion unit, wherein a first output end thereof receives the first pulse signal through a first driving unit, a second input end thereof receives the first pulse signal through a first inverter, a power supply end thereof receives the second power supply voltage, and a ground end thereof is connected to the power ground, and is used for performing voltage domain isolation processing and XOR processing on the differential first pulse signal, and outputting a first control signal; A second level conversion unit, wherein a first output end thereof receives the second pulse signal through a second driving unit, a second input end thereof receives the second pulse signal through a second inverter, a power supply end thereof receives the second power supply voltage, a ground end thereof is connected to the power ground, a voltage domain isolation process and an XOR process are performed on the differential second pulse signal, and a second control signal is output; The latch has a set terminal receiving the first control signal, a reset terminal receiving the second control signal, an output terminal outputting the second comparison signal, a power supply terminal receiving the second power supply voltage, and a ground terminal connected to the second power supply ground voltage.

11. The low-side drive overvoltage protection circuit according to claim 10, It is characterized in that The first level conversion unit includes a fourth resistor, a fifth resistor, a first capacitor, a second capacitor, a nineteenth NMOS tube, a twentieth NMOS tube, and a first XOR sub-unit; the second level conversion unit includes a sixth resistor, a seventh resistor, a third capacitor, a fourth capacitor, a twenty-first NMOS tube, a twenty-second NMOS tube, and a second XOR sub-unit; The first end of the fourth resistor and the first end of the fifth resistor are both connected to the second power supply voltage, the second end of the fourth resistor is coupled to the drain of the nineteenth NMOS tube through the first capacitor, the gate of the nineteenth NMOS tube receives the first pulse signal through the first driving unit, the source of the nineteenth NMOS tube is connected to the power ground, and the second end of the fourth resistor is also coupled to the first input end of the first XOR subunit to output a first output signal; The second end of the fifth resistor is coupled to the drain of the 20th NMOS transistor through the second capacitor, the gate of the 20th NMOS transistor receives the first pulse signal through the first inverter and the first driving unit in sequence, the source of the 20th NMOS transistor is connected to the power ground, and the second end of the fifth resistor is also coupled to the second input end of the first XOR subunit to output a second output signal; The output end of the first XOR subunit outputs the first control signal; The first end of the sixth resistor and the first end of the seventh resistor are both connected to the second power supply voltage, the second end of the sixth resistor is coupled to the drain of the twenty-first NMOS tube through the third capacitor, the gate of the twenty-first NMOS tube receives the second pulse signal through the second driving unit, the source of the twenty-first NMOS tube is connected to the power ground, and the second end of the sixth resistor is also coupled to the first input end of the second XOR subunit to output a third output signal; The second end of the seventh resistor is coupled to the drain of the twenty-second NMOS transistor through the fourth capacitor, the gate of the twenty-second NMOS transistor receives the second pulse signal through the second inverter and the second driving unit in sequence, the source of the twenty-second NMOS transistor is connected to the power ground, and the second end of the seventh resistor is also coupled to the second input end of the second XOR subunit to output a fourth output signal; The output terminal of the second XOR subunit outputs the second control signal.

12. An electronic device, It is characterized in that It comprises the low-side drive overvoltage protection circuit as claimed in any one of claims 1 to 11.

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