Zero power consumption control method of flyback converter and flyback converter

Abstract

The invention provides a zero power consumption control method of a flyback converter and the flyback converter. The flyback converter comprises a primary side controller arranged on a primary side, and a synchronous rectification controller and a protocol controller which are arranged on a secondary side, the protocol controller comprises an external equipment insertion detection module and is provided with a first output interface; an external equipment insertion detection module in the protocol controller is used for detecting whether external equipment is inserted or not and generating a first control signal; the protocol controller generates a second control signal at a first output interface of the protocol controller based on the first control signal; a communication circuit is arranged between the synchronous rectification controller and the protocol controller, the communication circuit generates a third control signal on a first pin of the synchronous rectification controller based on the second control signal, and the synchronous rectification controller generates a fourth control signal based on the third control signal and judges whether to enter a zero power consumption mode based on the fourth control signal; through the setting, the control of the zero power consumption mode can be reliably carried out.

Description

Technical Field

[0001] The present invention relates to the field of switching power supplies, and in particular to a zero-power consumption control method of a flyback converter and a flyback converter. Background Art

[0002] As a type of switching power supply, the flyback converter can be used to convert AC power into DC power to power subsequent loads or other module circuits. When the load is a device that can be plugged in or disconnected, and the device is plugged in, DC power can be used to power the load according to the power demand of the device; when the device is not plugged in, it is necessary to identify this state to control the operation of each module circuit in the flyback converter, so that the system can work in a low power consumption mode to avoid energy waste. Therefore, it is necessary to design a circuit that can control the operation of the system according to whether the device is plugged in or not, so that when no device is plugged in, it can reliably enter a low power consumption or even zero power consumption working mode. Summary of the invention

[0003] In order to solve the above technical problems, the present invention provides a zero-power consumption control method of a flyback converter and a flyback converter.

[0004] According to a first aspect of the present invention, a zero-power consumption control method for a flyback converter is provided, comprising a synchronous rectifier, a synchronous rectifier controller and a protocol controller arranged on a secondary side; characterized in that:

[0005] The protocol controller detects whether an external device is inserted and generates a first control signal; the protocol controller generates a second control signal at a first output interface of the protocol controller based on the first control signal;

[0006] A communication circuit is arranged between the synchronous rectification controller and the protocol controller; the communication circuit generates a third control signal on the first pin of the synchronous rectification controller based on the second control signal; the synchronous rectification controller generates a fourth control signal based on the third control signal, and determines whether to enter the zero power consumption mode based on the fourth control signal.

[0007] Optionally, when the external device insertion detection module detects that no external device is inserted, the first control signal having a first state is generated; when the external device insertion detection module detects that an external device is inserted, the first control signal having a second state is generated, and the first state is different from the second state;

[0008] The protocol controller generates a second control signal with different states at the first output interface based on the first control signal with different states;

[0009] The communication circuit generates a third control signal of different states on the first pin of the synchronous rectification controller based on the second control signal of different states;

[0010] The synchronous rectification controller generates a fourth control signal in different states based on the third control signal in different states, and determines whether to enter the zero power consumption mode based on the fourth control signal in different states;

[0011] The first control signal is a pulse signal.

[0012] Optionally, when the external device insertion detection module detects that no external device is inserted, it generates a first control signal with a first level, and when the duration of the first control signal being at the first level is greater than a first reference time threshold, after the first control signal is at the first level and before a first moment, or at the first moment, the flyback converter enters a zero power consumption mode; wherein the first moment is the moment after the first control signal is at the first level and the duration is after the first reference time threshold.

[0013] Optionally, when the external device insertion detection module detects that an external device is inserted, it generates a first control signal with a second level, and when the duration of the first control signal being at the second level is greater than a second reference time threshold, after the first control signal is at the second level and at a second moment, the flyback converter exits the zero power consumption mode; the second moment is the moment after the first control signal is at the second level and the duration is after the second reference time threshold.

[0014] Optionally, when the external device insertion detection module detects that no external device is inserted, a second control signal with a first level is generated at the first output interface corresponding to a moment when the first control signal is at a first level, or a moment later than a first delay time threshold of the moment, and before the first moment, an end moment after the second control signal is at the first level is the first moment;

[0015] The synchronous rectification controller generates a third control signal with a second level on the first pin based on the second control signal with a first level, and before a first moment, the end moment after the third control signal is at the second level is the first moment;

[0016] The synchronous rectification controller generates a fourth control signal having a first state at or before the first moment based on the third control signal, so that the flyback converter enters a zero power consumption mode.

[0017] Optionally, when the external device insertion detection module detects that an external device is inserted, a second control signal with a first level is generated at the first output interface corresponding to a moment when the first control signal is at a second level, or a moment later than a second delay time threshold of the moment, and before the second moment, an end moment after the second control signal is at the first level is the second moment;

[0018] The synchronous rectification controller generates a third control signal with a second level on the first pin based on the second control signal with a first level, and before a second moment, the end moment after the third control signal is at the second level is the second moment;

[0019] The synchronous rectification controller generates a fourth control signal having a second state at the second moment based on the third control signal, so that the flyback converter exits the zero power consumption mode;

[0020] The second state and the first state are different level states.

[0021] Optionally, the first reference time threshold is different from the second reference time threshold; the first delay time threshold and the second delay time threshold are smaller than the first reference time threshold and the second reference time threshold.

[0022] Optionally, the first level is a high level, and the second level is a low level.

[0023] Optionally, in the zero power consumption mode, when the output voltage is less than a first reference voltage threshold, the synchronous rectifier is controlled to be turned on intermittently; the first reference voltage threshold is a preset output voltage value.

[0024] Optionally, in the zero power consumption mode, when the output voltage is less than a first reference voltage threshold, the turn-on moment of the synchronous rectifier is controlled according to a first clock signal, and the first clock signal is used to limit the maximum operating frequency in the zero power consumption mode.

[0025] The present invention also provides a flyback converter, which includes a primary switch and a primary controller arranged on the primary side, and a synchronous rectifier, a synchronous rectifier controller and a protocol controller arranged on the secondary side, and is used to power an external device based on the output of the flyback converter; characterized in that:

[0026] The protocol controller includes an external device insertion detection module and has a first output interface; the external device insertion detection module is used to detect whether an external device is inserted and generate a first control signal; the protocol controller generates a second control signal at the first output interface according to the first control signal;

[0027] A communication circuit is arranged between the synchronous rectification controller and the protocol controller; the synchronous rectification controller has a first pin; the communication circuit generates a third control signal on the first pin according to the second control signal; the synchronous rectification controller generates a fourth control signal according to the third control signal, and determines whether to enter the zero power consumption mode based on the fourth control signal.

[0028] Optionally, when the external device insertion detection module detects that no external device is inserted, the first control signal having a first state is generated; when the external device insertion detection module detects that an external device is inserted, the first control signal having a second state is generated, and the first state is different from the second state;

[0029] The first control signal is a pulse signal.

[0030] Optionally, when the external device insertion detection module detects that no external device is inserted, a first control signal with a first level is generated, and when the duration of the first control signal being at the first level is greater than a first reference time threshold, after the first control signal is at the first level and before a first moment, or at the first moment, the flyback converter is caused to enter a zero power consumption mode; wherein the first moment is a moment after the first control signal is at the first level and the duration is after the first reference time threshold;

[0031] When the external device insertion detection module detects that an external device is inserted, it generates a first control signal with a second level, and when the duration of the first control signal being at the second level is greater than a second reference time threshold, after the first control signal is at the second level and at a second moment, the flyback converter exits the zero power consumption mode; the second moment is the moment after the first control signal is at the second level and the duration is after the second reference time threshold.

[0032] Optionally, the protocol controller includes a first comparator and a logic control module 1, the first comparator generates a first comparison signal according to the output voltage and the first reference voltage threshold; the logic module 1 generates the second control signal based on the first comparison signal and the first control signal;

[0033] The synchronous rectification controller includes a second comparator, a logic control module 2 and a logic control module 3; the second comparator generates a second comparison signal based on the third control signal and the second reference voltage threshold; the logic control module 2 generates the fourth control signal based on the second comparison signal; the logic control module 3 generates a fifth control signal based on the fourth control signal and the second comparison signal;

[0034] In the zero power consumption mode, the logic control module 3 generates a fifth control signal based on the second comparison signal, and the fifth control signal controls the turn-on time of the synchronous rectifier;

[0035] or,

[0036] The protocol controller further includes a logic control module 1; the logic control module 1 generates the second control signal based on the first control signal;

[0037] The synchronous rectification controller includes a first comparator, a second comparator, a logic control module 2 and a logic control module 3; the first comparator generates a first comparison signal based on the output voltage and a first reference voltage threshold; the second comparator generates a second comparison signal based on the third control signal and the second reference voltage threshold; the logic control module 2 generates the fourth control signal based on the second comparison signal; the logic control module 3 generates a fifth control signal based on the first comparison signal and the fourth control signal;

[0038] In the zero power consumption mode, the logic control module 3 generates a fifth control signal based on the first comparison signal, and the fifth control signal controls the turn-on time of the synchronous rectifier;

[0039] The first reference voltage threshold is a preset output voltage value; the second reference voltage threshold is a voltage value close to zero.

[0040] Optionally, in the zero power consumption mode, when the output voltage is less than a first reference voltage threshold, the synchronous rectifier is controlled to be turned on intermittently.

[0041] Optionally, the communication circuit includes a third switch tube arranged between the first pin and the ground terminal; a resistor is arranged between the first pin and the ground terminal, the third switch is connected in parallel with the resistor, and the control end of the third switch tube is connected to the first output interface.

[0042] The beneficial effects of the present invention include at least:

[0043] The present invention provides a zero-power control method for a flyback converter and a flyback converter, wherein the flyback converter includes a primary controller arranged on the primary side, and a synchronous rectifier, a synchronous rectification controller and a protocol controller arranged on the secondary side; the protocol controller includes an external device insertion detection module for detecting whether an external device is inserted and generating a first control signal; the protocol controller has a first output interface; the protocol controller generates a second control signal at the first output interface according to the first control signal; a communication circuit is provided between the synchronous rectification controller and the protocol controller; the synchronous rectification controller has a first pin; the communication circuit generates a third control signal on the first pin according to the second control signal; the synchronous rectification controller outputs a fourth control signal according to the third control signal, and determines whether to enter a zero-power consumption mode based on the fourth control signal; through the above-mentioned arrangement, the present invention can reliably enter the zero-power consumption mode when the external device is not connected.

[0044] Furthermore, in the zero power consumption mode, the conduction time of the synchronous rectifier is controlled based on the output voltage of the flyback converter to realize the zero voltage conduction function of the primary switch tube. In the zero power consumption mode, the conduction of the synchronous rectifier Q2 is controlled based on the output voltage, which can effectively reduce the power consumption of the system and make the system basically reach a zero power consumption state. In addition, the circuit of the present invention can be applied to applications with or without isolation devices. When there is no isolation device, communication between the primary and secondary sides can also be realized, which expands the scope of application and can save costs.

[0045] It should be noted that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 A schematic diagram showing the overall topological structure of the flyback converter of the present invention is shown;

[0047] Figure 2 A schematic diagram showing the working waveforms of various signals of the present invention;

[0048] Figure 3 A schematic diagram of the internal modules of the protocol controller U3 and the synchronous rectification controller U1 of the present invention is shown;

[0049] Figure 4 An embodiment of the internal logic control module of the protocol controller U3 of the present invention is shown;

[0050] Figure 5 Shows Figure 4 A working waveform diagram of each internal node;

[0051] Figure 6 An embodiment of each logic control module inside the synchronous rectification controller U1 of the present invention is shown;

[0052] Figure 7 Shows Figure 6 A working waveform diagram of each internal node;

[0053] Figure 8 Another schematic diagram showing the working waveforms of various signals of the present invention;

[0054] Fig. 9 Another schematic diagram of the internal modules of the protocol controller U3 and the synchronous rectification controller U1 of the present invention is shown;

[0055] Fig.10 Another embodiment of the internal logic control module of the protocol controller U3 of the present invention is shown;

[0056] Fig.11 Another embodiment of each logic control module inside the synchronous rectification controller U1 of the present invention is shown. DETAILED DESCRIPTION

[0057] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0058] Figure 1 The figure shows a schematic diagram of a flyback converter provided by the present invention, wherein the flyback converter comprises a rectifier U0 and a transformer T1, wherein the rectifier U0 is used to rectify the alternating current power supply AC into direct current VIN to supply power to subsequent modules; the transformer T1 comprises a primary inductor Np and a secondary inductor Ns; a primary switch tube Q1 and a primary controller U2 are provided on the primary side of the flyback converter, and the primary controller U2 is used to control the on or off of the primary switch tube Q1; a synchronous rectifier Q2, a synchronous rectifier controller U1 and a protocol controller U3 are provided on the secondary side of the flyback converter, and the on or off of the synchronous rectifier Q2 is controlled by the synchronous rectifier controller U1; the protocol controller U3 communicates with the protocol controller U3 via a USB (Universal Serial Bus) interface ( Figure 1 The output voltage VO of the flyback converter is used to power the protocol controller U3. When an external device is connected, the protocol controller U3 is used to convert the output voltage VO into the electrical parameters required by the external device to power the external device.

[0059] exist Figure 1In the embodiment, the primary side controller U2, the synchronous rectification controller U1 and the protocol controller U3 constitute a part for realizing zero power consumption control. An external device insertion detection module is arranged inside the protocol controller U3 to detect whether an external device is inserted and generate a first control signal N1; the protocol controller U3 is provided with at least one output interface, Figure 1 In the figure, GPIO (General-purpose input / output) is used to represent an interface with an output function. Of course, it can also be other interfaces with an output function. Based on the first control signal N1, a second control signal is generated on the first output interface (here the second control signal is directly represented by GPIO1). The synchronous rectification controller U1 is provided with a first pin ( Figure 1 A communication circuit is provided in the synchronous rectification controller U1 and the protocol controller U3, and the communication circuit generates a third control signal on the first pin based on the second control signal GPIO1 (the third control signal is directly represented by VT); the synchronous rectification controller U1 generates a fourth control signal Zero Power Loss Mode based on the third control signal VT, and determines whether to enter the zero power consumption mode based on the fourth control signal Zero Power LossMode.

[0060] Figure 1 It is shown that the flyback converter is also provided with other circuit elements, but only the parts related to the present invention are introduced, and the remaining circuit functions are not introduced in detail. In addition, Figure 1 The circuit structure is only a schematic diagram of the present invention, and does not mean that the flyback converter in the present invention has only this embodiment. The implementation method of realizing the same function as the present invention through other deformations is also within the scope of the present invention; wherein, the interface of each controller is only a schematic diagram, and other interfaces may also be set.

[0061] The specific working principle of the present invention to achieve zero power consumption control is further introduced below. As one of the embodiments of the present invention, when the external device insertion detection module inside the protocol controller U3 detects that no external device is inserted, a first control signal N1 with a first level is generated. When the duration of the first control signal N1 being the first level is greater than the first reference time threshold Tref1, the flyback converter enters the zero power consumption mode at the moment when the first control signal N1 is the first level and the duration is within the first reference time threshold Tref1, or at the end of the duration of the first reference time threshold Tref1 (which can be regarded as the first moment). When the external device insertion detection module inside the protocol controller U3 detects that an external device is inserted, a first control signal N1 with a second level is generated. When the duration of the first control signal being the second level is greater than the second reference time threshold Tref2, the flyback converter exits the zero power consumption mode at the moment when the first control signal N1 is the second level and the duration is within the second reference time threshold Tref2 (which can be regarded as the second moment). The second level is inverse to the first level. The following is an example in which the first level is a high level, the second level is a low level, the zero power consumption mode is entered at the first moment after the first control signal N1 is at the first level, and the zero power consumption mode is exited at the second moment after the first control signal N1 is at the second level.

[0062] In the following embodiment, the communication circuit is explained by taking the third switch tube Q3 as an example. Specifically, as shown in the figure, a resistor R1 is provided between the first pin and the ground terminal, the third switch tube Q3 is connected in parallel with the resistor R1, and the control end of the third switch tube Q1 is connected to the first output interface GPIO1; for this embodiment, the normal output on the first pin is a high level (for other embodiments, it may not be limited to a high level), and when the third switch tube Q3 is turned on, the level on the first pin is pulled down. Among them, the third switch tube Q3 as a communication circuit is only one of the examples of the present invention, and the present invention is not limited to this. In the present invention, the primary side controller U2 can be designed with a circuit module with lower power consumption to reduce system power consumption.

[0063] like Figure 2 The figure shows a schematic diagram of the working waveforms of various signals of the present invention. Before time t0, there is an external device inserted. At this time, the first control signal N1 is at a low level, and the second control signal GPIO1 generated on the first output interface based on the first control signal N1 is at a low level; the second control signal GPIO1 makes the third switch tube Q3 not conductive, and the third control signal VT is at a high level at this time, and the fourth control signal Zero Power LossMode generated based on the third control signal VT is at a low level, indicating that it is not a zero power consumption working mode, and the system is working in a normal working state at this time. Figure 2In the figure, Q2ZVS GON represents the control end signal of the synchronous rectifier Q2. Before the primary switch tube Q1 is turned on, the synchronous rectifier Q2 is turned on for a period of time to achieve zero voltage (ZVS) turn-on of the primary switch tube Q1 (the control end signal of the primary switch tube Q1 is represented by Q1 GON); when the primary switch tube Q1 is turned off, the synchronous rectifier Q2 is controlled to be turned on. At this time, the control end signal of the synchronous rectifier Q2 is represented by Q2 SR GON. After time t0, when the external device insertion detection module detects that no external device is inserted, the first control signal N1 generated is at a high level. When the time when the first control signal N1 is at a high level is greater than the first reference time threshold Tref1, corresponding to time t0, a second control signal GPIO1 with a high level is generated on the first output interface, and the duration of the high level is Tref1, that is, the high level of GPIO1 lasts until time t1; in the time period t0-t1, the second control signal GPIO1 acts on the third switch tube Q3 to pull down the third control signal VT; after time t1, the second control signal GPIO1 is at a low level, so that the third control signal VT returns to a high level. At time t1, based on the third control signal VT, the fourth control signal Zero Power Loss Mode jumps to a high level, which indicates that the system enters zero power consumption mode. At time t7, when the external device insertion detection module detects that an external device is connected, the generated first control signal N1 jumps to a low level. Starting from time t7, when the time when the first control signal N1 is at a low level is greater than the second reference time threshold Tref2, corresponding to time t7, a second control signal GPIO1 with a high level is generated on the first output interface, and its high level duration is Tref2, that is, the high level of GPIO1 lasts until time t8; in the time period t7-t8, the third control signal VT is a low level; after time t8, the second control signal GPIO1 is a low level, so that the third control signal VT returns to a high level, and at time t8, based on the third control signal VT, the fourth control signal Zero Power Loss Mode jumps to a low level, which indicates that the system exits the zero power consumption mode. After time t8, the system returns to normal working state. The fourth control signal Zero Power Loss Mode is a high level between t1-t8, which means that the system is in zero power consumption mode during this stage.

[0064] In zero power mode, some circuit modules in the original circuit can be turned off to reduce power consumption; for example, some circuits related to the feedback signal FB can be disabled in zero power mode, or other circuit modules with large current consumption can be disabled. In zero power mode, the turn-on time of the synchronous rectifier Q2 is controlled based on the output voltage VO of the flyback converter. Figure 2As shown in, after the protocol controller U3 detects that the output voltage VO is less than the first reference voltage threshold VREF, at time t3, a pulse signal is generated on the second control signal GPIO1, and the third control signal VT is pulled down based on the pulse signal acting on the third switch tube Q3, corresponding to the end time of the pulse or the rising edge time of the third control signal, that is, at time t4, Q2 ZVS GON is high level, that is, the synchronous rectifier Q2 is turned on, which is used to achieve zero voltage turn-on of the primary switch tube Q1. During the ZVS turn-on period of the synchronous rectifier Q2, a negative current is generated on the primary side, which is the negative current with Figure 1 The current in the opposite direction of ip in the primary side is provided; on the primary side, a resistor is provided between the source and the ground terminal of the primary switch tube Q1, and the primary controller U2 can detect the voltage VCS on the resistor to realize the detection of the primary current; after the synchronous rectifier Q2ZVS is turned off, the negative current can reach a certain value (via VCS to reflect the negative current) to realize the zero voltage conduction of the primary switch tube Q1. Among them, after the protocol controller U3 detects that the output voltage VO is less than the first reference voltage threshold VREF, the pulse signal generated at time t3 or t5 can be generated based on the first clock signal CLK, and the first clock signal CLK is used to limit the maximum operating frequency in the zero power consumption mode. The first reference voltage threshold VREF is a preset output voltage value.

[0065] Therefore, in the zero power consumption mode, the turn-on time of the synchronous rectifier Q2 is controlled based on the magnitude of the output voltage, and the ZVS turn-on of the synchronous rectifier is used to realize the zero voltage turn-on of the primary switch tube, which can reduce power consumption compared with the control based on the feedback loop. As another embodiment of the present invention, in the zero power consumption mode, after detecting that the output voltage VO is less than the first reference voltage threshold VREF, other circuits can also be used to control the synchronous rectifier Q2 to be intermittently turned on. The specific circuit can be set according to the actual situation and will not be described in detail here; that is, after the output voltage VO is less than the first reference voltage threshold VREF, the synchronous rectifier can always be controlled to be turned on regardless of whether it is based on the first clock signal CLK or based on other circuits. In addition, in the above embodiment, the primary and secondary sides do not need to be provided with an isolation device to realize the transmission of the primary and secondary side signals; as other embodiments of the present invention, the present invention is also applicable to applications where the primary and secondary sides have isolation devices.

[0066] It should be noted that Figure 2 The level of each signal in is only one example of the present invention, and the present invention is not limited thereto. For example, when the first control signal N1 is at a high level, the second control signal GPIO1 is at a low level. At this time, the communication circuit can be deformed accordingly to achieve the same function. In zero power consumption mode, Figure 2It is shown in the figure that after the primary switch tube Q1 is turned on, the synchronous rectifier Q2 is turned on by the Q2 SR GON signal, but the present invention is not limited to this. In the zero power consumption mode, the Q2 SR GON signal can also be made low, that is, the synchronous rectifier Q2 is controlled to be turned off, and the synchronous rectifier Q2 is only turned on when it is used to realize the zero voltage turn-on function of the primary switch tube. In addition, Figure 2 The diagram illustrates the judgment condition of whether to enter the zero power consumption mode based on the level of the first control signal and the duration of the corresponding level; however, the present invention is not limited to this. As other embodiments of the present invention, when the external device insertion detection module inside the protocol controller detects whether an external device is inserted or not, it can output first control signals of different states respectively, and generate second control signals of different states on the first output interface based on the first control signals of different states. The communication circuit converts the second control signals of different states into third control signals of different states. The synchronous rectification controller can identify whether the external device is inserted based on the third control signals of different states to determine whether to enter the zero power consumption mode; for example, when it is detected that no external device is inserted, a pulse signal of the first state is generated, and when it is detected that an external device is inserted, a pulse signal of the second state is generated. At this time, the first control signal can also be a pulse signal, and the judgment of whether to enter the zero power consumption mode is realized by different pulse signals.

[0067] Figure 3 This is a principle block diagram of the protocol controller U3 and the synchronous rectification controller U1 used to realize zero power consumption control in the present invention, and the output waveform of each signal is as follows: Figure 2 For example; specifically, the protocol controller U3 is provided with an external device insertion detection module for detecting whether an external device is inserted and generating a first control signal N1; the protocol controller U3 is also provided with a first comparator CMP1, which is used to output the voltage VO ( Figure 3VIN is connected to the output voltage VO) and is compared with the reference threshold voltage VREF to output a first comparison signal; the logic control module 1 generates a second control signal GPIO1 based on the first control signal N1 and the first comparison signal. The second control signal GPIO1 acts on the third switch tube Q3 to generate a third control signal VT. The synchronous rectification controller U1 is provided with a second comparator CMP2, a logic control module 2 and a logic control module 3; the second comparator CMP2 generates a second comparison signal based on the third control signal VT and the second reference voltage threshold VTVREF. In this embodiment, the second reference voltage threshold VTREF can be set to a voltage value close to zero; the logic control module 2 generates a fourth control signal Zero Power Loss Mode based on the second comparison signal, and determines whether to enter the zero power consumption mode based on the level of the fourth control signal; the logic control module 3 generates a Q2 ZVSGON signal based on the fourth control signal and the second comparison signal, which is used to control whether the synchronous rectifier Q2 is turned on. Among them, in the zero power consumption mode, that is, when the fourth control signal is valid, the logic control module 3 generates a Q2 ZVS GON signal based on the second comparison signal.

[0068] Below Figure 3 The logic control module circuits in the Figure 4 The figure shows a specific embodiment of the logic control module 1, which includes a rising edge trigger delay module 1, a rising edge trigger delay module 2, inverters INV1-INV3, AND gates (U4, U6, U7, U14), and OR gates (U5, U8). Figure 5 For the corresponding Figure 4 The waveform diagram of each node signal in is as follows: Figure 5As shown in, at time t0, when the external device insertion detection module detects that no external device is inserted, the output first control signal N1 jumps from low level to high level, and the rising edge triggers the delay module 1 to detect the rising edge of the first control signal N1 at this time, starting from time t0, after the delay of the first reference time threshold Tref1 (time t1), a high level is generated at the N3 node; the signal of the N3 node is acted upon by the inverter INV1, so that the signal of the N3' node is a high level before time t1; after the signal of the N3' node and the N1 signal pass through the AND gate U4, the signal of the N4 node is a low level before time t0, and a high level between t0-t1; after the N4 node acts on the OR gate U5, the node N6 follows the N4 node to be a high level between t0-t1; after the N6 node and the N1 node pass through the AND gate U6, the signal of the N7 node is also a high level between t0-t1; after the N7 node passes through the OR gate U8, the second control signal GPIO1 is a high level between t0-t1. Before time t1, the signal at the N8 node is the inverted signal of N1 (the effect of INV2). At this time, the rising edge trigger delay module 2 cannot detect the rising edge of the signal at the N8 node during this stage. Then, N9 follows N8, and N9' is the inverted signal of N9. After N9' and N8 pass through the AND gate U7, the signal generated at the N10 node is always at a low level before time t1. Therefore, before time t1, the second control signal GPIO1 follows N7. After the first comparator CMP1 detects that the output voltage VO is less than the first reference voltage threshold VREF, at time t3, the first comparison signal and the first clock signal CLK pass through the AND gate U14 to generate a short pulse signal (t3-t4) at the N5 node; at time t5, a short pulse signal (t5-t6) is also generated at the N5 node. After the short pulse signal passes through various logic gates, a corresponding short pulse signal is also generated on the second control signal GPIO1. Among them, Figure 5The number of medium and short pulses is just an example. At time t7, when the external device insertion detection module detects that a device has been inserted, the first control signal N1 jumps to a low level. The rising edge trigger delay module 1 cannot detect the rising edge of N1 at this time, and its output (N3) follows the N1 signal, that is, it jumps to a low level at time t7. After time t7, after the action of each logic gate, the signal generated at the N7 node is always at a low level. N8 is the inverted signal of N1, so after time t7, the N8 node signal jumps to a high level. At this time, the rising edge trigger delay module 2 detects the rising edge of N8, and after delaying the second reference time threshold Tref2, a high level is generated at the N9 node. The signal at the N9 node is acted on by the inverter INV3, so that the signal at the N9' node is a high level between t7-t8. N8 and N9' act on the AND gate U7 to make the signal at the N10 node a high level between t7-t8. Therefore, based on N10, the second control signal GPIO1 is a high level between t7-t8. Therefore, based on Figure 4 The circuit in Figure 2 : The waveform of the second control signal GPIO1 in .

[0069] Figure 6 The figure shows a specific embodiment of the logic control module 2 and the logic control module 3. The logic control module 2 includes a rising edge trigger delay module 3, a rising edge trigger delay module 4, an inverter INV4, an AND gate (U9, U12, U13), a falling edge trigger module 1, a falling edge trigger module 2 and an SR trigger U10. The logic control module 3 includes a falling edge trigger module 3 and an AND gate U11; Figure 7 For the corresponding Figure 6 The waveform diagram of each node signal in is as follows: Figure 7 As shown in, the third control signal VT is a signal opposite to the second control signal GPIO1, and the second comparison signal generated at the N11 node is also a signal opposite to the third control signal VT; after the rising edge trigger delay module 3 detects the rising edge of the N11 node signal at time t0, after the third reference time threshold Tref3, at time tb, a rising edge is generated at the N12 node, that is, it jumps to a high level, and at time t1, the signal of the N11 node jumps to a low level; since the lengths of the time periods corresponding to t3-t4, t5-t6, and t7-t8 are less than the third reference time threshold Tref3, the signals generated at the N12 node corresponding to these time periods will not jump to a high level, and will always maintain a low level state; the signal of the N12' node is a signal opposite to the N12 node signal; after the signals of the N11 node and the N12 node pass through the AND gate U9, the signal generated at the N13 node is as shown in FIG. Figure 7As shown in, it is high level only between tb-t1; at t1, after the falling edge trigger module 1 detects the falling edge of the signal at the N13 node, a short pulse signal is generated at the N14 node, and the short pulse signal acts on the set end S of the SR trigger U10, and a high-level fourth control signal Zero Power Loss Mode is generated at the output end of the SR trigger, that is, after t1, it enters the zero-power operation mode; after the rising edge trigger delay module 4 detects the rising edge of the signal at the N11 node at t0, after the fourth reference time threshold Tref4, at the ta moment, a rising edge is generated at the N15 node, and similarly, after the rising edge of the signal at the N11 node is detected at the t7 moment, after Tref4, at the tc moment, a rising edge is generated at the N15 node; since the time periods corresponding to t3-t4 and t5-t6 are less than Tref4, the signals generated corresponding to these two time periods will not generate high-level signals at the N15 node; after the signals at the N15 node and the N11 node pass through the AND gate U12, at the N16 node as shown Figure 7 The signal shown in is high level in the time periods of ta-t1 and tc-t8; after the signals of the N16 node and the N12' node pass through the AND gate U13, the N17 node generates the following Figure 7 The signal shown is at a high level during the ta-tb and tc-t8 time periods; at moments tb and t8, after the falling edge trigger module 2 detects the falling edge of the N17 node signal, a short pulse signal is generated at the N18 node, and the short pulse signal acts on the reset terminal R of the SR trigger U10, so as to reset the fourth control signal Zero Power Loss Mode; therefore, at moment t8, the fourth control signal Zero Power Loss Mode jumps to a low level, indicating exit from the zero power consumption mode. In the zero power mode time period (t1-t8), corresponding to the moments t3 and t5, a corresponding pulse signal is generated at the N11 node. After the falling edge trigger module 3 detects the falling edge of the N11 node signal at moments t4 and t6, a pulse signal is generated at the N19 node. After passing through the AND gate U11, the pulse signal becomes the Q2 ZVS GON signal, which is used to control the conduction of the synchronous rectifier Q2 to realize the ZVS function of the primary switch tube Q1. In the zero power mode, the signal based on the N19 node only determines the moment when the synchronous rectifier Q2 starts to conduct, and its specific conduction time can be determined by the ZVS pulse width generation module. The circuit is not shown in the figure, but it does not affect the understanding of the overall circuit. The specific setting can be set according to the actual application.

[0070] It should be noted that Figure 3-Figure 7The circuit structure and corresponding waveform in are only one embodiment of the present invention. By making corresponding deformations to each circuit to achieve the same function, it is also within the scope of the present invention. For the above embodiment, the first reference time threshold Tref1 and the second reference time threshold Tref2 are set to be different to distinguish the identification of the insertion or non-insertion of the external device. The above takes the first reference time threshold Tref1 greater than the second reference time threshold Tref2 as an example for explanation. Corresponding to Tref1 being greater than Tref2, the fourth reference time threshold Tref4 < the second reference time threshold Tref2 < the third reference time threshold Tref3 < the first reference time threshold Tref1 is set accordingly; the present invention is not limited to this, and the first reference time threshold Tref1 can also be set to be less than the second reference time threshold Tref2, and the circuit can be deformed accordingly to achieve the same function. Of course, when other circuits are used, Tre1 and Tref2 can also be set to be equal. As long as it can be realized to identify whether the device is inserted or not according to the level of the first control signal and the corresponding duration, it is also within the core idea of ​​the present invention. In addition, the above embodiment is described by taking the end time of the first reference time threshold Tref1 as an example to enter the zero power consumption mode. As other embodiments of the present invention, the zero power consumption mode may also be entered before the end time (t1) of the first reference time threshold Tref1. For example, Figure 2 In the embodiment, the system can also enter the zero power consumption mode at time tm before time t1, but an additional Q2 ZVS GON pulse will be triggered at time t1, which has no effect on the circuit function. At this time, it is only necessary to make corresponding changes to each circuit. As other embodiments of the present invention, Figure 5 As shown in, at time t0, after the first control signal N1 jumps to a high level, the circuit can be changed and set so that GPIO1 can jump to a high level at time t0', that is, in the time period t0-t0', GPIO1 is a low level; similarly, at time t7, after the first control signal N1 jumps to a low level, GPIO1 can jump to a low level at time t7', that is, in the time period t7-t7', GPIO1 is a low level, so as to avoid accidentally entering or exiting the zero power consumption mode; wherein the time periods t0-t0' and t7-t7' can be set smaller than Tref1 and Tref2. Figure 8 Another schematic diagram of the working waveforms of the signals of the present invention is shown in FIG. Figure 2 The difference is that, in the zero power consumption mode, the output voltage VO is detected based on the synchronous rectification controller U1, that is, in the zero power consumption mode, the turn-on time of the synchronous rectifier Q2 is determined by the internal circuit of the synchronous rectification controller; Fig. 9 Another principle block diagram for realizing zero power consumption control inside the protocol controller U3 and the synchronous rectification controller U1 of the present invention corresponds to Figure 8 The working waveform in , that is, the first comparator CMP1 is set in the synchronous rectification controller U1.

[0071] Figure 10-11 For the corresponding Fig. 9 An embodiment of each logic control module in, Fig.10 The principle of generating the second control signal GPIO1 based on the first control signal N1 is similar to Figure 4 In agreement, Fig.11 The principle of generating the fourth control signal Zero Power Loss Mode based on the third control signal VT is Figure 6 is consistent with the above, and will not be elaborated here. Figure 4 and Figure 6 The difference is that in this embodiment, the first comparator CMP1 is set in the synchronous rectification controller U1, and the AND gate U14 is set in the logic control module three. In the zero power consumption mode, when the output voltage VO is less than the first reference voltage threshold VREF, the first clock signal CLK and the effective first comparison signal generate a pulse signal after passing through the AND gate U14. The pulse signal generates a Q2 ZVS GON signal after passing through the AND gate U11 to turn on the synchronous rectifier Q2 and realize the zero voltage turn-on of the primary switch Q1. Similarly, the signal of the N19 node is only used to determine the turn-on time of the synchronous rectifier Q2, and its turn-on duration can be determined by the ZVS pulse width generation module, and its specific setting can be set according to the actual application.

[0072] The present invention also provides a zero-power consumption control method for a flyback converter, wherein the flyback converter includes a primary side controller arranged on the primary side, and a synchronous rectifier, a synchronous rectification controller and a protocol controller arranged on the secondary side; the control method includes: the protocol controller detects whether an external device is inserted and generates a first control signal; based on the first control signal, a second control signal is generated at a first output interface of the protocol controller; a communication circuit is arranged between the synchronous rectification controller and the protocol controller; the communication circuit generates a third control signal on a first pin on the synchronous rectifier based on the second control signal; the synchronous rectification controller generates a fourth control signal based on the third control signal, and determines whether to enter the zero-power consumption mode based on the fourth control signal.

[0073] Among them, the zero power consumption control method also includes the other functions described above, which will not be elaborated in detail here.

[0074] In summary, the present invention provides a zero-power control method and a flyback converter for a flyback converter, wherein the flyback converter includes a primary controller arranged on the primary side, and a synchronous rectifier, a synchronous rectification controller and a protocol controller arranged on the secondary side; the protocol controller includes an external device insertion detection module for detecting whether an external device is inserted and generating a first control signal; the protocol controller has a first output interface; the protocol controller generates a second control signal at the first output interface according to the first control signal; a communication circuit is provided between the synchronous rectification controller and the protocol controller; the synchronous rectification controller has a first pin; the communication circuit generates a third control signal on the first pin according to the second control signal; the synchronous rectification controller generates a fourth control signal according to the third control signal, and determines whether to enter the zero-power mode based on the fourth control signal. Through the above-mentioned configuration, the present invention can reliably enter the zero-power mode when the external device is not connected.

[0075] Furthermore, in the zero power consumption mode, the conduction time of the synchronous rectifier is controlled based on the output voltage of the flyback converter to achieve zero voltage conduction of the primary switch. In the zero power consumption mode, the conduction of the synchronous rectifier Q2 is controlled based on the output voltage, which can effectively reduce the power consumption of the system and make the system basically reach a zero power consumption state. In addition, the circuit of the present invention can be applied to applications with or without isolation devices. For application scenarios without isolation devices, communication between the primary and secondary sides can also be achieved, which expands the scope of application and can save costs.

[0076] Finally, it should be noted that: Obviously, the above embodiments are only examples for clearly explaining the present invention, and are not intended to limit the implementation methods. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from this are still within the scope of protection of the present invention.

Claims

1. A zero-power control method for a flyback converter, comprising a synchronous rectifier, a synchronous rectifier controller and a protocol controller arranged on a secondary side; characterized in that: The external device insertion detection module in the protocol controller detects whether an external device is inserted and generates a first control signal; the protocol controller generates a second control signal at the first output interface of the protocol controller based on the first control signal; A communication circuit is arranged between the synchronous rectification controller and the protocol controller; the communication circuit generates a third control signal on the first pin of the synchronous rectification controller based on the second control signal; the synchronous rectification controller generates a fourth control signal based on the third control signal, and determines whether to enter the zero power consumption mode based on the fourth control signal.

2. The zero power consumption control method according to claim 1, characterized in that: When the external device insertion detection module detects that no external device is inserted, a first control signal having a first state is generated; when the external device insertion detection module detects that an external device is inserted, a first control signal having a second state is generated, and the first state is different from the second state; The first control signal is a pulse signal.

3. The zero power consumption control method according to claim 1, characterized in that: When the external device insertion detection module detects that no external device is inserted, a first control signal with a first level is generated, and when the duration of the first control signal being the first level is greater than a first reference time threshold, the flyback converter enters a zero power consumption mode after the first control signal is the first level and before a first moment, or at the first moment; wherein the first moment is a moment after the first control signal is the first level and the duration is after the first reference time threshold.

4. The zero power consumption control method according to claim 3, characterized in that: When the external device insertion detection module detects that an external device is inserted, it generates a first control signal with a second level, and when the duration of the first control signal being at the second level is greater than a second reference time threshold, after the first control signal is at the second level and at a second moment, the flyback converter exits the zero power consumption mode; the second moment is the moment after the first control signal is at the second level and the duration is after the second reference time threshold.

5. The zero power consumption control method according to claim 4, characterized in that: When the external device insertion detection module detects that no external device is inserted, corresponding to the moment when the first control signal is at the first level, or at a moment later than the first delay time threshold of the moment, a second control signal with the first level is generated at the first output interface, and before the first moment, the end moment after the second control signal is at the first level is the first moment; The synchronous rectification controller generates a third control signal with a second level on the first pin based on the second control signal with a first level, and before a first moment, the end moment after the third control signal is at the second level is the first moment; The synchronous rectification controller generates a fourth control signal having a first state at or before the first moment based on the third control signal, so that the flyback converter enters a zero power consumption mode.

6. The zero power consumption control method according to claim 5, characterized in that: When the external device insertion detection module detects that an external device is inserted, a second control signal with a first level is generated at the first output interface corresponding to the moment when the first control signal is at the second level, or a moment later than the second delay time threshold of the moment, and before the second moment, the end moment after the second control signal is at the first level is the second moment; The synchronous rectification controller generates a third control signal with a second level on the first pin based on the second control signal with a first level, and before a second moment, the end moment after the third control signal is at the second level is the second moment; The synchronous rectification controller generates a fourth control signal having a second state at the second moment based on the third control signal, so that the flyback converter exits the zero power consumption mode; The second state and the first state are different level states.

7. The zero power consumption control method according to claim 6, characterized in that: The first reference time threshold is different from the second reference time threshold; the first delay time threshold and the second delay time threshold are smaller than the first reference time threshold and the second reference time threshold.

8. The zero power consumption control method according to claim 6, characterized in that: The first level is a high level, and the second level is a low level.

9. The zero power consumption control method according to any one of claims 1 to 8, characterized in that: In the zero power consumption mode, when the output voltage is less than a first reference voltage threshold, the synchronous rectifier is controlled to be turned on intermittently; the first reference voltage threshold is a preset output voltage value.

10. The zero power consumption control method according to claim 9, characterized in that: In the zero power consumption mode, when the output voltage is less than a first reference voltage threshold, the turn-on time of the synchronous rectifier is controlled according to a first clock signal, and the first clock signal is used to limit the maximum operating frequency in the zero power consumption mode.

11. A flyback converter, comprising a primary switch tube and a primary controller arranged on the primary side, and a synchronous rectifier, a synchronous rectifier controller and a protocol controller arranged on the secondary side, and the output of the flyback converter is used to power an external device; characterized in that: The protocol controller includes an external device insertion detection module and has a first output interface; the external device insertion detection module is used to detect whether an external device is inserted and generate a first control signal; the protocol controller generates a second control signal at the first output interface according to the first control signal; A communication circuit is arranged between the synchronous rectification controller and the protocol controller; the synchronous rectification controller has a first pin; the communication circuit generates a third control signal on the first pin according to the second control signal; the synchronous rectification controller generates a fourth control signal according to the third control signal, and determines whether to enter the zero power consumption mode based on the fourth control signal.

12. The flyback converter according to claim 11, characterized in that: When the external device insertion detection module detects that no external device is inserted, a first control signal having a first state is generated; when the external device insertion detection module detects that an external device is inserted, a first control signal having a second state is generated, and the first state is different from the second state; The first control signal is a pulse signal.

13. The flyback converter according to claim 11, characterized in that: When the external device insertion detection module detects that no external device is inserted, a first control signal with a first level is generated, and when the duration of the first control signal being at the first level is greater than a first reference time threshold, after the first control signal is at the first level and before a first moment, or at the first moment, the flyback converter enters a zero power consumption mode; wherein the first moment is a moment after the first control signal is at the first level and the duration is after the first reference time threshold; When the external device insertion detection module detects that an external device is inserted, it generates a first control signal with a second level, and when the duration of the first control signal being at the second level is greater than a second reference time threshold, after the first control signal is at the second level and at a second moment, the flyback converter exits the zero power consumption mode; the second moment is the moment after the first control signal is at the second level and the duration is after the second reference time threshold.

14. The flyback converter according to claim 13, characterized in that: The protocol controller comprises a first comparator and a logic control module 1, wherein the first comparator generates a first comparison signal according to the output voltage and the first reference voltage threshold; and the logic module 1 generates the second control signal based on the first comparison signal and the first control signal; The synchronous rectification controller includes a second comparator, a second logic control module and a third logic control module; the second comparator generates a second comparison signal based on the third control signal and the second reference voltage threshold; the second logic control module generates the fourth control signal based on the second comparison signal; The logic control module three generates a fifth control signal based on the fourth control signal and the second comparison signal; In the zero power consumption mode, the logic control module 3 generates a fifth control signal based on the second comparison signal, and the fifth control signal controls the turn-on time of the synchronous rectifier; or, The protocol controller further includes a logic control module 1; the logic control module 1 generates the second control signal based on the first control signal; The synchronous rectification controller includes a first comparator, a second comparator, a logic control module 2 and a logic control module 3; the first comparator generates a first comparison signal based on the output voltage and a first reference voltage threshold; the second comparator generates a second comparison signal based on the third control signal and the second reference voltage threshold; The second logic control module generates the fourth control signal based on the second comparison signal; The logic control module three generates a fifth control signal based on the first comparison signal and the fourth control signal; In the zero power consumption mode, the logic control module 3 generates a fifth control signal based on the first comparison signal, and the fifth control signal controls the turn-on time of the synchronous rectifier; The first reference voltage threshold is a preset output voltage value; The second reference voltage threshold is a voltage value close to zero.

15. The flyback converter according to any one of claims 11 to 14, characterized in that: In the zero power consumption mode, when the output voltage is less than a first reference voltage threshold, the synchronous rectifier is controlled to be turned on intermittently.

16. The flyback converter according to claim 11, characterized in that: The communication circuit includes a third switch tube arranged between the first pin and the ground end; a resistor is arranged between the first pin and the ground end, the third switch is connected in parallel with the resistor, and the control end of the third switch tube is connected to the first output interface.

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