Circuit for realizing power protection, corresponding power amplifier module and electronic equipment

Abstract

The invention discloses a circuit for realizing power protection, a corresponding power amplifier module and electronic equipment. The power amplifier module comprises a controller unit, a radio frequency power amplifier unit and a filter unit, wherein the controller unit is used for providing bias voltage for the radio frequency power amplifier unit; the radio frequency power amplifier unit is used for performing power amplification on the radio frequency signal; the filter unit is used for filtering the amplified radio frequency signal; when the input power of the radio frequency signal is increased to a first threshold value or reduced to a second threshold value, the controller unit generates a corresponding first control signal, a second control signal and a third control signal, so that the output first bias voltage is reduced or increased step by step; and the gain and the output power of the power amplifier module are reduced or increased step by step, so that the reliability of the power amplifier module is improved.

Description

Technical Field

[0001] The present invention relates to a circuit for realizing power protection, and also relates to a corresponding power amplifier module and an electronic device including the power amplifier module, belonging to the technical field of radio frequency integrated circuits. Background Art

[0002] With the rapid development of 5G communication technology, the mainstream RF front-end architecture has now developed to Phase7L (seventh-generation RF front-end solution) and Phase7LE (Phase7L enhanced version), and Phase8 (eighth-generation RF front-end solution) is also under planning and discussion. From its evolution history, the RF front-end solution has been developing towards high integration and miniaturization.

[0003] In the prior art, the most integrated L-PAMiD solution is to integrate power amplifiers, RF switches, analog controllers, low noise amplifiers, filters and other devices together in a modular manner. The advantages of this solution are high integration and small area occupied in the terminal motherboard. The disadvantage is that the device has reliability risks, that is, when the power amplifier is established or shut down under high input power, the power amplifier or filter is prone to burn out and fail. It is well known that when there is a reliability risk in the device, the high integration will significantly increase the cost of the device. This reliability risk will even affect the evolution of high integration and miniaturization of the RF front-end module. Therefore, how to improve the reliability of the power amplifier module under high input power conditions and meet the development requirements of high integration and miniaturization of the RF front-end is still one of the very important research topics in this field.

[0004] In the PCT international application with application number PCT / US2014 / 046043, a power amplifier circuit and an input power limiter circuit are disclosed. The power amplifier circuit includes an input matching network, a power detector, a directional coupler, a first power amplifier stage, a second power amplifier stage, a control circuit, a hysteresis circuit, an inter-stage matching network and a switching transistor. Among them, the power detector generates a voltage output proportional to the power level of the input signal, and the control circuit generates a gain reduction signal based on the comparison of the voltage output from the power detector with a predetermined voltage level corresponding to a specific power level of the input signal. The total gain of the power amplifier circuit is reduced according to the gain reduction signal that adjusts the configuration of the circuit components. This technical solution controls the bias circuit through a directional coupler, a programmable attenuator, an input power detector, and an output power detector, resulting in a complex and cumbersome logic process and low fault tolerance. Summary of the invention

[0005] The primary technical problem to be solved by the present invention is to provide a circuit for realizing power protection, which specifically includes a power detection circuit and a ladder logic control circuit.

[0006] Another technical problem to be solved by the present invention is to provide a power amplifier module including the above circuit.

[0007] Another technical problem to be solved by the present invention is to provide an electronic device including the power amplifier module.

[0008] In order to achieve the above object, the present invention adopts the following technical solutions:

[0009] According to a first aspect of an embodiment of the present invention, a power detection circuit is provided, which is used in a power amplifier module, and includes a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, a first NPN transistor and a first operational amplifier, as well as a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor and a seventh resistor, and a first capacitor, a second capacitor and a third capacitor; wherein,

[0010] The RF signal input terminal is connected to the first capacitor, the other end of the first capacitor is connected to the third resistor and the gate end of the first NMOS tube, the source end of the first NMOS tube and the source end of the second NMOS tube are commonly connected to the ground potential terminal, the gate end of the second NMOS tube is connected to the other end of the third resistor and the first resistor and the second resistor through the fourth resistor, the other end of the first resistor is connected to the first output end of the voltage / current bias generating circuit as a bias end, and the other end of the second resistor is connected to the ground potential end; the two ends of the second capacitor are respectively connected to the source end and the drain end of the first NMOS tube, and the two ends of the third capacitor are respectively connected to the source end and the drain end of the second NMOS tube; the drain end of the first NMOS tube is connected to the power supply voltage end through the fifth resistor on the one hand, and the other end of the power supply voltage end is connected to the power supply voltage end through the fifth resistor on the other hand. The surface is connected to the inverting input terminal of the first operational amplifier and the drain terminal of the second PMOS tube; the drain terminal of the second NMOS tube is connected to the power supply voltage terminal through the sixth resistor on the one hand, and is connected to the non-inverting input terminal of the first operational amplifier on the other hand; the output terminal of the first operational amplifier is connected to the base of the first NPN tube as the output terminal of the power detection circuit on the one hand, and is connected to the input terminal of the voltage hysteresis comparator on the other hand; the emitter of the first NPN tube is connected to the ground potential terminal through the seventh resistor, the collector of the first NPN tube is connected to the drain terminal of the first PMOS tube, the gate terminal and the drain terminal of the first PMOS tube are connected in parallel and then connected to the gate terminal of the second PMOS tube, and the source terminals of the first PMOS tube and the second PMOS tube are both connected to the power supply voltage terminal.

[0011] Preferably, the first NMOS transistor and the second NMOS transistor, the third resistor and the fourth resistor, the second capacitor and the third capacitor, and the fifth resistor and the sixth resistor are symmetrically arranged and have the same electrical parameters.

[0012] Preferably, the first NMOS transistor and the second NMOS transistor operate in a saturation region, and their current and voltage satisfy a square law characteristic;

[0013] The first NPN transistor operates in the amplification region, and its current and voltage satisfy exponential law characteristics.

[0014] Preferably, the input power of the RF signal generates a current / voltage offset at the inverting input terminal of the first operational amplifier. When the current / voltage offset and the feedback current act together on the inverting input terminal of the first operational amplifier, a logarithmic linear relationship is formed between the output detection voltage and the input power.

[0015] According to a second aspect of an embodiment of the present invention, a ladder logic control circuit is provided, which is used in a power amplifier module, and includes a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter and an eighth inverter, as well as a first AND gate, a second AND gate and a first OR gate, as well as a filtering module and a delay module; wherein,

[0016] The first output end of the filter module is connected to the input end of the delay module through the second inverter and the third inverter in sequence, and the output end of the delay module is connected to the first input end of the first AND gate on the one hand and to the first input end of the first OR gate on the other hand in sequence through the fourth inverter and the fifth inverter;

[0017] The second output end of the filtering module is connected to the second input end of the first AND gate and the second input end of the first OR gate respectively through the sixth inverter and the seventh inverter; the output end of the first AND gate is connected to the first output end of the ladder logic control circuit on the one hand, and is connected to the first input end of the second AND gate through the eighth inverter on the other hand, the output end of the first OR gate is connected to the second input end of the second AND gate, and the output end of the second AND gate is the second output end of the ladder logic control circuit.

[0018] Preferably, the filtering module is used to filter out glitches or pulses of the inverse signal of the first control signal to avoid false triggering of the protection mechanism due to short-term jitter of the input power;

[0019] The delay module is used to generate a delay time to achieve the continuation of the first bias voltage at a lower voltage level.

[0020] According to a third aspect of an embodiment of the present invention, a power amplifier module is provided, comprising a controller unit, a radio frequency power amplifier unit and a filter unit; wherein:

[0021] The RF signal input end is connected to the input end of the controller unit and the RF power amplifier unit respectively, the output end of the controller unit is connected to the bias of the RF power amplifier unit, the output end of the RF power amplifier unit is connected to the input end of the filter unit, and the output end of the filter unit is connected to the RF signal output end;

[0022] The controller unit includes the above-mentioned power detection circuit or ladder logic control circuit, which is used to provide a bias voltage for the radio frequency power amplifier unit.

[0023] According to a fourth aspect of an embodiment of the present invention, a power amplifier module is provided, comprising a controller unit, a radio frequency power amplifier unit and a filter unit; wherein:

[0024] The RF signal input end is connected to the input end of the controller unit and the RF power amplifier unit respectively, the output end of the controller unit is connected to the bias of the RF power amplifier unit, the output end of the RF power amplifier unit is connected to the input end of the filter unit, and the output end of the filter unit is connected to the RF signal output end;

[0025] The controller unit is used to provide a bias voltage for the RF power amplifier unit, and includes a bandgap reference circuit, a voltage / current bias generating circuit, a voltage hysteresis comparator, a bias power supply circuit, the above-mentioned power detection circuit and a ladder logic control circuit; wherein,

[0026] The bandgap reference circuit is used to generate and output a first reference voltage and a second reference voltage, respectively providing reference voltages for the voltage / current bias generating circuit and the bias power supply circuit;

[0027] The voltage / current bias generating circuit is used to generate and output a second bias voltage to the power detection circuit, and to generate and output a reference voltage and a bias current to the voltage hysteresis comparator;

[0028] The power detection circuit is used to detect the power of the input radio frequency signal, generate a detection voltage after conversion, and output it to the voltage hysteresis comparator;

[0029] The voltage hysteresis comparator is used to generate the first control signal after comparing the detection voltage with the reference voltage, and output the first control signal to the ladder logic control circuit;

[0030] The ladder logic control circuit is used to generate the second control signal and the third control signal after logical combination according to the first control signal, and output them to the bias power supply circuit;

[0031] The bias power supply circuit is used to generate the first bias voltage according to the second control signal and the third control signal, and output it to the RF power amplifier unit to provide a bias voltage therefor.

[0032] Preferably, the RF power amplifier unit is used to amplify the power of the RF signal and output the amplified RF signal to the filter unit;

[0033] The filter unit is used to filter the amplified radio frequency signal and output a radio frequency signal of a specific frequency band.

[0034] Preferably, the first output terminal of the bandgap reference circuit is connected to the input terminal of the voltage / current bias generating circuit, and the second output terminal is connected to the first input terminal of the bias power supply circuit; the first output terminal of the voltage / current bias generating circuit is connected to the bias terminal of the power detection circuit, and the second output terminal and the third output terminal are respectively connected to the reference voltage terminal and the bias terminal of the voltage hysteresis comparator; the input terminal of the power detection circuit is connected to the RF signal input terminal, and the output terminal is connected to the input terminal of the voltage hysteresis comparator; the output terminal of the voltage hysteresis comparator is connected to the input terminal of the ladder logic control circuit, and is connected to the input terminal of the filtering module through a first inverter; the output terminal of the ladder logic control circuit is connected to the second input terminal of the bias power supply circuit, and the output terminal of the bias power supply circuit is connected to the bias terminal of the RF power amplifier unit.

[0035] Preferably, the bias power supply circuit includes an error amplifier, a power tube, a first transmission gate and a second transmission gate, and a tenth resistor, an eleventh resistor and a twelfth resistor; wherein the non-inverting input terminal of the error amplifier is connected to the second output terminal of the bandgap reference circuit, the output terminal of the error amplifier is connected to the gate terminal of the power tube, the source terminal of the power tube and the power supply terminal of the error amplifier are both connected to the power supply voltage terminal, the drain terminal of the power tube is connected to the tenth resistor as the output terminal of the bias power supply circuit, the tenth resistor, the eleventh resistor and the twelfth resistor are connected in series in sequence, and the other end of the tenth resistor is connected to the ground potential terminal; the connection node of the tenth resistor and the eleventh resistor is connected to the input terminal of the second transmission gate, the connection node of the eleventh resistor and the twelfth resistor is connected to the input terminal of the first transmission gate, the output terminals of the first transmission gate and the second transmission gate are both connected to the inverting input terminal of the error amplifier, the control terminal of the first transmission gate is connected to the first output terminal of the ladder logic control circuit, and the control terminal of the second transmission gate is connected to the second output terminal of the ladder logic control circuit.

[0036] Preferably, when the input power of the RF signal increases to a first threshold value or decreases to a second threshold value, the controller unit generates corresponding first control signals, second control signals and third control signals to control the first bias voltage output by the controller unit to decrease or increase in steps in a step-by-step manner, thereby causing the gain and output power of the power amplifier module to decrease or increase in steps accordingly; wherein the first threshold value is greater than the second threshold value.

[0037] Preferably, when the input power increases to the first threshold value, the first control signal output by the voltage hysteresis comparator jumps from a low level to a high level; at this time, the second control signal output by the ladder logic control circuit jumps from a high level to a low level; the third control signal jumps from a low level to a high level, and after a set delay time, the third control signal jumps to a low level.

[0038] Preferably, when the input power decreases to the second threshold value, the first control signal output by the voltage hysteresis comparator changes from a high level to a low level; at this time, the third control signal output by the ladder logic control circuit changes from a low level to a high level, and after a set delay time, the third control signal changes to a low level, and at the same time, the second control signal changes from a low level to a high level.

[0039] Preferably, when the input power increases to the first threshold value, the first bias voltage output by the bias power supply circuit decreases and drops to zero after a set delay time;

[0040] When the input power decreases to the second threshold, the first bias voltage output by the bias power supply circuit increases, and increases to a preset value after a set delay time.

[0041] Preferably, when the input power increases to the first threshold, the gain of the power amplifier module decreases and drops to zero after a set delay time;

[0042] When the input power decreases to the second threshold, the gain of the power amplifier module increases, and increases to a preset value after a set delay time.

[0043] Preferably, when the input power increases to the first threshold, the output power of the power amplifier module decreases and drops to zero after a set delay time;

[0044] When the input power decreases to the second threshold, the output power of the power amplifier module increases, and increases to a preset value after a set delay time.

[0045] According to a fifth aspect of an embodiment of the present invention, an electronic device is provided, wherein the electronic device includes the above-mentioned power amplifier module.

[0046] Compared with the prior art, the present invention realizes fine bias control of the RF power amplifier unit through the coordinated work of the power detection circuit and the ladder logic control circuit in the controller unit. When the input power changes significantly, such as rising to a preset first threshold or falling to a second threshold, the controller unit can generate a corresponding control signal to adjust the bias voltage in steps in a ladder-like manner, so that the gain and output power of the power amplifier module can change smoothly accordingly, avoiding the risk of device damage caused by power mutation. This ladder protection mechanism not only improves the working reliability of the power amplifier module under extreme conditions, but also helps to extend the service life of the equipment and maintain the stability of communication quality. In addition, the circuit design of the present invention is ingenious and reasonable, with low cost, suitable for electronic equipment of various communication standards, and has broad application prospects and market potential. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 A structural block diagram of a power amplifier module provided by an embodiment of the present invention;

[0048] Figure 2 A timing comparison diagram of each functional unit in a power amplifier module in an embodiment of the present invention;

[0049] Figure 3 A circuit schematic diagram of a power detection circuit in an embodiment of the present invention;

[0050] Figure 4 A circuit schematic diagram of a voltage hysteresis comparator in an embodiment of the present invention;

[0051] Figure 5 is a schematic diagram of a first control signal output by a voltage hysteresis comparator in an embodiment of the present invention;

[0052] Figure 6 A circuit schematic diagram of a ladder logic control circuit in an embodiment of the present invention;

[0053] Figure 7 is a circuit schematic diagram of a bias power supply circuit in an embodiment of the present invention;

[0054] Figure 8 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0055] The technical content of the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0056] like Figure 1As shown, the power amplifier module provided by the embodiment of the present invention comprises at least a controller unit 100, a RF power amplifier unit 200 and a filter unit 300; wherein, the RF signal input terminal RFIN is respectively connected to the input terminals of the controller unit 100 and the RF power amplifier unit 200, the output terminal of the controller unit 100 is connected to the bias of the RF power amplifier unit 200, the output terminal of the RF power amplifier unit 200 is connected to the input terminal of the filter unit 300, and the output terminal of the filter unit 300 is connected to the RF signal output terminal RFOUT.

[0057] When the input power of the RF signal increases to a first threshold value or decreases to a second threshold value, the controller unit 100 generates corresponding first control signals, second control signals and third control signals, and controls the first bias voltage output by the controller unit 100 to decrease or increase in steps in a step-by-step manner, thereby causing the gain and output power of the power amplifier module to decrease or increase in steps accordingly.

[0058] The controller unit 100 is used to provide a bias voltage for the RF power amplifier unit 200; the controller unit 100 includes a bandgap reference circuit, a voltage / current bias generation circuit, a power detection circuit, a voltage hysteresis comparator, a ladder logic control circuit and a bias power supply circuit (VBIAS LDO). Among them, the first output end of the bandgap reference circuit is connected to the input end of the voltage / current bias generating circuit, and the second output end is connected to the first input end of the bias power supply circuit; the first output end of the voltage / current bias generating circuit is connected to the bias end of the power detection circuit, and the second output end and the third output end are respectively connected to the reference voltage end and the bias end of the voltage hysteresis comparator; the input end of the power detection circuit (that is, the input end of the controller unit 100) is connected to the RF signal input end RFIN, and the output end is connected to the input end of the voltage hysteresis comparator; the output end of the voltage hysteresis comparator is connected to the input end of the ladder logic control circuit, the output end of the ladder logic control circuit is connected to the second input end of the bias power supply circuit, and the output end of the bias power supply circuit (that is, the output end of the controller unit 100) is connected to the bias end of the RF power amplifier unit 200.

[0059] The bandgap reference circuit is used to generate and output a first reference voltage VBG1 and a second reference voltage VBG2, which respectively provide reference voltages for a voltage / current bias generating circuit and a bias power supply circuit.

[0060] The voltage / current bias generating circuit is used to generate and output a second bias voltage VG to the power detection circuit, and to generate and output a reference voltage VREF and a bias current IB2 to the voltage hysteresis comparator.

[0061] The power detection circuit is used to detect the power of the input RF signal. After conversion, it generates a detection voltage VDET (in V) that is logarithmically linear with the input power PIN (in dBm) and outputs it to the voltage hysteresis comparator.

[0062] The voltage hysteresis comparator is used to generate a first control signal ODP_EN after comparing the detection voltage VDET with the reference voltage VREF, and output it to the ladder logic control circuit. When the input power PIN increases and reaches the first threshold value Pth1, the first control signal ODP_EN is high; when the input power PIN decreases to the second threshold value Pth2, the first control signal ODP_EN is low; wherein the first threshold value Pth1 is greater than the second threshold value Pth2. The size of the reference voltage VREF can be set according to the required first threshold value Pth1. The hysteresis function of the voltage hysteresis comparator can realize that the set first threshold value Pth1 is slightly greater than the second threshold value Pth2, so that the voltage comparator has a certain hysteresis width to avoid repeated switching of the protection mechanism due to fluctuations in the input power.

[0063] The ladder logic control circuit is used to generate the second control signal HPM_EN and the third control signal LPM_EN_DEL after logical combination according to the first control signal ODP_EN, and output them to the bias power supply circuit, wherein the third control signal LPM_EN_DEL is a delayed automatic conversion signal.

[0064] The bias power supply circuit is used to generate a first bias voltage VBIAS according to the second control signal HPM_EN and the third control signal LPM_EN_DEL, and output it to the RF power amplifier unit 200 to provide a bias voltage for it. The magnitude of the first bias voltage VBIAS determines the DC operating point of the power amplifier circuit and the gain of the power amplifier module, and further determines the magnitude of the output power POUT. In the time sequence, when the power amplifier module enters the protection mechanism or exits the protection mechanism, the bias power supply circuit generates a first bias voltage VBIAS that decreases or increases in a step-like manner according to the control of the second control signal HPM_EN and the third control signal LPM_EN_DEL, and then controls the gain and output power of the power amplifier module to decrease or increase in a step-like manner.

[0065] The RF power amplifier unit 200 is used to amplify the power of the RF signal and output the amplified RF signal to the filter unit 300; the RF power amplifier unit 200 includes a power amplifier circuit and a bias circuit; wherein the input end of the power amplifier circuit is connected to the RF signal input end RFIN, the output end is connected to the input end of the filter unit 300, and the bias end is connected to the output end of the bias circuit; the input end of the bias circuit is connected to the output end of the controller unit 100.

[0066] The filter unit 300 is used to filter the amplified RF signal and output the RF signal of the required specific frequency band; the filter unit 300 includes filters for each frequency band, whose input end is connected to the output end of the RF power amplifier unit 200, and whose output end is connected to the RF signal output end RFOUT.

[0067] The functional circuits included in the controller unit 100 can be manufactured on one or more control chips, and the functional circuits included in the RF power amplifier unit 200 can also be manufactured on one or more amplifier chips. Figure 2 As shown, the circuit structure and working principle of each main functional unit are described in detail below in conjunction with the timing comparison diagram.

[0068] In one embodiment of the present invention, Figure 3As shown, the power detection circuit includes a first NMOS tube M1, a second NMOS tube M2, a first PMOS tube M3, a second PMOS tube M4, a first NPN tube Q1 and a first operational amplifier A1, as well as a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6 and a seventh resistor R7, and a first capacitor C1, a second capacitor C2 and a third capacitor C3. The radio frequency signal input terminal RFIN is connected to the first capacitor C1, the other end of the first capacitor C1 is connected to the third resistor R3 and the gate end of the first NMOS tube M1, the source end of the first NMOS tube M1 and the source end of the second NMOS tube M2 are commonly connected to the ground potential end, the gate end of the second NMOS tube M2 is connected to the other end of the third resistor R3 and the first resistor R1 and the second resistor R2 through the fourth resistor R4, the other end of the first resistor R1 is connected to the first output end of the voltage / current bias generating circuit as a bias end, and the other end of the second resistor R2 is connected to the ground potential end; the two ends of the second capacitor C2 are respectively connected to the source end and the drain end of the first NMOS tube M1, and the two ends of the third capacitor C3 are respectively connected to the source end and the drain end of the second NMOS tube M2; the drain end of the first NMOS tube M1 is connected to the power supply voltage through the fifth resistor R5. The first operational amplifier A1 is connected to the power supply voltage terminal through the sixth resistor R6, and is connected to the inverting input terminal of the first operational amplifier A1 and the drain terminal of the second PMOS tube M4 on the other hand; the drain terminal of the second NMOS tube M2 is connected to the power supply voltage terminal through the sixth resistor R6 on the one hand, and is connected to the non-inverting input terminal of the first operational amplifier A1 on the other hand; the output terminal of the first operational amplifier A1, as the output terminal of the power detection circuit, is connected to the base of the first NPN tube Q1 on the one hand, and is connected to the input terminal of the voltage hysteresis comparator on the other hand; the emitter of the first NPN tube Q1 is connected to the ground potential terminal through the seventh resistor R7, the collector of the first NPN tube Q1 is connected to the drain terminal of the first PMOS tube M3, the gate terminal and the drain terminal of the first PMOS tube M3 are connected in parallel and then connected to the gate terminal of the second PMOS tube M4, and the source terminals of the first PMOS tube M3 and the second PMOS tube M4 are both connected to the power supply voltage terminal.

[0069] In the power detection circuit, the first NMOS tube M1 and the second NMOS tube M2, the third resistor R3 and the fourth resistor R4, the second capacitor C2 and the third capacitor C3, the fifth resistor R5 and the sixth resistor R6 are symmetrically arranged, and the electrical parameters are the same. The first capacitor C1 is a DC isolation capacitor, and the second capacitor C2 is a filter capacitor. The input power PIN of the radio frequency signal is coupled to the gate end of the first NMOS tube M1 through the first capacitor C1; the second bias voltage VG provided by the voltage / current bias generation circuit provides a DC static operating point for the first NMOS tube M1 and the second NMOS tube M2 through the voltage division of the first resistor R1 and the second resistor R2, so that the first NMOS tube M1 and the second NMOS tube M2 work in the saturation region, and the current and voltage thereof satisfy the square law characteristic; the third resistor R3 and the fourth resistor R4 are used to isolate the gate ends of the first NMOS tube M1 and the second NMOS tube M2, so as to prevent the radio frequency signal coupled to the gate end of the first NMOS tube M1 from affecting the second NMOS tube M2, and the fifth resistor R5 and the sixth resistor R6 are used as the loads of the first NMOS tube M1 and the second NMOS tube M2 respectively. The first operational amplifier A1 is used as a deviation amplifier. When the input power PIN changes, the inverting input terminal of the first operational amplifier A1 will generate a corresponding current / voltage offset, and the output terminal of the first operational amplifier A1 will generate a corresponding detection voltage VDET; at the same time, the first NPN tube Q1 converts the change of the detection voltage VDET into a current signal according to an exponential relationship, and the current signal is mirrored into a feedback current IFB through a current mirror structure formed by the first PMOS tube M3 and the second PMOS tube M4, and fed back to the inverting input terminal of the first operational amplifier A1. The seventh resistor R7 is used to adjust the DC operating point of the first NPN tube Q1 so that it works in the amplification area within the input power range of interest and satisfies the state of the current and voltage exponential law characteristics.

[0070] In the power detection circuit, different input powers PIN generate different current / voltage offsets at the inverting input terminal of the first operational amplifier A1, different current / voltage offsets generate different detection voltages VDET, and different detection voltages VDET generate different feedback currents IFB. Since the input power PIN and the current / voltage offset satisfy a square law characteristic relationship, and the detection voltage VDET and the feedback current IFB satisfy an exponential law characteristic relationship, when the current / voltage offset and the feedback current IFB act together on the inverting input terminal of the first operational amplifier A1, the output detection voltage VDET and the input power PIN have a logarithmic linear relationship.

[0071] In one embodiment of the present invention, Figure 4As shown, the voltage hysteresis comparator circuit includes PMOS transistors 403 ˜ 406 , 411 ˜ 416 , and NMOS transistors 401 , 402 , 407 , 408 , 409 , 410 and an inverter 417 . Among them, the output end of the power detection circuit (i.e., the detection voltage VDET signal end) is connected to the gate ends of the PMOS tubes 414 and 415 (i.e., the input end of the voltage hysteresis comparator), the second output end of the voltage / current bias generating circuit (i.e., the reference voltage VREF signal end) is connected to the gate ends of the PMOS tubes 411 and 412 (i.e., the reference voltage end of the voltage hysteresis comparator), and the third output end of the voltage / current bias generating circuit (i.e., the bias current IB2 signal end) is connected to the drain end of the NMOS tube 401 (i.e., the bias end of the voltage hysteresis comparator); the drain end of the PMOS tube 406, the gate end of the PMOS tube 416 and the drain end of the NMOS tube 410 are connected in parallel with each other as the output end of the voltage hysteresis comparator, which is connected to the input end of the ladder logic control circuit on the one hand and to the inverter 417 on the other hand.

[0072] The first control signal ODP_EN output by the voltage hysteresis comparator is passed through the inverter 417 to obtain an inverted signal ODP_ENB. Figure 5 As shown, the voltage corresponding to the set first threshold value Pth1 is the first voltage V1, the voltage corresponding to the second threshold value Pth2 is the second voltage V2, and the first voltage V1> the second voltage V2. When the detection voltage VDET increases from a low voltage until it reaches the first voltage V1, the PMOS tubes 413 and 412 are in the cut-off state, the PMOS tubes 416 and 415 are in the on state, the first control signal ODP_EN output by the voltage hysteresis comparator is maintained at a low level, and the inverse signal ODP_ENB is a high level. When the detection voltage VDET decreases from a high voltage until it reaches the second voltage V2, the PMOS tubes 413 and 412 are in the on state, the PMOS tubes 416 and 415 are in the cut-off state, the first control signal ODP_EN output by the voltage hysteresis comparator is maintained at a high level, and the inverse signal ODP_ENB is a low level. Therefore, the number of input pairs corresponding to the increase and decrease of the detection voltage VDET is different, so that the flip threshold of the voltage comparator is different, thereby producing a hysteresis effect, and the hysteresis width can be changed by adjusting the size of the PMOS tubes 411, 412, 414, and 415 to avoid repeated switching of the protection mechanism due to fluctuations in the input power.

[0073] In one embodiment of the present invention, Figure 6As shown, the ladder logic control circuit includes a first inverter 501, a second inverter 503, a third inverter 504, a fourth inverter 506, a fifth inverter 507, a sixth inverter 508, a seventh inverter 509 and an eighth inverter 512, as well as a first AND gate 510, a second AND gate 513 and a first OR gate 511, a filter module 502 and a delay module 505. Among them, the output end of the voltage hysteresis comparator (i.e., the first control signal ODP_EN end) is connected to the input end of the filter module 502 through the first inverter 501, the first output end of the filter module 502 is connected to the input end of the delay module 505 through the second inverter 503 and the third inverter 504 in sequence, and the output end of the delay module 505 is connected to the first input end of the first AND gate 510 on the one hand, and to the first input end of the first OR gate 511 on the other hand through the fourth inverter 506 and the fifth inverter 507 in sequence; the filter module The second output end of 502 is connected to the second input end of the first AND gate 510 and the second input end of the first OR gate 511 respectively through the sixth inverter 508 and the seventh inverter 509; the output end of the first AND gate 510 is connected to the first output end of the ladder logic control circuit on the one hand, and is connected to the first input end of the second AND gate 513 through the eighth inverter 512 on the other hand, the output end of the first OR gate 511 is connected to the second input end of the second AND gate 513, and the output end of the second AND gate 513 is the second output end of the ladder logic control circuit.

[0074] In the ladder logic control circuit, the first control signal ODP_EN generates an inverse signal ODP_ENB through the first inverter 501, and the filter module 502 is used to filter out short-term glitches or pulses of the inverse signal ODP_ENB to avoid false triggering of the protection mechanism due to short-term jitter of the input power PIN. The function of the delay module 505 is to use the delay time t generated by it to realize the delayed automatic conversion of the third control signal LPM_EN_DEL, that is, the delay time t determines the duration of the first bias voltage VBIAS output by the bias power supply circuit to remain at the lower voltage VLPM when the change occurs. The filter module 502 and the delay module 505 can both be composed of RC circuits.

[0075] References Figure 2As shown in the timing control diagram, before the input power PIN increases but does not reach the first threshold value Pth1, the first control signal ODP_EN output by the voltage hysteresis comparator is at a low level, and the inverted signal ODP_ENB is at a high level. After the inverted signal ODP_ENB passes through the filtering module 502, on the one hand, it passes through the second inverter 503 and the third inverter 504, the delay module 505, the fourth inverter 506 and the fifth inverter 507, so that the first input terminal of the first AND gate 510 is at a high level and the first input terminal of the first OR gate 511 is at a high level; on the other hand, through the first After the sixth inverter 508 and the seventh inverter 509, the second input terminal of the first AND gate 510 is at a high level and the second input terminal of the first OR gate 511 is at a high level; therefore, the second control signal HPM_EN output by the first AND gate 510 is at a high level. After the second control signal HPM_EN passes through the eighth inverter 512, the first input terminal of the second AND gate 513 is at a low level. The first OR gate 511 outputs a high level, that is, the second input terminal of the second AND gate 513 is at a high level. Therefore, the third control signal LPM_EN_DEL output by the second AND gate 513 is at a low level.

[0076] When the input power PIN increases to the first threshold value Pth1, the first control signal ODP_EN output by the voltage hysteresis comparator jumps from a low level to a high level, and the inverse signal ODP_ENB is a low level. After the inverse signal ODP_ENB passes through the filtering module 502, it first passes through the sixth inverter 508 and the seventh inverter 509, so that the second input terminal of the first AND gate 510 is a low level and the second input terminal of the first OR gate 511 is a low level; therefore, the second control signal HPM_EN output by the first AND gate 510 jumps from a high level to a low level; at the same time, after the second control signal HPM_EN passes through the eighth inverter 512, the first input terminal of the second AND gate 513 becomes a high level, so the third control signal LPM_EN_DEL output by the second AND gate 513 jumps from a low level to a high level. After the delay time t, the inverted signal ODP_ENB passes through the second inverter 503 and the third inverter 504, the delay module 505, the fourth inverter 506 and the fifth inverter 507, so that the first input terminal of the first AND gate 510 becomes a low level and the first input terminal of the first OR gate 511 becomes a low level; at this time, the second control signal HPM_EN output by the first AND gate 510 remains at a low level, and the output of the first OR gate 511 becomes a low level, so the third control signal LPM_EN_DEL output by the second AND gate 513 becomes a low level.

[0077] It can be seen from the above analysis that when the input power PIN increases to the first threshold value Pth1, the third control signal LPM_EN_DEL changes from the original low level to the high level, maintains a delay time t, and then automatically jumps to the low level again. That is to say, the third control signal LPM_EN_DEL is a delayed automatic conversion signal, and the delay time t maintained during the transition determines the duration that the first bias voltage VBIAS output by the bias power supply circuit remains at the lower voltage VLPM.

[0078] When the input power PIN decreases to the second threshold value Pth2, the first control signal output by the voltage hysteresis comparator changes from a high level to a low level; at this time, the third control signal output by the ladder logic control circuit changes from a low level to a high level, and after a set delay time, the third control signal changes to a low level, and at the same time, the second control signal changes from a low level to a high level. The specific changes of each component in the ladder logic control circuit are similar to the above process, and will not be repeated here.

[0079] In one embodiment of the present invention, Figure 7 As shown, the bias power supply circuit includes an error amplifier 603, a power tube 604, a first transmission gate 601 and a second transmission gate 602, as well as a tenth resistor R10, an eleventh resistor R11 and a twelfth resistor R12; wherein, the in-phase input terminal of the error amplifier 603 (i.e., the first input terminal of the bias power supply circuit) is connected to the second output terminal of the bandgap reference circuit, the output terminal of the error amplifier 603 is connected to the gate terminal of the power tube 604, the source terminal of the power tube 604 and the power supply terminal of the error amplifier 603 are both connected to the power supply voltage terminal, the drain terminal of the power tube 604 is connected to the tenth resistor R10 as the output terminal of the bias power supply circuit, and the tenth resistor R11 is connected to the gate terminal of the power tube 604. 0, the eleventh resistor R11 and the twelfth resistor R12 are connected in series in sequence, and the other end of the tenth resistor R12 is connected to the ground potential end; the connection node of the tenth resistor R10 and the eleventh resistor R11 is connected to the input end of the second transmission gate 602, the connection node of the eleventh resistor R11 and the twelfth resistor R12 is connected to the input end of the first transmission gate 601, the output ends of the first transmission gate 601 and the second transmission gate 602 are both connected to the inverting input end of the error amplifier 603, the control end of the first transmission gate 601 is connected to the first output end of the ladder logic control circuit, and the control end of the second transmission gate 602 is connected to the second output end of the ladder logic control circuit. Among them, the tenth resistor R10, the tenth resistor R11 and the tenth resistor R12 constitute a resistor feedback network.

[0080] Under normal working conditions, the ladder logic control circuit outputs the second control signal HPM_EN as a high level, and the third control signal LPM_EN_DEL as a low level. Therefore, the first transmission gate 601 is turned on, the second transmission gate 602 is turned off, and the feedback voltage VBK input to the error amplifier 603 is the voltage on the twelfth resistor R12. At this time, the first bias voltage VBIAS output by the bias power supply circuit is a higher voltage VHPM.

[0081] When the input power PIN increases to the first threshold value Pth1, the ladder logic control circuit outputs the second control signal HPM_EN which jumps from a high level to a low level, and at the same time, the third control signal LPM_EN_DEL jumps from a low level to a high level, so the first transmission gate 601 is turned off, the second transmission gate 602 is turned on, and the feedback voltage VBK input to the error amplifier 603 is the voltage across the tenth resistor R11 and the tenth resistor R12. The feedback voltage VBK increases, so the first bias voltage VBIAS output by the bias power supply circuit is reduced to a lower voltage VLPM. After the delay time t, the third control signal LPM_EN_DEL jumps from a high level to a low level, and the second transmission gate 602 is also turned off. At this time, the feedback voltage VBK input to the error amplifier 603 is zero, so the first bias voltage VBIAS output by the bias power supply circuit drops to zero volts.

[0082] It can be seen from the above analysis that when the input power PIN increases to the first threshold value Pth1, the first bias voltage VBIAS output by the bias power supply circuit decreases in steps, that is, from a higher voltage VHPM to a lower voltage VLPM, and then decreases to zero voltage after a delay time t. The first bias voltage VBIAS is provided to the RF power amplifier unit 200, so that the working state of the RF power amplifier unit 200 changes accordingly. When the input power PIN decreases to the second threshold value Pth2, the change of the bias power supply circuit is similar to the above process, which will not be repeated here.

[0083] It should be noted that the voltage values ​​of the lower voltage VLPM and the higher voltage VHPM of the first bias voltage VBIAS output by the bias power supply circuit can be achieved by adjusting the values ​​of the series resistors in the resistor feedback network according to specific needs.

[0084] In the power amplifier module provided in the embodiment of the present invention, the power detection circuit detects the input power PIN of the input radio frequency signal in real time, as shown in FIG. Figure 2 The timing comparison diagram of each functional unit is shown below. The working process and working principle of the overall step protection mechanism of the power amplifier module when the input power PIN changes are described in detail.

[0085] When the input power PIN of the RF signal increases to the first threshold value Pth1, the detection voltage VDET output by the power detection circuit is greater than or equal to the reference voltage VREF, and the power amplifier module triggers the step protection mechanism. At this time, the first control signal ODP_EN output by the voltage hysteresis comparator jumps from a low level to a high level; the second control signal HPM_EN output by the step logic control circuit jumps from a high level to a low level, and at the same time, the third control signal LPM_EN_DEL jumps from a low level to a high level, and then jumps to a low level after maintaining the set delay time. The bias power supply circuit controls the resistor feedback network coefficient according to the second control signal HPM_EN and the third control signal LPM_EN_DEL, so that the bias The first bias voltage VBIAS output by the power supply circuit is reduced in steps in a step-by-step manner, that is, it is reduced from a higher voltage VHPM to a lower voltage VLPM, and then reduced to zero voltage after a set delay time; the RF power amplifier unit establishes a corresponding DC operating point according to the change of the first bias voltage VBIAS, so that the gain Gain of the power amplifier module is reduced in steps in a step-by-step manner, that is, it is reduced from a higher gain H_Gain to a lower gain L_Gain, and then reduced to zero gain after a set delay time, and the output power POUT is reduced in steps in a step-by-step manner, that is, it is reduced from a higher power H_Power to a lower power L_Power, and then reduced to zero power after a set delay time.

[0086] When the input power PIN decreases to the second threshold value Pth2, the detection voltage VDET output by the power detection circuit is less than the reference voltage VREF, and the power amplifier module exits the step protection mechanism. At this time, the first control signal ODP_EN output by the voltage hysteresis comparator jumps from a high level to a low level; the third control signal LPM_EN_DEL output by the step logic control circuit jumps from a low level to a high level, and then jumps to a low level after maintaining the set delay time. At the same time, the second control signal HPM_EN jumps from a low level to a high level; the bias power supply circuit controls the resistor feedback network coefficient according to the second control signal HPM_EN and the third control signal LPM_EN_DEL, so that the bias power supply circuit The first bias voltage VBIAS output by the circuit increases in steps in a step-by-step manner, that is, it increases from zero voltage to a lower voltage VLPM, and then increases to a preset higher voltage VHPM after a set delay time; the RF power amplifier unit establishes a corresponding DC operating point according to the change of the first bias voltage VBIAS, so that the gain Gain of the power amplifier module increases in steps in a step-by-step manner, that is, it increases from zero gain to a lower gain L_Gain, and then increases to a higher gain H_Gain after a set delay time, and the output power POUT increases in steps in a step-by-step manner, that is, it increases from zero power to a lower power L_Power, and then increases to a higher power H_Power after a set delay time.

[0087] The power amplifier module adopts the above-mentioned step protection mechanism for power protection, which can avoid the power amplifier or filter from burning out and failing when the power amplifier suddenly changes from high power to low power or zero power, or when it suddenly changes from zero power or low power to high power, thereby improving the working reliability of the power amplifier module.

[0088] The embodiment of the present invention further provides an electronic device, which includes the above-mentioned power amplifier module, which can be used as an important component of the communication component. The electronic device mentioned here refers to a computer device that can be used in a mobile environment and supports multiple communication formats such as GSM, EDGE, CDMA, TD_SCDMA, WCDMA, TDD_LTE, FDD_LTE, NR, etc., including mobile phones, laptops, tablet computers, car computers, etc. In addition, the technical solution provided by the present invention is also applicable to other occasions where radio frequency integrated circuits are applied, such as communication base stations, intelligent networked vehicles, etc.

[0089] like Figure 8 As shown, the electronic device at least includes a processor, a memory and a communication component, and may further include a sensor component, a power component, a multimedia component and an input / output interface according to actual needs. Among them, the memory, the communication component, the sensor component, the power component, the multimedia component and the input / output interface are all connected to the processor. The memory may be a static random access memory (SRAM), an electrically erasable programmable read-only memory (EEPROM), an erasable programmable read-only memory (EPROM), a programmable read-only memory (PROM), a read-only memory (ROM), a magnetic memory, a flash memory, etc., and the processor may be a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processing (DSP) chip, etc. Other communication components, sensor components, power components, multimedia components, etc. may all be implemented using general components, which will not be specifically described here.

[0090] In summary, compared with the prior art, the present invention realizes fine bias control of the RF power amplifier unit through the coordinated work of the power detection circuit and the ladder logic control circuit in the controller unit. When the input power changes significantly, such as rising to a preset first threshold or falling to a second threshold, the controller unit can generate a corresponding control signal to adjust the bias voltage in steps in a ladder-like manner, so that the gain and output power of the power amplifier module can change smoothly accordingly, avoiding the risk of device damage caused by power mutation. This ladder protection mechanism not only improves the working reliability of the power amplifier module under extreme conditions, but also helps to extend the service life of the equipment and maintain the stability of communication quality. In addition, the circuit design of the present invention is ingenious and reasonable, low cost, suitable for electronic equipment of various communication standards, and has broad application prospects and market potential.

[0091] It should be noted that the embodiments of the above-mentioned multiple functional circuits are only examples, and other circuit technical solutions can also be used to achieve the same functional effects, all of which are within the protection scope of the present invention.

[0092] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0093] The above is a detailed description of the circuit for implementing power protection and the corresponding power amplifier module and electronic equipment provided by the present invention. For those skilled in the art, any obvious changes made to it without departing from the essence of the present invention will constitute an infringement of the patent right of the present invention and will bear corresponding legal responsibilities.

Claims

1. A power detection circuit, used in a power amplifier module, characterized in that It includes a first NMOS tube, a second NMOS tube, a first PMOS tube, a second PMOS tube, a first NPN tube and a first operational amplifier, as well as a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor and a seventh resistor, and a first capacitor, a second capacitor and a third capacitor; wherein, The RF signal input terminal is connected to the first capacitor, the other end of the first capacitor is connected to the third resistor and the gate end of the first NMOS tube, the source end of the first NMOS tube and the source end of the second NMOS tube are commonly connected to the ground potential terminal, the gate end of the second NMOS tube is connected to the other end of the third resistor and the first resistor and the second resistor through the fourth resistor, the other end of the first resistor is connected to the first output end of the voltage / current bias generating circuit as a bias end, and the other end of the second resistor is connected to the ground potential end; the two ends of the second capacitor are respectively connected to the source end and the drain end of the first NMOS tube, and the two ends of the third capacitor are respectively connected to the source end and the drain end of the second NMOS tube; the drain end of the first NMOS tube is connected to the power supply voltage end through the fifth resistor on the one hand, and the other end of the power supply voltage end is connected to the power supply voltage end through the fifth resistor on the other hand. The surface is connected to the inverting input terminal of the first operational amplifier and the drain terminal of the second PMOS tube; the drain terminal of the second NMOS tube is connected to the power supply voltage terminal through the sixth resistor on the one hand, and is connected to the non-inverting input terminal of the first operational amplifier on the other hand; the output terminal of the first operational amplifier is connected to the base of the first NPN tube as the output terminal of the power detection circuit on the one hand, and is connected to the input terminal of the voltage hysteresis comparator on the other hand; the emitter of the first NPN tube is connected to the ground potential terminal through the seventh resistor, the collector of the first NPN tube is connected to the drain terminal of the first PMOS tube, the gate terminal and the drain terminal of the first PMOS tube are connected in parallel and then connected to the gate terminal of the second PMOS tube, and the source terminals of the first PMOS tube and the second PMOS tube are both connected to the power supply voltage terminal.

2. The power detection circuit according to claim 1, characterized in that: The first NMOS transistor and the second NMOS transistor, the third resistor and the fourth resistor, the second capacitor and the third capacitor, and the fifth resistor and the sixth resistor are symmetrically arranged and have the same electrical parameters.

3. The power detection circuit according to claim 2, characterized in that: The first NMOS transistor and the second NMOS transistor operate in a saturation region, and their current and voltage satisfy a square law characteristic; The first NPN transistor operates in the amplification region, and its current and voltage satisfy exponential law characteristics.

4. The power detection circuit as claimed in claim 3, characterized in that: The input power of the RF signal generates a current / voltage offset at the inverting input terminal of the first operational amplifier. When the current / voltage offset and the feedback current act together on the inverting input terminal of the first operational amplifier, a logarithmic linear relationship is formed between the output detection voltage and the input power.

5. A ladder logic control circuit, used in a power amplifier module, characterized in that It includes a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter and an eighth inverter, as well as a first AND gate, a second AND gate and a first OR gate, as well as a filtering module and a delay module; wherein, The first output end of the filter module is connected to the input end of the delay module through the second inverter and the third inverter in sequence, and the output end of the delay module is connected to the first input end of the first AND gate on the one hand and to the first input end of the first OR gate on the other hand in sequence through the fourth inverter and the fifth inverter; The second output end of the filtering module is connected to the second input end of the first AND gate and the second input end of the first OR gate respectively through the sixth inverter and the seventh inverter; the output end of the first AND gate is connected to the first output end of the ladder logic control circuit on the one hand, and is connected to the first input end of the second AND gate through the eighth inverter on the other hand, the output end of the first OR gate is connected to the second input end of the second AND gate, and the output end of the second AND gate is the second output end of the ladder logic control circuit.

6. The ladder logic control circuit according to claim 5, characterized in that: The filtering module is used to filter out the glitches or pulses of the inverse signal of the first control signal to avoid false triggering of the protection mechanism due to short-term jitter of the input power; The delay module is used to generate a delay time to achieve the continuation of the first bias voltage at a lower voltage level.

7. A power amplifier module, characterized in that It includes a controller unit, a radio frequency power amplifier unit and a filter unit; wherein, The RF signal input end is connected to the input end of the controller unit and the RF power amplifier unit respectively, the output end of the controller unit is connected to the bias of the RF power amplifier unit, the output end of the RF power amplifier unit is connected to the input end of the filter unit, and the output end of the filter unit is connected to the RF signal output end; The controller unit comprises the power detection circuit described in any one of claims 1 to 4 or the ladder logic control circuit described in any one of claims 5 to 6, and is used to provide a bias voltage for the radio frequency power amplifier unit.

8. A power amplifier module, characterized in that It includes a controller unit, a radio frequency power amplifier unit and a filter unit; wherein, The RF signal input end is connected to the input end of the controller unit and the RF power amplifier unit respectively, the output end of the controller unit is connected to the bias of the RF power amplifier unit, the output end of the RF power amplifier unit is connected to the input end of the filter unit, and the output end of the filter unit is connected to the RF signal output end; The controller unit is used to provide a bias voltage for the RF power amplifier unit, and includes a bandgap reference circuit, a voltage / current bias generating circuit, a voltage hysteresis comparator, a bias power supply circuit, a power detection circuit as described in any one of claims 1 to 4, and a ladder logic control circuit as described in any one of claims 5 to 6; wherein, The bandgap reference circuit is used to generate and output a first reference voltage and a second reference voltage, respectively providing reference voltages for the voltage / current bias generating circuit and the bias power supply circuit; The voltage / current bias generating circuit is used to generate and output a second bias voltage to the power detection circuit, and to generate and output a reference voltage and a bias current to the voltage hysteresis comparator; The power detection circuit is used to detect the power of the input radio frequency signal, generate a detection voltage after conversion, and output it to the voltage hysteresis comparator; The voltage hysteresis comparator is used to generate the first control signal after comparing the detection voltage with the reference voltage, and output the first control signal to the ladder logic control circuit; The ladder logic control circuit is used to generate the second control signal and the third control signal after logical combination according to the first control signal, and output them to the bias power supply circuit; The bias power supply circuit is used to generate the first bias voltage according to the second control signal and the third control signal, and output it to the RF power amplifier unit to provide a bias voltage therefor.

9. The power amplifier module according to claim 8, wherein: The RF power amplifier unit is used to amplify the power of the RF signal and output the amplified RF signal to the filter unit; The filter unit is used to filter the amplified radio frequency signal and output a radio frequency signal of a specific frequency band.

10. The power amplifier module according to claim 8, wherein: The first output end of the bandgap reference circuit is connected to the input end of the voltage / current bias generating circuit, and the second output end is connected to the first input end of the bias power supply circuit; the first output end of the voltage / current bias generating circuit is connected to the bias end of the power detection circuit, and the second output end and the third output end are respectively connected to the reference voltage end and the bias end of the voltage hysteresis comparator; the input end of the power detection circuit is connected to the RF signal input end, and the output end is connected to the input end of the voltage hysteresis comparator; the output end of the voltage hysteresis comparator is connected to the input end of the ladder logic control circuit, and is connected to the input end of the filtering module through a first inverter; the output end of the ladder logic control circuit is connected to the second input end of the bias power supply circuit, and the output end of the bias power supply circuit is connected to the bias end of the RF power amplifier unit.

11. The power amplifier module according to claim 8, wherein: The bias power supply circuit includes an error amplifier, a power tube, a first transmission gate and a second transmission gate, and a tenth resistor, an eleventh resistor and a twelfth resistor; wherein the non-inverting input terminal of the error amplifier is connected to the second output terminal of the bandgap reference circuit, the output terminal of the error amplifier is connected to the gate terminal of the power tube, the source terminal of the power tube and the power supply terminal of the error amplifier are both connected to the power supply voltage terminal, the drain terminal of the power tube is connected to the tenth resistor as the output terminal of the bias power supply circuit, the tenth resistor, the eleventh resistor and the twelfth resistor are connected in series in sequence, and the other end of the tenth resistor is connected to the ground potential terminal; the connection node of the tenth resistor and the eleventh resistor is connected to the input terminal of the second transmission gate, the connection node of the eleventh resistor and the twelfth resistor is connected to the input terminal of the first transmission gate, the output terminals of the first transmission gate and the second transmission gate are both connected to the inverting input terminal of the error amplifier, the control terminal of the first transmission gate is connected to the first output terminal of the ladder logic control circuit, and the control terminal of the second transmission gate is connected to the second output terminal of the ladder logic control circuit.

12. The power amplifier module according to claim 8, wherein: When the input power of the RF signal increases to a first threshold value or decreases to a second threshold value, the controller unit generates corresponding first control signals, second control signals and third control signals to control the first bias voltage output by the controller unit to decrease or increase in steps in a step-by-step manner, thereby causing the gain and output power of the power amplifier module to decrease or increase in steps accordingly; wherein the first threshold value is greater than the second threshold value.

13. The power amplifier module according to claim 12, wherein: When the input power increases to the first threshold value, the first control signal output by the voltage hysteresis comparator jumps from a low level to a high level; at this time, the second control signal output by the ladder logic control circuit jumps from a high level to a low level; the third control signal jumps from a low level to a high level, and after a set delay time, the third control signal jumps to a low level.

14. The power amplifier module according to claim 12, wherein: When the input power decreases to the second threshold, the first control signal output by the voltage hysteresis comparator jumps from a high level to a low level; at this time, the third control signal output by the ladder logic control circuit jumps from a low level to a high level, and after a set delay time, the third control signal jumps to a low level, and at the same time, the second control signal jumps from a low level to a high level.

15. The power amplifier module according to claim 12, wherein: When the input power increases to the first threshold, the first bias voltage output by the bias power supply circuit decreases and drops to zero after a set delay time; When the input power decreases to the second threshold, the first bias voltage output by the bias power supply circuit increases, and increases to a preset value after a set delay time.

16. The power amplifier module according to claim 12, wherein: When the input power increases to the first threshold, the gain of the power amplifier module decreases and drops to zero after a set delay time; When the input power decreases to the second threshold, the gain of the power amplifier module increases, and increases to a preset value after a set delay time.

17. The power amplifier module according to claim 12, wherein: When the input power increases to the first threshold, the output power of the power amplifier module decreases and drops to zero after a set delay time; When the input power decreases to the second threshold, the output power of the power amplifier module increases, and increases to a preset value after a set delay time.

18. An electronic device, characterized in that A power amplifier module comprising claim 7 or any one of claims 8 to 17.

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