Jitter injection circuit, analog-to-digital converter, chip and electronic device

Abstract

The invention discloses a jitter injection circuit, an analog-to-digital converter, a chip and electronic equipment, the jitter injection circuit comprises a jitter injection module connected with an input tube of a quantizer, the jitter injection module comprises at least two current branches, the at least two current branches are connected with the input tube, and the current branches are connected with the input tube. The jitter injection module is used for controlling the on-off state of the at least two current branches according to the control signal and outputting an adjustable current signal to the input tube so as to inject imbalance jitter to the analog-to-digital converter. According to the jitter injection circuit, the magnitude of the adjustable current signal output to the input tube is adjusted by controlling the on-off state of the current branch through the control signal, so that the amplitude adjustment of the offset jitter injected to the quantizer is realized, the control is convenient and fast, the implementation is easy, different application requirements can be met, and the application scene of the jitter injection circuit is expanded.

Description

Technical Field

[0001] The present application relates to the technical field of analog-to-digital conversion, and in particular to a jitter injection circuit, an analog-to-digital converter, a chip and an electronic device. Background Art

[0002] The main function of analog to digital converters (ADCs) is to convert analog signals (such as voltage and current) into digital signals to quantize analog signals. ADCs are important functional modules for communications, instrument measurement, and sensor control systems, and are widely used in the fields of analog integrated circuits and mixed analog and digital integrated circuits.

[0003] Delta Sigma Analog to Digital Converters (DSADC) is a type of ADC. When the input signal frequency of a conventional DSADC is low or the variation amplitude is small, some periodic code streams will appear in the output of its quantizer, resulting in idle tones in the spectrum of the output digital signal, which significantly degrades the frequency domain characteristics of the digital signal.

[0004] In the related art, an adder is added between the integrator and quantizer of the DSADC, and jitter is added by means of the adder to destroy the periodic bit stream to suppress the idle tone. However, different application scenarios have different requirements for jitter amplitude, and the current method is not convenient for adjusting the jitter amplitude. Therefore, its application scope has certain limitations. Summary of the invention

[0005] In view of the above problems, the present application provides a jitter injection circuit, an analog-to-digital converter, a chip and an electronic device to solve the above technical problems.

[0006] In a first aspect, the present application provides a jitter injection circuit for injecting offset jitter into an analog-to-digital converter, the analog-to-digital converter at least comprising a quantizer, the jitter injection circuit comprising a jitter injection module connected to an input tube of the quantizer;

[0007] The jitter injection module includes at least two current branches, which are connected to the input tube. The jitter injection module is used to control the on-off state of the at least two current branches according to the control signal, and output an adjustable current signal to the input tube to inject offset jitter into the analog-to-digital converter.

[0008] The jitter injection circuit can adjust the size of the adjustable current signal output to the input tube by controlling the on-off state of the current branch through a control signal, thereby realizing the amplitude adjustment of the offset jitter injected into the quantizer. The control is convenient and easy to implement, and can adapt to different application requirements, thus expanding the application scenarios of the jitter injection circuit.

[0009] In a second aspect, the present application also provides an analog-to-digital converter, including a quantizer and the above-mentioned jitter injection circuit.

[0010] In a third aspect, the present application also provides a chip, comprising the above-mentioned jitter injection circuit or analog-to-digital converter.

[0011] In a fourth aspect, the present application also provides an electronic device, including a device body and the above-mentioned chip, analog-to-digital converter or jitter injection circuit arranged in the device body.

[0012] The jitter injection circuit provided in the present application adjusts the on-off state of each current branch according to the control signal, thereby adjusting the size of the adjustable current signal output to the quantizer input tube to achieve the amplitude adjustment of the quantizer offset jitter. The circuit structure is simple, the control is convenient, and it is easy to implement. It can adapt to different application requirements, improve the flexibility of the jitter injection circuit, and expand the application scenarios of the jitter injection circuit.

[0013] These and other aspects of the present application will become more clearly understood in the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0015] Figure 1 It is a basic structural diagram of a delta-sigma analog-to-digital converter;

[0016] Figure 2 It is a structural schematic diagram of a DSADC in the related art that adds jitter to suppress open string sound;

[0017] Figure 3 It is a structural schematic diagram of adding jitter through the input end of the adder vectorizer in the related art;

[0018] Figure 4 is a schematic diagram of an application scenario of the jitter injection circuit provided in an embodiment of the present application;

[0019] Figure 5 is a module schematic diagram of a jitter injection circuit provided in an embodiment of the present application;

[0020] Figure 6 is another module schematic diagram of the jitter injection circuit provided in an embodiment of the present application;

[0021] Figure 7 This is a schematic diagram of the first structure of the jitter injection module provided in the embodiment of the present application;

[0022] Figure 8 This is a second structural diagram of the jitter injection module provided in an embodiment of the present application;

[0023] Fig. 9 This is a schematic diagram of the first structure of the current branch provided in the embodiment of the present application;

[0024] Fig.10 is a second structural schematic diagram of the current branch provided in the embodiment of the present application;

[0025] Fig.11 is a third structural schematic diagram of the current branch provided in the embodiment of the present application;

[0026] Fig.12 is a fourth structural schematic diagram of the current branch provided in the embodiment of the present application;

[0027] Fig.13 This is a fifth structural diagram of the current branch provided in the embodiment of the present application

[0028] Fig.14 is a sixth structural schematic diagram of the current branch provided in the embodiment of the present application;

[0029] Fig.15 This is a schematic diagram of a first connection structure between a jitter injection module and an input tube provided in an embodiment of the present application;

[0030] Fig.16 This is a schematic diagram of a second connection structure between the jitter injection module and the input tube provided in an embodiment of the present application;

[0031] Fig.17 This is a schematic diagram of a third connection structure between a jitter injection module and an input tube provided in an embodiment of the present application;

[0032] Fig.18 is a circuit structure diagram of a jitter injection circuit provided in an embodiment of the present application;

[0033] Fig.19 This is another circuit structure schematic diagram of a jitter injection circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0034] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0035] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application.

[0036] In the embodiments of the present application, it should be noted that, in this article, relational terms such as first and second, etc. are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0037] Moreover, the terms "comprises," "comprising," or any other variation thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0038] In the description of the embodiments of the present application, words such as "example" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "example" or "for example" in the embodiments of the present application is not to be interpreted as being more preferred or having more advantages than another embodiment or design. The use of words such as "example" or "for example" is intended to present relative concepts in a clear manner.

[0039] In addition, the "plurality" in the embodiments of the present application refers to two or more than two. In view of this, in the embodiments of the present application, "plurality" can also be understood as "at least two". "At least one" can be understood as one or more, for example, one, two or more. For example, including at least one means including one, two or more, and there is no limit on which ones are included. For example, including at least one of A, B and C, then A, B, C, A and B, A and C, B and C, or A, B and C can be included.

[0040] It should be noted that, in the embodiments of the present application, "and / or" describes the association relationship of the associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / ", unless otherwise specified, generally indicates that the associated objects before and after are in an "or" relationship.

[0041] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.

[0042] The first pole / first end of each transistor used in the embodiments of the present application is one of the source and the drain, and the second pole / second end of each transistor is the other of the source and the drain. Since the source and drain of the transistor can be symmetrical in structure, the source and drain thereof can be structurally indistinguishable, that is, the first pole / first end and the second pole / second end of the transistor in the embodiments of the present application can be structurally indistinguishable. Exemplarily, in the case where the transistor is a P-type transistor, the first pole / first end of the transistor is the source, and the second pole / second end is the drain; exemplarily, in the case where the transistor is an N-type transistor, the first pole / first end of the transistor is the drain, and the second pole / second end is the source.

[0043] Before introducing the jitter injection circuit, analog-to-digital converter, chip and electronic device of the present application, relevant background information of the embodiments of the present application is first introduced.

[0044] The main function of analog to digital converters (ADCs) is to convert analog signals (such as voltage and current) into digital signals to quantize analog signals. ADCs are important functional modules for communications, instrument measurement, and sensor control systems, and are widely used in the fields of analog integrated circuits and mixed analog and digital integrated circuits.

[0045] Delta Sigma Analog to Digital Converters (DSADC) is a type of ADC, which mainly includes an integrator, a quantizer, a digital to analog converter (DAC) and a digital filter. Its basic structure is as follows Figure 1 As shown, Vin is the analog input signal, and Dout is the final digital output code, that is, the digital output signal.

[0046] When the input signal frequency of a conventional DSADC is low or the amplitude of change is small, some periodic code streams will appear in the output of the quantizer, resulting in open string sounds in the spectrum of the digital output signal output by the digital filter, which significantly reduces the frequency domain characteristics of the digital output signal. Moreover, the frequency point of the open string sound is not fixed. With the difference of the analog input signal and the period of the code stream, the frequency point of the open string sound is naturally different, which means that the open string sound cannot be suppressed at a fixed frequency point through the filter.

[0047] This problem is common in DSADCs of different architectures. Whether it is a high-order DSADC or a low-order DSADC, single-bit quantization or multi-bit quantization, there are open string sounds of varying degrees of severity.

[0048] To solve this problem, a current approach is to add jitter between the integrator and the quantizer to destroy the periodicity and thus suppress the open string sound. Figure 2 As shown, the method adopted in the related art is to add an adder between the integrator and the quantizer of the DSADC, and use the adder to add jitter to the input signal at the input end of the quantizer to destroy the periodic code stream that appears, so as to suppress the idle tone.

[0049] See also Figure 3 , Figure 3 It is a structural diagram of adding jitter to the input end of a quantizer through an adder in the related art, wherein VB1 and VB2 are two voltage signals, a first capacitor C1 and a second capacitor C2 constitute an adder, and the integrator output signal and the jitter signal are combined together through the capacitor adder and input to the input end of the quantizer to achieve the addition of jitter.

[0050] However, although this method can suppress idle sounds, different application scenarios have different requirements for jitter amplitude. The current method is not convenient for adjusting the jitter amplitude. Therefore, its application scope has certain limitations.

[0051] Based on this, the embodiments of the present application provide a jitter injection circuit, an analog-to-digital converter, a chip, and an electronic device, which are described in detail below.

[0052] See also Figure 4 , Figure 4 1 is a schematic diagram of an application scenario of the jitter injection circuit provided in an embodiment of the present application. The jitter injection circuit 100 can be integrated into a micro controller unit (MCU) 200 .

[0053] It can be understood that the micro control unit 200 can be a general MCU or a dedicated MCU.

[0054] In some other application scenarios, the jitter injection circuit 100 may also be independent of the MCU, which may be specifically determined according to the actual application scenario.

[0055] Those skilled in the art will understand that Figure 4 The application environment shown in is only an application scenario adapted to the solution of the present application and does not constitute a limitation on the application scenario of the solution of the present application. The jitter injection circuit of the present application or the MCU integrating the jitter injection circuit can be used in application scenarios such as communications, audio amplifiers, power supply equipment, and automobiles, and is not specifically limited here.

[0056] See also Figure 5 , Figure 5 It is a module schematic diagram of a jitter injection circuit provided in an embodiment of the present application. The jitter injection circuit 100 can be used to inject offset jitter into an analog-to-digital converter (not shown). The analog-to-digital converter includes at least a quantizer 300. The jitter injection circuit 100 may include a jitter injection module 110 connected to an input tube 310 of the quantizer 300.

[0057] The jitter injection module 110 may include at least two current branches, which are connected to the input tube 310. The jitter injection module 110 may be used to control the on-off state of the at least two current branches according to a control signal, and output an adjustable current signal to the input tube 310 to inject offset jitter into the analog-to-digital converter.

[0058] In the embodiment of the present application, the on-off state of each current branch is controlled by a control signal, that is, each current branch can switch the on-off state in response to the received control signal.

[0059] The control signal is a signal that changes with time. Therefore, when the control signal changes, the on / off state of each current branch will also change accordingly.

[0060] For example, taking two current branches as an example, at a certain moment the control signal is 01, the first current branch is electrically disconnected and the second current branch is electrically conducted. If the control signal changes to 11 at the next moment, the first current branch switches from electrically disconnected to electrically conducted, and the second current branch remains electrically conducted. If the control signal changes to 10 at the next moment, the first current branch remains electrically conducted, and the second current branch switches from electrically conducted to electrically disconnected.

[0061] It can be understood that when a current branch is electrically conductive, a corresponding current will flow through the current branch. Since the current branch is connected to the input tube 310, the jitter injection module 110 can generate an adjustable current signal according to the current signal of the conductive current branch and output it to the input tube 310 of the quantizer 300. Here, the adjustable current signal can be the sum of the current signals of the conductive circuit branches. Therefore, as the control signal changes, the adjustable current signal output by the jitter injection module 110 also changes.

[0062] like Figure 6 As shown, in some other application scenarios, the jitter injection module 110 may also include N current branches, where N is a positive integer greater than 2, and the control signal may control the on-off state of each current branch, so that the jitter injection module 110 may also output an adjustable current signal to the input tube 310 according to the sum of the current signals of the turned-on current branches, so as to inject adjustable offset jitter into the quantizer 300.

[0063] It can be understood that the number of current branches in the embodiment of the present application can be determined according to the actual application scenario, and is not specifically limited here.

[0064] The jitter injection circuit 100 provided in the embodiment of the present application adjusts the on-off state of each current branch according to the control signal, thereby adjusting the size of the adjustable current signal output to the input tube 310 of the quantizer 300 to achieve the amplitude adjustment of the detuned jitter of the quantizer 300. The circuit structure is simple, the control is convenient, and it is easy to implement. It can not only achieve the effect of suppressing the open string sound and flexibly control the on or off of the jitter, but also adjust the spectrum noise floor by adjusting the jitter amplitude injected into the quantizer 300 to adapt to different application requirements, thereby improving the flexibility of the jitter injection circuit 100 and expanding the application scenarios of the jitter injection circuit 100.

[0065] Furthermore, unlike the related art in which the jitter signal is added to the integrator output signal by an adder and then input to the quantizer input, the jitter injection circuit 100 of the embodiment of the present application directly outputs the adjustable current signal to the input tube 310 of the quantizer 300, that is, the jitter is added to the inside of the quantizer without the help of an adder, which greatly reduces the circuit burden.

[0066] Next, continue to Figure 5 The modules shown and the specific implementation methods that may be used in practical applications are described in detail.

[0067] like Figure 7 As shown, in some embodiments of the present application, the jitter injection module 110 may further include a switch device corresponding to each current branch, and each switch device is turned on or off according to a control signal to adjust the on-off state of the corresponding current branch.

[0068] In the embodiment of the present application, the switch device may be any existing controllable switch device, and the types of the switch devices may be the same or different.

[0069] It can be understood that when the switch device is closed in response to the control signal, the corresponding current branch is electrically conductive, and the current signal of the current branch is output to the input tube 310; conversely, when the switch device is opened in response to the control signal, the corresponding current branch is electrically disconnected, and at this time, the current branch has no current signal output.

[0070] like Figure 8 As shown, in some embodiments of the present application, the jitter injection circuit 100 may further include a random number generator 120, and the random number generator 120 may be used to generate a control signal.

[0071] In the embodiment of the present application, the random number generator 120 can be any type of existing random number generator, which can generate a random number sequence, that is, a control signal, to control the on-off state of the current branch.

[0072] It can be understood that the control signal in the embodiment of the present application can be a pseudo-random digital code, or a code stream composed of a pseudo-random digital code and a sine wave, or a code stream after adding a weight configuration to the pseudo-random digital code, etc. The number of bits of the control signal can be determined according to the number of current branches in the actual application scenario, and the type of the control signal can also be determined according to the actual application scenario, which is not specifically limited here.

[0073] In some embodiments of the present application, each current branch may include a current source connected to a corresponding switching device, and each current source may be used to provide a branch current.

[0074] In a first implementation, one end of the current source of each current branch may be connected to the voltage output end, and the other end may be connected to the input tube 310 through a switch device.

[0075] See also Fig. 9 , Fig. 9 It is a first structural schematic diagram of the current branch provided in an embodiment of the present application, wherein the first current branch includes a first current source CS1, and the second current branch includes a second current source CS2, one end of the first current source CS1 is connected to the voltage output terminal V1, and the other end is connected to the input tube 310 through the first switching device SW1; one end of the second current source CS2 is connected to the voltage output terminal V1, and the other end is connected to the input tube 310 through the second switching device SW2.

[0076] In this embodiment, the voltage outputted by the voltage output terminal V1 may be a power supply voltage, a ground voltage, or any other voltage such as a common mode voltage. It can be understood that when any switch device is closed in response to a control signal, its corresponding current branch may form a path based on the voltage outputted by the voltage output terminal V1, so that the current branch may output a current signal to the input tube 310.

[0077] In an embodiment of the present application, the current source of the current branch can be a current source formed by a metal-oxide semiconductor field-effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET), or it can be a current source formed by a pre-charged capacitor. The specific selection can be based on the actual application scenario and is not limited here.

[0078] It can be understood that after the switch devices of each current branch are closed, the current signals formed may be current signals of the same magnitude, or current signals of different magnitudes arranged according to a certain rule.

[0079] For example, if there are three current branches, taking the current size of the first current branch when electrically conductive as a reference, the current of the second current branch when conductive can be twice the conductive current of the first current branch, and the current of the third current branch when conductive can be three times the conductive current of the first current branch.

[0080] In a second implementation, each current branch may also include a current source, one end of which may be connected to the input tube 310 , and the other end of which may be connected to the voltage output terminal V1 through a switch device.

[0081] See also Fig.10 , Fig.10 It is a second structural schematic diagram of the current branch provided in the embodiment of the present application, wherein one end of the first current source CS1 is connected to the input tube 310, and the other end is connected to the voltage output terminal V1 through the first switch device SW1; one end of the second current source CS2 is connected to the input tube 310, and the other end is connected to the voltage output terminal V1 through the second switch device SW2.

[0082] In this embodiment, the voltage output terminal V1 can be a power supply voltage output terminal or a ground terminal, and its output voltage can also be a power supply voltage, a ground voltage, or any other voltage such as a common mode voltage. The type of current source and the magnitude relationship of the current signal of each current branch can refer to the description in the above embodiment, and will not be repeated here.

[0083] In a third implementation, each current branch may also include a current source, and each current branch may correspond to a pair of switching devices. In this case, one end of the current source may be connected to the input tube 310 through one of the switching devices, and the other end may be connected to the voltage output terminal V1 through another switching device.

[0084] See also Fig.11 , Fig.11 This is a third structural schematic diagram of the current branch provided in the embodiment of the present application, wherein one end of the first current source CS1 is connected to the input tube 310 through the first switch device SW1, and the other end is connected to the voltage output terminal V1 through the first sub-switch device SW1'; one end of the second current source CS2 is connected to the input tube 310 through the second switch device SW2, and the other end is connected to the voltage output terminal V1 through the second sub-switch device SW2'.

[0085] In this embodiment, a pair of switch devices on the same current branch can act synchronously, that is, the control signal can control a pair of switch devices on the same current branch to close or open simultaneously to adjust the size of the adjustable current signal.

[0086] It is worth noting that when the switch devices are actuated simultaneously, there may be a large glitch signal in the current branch. Therefore, in order to reduce the glitch signal, the action time of the two switch devices on the same current branch may have a certain time delay. For example, after the first switch device is closed in response to the control signal, after a certain delay time, the second switch device is closed in response to the digital jitter signal. The specific delay time can be determined according to the actual application scenario and is not limited here.

[0087] In some embodiments of the present application, each current branch may include a transistor, and the transistor of each current branch may be connected to the input tube 310 through a corresponding switching device; the transistor can be used to turn on or off according to an input signal and provide a branch current when turned on. The input signal is a signal input to the control end of the input tube 310, that is, the input signal of the quantizer 300.

[0088] In a fourth implementation manner, the first end of the transistor may be connected to the first end of the input tube 310 through a switch device, and the second end of the transistor may be connected to the second end of the input tube 310 .

[0089] like Fig.12 As shown, Fig.12 This is a fourth structural schematic diagram of the current branch provided in the embodiment of the present application, wherein the first current branch includes a first transistor M1, the second current branch includes a second transistor M2, and the control end of the first transistor M1, the control end of the second transistor M2 and the control end of the input tube 310 are all used to receive the input signal Vi of the quantizer 300.

[0090] The first end of the first transistor M1 is connected to the input tube 310 through the first switch device SW1, and the first end of the second transistor M2 is connected to the input tube 310 through the second switch device SW2; the second end of the first transistor M1 and the second end of the second transistor M2 are both connected to the second end of the input tube 310.

[0091] In the embodiment of the present application, when each switch device is closed in response to a control signal, the corresponding transistor is turned on, so that a current signal exists in the current branch where the transistor is located and is output to the input tube 310 .

[0092] like Fig.12 As shown, the transistor of the current branch may be an N-channel Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), namely an NMOS tube.

[0093] It is understandable that in some other application scenarios, the transistor can also be a P-channel metal-oxide semiconductor field-effect transistor (MOSFET), i.e., a PMOS tube, or a combination of an NMOS tube and a PMOS tube, or even a triode, a combination of a triode and an NMOS tube, a combination of a triode and a PMOS tube, etc.

[0094] In this embodiment, the sizes of the transistors may be the same or different, and may be determined based on actual application requirements, which is not limited here.

[0095] In a fifth implementation, the first end of the transistor may be connected to the first end of the input tube 310 , and the second end of the transistor may be connected to the second end of the input tube 310 through a switch device.

[0096] like Fig.13 As shown, Fig.13 is a fifth structural diagram of the current branch provided in the embodiment of the present application. Fig.12 The structure shown is similar, the difference is that the first switch device SW1 is changed from being connected between the first end of the first transistor M1 and the first end of the input tube 310 to being connected between the second end of the first transistor M1 and the second end of the input tube 310, and the second switch device SW2 is changed from being connected between the first end of the second transistor M2 and the first end of the input tube 310 to being connected between the second end of the second transistor M2 and the second end of the input tube 310.

[0097] It can be understood that in some other application scenarios, the first switching device SW1 can be connected between the first end of the first transistor M1 and the first end of the input tube 310, and the second switching device SW2 can be connected between the second end of the second transistor M2 and the second end of the input tube 310, that is, the connection position of the switching device can be selected according to actual needs.

[0098] like Fig.14 As shown, Fig.14 This is a sixth structural diagram of the current branch provided in the embodiment of the present application. It can be understood that in some other application scenarios, the on-off state of the current branch can also be controlled by a pair of switching devices, wherein the first end of the first transistor M1 can be connected to the first end of the input tube 310 through the first switching device SW1, and the second end of the first transistor M1 can be connected to the second end of the input tube 310 through the first sub-switch device SW1'; similarly, the first end of the second transistor M2 is connected to the first end of the input tube 310 through the second switching device SW2, and the second end of the second transistor M2 is connected to the second end of the input tube 310 through the second sub-switch device SW2'.

[0099] At this time, the two switching devices connected to the transistor can be closed / opened synchronously, or they can be closed / opened one after another with a certain delay time. The specific time can be determined according to the actual application scenario and is not limited here.

[0100] The above embodiments describe some possible implementations of the jitter injection circuit 100 when the input signal of the quantizer 300 is a single-ended input signal. It can be understood that the jitter injection circuit 100 of the present application can also be applied to the scenario where the input signal of the quantizer 300 is a differential input signal.

[0101] In some embodiments of the present application, the input pipe 310 of the quantizer 300 may include a positive input pair pipe Mip and a negative input pair pipe Min, and the first jitter injection module 110 may be connected to the positive input pair pipe Mip or the negative input pair pipe Min.

[0102] like Fig.15 As shown, Fig.15 It is a schematic diagram of the first connection structure between the jitter injection module and the input tube provided in the embodiment of the present application. In this embodiment, the positive input pair Mip and the negative input pair Min are both transistors. It can be understood that the positive input pair Mip and the negative input pair Min can be NMOS tubes, PMOS tubes or a combination of the two. They can also be triodes, a combination of triodes and NMOS tubes, a combination of triodes and PMOS tubes, etc.

[0103] Fig.15Taking the positive input pair Mip and the negative input pair Min as NMOS tubes as an example, Vp is the positive input signal of the quantizer 300, which is input to the control end of the positive input pair Mip, and Vn is the negative input signal of the quantizer 300, which is input to the control end of the negative input pair Min. The jitter injection module 110 is connected to the first end of the positive input pair Mip to output the adjustable current signal to the positive input pair Mip, and the first end of the negative input pair Min receives a working voltage signal V2 to ensure that the negative input pair Min works normally.

[0104] like Fig.16 As shown, Fig.16 This is a schematic diagram of the second connection structure between the jitter injection module and the input tube provided in an embodiment of the present application. At this time, the jitter injection module 110 is connected to the first end of the negative input pair tube Min to output the adjustable current signal to the negative input pair tube Min, and the first end of the positive input pair tube Mip receives a working voltage signal V3 to ensure that the positive input pair tube Mip works normally.

[0105] For a detailed structure of the jitter injection module 110, please refer to Figures 5 to 14 The description of the jitter injection module in any embodiment will not be repeated here.

[0106] See also Fig.17 In some embodiments of the present application, the jitter injection module 110 may also be connected to the positive input pair Mip and the negative input pair Min respectively. In this case, the jitter injection module 110 may include a first jitter injection unit 1101 connected to the positive input pair Mip and a second jitter injection unit 1102 connected to the negative input pair Min. The first jitter injection unit 1101 and the second jitter injection unit 1102 may each include at least one current branch.

[0107] The first jitter injection unit 1101 can be used to control the on-off state of at least one current branch thereof according to the first control signal, and output a first adjustable current signal to the positive input pair transistor Mip.

[0108] The second jitter injection unit 1102 can be used to control the on / off state of at least one current branch thereof according to a second control signal, and output a second adjustable current signal to the negative input pair tube Min, and the second control signal is different from the first control signal.

[0109] In an embodiment of the present application, the first control signal and the second control signal can both be randomly changing signals generated by a random number generator, and the two signals are unrelated to each other; alternatively, the second control signal can be a signal obtained by inverting the first control signal, which can be specifically set according to the actual application scenario.

[0110] The first control signal controls the on-off state of the first positive current branch. When the first positive current branch is electrically conductive, its current signal will be output to the positive input pair Mip; the second control signal controls the on-off state of the first negative current branch. When the first negative current branch is electrically conductive, its current signal will be output to the negative input pair Min; since the second control signal and the first control signal are both random and unrelated signals, the first positive current branch and the first negative current branch will not be turned on or off at the same time, that is, at the same time, the first adjustable current signal received by the positive input pair Mip and the second adjustable current signal received by the negative input pair Min are different, which causes the input offset of the quantizer 300 to be different, resulting in the input offset of the quantizer 300 being jittery, and the randomness of the offset jitter is enhanced, and the idle tone is caused by the periodicity of the quantization result, and this periodicity is destroyed by adding offset jitter, so that the idle tone can be suppressed.

[0111] It can be understood that when the number of current branches of the first jitter injection unit 1101 and the second jitter injection unit 1102 is greater than 1, since the two control signals are random and unrelated to each other, the number of positive current branches turned on at the same time is different from the number of negative current branches turned on. In this way, the first adjustable current signal received by the positive input pair Mip and the second adjustable current signal received by the negative input pair Min are also different, which can cause the input offset of the quantizer 300 to be different, so that the input offset of the quantizer 300 is jittered to suppress idle sound.

[0112] Based on the above embodiments, the present application also provides an analog-to-digital converter, which may include a quantizer and a Figures 5 to 17 The jitter injection circuit 100 in any embodiment may be used to inject adjustable offset jitter into the quantizer 300 .

[0113] In this embodiment, the analog-to-digital converter can be a first-order or higher DSADC, or an incremental ADC or other hybrid structures of DSADC, for example, a Delta Sigma Successive Approximation Register (DS_SAR) ADC, a Delta Sigma Cyclic (DS_Cyclic) ADC, an Incremental-SAR ADC, an Incremental-Cyclic ADC, etc.

[0114] Since the analog-to-digital converter is provided with the jitter injection circuit of the above embodiment, it has all the beneficial effects of the jitter injection circuit in any of the above embodiments, which will not be described in detail here.

[0115] Based on the above embodiments, the present application also provides a chip, which may include: Figures 5 to 17 The jitter injection circuit in any embodiment. The chip may be an integrated circuit (IC), or a microcircuit, a microchip, or a wafer / chip. The chip may be, but is not limited to, a system on chip (SOC) or a system in package (SIP) chip.

[0116] Since the chip is provided with the jitter injection circuit of the above embodiment, it has all the beneficial effects of the jitter injection circuit in any of the above embodiments, which will not be described in detail here.

[0117] The embodiment of the present application also provides an electronic device, which may include a device body and a chip, analog-to-digital converter or jitter injection circuit as described above, which is arranged in the device body. The electronic device may be, but is not limited to, a weight scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a human body composition analyzer, a mobile power supply, a wireless charger, a fast charger, a car charger, an adapter, a display, a Universal Serial Bus (USB) docking station, a stylus, a True Wireless Stereo (TWS) headset, a car console, a car, a smart wearable device, a mobile terminal, and a smart home device.

[0118] Among them, smart wearable devices include but are not limited to smart watches, smart bracelets, and cervical massagers. Mobile terminals include but are not limited to smart phones, laptops, tablets, and point of sales terminals (POS). Smart home devices include but are not limited to smart sockets, smart rice cookers, smart sweepers, and smart lights.

[0119] Since the electronic device is provided with the jitter injection circuit of the above embodiment, it has all the beneficial effects of the jitter injection circuit in any of the above embodiments, which will not be described in detail here.

[0120] like Fig.18 As shown, Fig.18It is a circuit structure schematic diagram of a jitter injection circuit provided in an embodiment of the present application, wherein the jitter injection circuit includes a positive jitter input unit connected to the positive input pair of tubes Mip of the quantizer and a negative jitter input unit connected to the negative input pair of tubes Min of the quantizer, wherein the positive jitter input unit includes k current source branches, and the k current source branches are connected to k switches (swp1, ..., swpk) in a one-to-one correspondence, and each current source branch is connected to the first end of the positive input pair of tubes Mip through a corresponding switch.

[0121] The negative jitter input unit also includes k current source branches, each of which is connected to k switches (swn1, ..., swnk) in a one-to-one correspondence, and each current source branch is connected to the first end of the negative input pair Min through a corresponding switch.

[0122] The second end of the positive input pair Mip is connected to the second end of the negative input pair Min, the control end of the positive input pair Mip receives the positive input signal Vp of the quantizer, and the control end of the negative input pair Min receives the negative input signal Vn of the quantizer.

[0123] Among them, the positive terminal voltage signal VB1P is the ground voltage, the negative terminal voltage signal VB1N is the power supply voltage, the k switches (swp1, ..., swpk) of the positive jitter input unit are controlled by the first control signal, and the k switches (swn1, ..., swnk) of the negative jitter input unit are controlled by the second control signal.

[0124] A pseudo-random digital code, i.e., a control signal, is generated by a pseudo-random number generator to control the closing or opening of switches swp1, ..., swpk and swn1, ..., swnk. When any one of the switches is closed, the current source connected to the switch is connected to the input pair of tubes of the quantizer. When the sum of the current sources connected to the two input pairs of tubes is different, an input offset of the quantizer is generated.

[0125] Since the current source is turned on by a pseudo-random digital code, the pseudo-random digital code generated at different times causes different quantizer input offsets, which means that the quantizer input offset is jittery. Since the idle tone is caused by the periodicity of the quantization result, the added offset jitter destroys this periodicity, so the idle tone can be suppressed. Moreover, by adjusting the on-off state of the current source branch through the pseudo-random digital code, the amplitude of the quantizer offset jitter can be easily adjusted, thereby taking into account the idle tone and the noise floor, optimizing the output performance of the ADC to adapt to different application requirements, with high flexibility.

[0126] like Fig.19 As shown, Fig.19: is another circuit structure schematic diagram of a jitter injection circuit provided in an embodiment of the present application, wherein Mp1, ..., Mpk are k transistors connected to both ends of the positive input pair Mip of the quantizer through switches (swp1, ..., swpk and swp1', ..., swpk'), and Mn1, ..., Mnk are k transistors connected to both ends of the negative input pair Min of the quantizer through switches (swn1, ..., swnk and swn1', ..., swnk'); the control ends of the transistors Mp1, ..., Mpk and the control ends of the positive input pair Mip receive the positive input signal Vp of the quantizer, and the control ends of the transistors Mn1, ..., Mnk and the control ends of the negative input pair Min receive the negative input signal Vn of the quantizer.

[0127] The two switches connected at two ends of the same transistor are a pair of synchronous switches, which can be closed or opened simultaneously in response to a control signal.

[0128] When the two switches on a branch are closed at the same time, the transistors on the branch are connected in parallel with their corresponding input pairs. When the number of transistors connected in parallel on the two input pairs is different, input offset of the quantizer occurs.

[0129] Since the switch is turned on by a pseudo-random digital code, the pseudo-random digital code generated at different times causes different quantizer input offsets, which means that the quantizer input offset is jittery. Since the idle tone is caused by the periodicity of the quantization result, the added offset jitter destroys this periodicity, so the idle tone can be suppressed. In addition, the amplitude of the quantizer offset jitter can be adjusted by adjusting the number of parallel transistors through the pseudo-random digital code, thereby taking into account the idle tone and the noise floor, optimizing the output performance of the ADC to adapt to different application requirements, with high flexibility.

[0130] It can be understood that in other implementations, the jitter injection circuit may include k current source branches connected to the positive input pair Mip through k switches (swp1, ..., swpk), and k transistors connected to the negative input pair Min through k pairs of switches (swn1, ..., swnk and swn1', ..., swnk').

[0131] Similarly, since the switch is turned on by a pseudo-random digital code, when the number of current sources connected to the two input pairs is different from the number of transistors, the input offset of the quantizer is generated. Therefore, the pseudo-random digital codes generated at different times cause different input offsets of the quantizer, which means that the input offset of the quantizer is jittery. Since the idle tone is caused by the periodicity of the quantization result, the added offset jitter destroys this periodicity, so the idle tone can be suppressed. In addition, the amplitude of the quantizer offset jitter can be adjusted by adjusting the number of current sources and transistors connected by the pseudo-random digital code, thereby taking into account the idle tone and the noise floor, optimizing the output performance of the ADC to adapt to different application requirements, with high flexibility.

[0132] The above are only preferred embodiments of the present application, and are not intended to limit the present application in any form. Although the present application has been disclosed as above with preferred embodiments, it is not intended to limit the present application. Any technical personnel in the field can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present application. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A jitter injection circuit, characterized in that: Used to inject offset jitter into an analog-to-digital converter, the analog-to-digital converter at least comprising a quantizer, and the jitter injection circuit comprising a jitter injection module connected to an input tube of the quantizer; The jitter injection module includes at least two current branches, and the at least two current branches are connected to the input tube. The jitter injection module is used to control the on-off state of the at least two current branches according to a control signal, and output an adjustable current signal to the input tube to inject the offset jitter into the analog-to-digital converter.

2. The jitter injection circuit according to claim 1, characterized in that: The jitter injection module further includes a switch device corresponding to each of the current branches, and each of the switch devices is turned on or off according to the control signal to adjust the on-off state of the corresponding current branch.

3. The jitter injection circuit according to claim 1, characterized in that: The jitter injection circuit further includes a random number generator, and the random number generator is used to generate the control signal.

4. The jitter injection circuit according to claim 2, characterized in that: Each of the current branches includes a current source connected to the corresponding switch device, and the current source is used to provide a branch current.

5. The jitter injection circuit according to claim 2, characterized in that: Each of the current branches includes a transistor, which is connected to the input tube through the corresponding switching device; the transistor is used to be turned on or off according to an input signal and provide a branch current when turned on, and the input signal is a signal input to the control end of the input tube.

6. The jitter injection circuit according to any one of claims 1 to 5, characterized in that: The input tubes include a positive input pair of tubes and a negative input pair of tubes, and the jitter injection module is connected to the positive input pair of tubes or the negative input pair of tubes.

7. The jitter injection circuit according to any one of claims 1 to 5, characterized in that: The input tubes include a positive input pair of tubes and a negative input pair of tubes, and the jitter injection module includes a first jitter injection unit connected to the positive input pair of tubes and a second jitter injection unit connected to the negative input pair of tubes; The first jitter injection unit and the second jitter injection unit respectively include at least one current branch; The first jitter injection unit is used to control the on / off state of at least one of the current branches according to the first control signal, and output a first adjustable current signal to the positive input pair of transistors; The second jitter injection unit is used to control the on / off state of at least one of the current branches according to a second control signal and output a second adjustable current signal to the negative input pair of transistors, and the second control signal is different from the first control signal.

8. An analog-to-digital converter, characterized in that: The invention comprises a quantizer and a jitter injection circuit as claimed in any one of claims 1 to 7, wherein the jitter injection circuit is used for injecting adjustable offset jitter into the quantizer.

9. A chip, characterized in that: It comprises the jitter injection circuit according to any one of claims 1 to 7 or the analog-to-digital converter according to claim 8.

10. An electronic device, characterized in that: The device comprises a device body and a chip as claimed in claim 9, an analog-to-digital converter as claimed in claim 8 or a jitter injection circuit as claimed in any one of claims 1-7, which is arranged in the device body.

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