CAN transceiver

Abstract

The invention discloses a CAN transceiver, which comprises a data sending port, a high-side bus port, a low-side bus port, an output stage circuit, a first adjusting circuit and a second adjusting circuit, and is characterized in that the first adjusting circuit and the second adjusting circuit are used for increasing pull-up current or pull-down current in an output circuit by receiving an abnormal voltage signal and outputting an adjusting signal; error code elimination of differential signals is achieved, a first adjusting circuit adjusts error codes generated by abnormal positive high-voltage pulses coupled into a high-side bus port, and a second adjusting circuit adjusts error codes generated by abnormal negative high-voltage pulses coupled into a low-side bus port. After the first adjusting circuit and the second adjusting circuit are applied to the CAN transceiver, the influence of abnormal high-voltage pulse signals in the CAN bus on the error codes of output signals of the CAN transceiver is reduced, and the EMC performance of the CAN transceiver is improved.

Description

Technical Field

[0001] The present application belongs to the technical field of CAN transceivers, and specifically relates to a CAN transceiver. Background Art

[0002] The CAN transceiver is a key component in the CAN (Controller Area Network) bus communication. It is used for data transmission between the CAN bus and the CAN controller. It converts the single-ended signal output by the CAN controller into the differential signal required by the CAN bus, and converts the differential signal on the CAN bus back to a single-ended signal for transmission to the CAN controller. Due to the complex electromagnetic environment in the application scenario of CAN bus communication, the CAN transceiver is usually subject to abnormal high-voltage interference. For example, the on-board electrical environment may couple tens or hundreds of volts of positive and negative high voltage to the CAN bus, causing the protection diode in the output stage circuit of the CAN transceiver to generate reverse recovery current in the process of changing from forward conduction to reverse cutoff, causing the output state of the CAN transceiver to change from dominant to recessive, thereby affecting the stability of the differential signal. Summary of the invention

[0003] The present application provides a CAN transceiver to solve the problem that the output circuit of the current CAN transceiver is easily interfered by abnormal high voltage, resulting in bit errors in the output signal of the CAN transceiver, so as to improve the EMC (Electromagnetic Compatibility) of the CAN transceiver.

[0004] According to the first aspect of the present application, the present application provides a CAN transceiver, including: a sending data port, receiving a sending data signal; a high-side bus port, outputting a high-side bus signal; a low-side bus port, outputting a low-side bus signal; a high-side transistor, having a first end, a second end and a third end, wherein the first end receives a power supply voltage and the second end receives a high-side gate signal; a high-side switch tube, having a first end coupled to the third end of the high-side transistor, and a second end coupled to the high-side bus port, and the voltage at the first end of the high-side switch tube is a high-side detection voltage; a low-side transistor, having a first end, a second end and a third end, wherein the first end is coupled to a reference ground, and the second end receives a low-side gate signal; a low-side switch tube, having a first end coupled to the low-side bus port, and a second end coupled to the third end of the low-side transistor, and the voltage at the second end of the low-side switch tube is a low-side detection voltage. voltage measurement; a first regulating circuit, having a first input terminal and a second input terminal, wherein the first input terminal receives a power supply voltage, the second input terminal receives a high-side detection voltage, and the first regulating circuit generates a first regulating signal according to the power supply voltage and the high-side detection voltage; a second regulating circuit, having a first input terminal and a second input terminal, wherein the first input terminal is coupled to a reference ground, the second input terminal receives a low-side detection voltage, and the second regulating circuit generates a second regulating signal according to the reference ground and the low-side detection voltage; and a logic circuit, generating a high-side gate signal and a low-side gate signal according to the transmitted data signal, the first regulating signal and the second regulating signal; wherein, when the high-side detection voltage is greater than the sum of the power supply voltage and the first threshold value, the forward current flowing through the low-side switch tube increases, and when the low-side detection voltage is less than the second threshold value, the forward current flowing through the high-side switch tube increases.

[0005] According to a second aspect of the present application, the present application provides a CAN transceiver, comprising: a transmitting data port, receiving a transmitting data signal; a high-side bus port, outputting a high-side bus signal; a low-side bus port, outputting a low-side bus signal; a high-side transistor, having a first end, a second end and a third end, wherein the first end receives a power supply voltage and the second end receives a transmitting data signal; a high-side switch tube, having a first end coupled to the third end of the high-side transistor, and a second end coupled to the high-side bus port, wherein the voltage at the first end of the high-side switch tube is a high-side detection voltage; a low-side transistor, having a first end, a second end and a third end, wherein the first end is coupled to a reference ground, and the second end receives a transmitting data non-signal; a low-side switch tube, having a first end coupled to the low-side bus port, and a second end coupled to the third end of the low-side transistor, wherein the voltage at the second end of the low-side switch tube is a low-side detection voltage; a first regulating circuit, having a first input end and a second input end, wherein the first input end receives a power supply voltage, The second input terminal receives the high-side detection voltage, and the first regulation circuit generates a first regulation signal according to the power supply voltage and the high-side detection voltage; the second regulation circuit has a first input terminal and a second input terminal, wherein the first input terminal is coupled to the reference ground, the second input terminal receives the low-side detection voltage, and the second regulation circuit generates a second regulation signal according to the reference ground and the low-side detection voltage; the first regulation transistor has a first terminal, a second terminal and a third terminal, wherein the first terminal is coupled to the second terminal of the low-side switch tube, the second terminal is coupled to the reference ground, and the third terminal receives the first regulation signal; and the second regulation transistor has a first terminal, a second terminal and a third terminal, wherein the first terminal is coupled to the power supply voltage, the second terminal is coupled to the first terminal of the high-side switch tube, and the third terminal receives the second regulation signal; wherein, when the high-side detection voltage is greater than the sum of the power supply voltage and the first threshold, the forward current flowing through the low-side switch tube increases, and when the low-side detection voltage is less than the second threshold, the forward current flowing through the high-side switch tube increases.

[0006] Through one or more of the above embodiments of the present invention, at least the following technical effects can be achieved:

[0007] In this embodiment, the regulation circuit samples the terminal voltage of the switch tube in the output circuit of the CAN transceiver to detect the abnormal high-voltage pulse by acquiring the voltage signal, and generates the regulation signal by using the abnormal voltage signal, thereby regulating the abnormal current of the CAN bus caused by the abnormal high-voltage pulse, thereby ensuring that the differential signal does not have bit errors when the high-side output current or the low-side output current of the CAN transceiver is abnormal, thereby improving the anti-interference capability of the CAN transceiver and realizing EMC enhancement of the CAN transceiver. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0009] Figure 1 The schematic diagram of the output stage circuit structure of the existing CAN transceiver is given;

[0010] Figure 2 The signal timing diagram of the existing CAN transceiver output stage circuit is given;

[0011] Figure 3 A circuit structure diagram of a CAN transceiver according to an embodiment of the present invention is given;

[0012] Figure 4 A schematic diagram of a logic switch S2 according to an embodiment of the present invention is given;

[0013] Figure 5 A circuit structure diagram of a CAN transceiver according to an embodiment of the present invention is given;

[0014] Figure 6 An example diagram of the signal timing of the CAN transceiver circuit of each embodiment of the present invention is given; DETAILED DESCRIPTION

[0015] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0016] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0017] It should be understood that in the following description, "circuit" refers to a conductive loop composed of at least one element or subcircuit through electrical connection or electromagnetic connection. When an element or circuit is said to be "connected to" another element or an element / circuit is said to be "connected between" two nodes, it can be directly coupled or connected to another element or there can be an intermediate element, and the connection between the elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.

[0018] In the application scenario of CAN bus communication, there may be high-voltage pulse interference in the complex electrical environment, such as sudden pulse (Impulse, IMP) events or direct power injection (Direct Power Injection, DPI) events in the vehicle electrical environment. Therefore, diodes are usually used inside the CAN transceiver for transient high voltage protection. Under normal circumstances, the difference signal between the high-side bus signal CANH and the low-side bus signal CANL in the CAN bus is defined as the differential signal VDIFF of the CAN bus. When the high-side bus signal CANH is a logic high level and the low-side bus signal CANL is a logic low level, the actual level difference between the two is large, and the differential signal VDIFF is a logic high state, indicating that the CAN bus is working in a dominant state. When the high-side bus signal CANH is a logic low level and the low-side bus signal CANL is a logic high level, the actual level difference between the two is small, and the differential signal VDIFF is a logic low state, indicating that the CAN bus is working in a recessive state. When an IMP event or a DPI event occurs, due to the influence of the instantaneous high voltage, the diode may be forward-conducted. Switch to reverse cutoff. Since there is diffusion capacitance in the diode when it is forward-conducting, when the diode bias is switched from positive voltage to negative voltage, it takes a while to reverse charge the voltage of the diffusion capacitance. At the same time, the carriers inside the diode need a certain amount of time to recombine and disappear completely. Only then can the voltage drop inside the diode reach the negative voltage and completely cut off. During this period of time, the current seen from the outside of the diode flows from the cathode to the anode of the diode, so it is called the diode reverse recovery current. The existence of this reverse recovery current may cause the input and output states of the CAN bus to change from logic high to logic low, which may cause the communication on the CAN bus to be interfered by bit errors, and the transmitted message may be mistakenly considered to be a recessive state instead of the expected dominant state. Similarly, when a field effect transistor is used as a protection switch inside the CAN transceiver, the parasitic diode inside the field effect transistor will also appear under the influence of instantaneous high voltage, and reverse recovery current will appear, which will cause abnormal input and output states of the CAN bus and bit errors.

[0019] Figure 1 The schematic diagram of the output stage circuit structure of the existing CAN transceiver is given, such as Figure 1As shown, the CAN transceiver output stage circuit 10 includes a high-side transistor MH, a high-side switch tube DH, a low-side switch tube DL, and a low-side transistor ML, wherein the gate end of the high-side transistor MH receives a transmit data signal TXD, and the gate end of the low-side transistor ML receives a transmit data non-signal TXDN, that is, the transmit data signal TXD and the transmit data non-signal TXDN of the CAN transceiver are used as control signals of the high-side transistor MH and the low-side transistor ML, respectively. When the TXD signal is dominant, the gate voltage of the high-side transistor MH is low, the high-side transistor MH is turned on, the high-side switch tube DH is forward-conducted, and the high-side bus port CANH outputs the forward conduction current ID_H of the high-side switch tube DH, that is, the high-side bus signal CANH is a logic high level. At this time, the TXDN signal is high, that is, the gate voltage of the low-side transistor ML is high, which controls the low-side transistor ML to turn on, and the low-side switch tube DL is forward-conducted. The low-side bus port CANL outputs the forward conduction current ID_L of the low-side switch tube DL, that is, the low-side bus signal CANL is a logic low level. At this time, the differential signal in the CAN bus is a logic high level, indicating that the CAN bus state is dominant. When the TXD signal is recessive, the gate voltage of the high-side transistor MH is high, the high-side transistor MH is turned off, the high-side switch tube DH is cut off, the forward conduction current ID_H of the high-side switch tube DH is approximately zero, and the high-side bus signal CANH is a logic low. At this time, the TXDN signal is low, that is, when the gate voltage of the low-side transistor ML is low, the low-side transistor ML is cut off, the low-side switch tube DL is cut off, and the forward conduction current ID_L of the low-side switch tube DL is approximately zero, and the low-side bus signal CANL is a logic high. Since both the high-side switch tube DH and the low-side switch tube DL are cut off, the high-side bus and low-side bus voltages in the CAN bus are close, that is, the differential signal in the CAN bus is a logic low, indicating that the CAN bus state is recessive.

[0020] Figure 2 The signal timing diagram of the existing CAN transceiver output stage circuit is given to illustrate Figure 1 The existing CAN transceiver output stage circuit structure shown in the figure has EMC performance problems. Take the sudden IMP event or DPI event causing +100V high voltage interference in the CAN bus as an example. When the high voltage interference signal RF_IN is coupled into the CAN bus through the capacitor, if the TXD signal is dominant at this time, then at the moment of the IMP event or DPI event, the negative terminal voltage of the high-side switch tube DH rises sharply, and the bias state of the high-side switch tube DH switches from forward conduction to reverse cutoff, and its reverse recovery current flows from the negative electrode of the high-side switch tube DH to the positive electrode, resulting in Figure 2At the moment of +100V high voltage, the high-side detection voltage VD_H exceeds the power supply voltage VCC. At this time, the forward conduction current ID_H of the high-side switch tube DH jumps ①, that is, the forward conduction current ID_H of the high-side switch tube DH cannot be cut off to 0 at the moment when the high-side switch tube DH switches to reverse cutoff, but reverse current appears, causing the polarity jump of the high-side bus signal CANH in the CAN bus, which in turn causes the corresponding jump of the differential signal VDIFF in the CAN bus ③, that is, bit errors occur. Similarly, when a sudden IMP event or DPI event causes -100V high voltage interference in the CAN bus, the TXD signal is dominant at this time, then at the moment of the IMP event or DPI event, the positive terminal voltage of the low-side switch tube DL drops sharply, and the bias state of the low-side switch tube DL switches from forward conduction to reverse cutoff, and the reverse recovery current flows from the negative pole to the positive pole of the low-side switch tube DL, resulting in Figure 2 The mid-low side detection voltage VD_L appears a negative high voltage lower than GND at the moment when the -100V high voltage comes. At this time, the forward conduction current ID_L of the low side switch tube DL jumps②, that is, the forward conduction current ID_L of the low side switch tube DL cannot be cut off to 0 at the moment when the low side switch tube DL switches to reverse cutoff, but a reverse current appears, causing the polarity of the low side bus signal CANL in the CAN bus to jump, and then causing the differential signal VDIFF in the CAN bus to jump accordingly④, that is, a bit error occurs.

[0021] Figure 3 A schematic diagram of the circuit structure of a CAN transceiver according to an embodiment of the present invention is given. Figure 3As shown, the circuit structure of the CAN transceiver includes a data transmission port, a high-side bus port, a low-side bus port, a high-side transistor MH, a high-side switch tube DH, a low-side transistor ML, a low-side switch tube DL, a first regulating circuit 103, a second regulating circuit 104 and a logic circuit, wherein the data transmission port receives a data transmission signal TXD, the high-side bus port outputs a high-side bus signal CANH, and the low-side bus port outputs a low-side bus signal CANL. The high-side transistor MH has a first end, a second end and a third end, wherein the first end receives a power supply voltage VCC, and the second end receives a high-side gate signal GH. The high-side switch tube DH has a first end coupled to the third end of the high-side transistor MH, and a second end coupled to the high-side bus port, wherein the voltage of the first end is used as the high-side detection voltage VD_H in this embodiment. The low-side transistor ML has a first end, a second end and a third end, wherein the first end is coupled to the reference ground GND, and the second end receives the low-side gate signal GL. The low-side switch tube DL has a first end coupled to the low-side bus port, and a second end coupled to the third end of the low-side transistor ML, wherein the voltage of the second end is used as the low-side detection voltage VD_L in this embodiment. The first regulating circuit 103 has a first input end, a second input end and an output end, wherein the first input end receives the power supply voltage VCC, the second input end is coupled to the positive terminal of the high-side switch tube DH, receives the high-side detection voltage VD_H, and the output end outputs a first regulating signal CompH according to the high-side detection voltage VD_H and the power supply voltage VCC. The second regulating circuit 104 has a first input end, a second input end and an output end, wherein the first input end is coupled to the reference ground GND, the second input end is coupled to the negative terminal of the low-side switch tube DL, receives the low-side detection voltage VD_L, and the output end outputs a second regulating signal CompL according to the low-side detection voltage VD_L and the reference ground GND.

[0022] Further, the first regulating circuit 103 includes a first regulating voltage source Vos1 and a first comparison circuit 1031. The first regulating voltage source Vos1 has a first end and a second end, wherein the first end is coupled to the positive end of the high-side switch tube DH. The first comparison circuit 1031 has a first input end for receiving the power supply voltage VCC, a second input end coupled to the second end of the first regulating voltage source Vos1, and an output end coupled to the second end of the low-side transistor ML. The first regulating voltage source Vos1 provides the first threshold required for the first regulating circuit 103 to generate the first regulating signal CompH. The second regulating circuit 104 includes a second regulating voltage source Vos2 and a second comparison circuit 1041. The second regulating voltage source Vos2 has a first end and a second end, wherein the first end is coupled to the negative end of the low-side switch tube DL. The second comparison circuit has a first input end coupled to the reference ground GND, a second input end coupled to the second end of the first regulating voltage source Vos1, and an output end coupled to the second end of the high-side transistor MH. The second regulating voltage source Vos2 provides the second threshold required for the second regulating circuit 104 to generate the second regulating signal CompL. In this embodiment, the first comparison circuit 1031 includes a first comparator Comp1, the first input terminal of the first comparison circuit 1031 is the inverting input terminal of the first comparator Comp1, the voltage of the first regulating voltage source Vos1 is 0mV to 500mV, the first terminal is the positive terminal of the power supply, and the second terminal is the negative terminal of the power supply, so that the provided first threshold value is 0mV to 500mV. The second comparison circuit 1041 includes a second comparator Comp2, the first input terminal of the second comparison circuit is the non-inverting input terminal of the second comparator Comp2, the voltage of the second regulating voltage source Vos2 is 0mV to 500mV, the first terminal is the negative terminal of the power supply, and the second terminal is the positive terminal of the power supply, so that the provided second threshold value is -500mV to 0mV.

[0023] In the above embodiment, when the voltage at the first end of the high-side switch tube DH is greater than the sum of the power supply voltage VCC and the voltage value of the first regulating voltage source Vos1, that is, when the high-side detection voltage VD_H is greater than the sum of the power supply voltage VCC and the first threshold, the first regulating circuit 103 increases the voltage at the second end of the low-side transistor ML by outputting the first regulating signal CompH, and increases the on-current of the low-side transistor ML by increasing the bias voltage of the low-side transistor ML, that is, increases the forward on-current ID_L of the low-side switch tube DL. When the voltage at the second end of the low-side switch tube DL is less than the negative value of the voltage value of the second regulating voltage source, that is, when the low-side detection voltage VD_L is less than the second threshold, the second regulating circuit 104 outputs the second regulating signal CompL to reduce the voltage at the second end of the high-side transistor MH, and increases the on-current of the high-side transistor MH by increasing the bias voltage of the high-side transistor MH, that is, increases the forward on-current ID_H of the high-side switch tube DH.

[0024] exist Figure 3 In the circuit structure of the CAN transceiver shown, the logic circuit includes a logic switch S1 and a logic switch S2, wherein the output end of the logic switch S1 is coupled to the second end of the high-side transistor MH, the output end of the logic switch S2 is coupled to the second end of the low-side transistor ML, the logic switch S2 generates a low-side gate signal GL according to the first adjustment signal CompH and the transmit data non-signal TXDN, and the logic switch S1 generates a high-side gate signal GH according to the second adjustment signal CompL and the transmit data signal TXD; further, in order to unify the gate voltage selection logic of the high-side transistor MH and the low-side transistor ML, and use the same logic switch structure, after the transmit data port receives the transmit data signal TXD, the transmit data signal TXD is input into the logic switch S1, and is input into the high-side output stage circuit 101 through the logic switch S1, and the transmit data signal TXD is inverted to generate a transmit data non-signal TXDN, which is then input into the logic switch S2, and is input into the low-side output stage circuit 102 through the logic switch S2. Through the logic switch S1 and the logic switch S2, the data transmission signal line and the data transmission non-signal line can be prevented from directly participating in the control logic of the high-side transistor MH and the low-side transistor ML, thereby preventing the short circuit of the root logic line. In this embodiment, the root logic line corresponds to the transmission line for transmitting the data transmission signal TXD and the data transmission non-signal TXDN.

[0025] exist Figure 3 In the illustrated embodiment, the high-side transistor MH is a P-channel field effect transistor, and the low-side transistor ML is an N-channel field effect transistor.

[0026] In the above embodiment, the high-side switch tube DH and the low-side switch tube DL in the high-side output stage circuit 101 and the low-side output stage circuit 102 may be field effect transistors or diodes.

[0027] Figure 4 A schematic diagram of a logic switch S2 according to an embodiment of the present invention is given. Figure 3 The CAN transceiver shown in FIG. 1 illustrates the working process of the logic switch S2. Figure 4As shown, the logic switch S2 outputs the low-side gate signal GL, with its output terminal coupled to the gate of the low-side transistor ML, according to the transmitted data signal TXD, the inverted transmitted data signal TXDN, the first regulation signal CompH and the first inverted regulation signal CompHN of the first regulation circuit 103. At the same time, three selection voltages V1 > V2 > V3 = 0 are set. The first inverted regulation signal CompHN and the first regulation signal CompH are complementary signals, that is, when the first regulation signal CompH is at a logic high level, the first inverted regulation signal CompHN is at a logic low level, and when the first regulation signal CompH is at a logic low level, the first inverted regulation signal CompHN is at a logic high level. When the CAN transceiver operates in the recessive state, the transmitted data signal TXD is at a logic high level, making GL = V3 and the low-side transistor ML operate in the cut-off state. When the CAN transceiver operates in the dominant state, the inverted transmitted data signal TXDN is at a logic high level. The logic switch S2 selects the low-side gate signal GL to be V1 or V2 according to the first regulation signal CompH and the first inverted regulation signal CompHN. When the first regulation signal CompH is at a logic high level, the low-side gate signal GL is V1, and when the first inverted regulation signal CompHN is at a logic high level, the low-side gate signal GL is V2. When the voltage at the first end of the high-side switch tube DH, i.e., the high-side detection voltage VD_H, is greater than the sum of the supply voltage VCC and the voltage value of the first regulation voltage source Vos1, the first regulation circuit 103 controls the bias voltage of the low-side transistor ML, i.e., the low-side gate signal GL, to change from V2 to V1 by outputting the first regulation signal CompH, so as to increase the conduction current of the low-side transistor ML, that is, the forward current ID_L of the low-side switch tube DL increases. Similarly, in the above Figure 3 The logic switch S1 in the embodiment shown is similar in structure and principle to the logic switch S2 in this embodiment. Correspondingly, the selected logic voltages V1, V2, and V3 are set to V1 < V2 < V3 = VCC, and their specific structures and principles will not be elaborated here.

[0028] Figure 5 The circuit structure diagram of a CAN transceiver according to another embodiment of the present invention is given. As Figure 5As shown, the circuit structure of the CAN transceiver includes a transmission data port, a high-side bus port, a low-side bus port, a high-side transistor MH, a high-side switch tube DH, a low-side transistor ML, a low-side switch tube DL, a first regulating circuit 103 and a second regulating circuit 104. After the transmission data port receives the transmission data signal TXD, the high-side output stage circuit 101 receives the transmission data signal TXD, and the low-side output stage circuit 102 receives the transmission data non-signal TXDN, wherein the transmission data non-signal TXDN and the transmission data signal TXD are complementary signals. The high-side bus port outputs the high-side bus signal CANH, and the low-side bus port outputs the low-side bus signal CANL. The high-side transistor MH has a first end, a second end and a third end, wherein the first end receives the power supply voltage VCC, and the second end receives the transmission data signal TXD. The high-side switch tube DH has a first end coupled to the third end of the high-side transistor MH, and a second end coupled to the high-side bus port, wherein the voltage of the first end is used as the high-side detection voltage VD_H in this embodiment. The low-side transistor ML has a first end, a second end and a third end, wherein the first end is coupled to the reference ground GND, and the second end receives the transmit data non-signal TXDN. The low-side switch tube DL has a first end coupled to the low-side bus port, and a second end coupled to the third end of the low-side transistor ML, wherein the voltage of the second end is used as the low-side detection voltage VD_L in this embodiment. The first regulating circuit 103 has a first input end, a second input end and an output end, wherein the first input end receives the power supply voltage VCC, the second input end is coupled to the first end of the high-side switch tube DH, receives the high-side detection voltage VD_H, and the output end is coupled to the second end of the low-side switch tube DL, and outputs the first regulating signal CompH according to the high-side detection voltage VD_H and the power supply voltage VCC. The second regulating circuit 104 has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the reference ground GND, the second input terminal is coupled to the second terminal of the low-side switch tube DL, receives the low-side detection voltage VD_L, and the output terminal is coupled to the first terminal of the high-side switch tube DH, and outputs the second regulating signal CompL according to the low-side detection voltage VD_L and the reference ground GND.

[0029] Figure 5 The circuit structure of the CAN transceiver shown also includes a first regulating transistor MR1 and a second regulating transistor MR2. The first regulating transistor MR1 has a first end, a second end and a third end, wherein the first end is coupled to the second end of the low-side switch tube DL, the second end is coupled to the reference ground GND, and the third end receives the first regulating signal CompH; the second regulating transistor MR2 has a first end, a second end and a third end, wherein the first end is coupled to the power supply voltage VCC, the second end is coupled to the first end of the high-side switch tube DH, and the third end receives the second regulating signal CompL.

[0030] Further, the first regulating circuit 103 includes a first regulating voltage source Vos1 and a first comparison circuit 1031, wherein the first regulating voltage source Vos1 has a first terminal and a second terminal, wherein the first terminal is coupled to the first terminal of the high-side switch tube DH. The first comparison circuit 1031 has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal receives the power supply voltage VCC, the second input terminal is coupled to the second terminal of the first regulating voltage source Vos1, and the output terminal is coupled to the third terminal of the first regulating transistor MR1, and outputs the first regulating signal CompH. The first regulating voltage source Vos1 provides the first threshold value required for the first regulating circuit 103 to generate the first regulating signal CompH. The second regulating circuit 104 includes a second regulating voltage source Vos2 and a second comparison circuit 1041. The second regulating voltage source Vos2 has a first terminal and a second terminal, wherein the first terminal is coupled to the second terminal of the low-side switch tube DL. The second comparison circuit 1041 has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the reference ground GND, the second input terminal is coupled to the second terminal of the first regulating voltage source Vos1, and the output terminal is coupled to the third terminal of the second regulating transistor MR2, and outputs a second regulating signal CompL. The second regulating voltage source Vos2 provides the second threshold value required for the second regulating circuit 104 to generate the second regulating signal CompL. In this embodiment, the first comparison circuit 1031 includes a first comparator Comp1, the first input terminal of the first comparison circuit 1031 is the non-inverting input terminal of the first comparator Comp1, the first regulating transistor MR1 is an N-channel field effect transistor, the voltage value of the first regulating voltage source Vos1 is 0mV~500mV, the first terminal is the positive terminal of the power supply, and the second terminal is the negative terminal of the power supply, so that the provided first threshold value is 0mV~500mV; the second comparison circuit 1041 includes a second comparator Comp2, the first input terminal of the second comparison circuit 1041 is the non-inverting input terminal of the second comparator Comp1, the second regulating transistor MR2 is a P-channel field effect transistor, the voltage value of the second regulating voltage source Vos2 is 0mV~500mV, the first terminal is the negative terminal of the power supply, and the second terminal is the positive terminal of the power supply, so that the provided second threshold value is -500mV~0mV. In an embodiment of the present application, normal fluctuations in the bus signal may cause the high-voltage detection signal VD_H to be close to the power supply voltage VCC or slightly higher than the power supply voltage VCC, and may also cause the low-voltage detection signal VD_L to be slightly lower than the reference voltage GND, resulting in false triggering of the circuit's adjustment mechanism. The setting of the first threshold and the second threshold can prevent the adjustment mechanism from being falsely triggered in the absence of abnormal high voltage disturbance.

[0031] In the above Figure 5In the illustrated embodiment, when the voltage at the first end of the high-side switch tube DH is greater than the voltage value of the power supply voltage VCC and the first regulating current source Vos1, the first comparison circuit 1031 in the first regulating circuit 103 outputs the first regulating signal CompH to the third end of the first regulating transistor MR1, so that the first regulating transistor MR1 is turned on, thereby increasing the current flowing from the second end of the low-side switch tube DL to the reference ground GND to supplement the current of the low-side bus in the CAN bus; when the voltage at the second end of the low-side switch tube DL is less than the negative value of the voltage value of the second regulating current source Vos2, the second comparison circuit 1041 in the second regulating circuit 104 outputs the second regulating signal CompL to the third end of the second regulating transistor MR2, so that the second regulating transistor MR2 is turned on, thereby increasing the current flowing from the power supply voltage VCC to the first end of the high-side switch tube DH, that is, the forward conduction current ID_H of the high-side switch tube DH, so as to supplement the current of the high-side bus in the CAN bus.

[0032] exist Figure 5 In the illustrated embodiment, the high-side transistor MH is a P-channel field effect transistor, and the low-side transistor ML is an N-channel field effect transistor.

[0033] In another embodiment, the high-side switch tube and the low-side switch tube in the high-side output stage circuit 101 and the low-side output stage circuit 102 can use field effect transistors to replace the above Figure 5 The high-side switch tube DH and the low-side switch tube DL in the embodiment shown.

[0034] Figure 6 An example diagram of the signal timing of a CAN transceiver circuit according to an embodiment of the present invention is provided to further illustrate the principle of improving the EMC performance of the circuit structure of the CAN transceiver in the above embodiments. Figure 3 or Figure 5 In the embodiment shown, a sudden IMP event or DPI event causes +100V high voltage interference in the CAN bus. For example, when the high voltage interference signal RF_IN is coupled into the CAN bus through a capacitor, if the TXD signal is dominant at this time, then at the moment of the IMP event or DPI event, the voltage at the second end of the high side switch tube DH rises sharply, and the bias state of the high side switch tube DH switches from forward conduction to reverse cutoff, and the reverse recovery current flows from the second end of the high side switch tube DH to the first end, resulting in Figure 2When the +100V high voltage comes, the VD_H signal in the middle appears a high voltage exceeding the power supply voltage VCC, and the forward conduction current ID_H of the high-side switch tube DH jumps at this time①, that is, the forward conduction current ID_H of the high-side switch tube DH cannot be cut off to 0 at the moment when the high-side switch tube DH switches to reverse cutoff, but a reverse current appears, resulting in a level jump or even a polarity jump of the high-side bus signal CANH in the CAN bus. According to the circuit structure of the first regulation circuit 103 in the above embodiments, it can be known that at this time, the high-side detection voltage VD_H is collected to the second input terminal of the first regulation circuit 103, and after being compared with the power supply voltage VCC, the first regulation circuit 103 generates a first regulation signal CompH. In the embodiment of applying the first comparator Comp1, the voltage at the output end of Comp1, i.e., the first regulating signal CompH, generates a corresponding jump voltage when the high voltage of +100V comes, so that the first regulating signal CompH changes from the logic low LogicL to the logic high LogicH, thereby increasing the bias voltage of the low-side transistor ML or turning on the first regulating transistor MR1, so that the forward conduction current ID_L of the low-side switch tube DL jumps at this time⑤, that is, the current in the low-side bus is compensated, so that the absolute value of the actual level in the low-side bus signal CANL increases accordingly, so that the polarity of the differential signal VDIFF does not jump to the logic low state or jump to the inversion, but appears as follows Figure 6 As shown in the jump ⑦, the differential signal VDIFF still represents the dominant state, that is, the generation of bit errors is prevented. The differential signal VDIFF is the difference signal between the high-side bus signal CANH and the low-side bus signal CANL in the CAN bus.

[0035] Similarly, when a sudden IMP event or DPI event causes -100V high voltage interference in the CAN bus, the TXD signal is dominant at this time. At the moment of the IMP event or DPI event, the voltage at the second end of the low-side switch tube DL drops sharply, and the bias state of the low-side switch tube DL switches from forward conduction to reverse cutoff. The reverse recovery current flows from the second end of the low-side switch tube DL to the first end, resulting in Figure 2The low-side detection voltage VD_L appears a negative high voltage lower than the reference ground voltage GND at the moment when the -100V high voltage comes, and ID_L jumps at this time, that is, the forward conduction current ID_L of the low-side switch tube DL cannot be cut off to 0 at the moment when the low-side switch tube DL switches to the reverse cut-off, but a reverse current appears, resulting in a level jump or even a polarity jump of the low-side bus signal CANL in the CAN bus. According to the circuit structure of the second regulation circuit 104 in the above embodiments, it can be known that at this time, the low-side detection voltage VD_L is collected to the second input terminal of the second regulation circuit 104, and after being compared with the reference ground voltage GND, the second regulation circuit 104 generates a second regulation signal CompL, and the second comparator Comp2 is applied in the second comparison circuit 1041. In the embodiment, the voltage at the output end of Comp2, i.e., the second regulating signal CompL, when the -100V high voltage comes, the low-side detection voltage VD_L generates a corresponding jump voltage, so that the second regulating signal CompL changes from a logic low LogicL to a logic high LogicH, thereby increasing the bias of the high-side transistor MH or turning on the second regulating transistor MR2, so that the forward conduction current ID_H of the high-side diode DH jumps at this time⑥, that is, the current in the high-side bus is compensated, so that the actual level of the high-side bus signal CANH increases accordingly, thereby compensating for the actual level difference between the high-side bus signal CANH and the low-side bus signal CANL, that is, the polarity of the differential signal VDIFF does not jump to a logic low state or jump to an inverted state, but appears as follows Figure 5 As shown in the jump ⑧, the differential signal VDIFF still represents the dominant state, that is, the generation of bit errors is prevented. The differential signal VDIFF is the difference signal between the high-side bus signal CANH and the low-side bus signal CANL in the CAN bus.

[0036] The circuit structure of the CAN transceiver provided in each embodiment of the present application utilizes two adjustment circuits to sample abnormal pulse voltages of the high-side output stage circuit 101 and the low-side output stage circuit 103 respectively, and prevents the explicit differential voltage from being too low due to the reverse recovery current of the switch tube by increasing the pull-up and pull-down currents, thereby keeping the differential voltage of the bus output stable, thereby improving the overall anti-interference capability of the circuit and improving the reliability and stability of communication.

[0037] Although the present invention has been described with reference to illustrative embodiments, this description is not intended to be interpreted in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the present invention, will be apparent to those skilled in the art when referring to the description. It is therefore intended that the appended claims cover all such modifications or embodiments.

Claims

1. A CAN transceiver, comprising: Sending data port, receiving sending data signal; High-side bus port, outputting high-side bus signal; Low-side bus port, outputting low-side bus signal; A high-side transistor has a first terminal, a second terminal and a third terminal, wherein the first terminal receives a power supply voltage and the second terminal receives a high-side gate signal; A high-side switch tube has a first end coupled to the third end of the high-side transistor, a second end coupled to the high-side bus port, and a voltage at the first end of the high-side switch tube is a high-side detection voltage; A low-side transistor having a first terminal, a second terminal and a third terminal, wherein the first terminal is coupled to a reference ground and the second terminal receives a low-side gate signal; A low-side switch tube has a first end coupled to the low-side bus port, a second end coupled to the third end of the low-side transistor, and a voltage at the second end of the low-side switch tube is a low-side detection voltage; A first regulating circuit has a first input terminal and a second input terminal, wherein the first input terminal receives a power supply voltage, the second input terminal receives a high-side detection voltage, and the first regulating circuit generates a first regulating signal according to the power supply voltage and the high-side detection voltage; A second regulating circuit has a first input terminal and a second input terminal, wherein the first input terminal is coupled to a reference ground, the second input terminal receives a low-side detection voltage, and the second regulating circuit generates a second regulating signal according to the reference ground and the low-side detection voltage; as well as A logic circuit generates a high side gate signal and a low side gate signal according to a transmission data signal, a first adjustment signal and a second adjustment signal; When the high-side detection voltage is greater than the sum of the power supply voltage and the first threshold, the forward current flowing through the low-side switch tube increases; when the low-side detection voltage is less than the second threshold, the forward current flowing through the high-side switch tube increases.

2. The CAN transceiver according to claim 1, wherein: When the high-side detection voltage is greater than the sum of the power supply voltage and the first threshold, the low-side gate signal controls the current flowing through the low-side transistor to increase; when the low-side detection voltage is less than the second threshold, the high-side gate signal controls the current flowing through the high-side transistor to increase. 3 . The CAN transceiver according to claim 1 , wherein the first threshold value ranges from 0 mV to 500 mV. 4 . The CAN transceiver according to claim 1 , wherein the second threshold value is in the range of -500 mV to 0 mV. 5 . The CAN transceiver according to claim 1 , wherein the high-side transistor is a P-type field effect transistor, and the low-side transistor is an N-type field effect transistor. 6 . The CAN transceiver according to claim 1 , wherein the high-side switch tube and the low-side switch tube comprise field effect transistors or diodes.

7. A CAN transceiver, comprising: Sending data port, receiving sending data signal; High-side bus port, outputting high-side bus signal; Low-side bus port, outputting low-side bus signal; A high-side transistor having a first end, a second end and a third end, wherein the first end receives a power supply voltage and the second end receives a transmission data signal; A high-side switch tube has a first end coupled to the third end of the high-side transistor, a second end coupled to the high-side bus port, and a voltage at the first end of the high-side switch tube is a high-side detection voltage; A low-side transistor having a first terminal, a second terminal and a third terminal, wherein the first terminal is coupled to a reference ground and the second terminal receives a transmission data non-signal; A low-side switch tube has a first end coupled to the low-side bus port, a second end coupled to the third end of the low-side transistor, and a voltage at the second end of the low-side switch tube is a low-side detection voltage; A first regulating circuit has a first input terminal and a second input terminal, wherein the first input terminal receives a power supply voltage, the second input terminal receives a high-side detection voltage, and the first regulating circuit generates a first regulating signal according to the power supply voltage and the high-side detection voltage; A second regulating circuit has a first input terminal and a second input terminal, wherein the first input terminal is coupled to a reference ground, the second input terminal receives a low-side detection voltage, and the second regulating circuit generates a second regulating signal according to the reference ground and the low-side detection voltage; A first regulating transistor has a first end, a second end and a third end, wherein the first end is coupled to the second end of the low-side switch tube, the second end is coupled to the reference ground, and the third end receives a first regulating signal; as well as A second regulating transistor has a first end, a second end and a third end, wherein the first end is coupled to the power supply voltage, the second end is coupled to the first end of the high-side switch tube, and the third end receives a second regulating signal; When the high-side detection voltage is greater than the sum of the power supply voltage and the first threshold, the forward current flowing through the low-side switch tube increases; when the low-side detection voltage is less than the second threshold, the forward current flowing through the high-side switch tube increases.

8. The CAN transceiver according to claim 7, wherein: When the high-side detection voltage is greater than the sum of the power supply voltage and the first threshold, the first adjustment signal controls the first adjustment transistor to turn on; when the low-side detection voltage is less than the second threshold, the second adjustment signal controls the second adjustment transistor to turn on. 9 . The CAN transceiver according to claim 7 , wherein the first threshold value ranges from 0 mV to 500 mV. 10 . The CAN transceiver according to claim 7 , wherein the second threshold value is in the range of −500 mV to 0 mV. 11 . The CAN transceiver according to claim 7 , wherein the high-side transistor is a P-channel field effect transistor, and the low-side transistor is an N-channel field effect transistor. 12 . The CAN transceiver according to claim 7 , wherein the first regulating transistor is an N-channel field effect transistor, and the second regulating transistor is a P-channel field effect transistor.

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