Read transistor structure, preparation method thereof and memory

Abstract

The invention relates to a read transistor structure, a preparation method thereof and a memory. The read transistor structure comprises a substrate, a dielectric layer, a first transistor, a second transistor and an isolation layer. The dielectric layer is located on the substrate. The first transistor is embedded in the dielectric layer. The second transistor is embedded in the dielectric layer and is opposite to the first transistor in the thickness direction of the dielectric layer, a source electrode of the second transistor is electrically connected with a source electrode of the first transistor, and a drain electrode of the second transistor is electrically connected with a drain electrode of the first transistor. The isolation layer is located between the first transistor and the second transistor. According to the read transistor structure, the preparation method thereof and the memory, one of the first transistor and the second transistor of the read transistor structure is used for forming the storage node and is electrically connected with the write transistor structure, and the other one is used for being connected with the read word line; therefore, mutual interference between writing and reading of the memory can be effectively reduced, and the performance of the device is improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a read transistor structure and a preparation method thereof, and a memory. Background Art

[0002] As the size of memory continues to shrink, the storage capacitance limitation of 1T1C structure memory becomes more and more obvious, resulting in the 1T1C structure facing a shrinking bottleneck. Nowadays, 2T0C structure memory is increasingly widely used.

[0003] The 2T0C structure is a structure in which two connected transistors serve as a memory cell. However, the performance of the existing 2T0C structure memory still needs to be improved. Summary of the invention

[0004] Based on this, it is necessary to provide a read transistor structure and a preparation method thereof to address the problem that the number of memory cells connected to a read word line in the prior art is limited.

[0005] In order to achieve the above object, on the one hand, the present invention provides a read transistor structure,

[0006] substrate;

[0007] a dielectric layer, located on the substrate,

[0008] A first transistor, embedded in the dielectric layer;

[0009] a second transistor, embedded in the dielectric layer, arranged opposite to the first transistor in the thickness direction of the dielectric layer, with a source of the second transistor electrically connected to the source of the first transistor, and a drain of the second transistor electrically connected to the drain of the first transistor;

[0010] An isolation layer is located between the first transistor and the second transistor.

[0011] In one embodiment, the read transistor structure includes:

[0012] A groove penetrates the dielectric layer in the thickness direction of the dielectric layer, and in the thickness direction of the dielectric layer, the groove includes a lower groove portion, a middle groove portion and a middle groove portion which are sequentially arranged, the first transistor is embedded in the lower groove portion, the isolation layer is located in the middle groove portion, and the second transistor is embedded in the upper groove portion.

[0013] In one embodiment, the read transistor structure includes:

[0014] A common source electrode, penetrating the dielectric layer on one side of the trench and spaced apart from the trench, wherein the common source electrode is connected to the first transistor and the second transistor;

[0015] The common drain penetrates the dielectric layer at the other side of the trench and is spaced apart from the trench. The common source is connected to the first transistor and the second transistor.

[0016] In one embodiment, the first transistor comprises:

[0017] A first gate, located in the trench;

[0018] A first gate dielectric layer is located in the trench and on the sidewall and top of the first gate;

[0019] A first active layer is located in the trench, on the sidewalls and top of the first gate dielectric layer, and in a region between the sidewalls of the first gate and the sidewalls of the trench;

[0020] The first source and the first drain are respectively located between the dielectric layer and the substrate at both sides of the groove and connected to the two ends of the first active layer. The first source is connected to the common source, and the first drain is connected to the common drain.

[0021] In one embodiment, the material of the first gate is the same as the material of the first source and / or the material of the first drain.

[0022] In one embodiment, the second transistor comprises:

[0023] A second active layer, located on the upper surface of the dielectric layer, the sidewall of the trench and the upper surface of the isolation layer, and having two ends connected to the common source and the common drain respectively;

[0024] A second gate dielectric layer, located on the sidewall of the second active layer and the upper surface of the second active layer in the trench;

[0025] The second gate is located on the surface of the second gate dielectric layer.

[0026] In one embodiment, the second gate fills up the trench.

[0027] In one embodiment, the isolation layer includes a first nitride layer;

[0028] Alternatively, the isolation layer includes a first oxide layer, a second nitride layer and a second oxide layer which are stacked;

[0029] Alternatively, the isolation layer includes a third nitride layer, a third oxide layer and a fourth nitride layer which are stacked.

[0030] The present invention also provides a method for preparing a read transistor structure, comprising the following steps:

[0031] providing a substrate;

[0032] forming a dielectric layer on the substrate;

[0033] forming a first transistor embedded in the dielectric layer on the dielectric layer;

[0034] forming an isolation layer on the first transistor;

[0035] A second transistor embedded in the dielectric layer is formed on the isolation layer, the second transistor is arranged opposite to the first transistor, the source of the second transistor is electrically connected to the source of the first transistor, and the drain of the second transistor is electrically connected to the drain of the first transistor.

[0036] In one embodiment, forming a dielectric layer on the substrate includes:

[0037] forming a dielectric material layer on the substrate;

[0038] Etching the dielectric material layer to form a groove penetrating the dielectric material layer, and the remaining dielectric material layer forms the dielectric layer, wherein in the thickness direction of the dielectric layer, the groove includes a groove lower portion, a groove middle portion, and a groove upper portion which are sequentially arranged;

[0039] The step of forming a first transistor embedded in the dielectric layer on the dielectric layer comprises:

[0040] forming the first transistor at the bottom of the trench;

[0041] forming an isolation layer on the first transistor, comprising:

[0042] forming the isolation layer in the middle of the trench;

[0043] forming a second transistor embedded in the dielectric layer on the isolation layer;

[0044] The second transistor is formed on the upper portion of the trench.

[0045] In one embodiment, before forming a dielectric material layer on the substrate, the method includes:

[0046] forming a sacrificial material layer on the substrate;

[0047] Etching the dielectric material layer to form a groove penetrating the dielectric material layer includes:

[0048] Etching the dielectric material layer and the sacrificial material layer to form a groove penetrating the dielectric material layer and the sacrificial material layer, and the remaining sacrificial material layer forms a sacrificial layer;

[0049] The forming of the first transistor at the bottom of the trench comprises:

[0050] removing the sacrificial layer;

[0051] Forming a first source electrode and a first drain electrode between the dielectric layer and the substrate at both sides of the trench respectively, and forming a first gate electrode at the bottom of the trench;

[0052] forming a first gate dielectric layer on the sidewall and top of the first gate;

[0053] A first active layer is formed on the sidewall and top of the first gate dielectric layer, and the first active layer fills the area between the sidewall of the first gate and the sidewall of the trench.

[0054] In one embodiment, a first source and a first drain are respectively formed between the dielectric layer and the substrate on both sides of the trench, and a first gate is formed at the bottom of the trench, including:

[0055] forming a conductive material layer on the surface of the substrate and the surface of the dielectric layer;

[0056] The conductive material layer is patterned to form the first gate, the first source and the first drain.

[0057] In one embodiment, forming the second transistor on the upper portion of the trench includes:

[0058] forming a second active layer on the upper surface of the isolation layer, the sidewalls of the trench and the upper surface of the dielectric layer;

[0059] forming a second gate dielectric layer on the sidewalls of the second active layer and on the upper surface of the second active layer in the trench;

[0060] A second gate is formed on the surface of the second gate dielectric layer.

[0061] In one embodiment, after forming the second transistor on the upper portion of the trench, the method includes:

[0062] Sequentially etching the second active layer and the dielectric layer located on the upper surface of the dielectric layer on both sides of the trench to form a first interconnection hole and a second interconnection hole penetrating to the first source electrode and the first drain electrode respectively;

[0063] Conductive material is filled in the first interconnection hole and the second interconnection hole to form a common source and a common drain respectively.

[0064] In one embodiment,

[0065] The present invention also provides a memory, comprising: a write transistor structure and a read transistor structure; the read transistor structure comprises a first transistor and a second transistor, the source of the second transistor is electrically connected to the source of the first transistor, and the drain of the second transistor is electrically connected to the drain of the first transistor; the first electrode of the write transistor structure is connected to the gate of the first transistor or the gate of the second transistor, and the first electrode is the source or the drain.

[0066] The above-mentioned read transistor structure, preparation method thereof and memory can effectively reduce the mutual interference between memory writing and reading by using the first transistor and the second transistor of the read transistor structure, one of which is used to form a storage node and is electrically connected to the write transistor structure, and the other is used to connect to the read word line, thereby improving device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0068] Figure 1 is a schematic diagram of a read transistor structure provided in an embodiment;

[0069] Figure 2 A schematic diagram of a storage unit provided in an embodiment;

[0070] Figure 3 A schematic diagram of a storage array provided in an embodiment;

[0071] Figure 4 A schematic diagram of a storage unit in a related art provided in an embodiment;

[0072] Figure 5 A schematic diagram of a storage array in a related art provided in an embodiment;

[0073] Figure 6 is a flow chart of a method for preparing a read transistor structure provided in an embodiment;

[0074] Figure 7 is a schematic diagram of a substrate provided in an embodiment;

[0075] Figure 8 A schematic diagram of a groove provided in an embodiment;

[0076] Fig. 9 A schematic diagram of a first gate, a first source, and a first drain provided in an embodiment;

[0077] Fig.10 is a schematic diagram of a first transistor provided in an embodiment;

[0078] Fig.11 is a schematic diagram of an isolation layer provided in an embodiment;

[0079] Fig.12 is a schematic diagram of a second transistor provided in an embodiment;

[0080] Fig.13 A schematic diagram of a first interconnection hole and a second interconnection hole provided in an embodiment;

[0081] Fig.14 A schematic diagram of a common source and a common drain provided in an embodiment;

[0082] Fig.15 A schematic diagram of a source conductive contact structure and a drain conductive contact structure provided in an embodiment;

[0083] Fig.16 A schematic diagram of an upper portion, a middle portion and a lower portion of a groove provided in an embodiment;

[0084] Fig.17 is a schematic diagram of a first active layer provided in an embodiment;

[0085] Fig.18 FIG. 4 is a schematic diagram of a second active layer provided in an embodiment.

[0086] Description of reference numerals: 10 - read transistor structure; 20 - write transistor structure; 21 - first electrode; 22 - second electrode; 30 - single-gate read transistor; 100 - substrate; 110 - trench; 111 - lower part of trench; 112 - middle part of trench; 113 - upper part of trench; 120 - first transistor; 121 - first gate; 122 - first drain; 123 - first source; 124 - first gate dielectric layer; 125 - first active layer; 130 - isolation layer; 140 -second transistor; 141-second gate; 142-second drain; 143-second source; 144-second active layer; 145-second gate dielectric layer; 150-first interconnection hole; 151-second interconnection hole; 160-common source; 161-common drain; 170-source conductive contact structure; 171-drain conductive contact structure; 200-dielectric layer; 201-dielectric material layer; 300-photoresist layer; 400-sacrificial layer; 401-sacrificial material layer. DETAILED DESCRIPTION

[0087] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0088] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0089] It should be understood that when an element or layer is referred to as being "on...", "connected to" other elements or layers, it may be directly on, connected to, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on...", "directly connected to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, and layers, these elements, components, regions, and layers should not be limited by these terms. These terms are merely used to distinguish one element, component, region, or layer from another element, component, region, or layer. Therefore, without departing from the teachings of the present invention, the first element, component, region, or layer discussed below may be represented as a second element, component, region, or layer.

[0090] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0091] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0092] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic representations of idealized embodiments (and intermediate structures) of the invention, and variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are contemplated. Thus, embodiments of the invention should not be limited to the particular shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. The regions shown in the figures are schematic in nature, and their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the invention.

[0093] In one embodiment, see Figure 1 and Figure 2 , a memory is provided. The memory includes a read transistor structure 10 and a write transistor structure 20. In addition, the memory may further include a bit line BL, a write word line WWL and a read word line RWL.

[0094] The read transistor structure 10 includes a first transistor 120 and a second transistor 140. The source of the second transistor 140 is electrically connected to the source of the first transistor 120 to form the source of the read transistor structure 10. The drain of the second transistor 140 is electrically connected to the drain of the first transistor 120 to form the drain of the read transistor structure 10.

[0095] One of the source and drain of the read transistor structure 10 is connected to the bit line BL, and the other is connected to the ground terminal GND. At the same time, the gate of one of the first transistor 120 and the second transistor 140 is connected to the first electrode 21 of the write transistor structure 20, thereby forming a storage node SN. The first electrode 21 is the source or drain of the transistor structure 20. The gate of the other of the first transistor 120 and the second transistor 140 is connected to the read word line RWL. As an example, see Figure 2 The gate of the first transistor 120 is connected to the first electrode 21 of the write transistor structure 20, thereby forming a storage node SN of the memory cell, and the gate of the second transistor 140 is connected to the read word line RWL.

[0096] The gate of the write transistor structure 20 is connected to the write word line WWL. At the same time, the first electrode 21 of the write transistor structure 20 is connected to the gate of the first transistor 120, and the second electrode 22 of the write transistor structure 20 is connected to the bit line BL. Among them, one of the first electrode 21 and the second electrode 22 is the source of the write transistor structure 20, and the other is the drain of the write transistor structure 20.

[0097] See also Figure 3 The memory includes a plurality of memory cells arranged in an array. Each memory cell includes a read transistor structure 10 and a write transistor structure 20, thereby forming a 2T0C cell architecture.

[0098] For related technologies, see Figure 4 In a 2T0C cell architecture, the read transistor structure is often a single-gate read transistor 30. The read word line RWL and the read bit line RBL are respectively connected to the source and drain of the single-gate read transistor 30. The first electrode 21 of the write transistor structure 20 is connected to the gate of the single-gate read transistor 30, thereby forming a storage node SN. In addition, the second electrode 22 of the write transistor structure 20 is connected to the write bit line WBL. The gate of the write transistor structure 20 is connected to the write word line WWL.

[0099] When writing to the memory cell, a corresponding voltage is applied to the write word line WWL to turn on the write transistor structure 20. A corresponding voltage is applied to the write bit line WBL to charge the storage node SN to present a high voltage or a low voltage, so that the storage node SN is written with data "1" or "0".

[0100] When reading a memory cell, a voltage is applied to the read word line RWL so that there is a certain voltage difference between it and the read bit line RBL. When the storage node SN is at a high voltage, the single-gate read transistor 30 is turned on. At this time, the read bit line RWL can read the current, thereby reading the data "1". On the contrary, when the storage node SN is at a low voltage, the single-gate read transistor 30 is turned off, and no current is read on the read bit line RWL, thereby reading the data "0".

[0101] However, see Figure 5When the 2T0C unit architecture of the single-gate read transistor 30 is adopted, the read word line RWL in the single-gate read transistor 30 is connected to the source of the single-gate read transistor 30, and current passes through when the read operation is performed. At this time, if the number of memory cells connected to each read word line RWL is large, the read word line RWL has a current accumulation effect and a voltage reduction effect, thereby affecting the memory performance. Therefore, when the 2T0C unit architecture of the single-gate read transistor 30 is adopted, the number of memory cells connected to each read word line RWL is limited. At the same time, the read bit line RBL and the write bit line WBL are independently set, and the two are connected to different signal amplifiers, thereby occupying a larger chip area, thereby affecting the storage density.

[0102] In this embodiment, see Figure 1 and Figure 2 The read transistor structure 10 includes a first transistor 120 and a second transistor 140. A gate of one of the first transistor 120 and the second transistor 140 is used to form a storage node SN, and a gate of the other is connected to a read word line RWL for controlling a read operation.

[0103] The following describes the reading and writing process of the storage unit by taking the example that the gate of the first transistor 120 is used to form the storage node SN and the gate of the second transistor 140 is connected to RWL.

[0104] When writing to the memory cell, a corresponding voltage is applied to the write word line WWL to turn on the write transistor structure 20. A corresponding voltage is applied to the bit line BL to charge the storage node SN to present a high voltage or a low voltage, so that the storage node SN is written with data "1" or "0".

[0105] When the voltage written to the storage node SN is different in level, the first transistor 120 connected thereto will be in different conduction states.

[0106] When reading the memory cell, a corresponding voltage is applied to the read word line RWL to turn on the second transistor 140. At this time, since the different voltages written on the storage node SN will cause the first transistor 120 to be in different conduction states, different currents can be read on the bit line BL when different data are written to the storage node SN, so that the data "1" or data "0" written to the storage node SN can be read.

[0107] In this embodiment, the gate of a transistor (the first transistor 120 or the second transistor 140) in the read transistor structure 10 is connected by the read word line RWL to control the read operation, thereby making the read operation more efficient and flexible. At the same time, when the read word line RWL is connected to the gate of one of the transistors, the magnitude of the current flowing through the read word line RWL is very small, and it can be considered that no current flows through the read word line RWL. Therefore, at this time, the current accumulation effect and the voltage reduction effect on the read word line RWL can be effectively avoided or reduced, so that the number of storage cells connected to the read word line RWL can be effectively increased, and the storage density can be effectively improved.

[0108] At the same time, in this embodiment, the read transistor structure 10 and a write transistor structure 20 are connected to the same bit line BL, which can reduce the number of bit lines BL. At this time, the number of signal amplifiers connected to the bit line BL is also reduced accordingly, and the area of ​​the memory chip occupied is reduced, thereby effectively improving the storage density.

[0109] In addition, the read transistor structure 10 of this embodiment includes a first transistor 120 and a second transistor 140 that are independently arranged, one of which is used to form a storage node SN, and the other is used to connect to the read word line RWL, thereby effectively reducing the mutual interference between writing and reading, thereby improving device performance.

[0110] In one embodiment, see Figure 6 , a method for preparing a read transistor structure 10 is provided, comprising the following steps:

[0111] Step S100: providing a substrate 100 .

[0112] Step S300 : forming a dielectric layer 200 on the substrate 100 .

[0113] Step S400 : forming a first transistor 120 embedded in the dielectric layer 200 on the dielectric layer 200 .

[0114] Step S500 : forming an isolation layer 130 on the first transistor 120 .

[0115] Step S600 : forming a second transistor 140 embedded in the dielectric layer 200 on the isolation layer 130 , the second transistor 140 being arranged opposite to the first transistor 120 , and the source of the second transistor 140 being electrically connected to the source of the first transistor 120 , and the drain of the second transistor 140 being electrically connected to the drain of the first transistor 120 .

[0116] In step S100, the base 100 may include a substrate. Of course, other structures, such as bit lines, etc., may also be provided on the substrate.

[0117] In step S300, refer to Figure 8 The dielectric layer 200 may include one layer or multiple layers. As an example, the dielectric layer 200 may include a silicon dioxide layer, a silicon oxide layer, a silicon oxynitride layer, and the like.

[0118] In step S400, refer to Fig.10 The dielectric layer 200 may include a lower surface and an upper surface relative to each other. The surface of the dielectric layer 200 facing the substrate 100 may be the lower surface, and the surface away from the substrate 100 may be the upper surface. The first transistor 120 may be partially embedded in the dielectric layer 200 and partially located below the lower surface. Of course, the first transistor 120 may also be fully embedded in the dielectric layer 200.

[0119] In step S500, refer to Fig.11 , an isolation layer 130 may be formed above the first transistor 120. The isolation layer 130 is used to isolate the first transistor 120 from a second transistor 140 formed in a subsequent step.

[0120] The isolation layer 130 may be a single-layer structure or a multi-layer structure. For example, when the isolation layer 130 is a single-layer structure, the isolation layer 130 may include a first nitride layer. When the isolation layer 130 is a multi-layer structure, the isolation layer 130 may include a first oxide layer, a second nitride layer, and a second oxide layer stacked to form an ONO (Oxide-Nitride-Oxide) structure. Alternatively, the isolation layer 130 includes a third nitride layer, a third oxide layer, and a fourth nitride layer stacked to form a NON (Nitride Oxide Nitride) structure.

[0121] In step S600, refer to Fig.12 , the second transistor 140 is arranged opposite to the first transistor 120. It can be understood that the second transistor 140 can be partially embedded in the dielectric layer 200 and partially located on the upper surface of the dielectric layer 200. Of course, the second transistor 140 can also be fully embedded in the dielectric layer 200.

[0122] See also Fig.15 The source of the first transistor 120 is electrically connected to the source of the second transistor 140 to form the source of the read transistor structure 10 . The drain of the first transistor 120 is electrically connected to the drain of the second transistor 140 to form the drain of the read transistor structure 10 .

[0123] In this embodiment, the read transistor structure 10 includes a first transistor 120 and a second transistor 140 arranged opposite to each other on the surface of the dielectric layer 200, and an isolation layer 130 is located between the first transistor 120 and the second transistor 140, thereby effectively reducing the coupling problem between the first transistor 120 and the second transistor 140, reducing the degree of mutual influence between the first transistor 120 and the second transistor 140, and thus improving the performance of the read transistor structure 10. Moreover, the first transistor 120 and the second transistor 140 are arranged opposite to each other, so that the source of the first transistor 120 is electrically connected to the source of the second transistor 140, and the drain of the first transistor 120 is electrically connected to the drain of the second transistor 140.

[0124] In one embodiment, step S300 includes:

[0125] Step S310 : forming a dielectric material layer 201 on the substrate 100 .

[0126] Step S320: etching the dielectric material layer 201 to form a trench 110 penetrating the dielectric material layer 201, and the remaining dielectric material layer 201 forms the dielectric layer 200. In the thickness direction of the dielectric layer 200, the trench 110 includes a trench upper portion 113, a trench middle portion 112 and a trench lower portion 111 arranged in sequence.

[0127] Step S400 includes:

[0128] Step S410 : forming a first transistor 120 in the trench lower portion 111 .

[0129] Step S500 includes:

[0130] Step S510 : forming an isolation layer 130 in the middle portion 112 of the trench.

[0131] Step S600 includes:

[0132] Step S610 : forming a second transistor 140 in the trench lower portion 111 .

[0133] In step S310, refer to Figure 7 The dielectric material layer 201 may be formed by a deposition process. The deposition process may include but is not limited to one or more of a chemical vapor deposition process, an atomic layer deposition process, a high-density plasma deposition process, a plasma enhanced deposition process, and a spin-coating insulating dielectric layer process.

[0134] In step S320, refer to Figure 7 , a photoresist layer 300 may be first formed on the dielectric material layer 201. The photoresist layer 300 has an opening, which exposes the dielectric material layer 201 and defines the position of the trench 110 to be formed subsequently.

[0135] See also Figure 8 Based on the photoresist layer 300, the dielectric material layer 201 is etched to form a groove 110 penetrating the dielectric material layer 201, and the remaining dielectric material layer 201 forms the dielectric layer 200. When etching the dielectric material layer 201, dry etching or wet etching can be used. For example, dry etching can include any one of reactive ion etching, inductively coupled plasma etching or high concentration plasma etching.

[0136] See also Fig.16 In the thickness direction of the dielectric layer 200, the trench 110 includes a trench upper portion 113, a trench middle portion 112, and a trench lower portion 111 which are sequentially arranged. In this embodiment, the trench upper portion 113, the trench middle portion 112, and the trench lower portion 111 are only illustrative, and are not specifically limited to the trench upper portion 113, the trench middle portion 112, and the trench lower portion 111.

[0137] In step S410, refer to Fig. 9 and Fig.10 , the first transistor 120 is formed in the lower portion 111 of the trench.

[0138] In step S510, refer to Fig.11 , the isolation layer 130 is formed in the middle portion 112 of the trench.

[0139] In step S610, refer to Fig.12 , the second transistor 140 is formed in the upper portion 113 of the trench 110 .

[0140] At this time, the first transistor 120 , the isolation layer 130 , and the second transistor 140 are all formed in the trench 110 , so that the first transistor 120 and the second transistor 140 are arranged relative to each other, and the first transistor 120 and the second transistor 140 can be effectively isolated by the isolation layer 130 .

[0141] In one embodiment, before step S300, the following steps are included:

[0142] Step S200 : forming a sacrificial material layer 401 on the substrate 100 .

[0143] Step S320 includes:

[0144] Step S321 : etching the dielectric material layer 201 and the sacrificial material layer 401 to form a groove 110 penetrating the dielectric material layer 201 and the sacrificial material layer 401 , and the remaining sacrificial material layer 401 forms a sacrificial layer 400 .

[0145] Step S410 includes:

[0146] Step S411 : removing the sacrificial layer 400 .

[0147] Step S412 : forming a first source 123 and a first drain 122 between the dielectric layer 200 and the substrate 100 on both sides of the trench 110 , respectively, and forming a first gate 121 at the bottom of the trench 110 .

[0148] Step S413 : forming a first gate dielectric layer 124 on the sidewall and top of the first gate 121 .

[0149] Step S414 : forming a first active layer 125 on the sidewalls and the top of the first gate dielectric layer 124 , wherein the first active layer 125 fills the area between the sidewalls of the first gate 121 and the sidewalls of the trench.

[0150] In step S200, refer to Figure 7 The sacrificial material layer 401 may be formed by chemical vapor deposition or physical vapor deposition. The sacrificial material layer 401 may be a single-layer structure or a multi-layer structure.

[0151] In step S321, refer to Figure 7 , the photoresist layer 300 may be formed on the upper surface of the dielectric material layer 201. Figure 7 and Figure 8 Based on the photoresist layer 300 , the dielectric layer 200 and the sacrificial material layer 401 are etched to form the groove 110 penetrating the dielectric material layer 201 and the sacrificial material layer 401 . After etching, the remaining dielectric material layer 201 forms the dielectric layer 200 , and the remaining sacrificial material layer 401 forms the sacrificial layer 400 .

[0152] In step S411 , the sacrificial layer 400 may be removed by wet etching or the like.

[0153] In step S412, refer to Fig. 9 After the sacrificial layer 400 is removed, there is a gap between the lower surface of the dielectric layer 200 and the upper surface of the substrate 100. At this time, a first source 123 and a first drain 122 can be formed between the dielectric layer 200 and the substrate 100 on both sides of the trench 110. At the same time, a first gate 121 can be formed at the bottom of the trench 110.

[0154] The first gate 121 may be formed simultaneously with the first source 123 and the first drain 122 , or may be formed in steps.

[0155] The material of the first gate 121 may include, but is not limited to, any one or more of titanium nitride, titanium, tungsten silicide, and tungsten.

[0156] In step S413, refer to Fig.10, forming a first gate dielectric layer 124 on the sidewalls and top of the first gate 121. As an example, the first gate dielectric material layer may be firstly deposited on the upper surface and sidewalls of the first gate 121, the bottom and sidewalls of the trench 110, and the entire upper surface of the dielectric layer 200, and then the first gate dielectric material layer located on the upper surface of the dielectric layer 200 and a portion of the first gate dielectric material layer on the bottom and sidewalls of the trench 110 are removed by etching or other methods, and the first gate dielectric material layer covering the upper surface and sidewalls of the first gate 121 is retained to form the first gate dielectric layer 124.

[0157] The material of the first gate dielectric layer 124 may include a material with a high-k dielectric constant, such as aluminum oxide, hafnium oxide, hafnium oxynitride, zirconium oxide, tantalum oxide, titanium oxide, or strontium titanium oxide.

[0158] In step S414, refer to Fig.10 , a first active material layer may be deposited on the surface of the first gate dielectric layer 124, the sidewall of the trench 110, and the upper surface of the dielectric layer 200, and then the first active material layer on the upper surface of the dielectric layer 200 and part of the first active material layer on the sidewall of the trench 110 may be removed by etching, and the first active material layer located on the upper surface of the first gate dielectric layer 124 and between the sidewall of the first gate dielectric layer 124 and the sidewall of the trench 110 may be retained to form a first active layer 125. The first active layer 125 surrounds the first gate dielectric layer 124. Moreover, the first active layer 125 may fill the area between the sidewall of the first gate 121 and the sidewall of the trench, so that the first active layer 125 is connected to the first source 123 and the first drain 122. As an example, the material of the first active layer 125 may include indium gallium zinc oxide (IGZO).

[0159] In this embodiment, by forming a sacrificial layer 400 , it is convenient to form a first source 123 and a first drain 122 at the bottom of both sides of the trench, so as to facilitate connection with the source and drain of the second transistor 140 formed subsequently to form the source and drain of the read transistor structure 10 .

[0160] At the same time, the first active layer 125 is located on the sidewall and top of the first gate dielectric layer 124. Fig.17 , the channel length value of the first transistor 120 is the sum of the length of region 1, the length of region 2, and the length of region 3. Compared with the planar transistor, within the same area, the first transistor 120 has a longer channel length to improve its gate control capability. Moreover, by adjusting the depth of the trench 110 and the height of the first gate 121, channel lengths of different lengths can be obtained, which is convenient for miniaturizing the planar size of the transistor.

[0161] Of course, in other embodiments, the first transistor 120 may also be a planar transistor.

[0162] In one embodiment, step S412 includes:

[0163] Step S4121 : forming a conductive material layer on the surface of the substrate 100 and the surface of the dielectric layer 200 .

[0164] Step S4122 : performing patterning on the conductive material layer to form a first gate 121 , a first source 123 and a first drain 122 .

[0165] In step S4121, a conductive material layer may be deposited on the upper surface of the dielectric layer 200, the sidewalls of the dielectric layer 200, the lower surface of the dielectric layer 200, and the bottom of the trench 110. Since the sacrificial layer 400 is removed in the above step, there is a gap between the lower surface of the dielectric layer 200 and the upper surface of the substrate 100. Therefore, the conductive material layer may fill the gap between the lower surface of the dielectric layer 200 and the upper surface of the substrate 100.

[0166] In step S4122, refer to Fig. 9 , a portion of the conductive material layer can be removed by etching or other methods, and the conductive material layer between the lower surface of the dielectric layer 200 and the upper surface of the substrate 100 is retained to form the first source 123 and the first drain 122, and a portion of the conductive material layer at the bottom of the trench is retained to form the first gate 121. At this time, the first gate 121, the first source 123, and the first drain 122 are made of the same material, which can be conductive materials.

[0167] After step S4122, a first gate dielectric layer 124 and a first active layer 125 may be formed to form a first transistor 120. Thereafter, an isolation layer 130 is formed in the trench.

[0168] In this embodiment, by forming a conductive material layer on the surface of the substrate 100 and the surface of the dielectric layer 200, and then patterning the conductive material layer, the first gate 121, the first source 123, and the first drain 122 can be formed simultaneously. In this case, the process steps for forming the first gate 121, the first source 123, and the first drain 122 can be simplified.

[0169] In one embodiment, step S610 includes:

[0170] Step S611 : forming a second active layer 144 on the upper surface of the isolation layer 130 , the sidewalls of the trench, and the upper surface of the dielectric layer 200 .

[0171] Step S612 : forming a second gate dielectric layer 145 on the sidewalls of the second active layer 144 and the upper surface of the second active layer 144 in the trench 110 .

[0172] Step S613 : forming a second gate 141 on the surface of the second gate dielectric layer 145 .

[0173] In step S611, refer to Fig.13 The second active layer 144 may be formed on the upper surface of the isolation layer 130, the sidewall of the trench, and the upper surface of the dielectric layer 200 by deposition or the like. As an example, the material of the second active layer 144 may include IGZO.

[0174] The portion of the second active layer 144 located on the upper surface of the dielectric layer 200 may be formed into a second source 143 and a second drain 142 through steps such as doping.

[0175] In step S612, the second gate dielectric layer 145 is located on the sidewalls and the upper surface of the second active layer 144. Similar to the first gate dielectric layer 124, the material of the second gate dielectric layer 145 may also include a material with a high-k dielectric constant. For example, aluminum oxide, hafnium oxide, hafnium oxynitride, zirconium oxide, tantalum oxide, titanium oxide, or strontium titanium oxide. The material of the second gate dielectric layer 145 may be the same as or different from the material of the first gate dielectric layer 124.

[0176] In step S613, the second gate 141 is located on the surface of the second gate dielectric layer 145. At this time, the second gate 141, the second gate dielectric layer 145 and the second active layer 144 can fill the trench 110. The material of the second gate 141 can include but is not limited to any one or more of titanium nitride, titanium, tungsten silicide and tungsten. The material of the second gate 141 can be the same as that of the first gate 121.

[0177] As an example, when forming the second gate dielectric layer 145, the second gate dielectric material layer can be first deposited on the entire surface of the second active layer 144, and then the second gate material layer can be deposited on the surface of the second gate dielectric material layer. Then, a planarization treatment is performed to remove the second gate dielectric material layer and the second gate material layer located on the upper surface of the dielectric layer 200. The remaining second gate dielectric material layer forms the second gate dielectric layer 145, and the remaining second gate material layer forms the second gate 141.

[0178] In this embodiment, similar to the first active layer 125, see Fig.18 , the channel length of the second transistor 140 is the sum of the length of the 4th region, the length of the 5th region, and the length of the 6th region. Compared with the planar transistor, within the same area, the second transistor 140 has a longer channel length to improve its gate control capability. Moreover, by adjusting the depth of the upper portion 113 of the trench, channel lengths of different lengths can be obtained, which facilitates miniaturization of the transistor plane size.

[0179] Of course, in other embodiments, the second transistor 140 may also be a planar type.

[0180] Furthermore, the second source 143 and the second drain 142 formed by doping the second active layer 144 on the upper surface of the dielectric layer 200 can also be easily connected to the first transistor 120 .

[0181] In one embodiment, after step S610, the following steps are included:

[0182] Step S700 : etching the second active layer 144 and the dielectric layer 200 on the upper surface of the dielectric layer 200 on both sides of the trench 110 in sequence to form a first interconnection hole 150 and a second interconnection hole 151 penetrating the first source 123 and the first drain 122 respectively.

[0183] Step S710 : Filling the first interconnection hole 150 and the second interconnection hole 151 with a conductive material to form a common source 160 and a common drain 161 , respectively.

[0184] In step S700, refer to Fig.12 and Fig.13 The second source electrode 143 , the dielectric layer 200 and the first source electrode 123 may be sequentially etched from the upper surface of the second source electrode 143 to form the first interconnection hole 150 .

[0185] Similarly, the second drain electrode 142 , the dielectric layer 200 and the first drain electrode 122 may be etched in sequence from the upper surface of the second drain electrode 142 to form the second interconnection hole 151 .

[0186] In step S710, refer to Fig.14 , the first interconnection hole 150 and the second interconnection hole 151 may be filled with a conductive material to form a common source 160 and a common drain 161 .

[0187] At this time, the common source 160 is connected to the first source 123 and the second source 143 , and the common drain 161 is connected to the first drain 122 and the second drain 142 , thereby forming the source and drain of the read transistor structure 10 .

[0188] A metal barrier layer may also be provided between the common source 160, the common drain 161 and the dielectric layer 200. The metal barrier layer includes but is not limited to at least one of a titanium nitride layer, a cobalt layer, a platinum layer and a titanium tungsten layer.

[0189] In the memory, the common source 160 and the common drain 161 can control the disconnection or conduction of the read transistor.

[0190] Of course, see Fig.15A source conductive contact structure 170 and a drain conductive contact structure 171 may be formed above the common source 160 and the common drain 161. Through the source conductive contact structure 170 and the drain conductive contact structure 171. One of the source conductive contact structure 170 and the drain conductive contact structure 171 may be connected to the bit line BL, and the other may be connected to the ground terminal GND.

[0191] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0192] Based on the same inventive concept, in one embodiment, please refer to Figure 1 , a read transistor structure 10 is provided, including a substrate 180 , a dielectric layer 200 , a first transistor 120 , an isolation layer 130 and a second transistor 140 .

[0193] The base 100 may include a substrate, and a bit line structure and the like may also be disposed on the base 100 .

[0194] The dielectric layer 200 is located on the substrate 100. The dielectric layer 200 may include one layer or multiple layers. As an example, the dielectric layer 200 may include a silicon dioxide layer, a silicon oxide layer, a silicon oxynitride layer, and the like.

[0195] The first transistor 120 is embedded in the dielectric layer 200. The first transistor 120 may be partially embedded in the dielectric layer 200. Of course, the first transistor 120 may also be fully embedded in the dielectric layer 200.

[0196] The isolation layer 130 is located in the dielectric layer 200 between the first transistor 120 and the second transistor 140 , and is used to isolate the first transistor 120 from the second transistor 140 .

[0197] The second transistor 140 is embedded in the dielectric layer 200. The second transistor 140 may be partially embedded in the dielectric layer 200. Of course, the second transistor 140 may also be fully embedded in the dielectric layer 200.

[0198] The second transistor 140 is disposed opposite to the first transistor 120 in the thickness direction of the dielectric layer 200 , and the source of the second transistor 140 is electrically connected to the source of the first transistor 120 , and the drain of the second transistor 140 is electrically connected to the drain of the first transistor 120 .

[0199] In this embodiment, the read transistor structure 10 includes a first transistor 120 and a second transistor 140 disposed opposite to each other on the surface of the dielectric layer 200, and electrodes corresponding to the first transistor 120 and the second transistor 140 are electrically connected to form a source and a drain of the read transistor structure 10. The isolation layer 130 reduces the coupling problem between the first transistor 120 and the second transistor 140, reduces the degree of mutual influence between the first transistor 120 and the second transistor 140, and thus improves the performance of the read transistor structure 10.

[0200] In one embodiment, read transistor structure 10 includes trench 110 .

[0201] The groove 110 penetrates the dielectric layer 200 in the thickness direction of the dielectric layer 200. Fig.16 In the thickness direction of the dielectric layer 200, the trench 110 includes a trench upper portion 113, a trench middle portion 112, and a trench lower portion 111 arranged in sequence. At this time, the first transistor 120 is embedded in the trench upper portion 113, the isolation layer 130 is located in the trench middle portion 112, and the second transistor 140 is embedded in the trench lower portion 111.

[0202] In one embodiment, see Figure 1 , the read transistor structure 10 includes a common source 160 and a common drain 161 .

[0203] The common source 160 penetrates the dielectric layer 200 on one side of the trench 110 and is spaced apart from the trench 110. The common source 160 is connected to the first transistor 120 and the second transistor 140.

[0204] The common drain 161 penetrates the dielectric layer 200 on the other side of the trench 110 and is spaced apart from the trench 110. The common source 160 is connected to the first transistor 120 and the second transistor 140.

[0205] The common source 160 and the common drain 161 can be made of conductive materials, such as cobalt, nickel, titanium, tungsten, copper, aluminum and other metal materials.

[0206] The common source 160 is the source of the read transistor structure 10, and the common drain 161 is the drain of the common drain 161. In the memory, the common source 160 and the common drain 161 can control the disconnection or conduction of the read transistor.

[0207] Of course, a metal barrier layer may also be provided between the common source 160, the common drain 161 and the dielectric layer 200. The metal barrier layer includes but is not limited to at least one of a titanium nitride layer, a cobalt layer, a platinum layer and a titanium tungsten layer.

[0208] A source conductive contact structure 170 and a drain conductive contact structure 171 may also be formed above the common source 160 and the common drain 161. The read transistor structure 10 may be connected to other devices through the source conductive contact structure 170 and the drain conductive contact structure 171. For example, see Figure 4 One of the source conductive contact structure 170 and the drain conductive contact structure 171 may be connected to the bit line BL, and the other may be connected to the ground terminal GND.

[0209] In one embodiment, see Figure 1 The first transistor 120 includes a first gate 121 , a first gate dielectric layer 124 , a first active layer 125 , a first source 123 and a first drain 122 .

[0210] The first gate 121 is located in the trench 110. The material of the first gate 121 may include but is not limited to any one or more of titanium nitride, titanium, tungsten silicide and tungsten.

[0211] The first gate dielectric layer 124 is located in the trench 110 and on the sidewalls and the top of the first gate 121. The first gate dielectric layer 124 surrounds the first gate 121. The material of the first gate dielectric layer 124 may include a material with a high-k dielectric constant, such as aluminum oxide, hafnium oxide, hafnium oxynitride, zirconium oxide, tantalum oxide, titanium oxide, or strontium titanium oxide.

[0212] The first active layer 125 is located in the trench 110, and is located on the sidewall and top of the first gate dielectric layer 124, and is located in the area between the sidewall of the first gate 121 and the sidewall of the trench 110. The first active layer 125 surrounds the first gate dielectric layer 124, making the entire channel area more stable. As an example, the material of the first active layer 125 may include IGZO.

[0213] The first source 123 and the first drain 122 are respectively located between the dielectric layer 200 and the substrate 100 on both sides of the trench 110 and connect two ends of the first active layer 125. As an example, the material of the first gate 121 is the same as that of the first source 123 and / or the first drain 122.

[0214] Likewise, in one embodiment, see Figure 1 The second transistor 140 includes a second gate 141 , a second gate dielectric layer 145 , a second active layer 144 , a second source 143 and a second drain 142 .

[0215] The second active layer 144 may be located on the isolation layer 130 and the upper surface and the sidewall of the trench of the dielectric layer 200. As an example, the material of the second active layer 144 may include IGZO.

[0216] The two parts of the second active layer 144 located on the upper surface of the dielectric layer 200 may be respectively the second source 143 and the second drain 142. It can be understood that the second source 143 and the second drain 142 may be formed by doping the two parts of the second active layer 144 located on the upper surface of the dielectric layer 200. Of course, when doping, it can be divided into a heavily doped area, a lightly doped area, etc.

[0217] The second gate dielectric layer 145 is located on the sidewalls of the second active layer 144 and the upper surface of the second active layer 144 in the trench 110. The material of the second gate dielectric layer 145 may include a material with a high-k dielectric constant, such as aluminum oxide, hafnium oxide, hafnium oxynitride, zirconium oxide, tantalum oxide, titanium oxide, or strontium titanium oxide.

[0218] The second gate 141 is located on the surface of the second gate dielectric layer 145. The material of the second gate 141 may include but is not limited to any one or more of titanium nitride, titanium, tungsten silicide and tungsten.

[0219] Exemplarily, the second gate 141 fills up the trench 110. The upper surface of the second gate 141, the upper surface of the second gate dielectric layer 145, and the upper surface of the second active layer 144 may be flush.

[0220] In one embodiment, the isolation layer 130 includes a first nitride layer. Alternatively, the isolation layer 130 includes a first oxide layer, a second nitride layer, and a second oxide layer (ONO structure) stacked together. Alternatively, the isolation layer 130 includes a third nitride layer, a third oxide layer, and a fourth nitride layer (NON structure) stacked together. By stacking oxide and nitride to form the isolation layer 130, the electrical isolation effect of the isolation layer 130 can be improved.

[0221] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0222] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A read transistor structure, characterized in that: include: substrate; a dielectric layer, located on the substrate, A first transistor, embedded in the dielectric layer; a second transistor, embedded in the dielectric layer, arranged opposite to the first transistor in the thickness direction of the dielectric layer, with a source of the second transistor electrically connected to the source of the first transistor, and a drain of the second transistor electrically connected to the drain of the first transistor; An isolation layer is located between the first transistor and the second transistor.

2. The read transistor structure according to claim 1, characterized in that: The read transistor structure includes: A groove penetrates the dielectric layer in the thickness direction of the dielectric layer, and in the thickness direction of the dielectric layer, the groove includes a lower groove portion, a middle groove portion and a middle groove portion which are sequentially arranged, the first transistor is embedded in the lower groove portion, the isolation layer is located in the middle groove portion, and the second transistor is embedded in the upper groove portion.

3. The read transistor structure according to claim 2, characterized in that: The read transistor structure includes: a common source electrode, penetrating the dielectric layer on one side of the trench and spaced apart from the trench, wherein the common source electrode is connected to the first transistor and the second transistor; The common drain penetrates the dielectric layer at the other side of the trench and is spaced apart from the trench. The common source is connected to the first transistor and the second transistor.

4. The read transistor structure according to claim 3, characterized in that: The first transistor comprises: A first gate, located in the trench; A first gate dielectric layer is located in the trench and on the sidewall and top of the first gate; A first active layer is located in the trench, on the sidewalls and top of the first gate dielectric layer, and in a region between the sidewalls of the first gate and the sidewalls of the trench; The first source and the first drain are respectively located between the dielectric layer and the substrate at both sides of the groove and connected to the two ends of the first active layer. The first source is connected to the common source, and the first drain is connected to the common drain.

5. The read transistor structure according to claim 4, characterized in that: The material of the first gate electrode is the same as the material of the first source electrode and / or the material of the first drain electrode.

6. The read transistor structure according to claim 3, characterized in that: The second transistor comprises: A second active layer, located on the upper surface of the dielectric layer, the sidewall of the trench and the upper surface of the isolation layer, and having two ends connected to the common source and the common drain respectively; A second gate dielectric layer, located on the sidewall of the second active layer and the upper surface of the second active layer in the trench; The second gate is located on the surface of the second gate dielectric layer.

7. The read transistor structure according to claim 6, characterized in that: The second gate fills up the trench.

8. The read transistor structure according to claim 1, wherein: The isolation layer includes a first nitride layer; Alternatively, the isolation layer includes a first oxide layer, a second nitride layer and a second oxide layer which are stacked; Alternatively, the isolation layer includes a third nitride layer, a third oxide layer and a fourth nitride layer which are stacked.

9. A method for preparing a read transistor structure, characterized in that: The steps include: providing a substrate; forming a dielectric layer on the substrate; forming a first transistor embedded in the dielectric layer on the dielectric layer; forming an isolation layer on the first transistor; A second transistor embedded in the dielectric layer is formed on the isolation layer, the second transistor is arranged opposite to the first transistor, the source of the second transistor is electrically connected to the source of the first transistor, and the drain of the second transistor is electrically connected to the drain of the first transistor.

10. The method for preparing a read transistor structure according to claim 9, characterized in that: The step of forming a dielectric layer on the substrate comprises: forming a dielectric material layer on the substrate; Etching the dielectric material layer to form a groove penetrating the dielectric material layer, and the remaining dielectric material layer forms the dielectric layer, wherein in the thickness direction of the dielectric layer, the groove includes a groove lower portion, a groove middle portion, and a groove upper portion which are sequentially arranged; The step of forming a first transistor embedded in the dielectric layer on the dielectric layer comprises: forming the first transistor at the bottom of the trench; forming an isolation layer on the first transistor, comprising: forming the isolation layer in the middle of the trench; forming a second transistor embedded in the dielectric layer on the isolation layer; The second transistor is formed on the upper portion of the trench.

11. The method for preparing a read transistor structure according to claim 10, characterized in that: Before forming a dielectric material layer on the substrate, the method includes: forming a sacrificial material layer on the substrate; Etching the dielectric material layer to form a groove penetrating the dielectric material layer includes: Etching the dielectric material layer and the sacrificial material layer to form a groove penetrating the dielectric material layer and the sacrificial material layer, and the remaining sacrificial material layer forms a sacrificial layer; The forming of the first transistor at the bottom of the trench comprises: removing the sacrificial layer; Forming a first source electrode and a first drain electrode between the dielectric layer and the substrate at both sides of the trench respectively, and forming a first gate electrode at the bottom of the trench; forming a first gate dielectric layer on the sidewall and top of the first gate; A first active layer is formed on the sidewall and top of the first gate dielectric layer, and the first active layer fills the area between the sidewall of the first gate and the sidewall of the trench.

12. The method for preparing a read transistor structure according to claim 11, characterized in that: A first source and a first drain are respectively formed between the dielectric layer and the substrate on both sides of the trench, and a first gate is formed at the bottom of the trench, including: forming a conductive material layer on the surface of the substrate and the surface of the dielectric layer; The conductive material layer is patterned to form the first gate, the first source and the first drain.

13. The method for preparing a read transistor structure according to claim 11, characterized in that: The forming of the second transistor on the upper portion of the trench comprises: forming a second active layer on the upper surface of the isolation layer, the sidewalls of the trench and the upper surface of the dielectric layer; forming a second gate dielectric layer on the sidewalls of the second active layer and on the upper surface of the second active layer in the trench; A second gate is formed on the surface of the second gate dielectric layer.

14. The method for preparing a read transistor structure according to claim 13, characterized in that: After forming the second transistor on the upper portion of the trench, the method includes: Sequentially etching the second active layer and the dielectric layer located on the upper surface of the dielectric layer on both sides of the trench to form a first interconnection hole and a second interconnection hole penetrating to the first source electrode and the first drain electrode respectively; Conductive material is filled in the first interconnection hole and the second interconnection hole to form a common source and a common drain respectively.

15. A memory, characterized in that: include: a write transistor structure and a read transistor structure; The read transistor structure includes a first transistor and a second transistor, wherein a source of the second transistor is electrically connected to a source of the first transistor, and a drain of the second transistor is electrically connected to a drain of the first transistor; The first electrode of the write transistor structure is connected to the gate of the first transistor or the gate of the second transistor, and the first electrode is a source or a drain.

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