Hall sensor and preparation method thereof

Abstract

The invention discloses a Hall sensor and a preparation method thereof. The Hall sensor comprises a substrate, a channel layer, a barrier layer, a first electrode, a second electrode, a third electrode and a fourth electrode. Wherein the barrier layer comprises a middle part and a peripheral part, the peripheral part is located on the periphery of the middle part, and the thickness of the middle part is smaller than that of the peripheral part in the direction perpendicular to the substrate. The first electrode and the second electrode are oppositely arranged in the first direction parallel to the substrate, the third electrode and the fourth electrode are oppositely arranged in the second direction parallel to the substrate, and the second direction intersects with the first direction. A portion of the first electrode and a portion of the second electrode are embedded in the peripheral portion, and / or a portion of the third electrode and a portion of the fourth electrode are embedded in the peripheral portion. The carrier concentration in the material is reduced by reducing the thickness of the middle part, and the ohmic contact resistance is reduced by embedding the electrode part into the peripheral part, so that the sensitivity of the device is improved.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular, relates to a Hall sensor and a preparation method thereof. Background Art

[0002] Hall sensors have the advantages of non-contact measurement, wide range, high precision and stability, fast response time, adaptability to high-frequency current, and strong anti-interference ability, which makes them have broad application prospects in the fields of power grids and automobiles. However, due to the influence of material properties, the sensitivity of some Hall sensors is low. How to improve the sensitivity of Hall sensors is a current research direction. Summary of the invention

[0003] The present application provides a Hall sensor and a method for preparing the same, aiming to improve the sensitivity characteristics of the device.

[0004] In the first aspect, the present application provides a Hall sensor, comprising: a substrate, a channel layer, a barrier layer, a first electrode, a second electrode, a third electrode and a fourth electrode. The channel layer is arranged on the substrate, the barrier layer is arranged on the side of the channel layer away from the substrate, the barrier layer includes a middle part and a peripheral part, the peripheral part is located around the middle part, and the thickness of the middle part is less than the thickness of the peripheral part along the direction perpendicular to the substrate. The first electrode and the second electrode are arranged on the side of the peripheral part away from the substrate, along the first direction parallel to the substrate, the first electrode and the second electrode are arranged opposite to each other, and are located on both sides of the middle part. The third electrode and the fourth electrode are arranged on the side of the peripheral part away from the substrate, along the second direction parallel to the substrate, the third electrode and the fourth electrode are arranged opposite to each other, and are located on both sides of the middle part, wherein the second direction intersects with the first direction. In addition, part of the first electrode and part of the second electrode are embedded in the peripheral part, and / or part of the third electrode and part of the fourth electrode are embedded in the peripheral part.

[0005] In some embodiments, the middle portion includes a first surface away from the substrate, the peripheral portion includes a second surface away from the substrate, and the first surface is located on a side of the second surface close to the substrate.

[0006] In some embodiments, a ratio of the thickness of the middle portion to the thickness of the peripheral portion is greater than or equal to 0.23 and less than 1.

[0007] In some embodiments, the thickness of the middle portion ranges from 7 nm to 20 nm, and the thickness of the peripheral portion ranges from 15 nm to 30 nm.

[0008] In some embodiments, the material of the channel layer includes at least one of gallium nitride, gallium arsenide, or indium gallium arsenide, and the material of the barrier layer includes at least one of indium gallium nitride, aluminum gallium nitride, indium phosphide, aluminum gallium arsenide, or indium aluminum arsenide.

[0009] In some embodiments, the Hall sensor further includes a gate disposed on a side of the middle portion away from the substrate.

[0010] In the embodiment of the present application, the barrier layer includes a middle part and a peripheral part, the peripheral part is located around the middle part, and the thickness of the middle part is less than the thickness of the peripheral part along the direction perpendicular to the substrate. By reducing the thickness of the middle part, the carrier concentration in the material is reduced, and the electron mobility is not affected by the material thickness, thereby improving the sensitivity of the device.

[0011] On the other hand, the present application also provides a method for preparing a Hall sensor, comprising the following steps S10 to S30:

[0012] Step S10: A stacked channel layer, a barrier layer and an ohmic contact layer are sequentially formed on the substrate, wherein the barrier layer includes a middle part and a peripheral part, the peripheral part is located around the middle part, the ohmic contact layer is located on a side of the peripheral part away from the channel layer, and a portion of the ohmic contact layer is embedded in the peripheral part.

[0013] Step S20: thinning the middle portion along a direction perpendicular to the substrate so that the thickness of the middle portion is smaller than the thickness of the peripheral portion.

[0014] Step S30: forming a first electrode, a second electrode, a third electrode and a fourth electrode. The first electrode and the second electrode are located on the side of the ohmic contact layer away from the substrate. Along a first direction parallel to the substrate, the first electrode and the second electrode are arranged opposite to each other and are located on both sides of the middle portion. The third electrode and the fourth electrode are located on the side of the ohmic contact layer away from the substrate. Along a second direction parallel to the substrate, the third electrode and the fourth electrode are arranged opposite to each other and are located on both sides of the middle portion. The second direction intersects with the first direction.

[0015] In some embodiments, thinning the middle portion further includes steps S21 to S22:

[0016] Step S21: forming a first passivation layer, wherein the first passivation layer covers the peripheral portion and exposes the middle portion.

[0017] Step S22: using the first passivation layer as a mask to etch the middle portion.

[0018] In some embodiments, after forming the first passivation layer and before etching the middle portion, the preparation method further includes: using the first passivation layer as a mask to oxidize the surface of the middle portion to form a surface oxide layer. Etching the middle portion includes: using the first passivation layer as a mask to etch the surface oxide layer using a wet etching process.

[0019] In some embodiments, after thinning the middle portion and before forming the first electrode, the second electrode, the third electrode and the fourth electrode, the preparation method further includes: forming a gate, wherein the gate is located on a side of the middle portion away from the substrate.

[0020] In the embodiment of the present application, the middle part of the barrier layer is thinned so that the thickness of the middle part is smaller than the thickness of the peripheral part, thereby accurately reducing the thickness of the barrier layer of the Hall sensor, reducing the carrier concentration of the material, and improving the sensitivity of the device.

[0021] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0023] Figure 1 A schematic diagram of the structure of a Hall sensor provided in an embodiment of the present application;

[0024] Figure 2 A schematic diagram of another Hall sensor structure provided in an embodiment of the present application;

[0025] Figure 3 A partial cross-sectional schematic diagram of a Hall sensor provided in an embodiment of the present application;

[0026] Figure 4 A partial cross-sectional schematic diagram of another Hall sensor provided in an embodiment of the present application;

[0027] Figure 5 A flow chart of a method for preparing a Hall sensor provided in an embodiment of the present application;

[0028] Figure 6 to Figure 12 A diagram of the steps for preparing a Hall sensor provided in an embodiment of the present application;

[0029] Figure 13 to Figure 17 A diagram of the steps for preparing a Hall sensor provided in an embodiment of the present application. DETAILED DESCRIPTION

[0030] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present application.

[0031] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, ie, meaning "including, but not limited to."

[0032] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.

[0033] When describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. For example, when describing some embodiments, the term "connection" may be used to indicate that two or more components are in direct physical or electrical contact with each other.

[0034] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0035] It will be understood that when a layer or an element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0036] Exemplary embodiments are described herein with reference to cross-sectional views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include deviations in shape due to, for example, manufacturing. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0037] Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0038] Hall sensors have the advantages of non-contact measurement, wide measuring range, high precision and stability, fast response time, adaptability to high-frequency current, and strong anti-interference ability, which makes them have broad application prospects in the fields of power grids, automobiles, etc.

[0039] The Hall sensor is affected by its material properties, that is, the lower the carrier concentration in the material and the higher the electron mobility, the more obvious the Hall effect and the higher the sensitivity of the Hall sensor. The materials of some Hall sensors give them advantages such as fast response time, high linearity, and high temperature operation, but the electron mobility of the material limits the sensitivity.

[0040] Therefore, in order to further improve its sensitivity, the present application provides a Hall sensor, such as Figure 1 As shown, Figure 1 A schematic diagram of the structure of a Hall sensor provided in an embodiment of the present application.

[0041] The Hall sensor 100 includes a substrate 1, a channel layer 2, a barrier layer 3, a first electrode 11, a second electrode 12, a third electrode 13 and a fourth electrode 14. The channel layer 2 is disposed on the substrate 1. Figure 1 The substrate 1 is covered by the channel layer 2 and is therefore not shown. The barrier layer 3 is arranged on the side of the channel layer 2 away from the substrate 1. The barrier layer 3 includes a middle portion 31 and a peripheral portion 32. The peripheral portion 32 is located around the middle portion 31. In the direction perpendicular to the substrate 1, the thickness of the middle portion 31 is less than the thickness of the peripheral portion 32. The first electrode 11 and the second electrode 12 are arranged on the side of the peripheral portion 32 away from the substrate 1. In the first direction F1 parallel to the substrate 1, the first electrode 11 and the second electrode 12 are arranged opposite to each other and are located on both sides of the middle portion 31. The third electrode 13 and the fourth electrode 14 are arranged on the side of the peripheral portion 32 away from the substrate 1. In the second direction F2 parallel to the substrate 1, the third electrode 13 and the fourth electrode 14 are arranged opposite to each other and are located on both sides of the middle portion 31. The second direction F2 intersects with the first direction F1. In addition, a portion of the first electrode 11 and a portion of the second electrode 12 are embedded in the peripheral portion 32, and / or a portion of the third electrode 13 and a portion of the fourth electrode 14 are embedded in the peripheral portion.

[0042] The Hall sensor 100 utilizes the Hall principle and the Ampere's law. When the device is in the on state and is subjected to an external magnetic field, electrons will move in a certain direction under the action of the Lorentz force, thereby generating a potential difference between the left and right ends of the device in a certain direction. By collecting this potential difference, the size of the magnetic field can be inferred, and then the size of the current that generates the magnetic field can be obtained.

[0043] In the embodiment of the present application, the first electrode 11 and the second electrode 12 can be used as a group of input electrodes for connecting to a working power supply to provide an excitation current for the Hall sensor 100, and correspondingly, the third electrode 13 and the fourth electrode 14 are used as a group of output electrodes for outputting the above-mentioned potential difference. Or vice versa, the third electrode 13 and the fourth electrode 14 are used as a group of input electrodes, and the first electrode 11 and the second electrode 12 are used as a group of output electrodes.

[0044] In addition, the barrier layer 3 and the channel layer 2 form a heterojunction, and a two-dimensional potential well is formed at the heterojunction interface. The positive charge attracts electrons to form a two-dimensional electron gas in the potential well. The two-dimensional electron gas is confined in the potential well and can only move in two dimensions along a plane parallel to the heterojunction interface.

[0045] Along the direction perpendicular to the substrate 1 , the thickness of the middle portion 31 of the barrier layer 3 is smaller than that of the peripheral portion 32 , that is, the thickness of the middle portion 31 is reduced, which can reduce the two-dimensional electron gas concentration of the material.

[0046] Since the Hall effect is affected by both carrier concentration and electron mobility, the lower the former and the higher the latter, the more obvious the Hall effect. Therefore, by precisely reducing the thickness of the barrier layer 3 of the Hall sensor 100, the two-dimensional electron gas concentration of the material is reduced, while the electron mobility is less affected, thus greatly improving the sensitivity characteristics of the device.

[0047] It should be noted that Figure 1 The figure is only for illustration and does not limit the morphology of the barrier layer 3 and the morphology of the first electrode 11, the second electrode 12, the third electrode 13 and the fourth electrode 14. Figure 2 As shown, Figure 2 A schematic diagram of another Hall sensor structure provided in an embodiment of the present application. Figure 2 The bid number and Figure 1 The components shown in the figure have the same structure and function, which will not be described in detail here.

[0048] The first electrode 11, the second electrode 12, the third electrode 13 and the fourth electrode 14 mentioned above include, in addition to the electrode metal, an ohmic contact layer 5. Figure 3 As shown, Figure 3 A partial cross-sectional schematic diagram of a Hall sensor provided in an embodiment of the present application.

[0049] The above-mentioned “a portion of the first electrode 11 and a portion of the second electrode 12 are embedded in the peripheral portion 32, and / or a portion of the third electrode 13 and a portion of the fourth electrode 14 are embedded in the peripheral portion” means that a portion of the ohmic contact layer 5 of the first electrode 11 is embedded in the peripheral portion 32, and a portion of the ohmic contact layer 5 of the second electrode 12 is embedded in the peripheral portion 32. Alternatively, a portion of the ohmic contact layer 5 of the third electrode 13 is embedded in the peripheral portion 32, and a portion of the ohmic contact layer 5 of the fourth electrode 14 is embedded in the peripheral portion 32. Alternatively, a portion of the ohmic contact layer 5 of the first electrode 11 is embedded in the peripheral portion 32, a portion of the ohmic contact layer 5 of the second electrode 12 is embedded in the peripheral portion 32, and a portion of the ohmic contact layer 5 of the third electrode 13 is embedded in the peripheral portion 32, and a portion of the ohmic contact layer 5 of the fourth electrode 14 is embedded in the peripheral portion 32.

[0050] By embedding part of the ohmic contact layer 5 of each electrode into the peripheral portion 32 , the ohmic contact resistance of each electrode can be reduced, thereby improving the sensitivity of the Hall sensor 100 .

[0051] In some embodiments, Figure 3 As shown, the middle portion 31 of the barrier layer 3 includes a first surface P1 away from the substrate 1 , the peripheral portion 32 includes a second surface P2 away from the substrate 1 , and the first surface P1 is located on a side of the second surface P2 close to the substrate 1 .

[0052] That is, a step morphology is formed on the upper surface of the barrier layer 3 away from the substrate 1, so that the thickness of the middle portion 31 is smaller than the thickness of the peripheral portion 32. In the heterojunction region formed by the middle portion 31 and the channel layer 2, the concentration of the two-dimensional electron gas is reduced, thereby improving the sensitivity of the Hall sensor 100.

[0053] In some embodiments, Figure 3 As shown, the ratio of the thickness of the middle portion 31 to the thickness of the peripheral portion 32 is greater than or equal to 0.23 and less than 1. For example, the ratio of the thickness of the middle portion 31 to the thickness of the peripheral portion 32 is 0.23, 0.25, 0.3, 0.4, 0.5, 0.6, 0.8, etc. When the ratio of the thickness of the middle portion 31 to the thickness of the peripheral portion 32 is within the above range, the concentration of the two-dimensional electron gas in the barrier layer 3 can be greatly reduced, and the conductive transmission performance of the two-dimensional electron gas can be guaranteed, so that the electron mobility is less affected, thereby greatly improving the sensitivity characteristics of the device.

[0054] In some embodiments, Figure 3As shown, the thickness of the middle portion 31 ranges from 7nm to 20nm, and the thickness of the peripheral portion 32 ranges from 15nm to 30nm. For example, the thickness of the middle portion 31 is 7nm, 8nm, 10nm, 12nm...20nm, etc., and the thickness of the peripheral portion 32 is 15nm, 18nm, 20nm, 25nm...30nm, etc. The smaller the thickness of the middle portion 31, the more conducive it is to improving the sensitivity of the device.

[0055] In some embodiments, the material of the channel layer 2 includes at least one of gallium nitride, gallium arsenide or indium gallium arsenide, and the material of the barrier layer 3 includes at least one of indium gallium nitride, aluminum gallium nitride, indium phosphide, aluminum gallium arsenide or indium aluminum arsenide.

[0056] The above materials have high electron mobility and good semiconductor properties, so that the Hall sensor 100 has high sensitivity, and some materials such as gallium nitride are conducive to the application of the Hall sensor 100 in high temperature environments.

[0057] In some embodiments, Figure 4 As shown, Figure 4 This is a partial cross-sectional schematic diagram of another Hall sensor provided in an embodiment of the present application. The Hall sensor 100 further includes a gate 10 . The gate 10 is disposed on a side of the middle portion 31 away from the substrate 1 .

[0058] By applying a voltage to the gate 10, the carrier concentration in the Hall sensor 100 is regulated. For example, applying a negative voltage to the gate 10 can reduce the carrier concentration, thereby further improving the sensitivity of the Hall sensor 100, and by adjusting the magnitude of the applied voltage, the sensitivity characteristics of the Hall sensor can be adjusted.

[0059] On the other hand, the present application also provides a method for preparing a Hall sensor, such as Figure 5 As shown, Figure 5 A flow chart of a method for preparing a Hall sensor provided in an embodiment of the present application. Figure 6 to Figure 12 A diagram of the steps for preparing a Hall sensor provided in an embodiment of the present application.

[0060] like Figure 5 As shown, the preparation method includes the following steps S10 to S30:

[0061] Step S10: Figure 6 to Figure 8 As shown, a stacked channel layer 2, a barrier layer 3 and an ohmic contact layer 5 are sequentially formed on a substrate 1, the barrier layer 3 includes a middle portion 31 and a peripheral portion 32, the peripheral portion 32 is located around the middle portion 31, the ohmic contact layer 5 is located on a side of the peripheral portion 32 away from the channel layer 2, and a portion of the ohmic contact layer 5 is embedded in the peripheral portion 32.

[0062] The substrate 1 is usually a silicon substrate or a sapphire substrate, and the channel layer 2 usually includes IIIA-VA group elements, such as gallium nitride, gallium arsenide or indium gallium arsenide, etc. In order to avoid the generation of lattice mismatch and dislocation, a buffer layer 4 is usually provided between the substrate 1 and the channel layer 2 to reduce the lattice mismatch and dislocation density, thereby improving the performance and reliability of the device.

[0063] like Figure 6 As shown, a structure is formed in which a substrate 1, a buffer layer 4, a channel layer 2 and a barrier thin layer 30 are stacked in sequence. The thickness of the barrier thin layer 30 is in the range of 15nm to 30nm.

[0064] Afterwards, if Figure 7 As shown, the barrier thin layer 30 is patterned, and the barrier thin layer 30 in the redundant area is etched away, and the barrier thin layer 30 in the required area of ​​the middle part 31 and the peripheral part 32 of the barrier layer 3 is retained. Figure 1 or Figure 2 The projection area of ​​the barrier layer 3 on the substrate 1 is shown, and the barrier thin layer 30 in the area is retained by patterning, and the excess barrier thin layer 30 around is removed by etching. Exemplarily, the barrier thin layer 30 can be removed by etching with an inductively coupled plasma etching process.

[0065] To form good electrical contact, Figure 8 As shown, after the patterning process is completed, an ohmic contact layer 5 is also formed on the peripheral portion 32. Exemplarily, the metal patterning of the ohmic contact is formed by metal evaporation and rapid annealing, and the metal types include but are not limited to gold, aluminum, platinum, molybdenum, etc., and the thickness ranges from 50nm to 1000nm.

[0066] Part of the ohmic contact layer 5 is embedded in the peripheral portion 32. Exemplarily, the peripheral portion 32 can be locally etched by an inductively coupled plasma etching process. The shape of the etched peripheral portion 32 can be a mesh, a cross or a strip. The thickness of the remaining peripheral portion 32 after etching is 2nm to 10nm.

[0067] Step S20: Figure 9-10 As shown, the middle portion 31 is thinned along a direction perpendicular to the substrate 1 so that the thickness of the middle portion 31 is smaller than the thickness of the peripheral portion 32 .

[0068] In some embodiments, thinning the middle portion 31 further includes steps S21 to S22:

[0069] Step S21: Fig. 9 As shown, a first passivation layer 6 is formed, and the first passivation layer 6 covers the peripheral portion 32 and exposes the middle portion 31 .

[0070] Step S22: Fig.10As shown, the middle portion 31 is etched using the first passivation layer 6 as a mask.

[0071] Exemplarily, in some embodiments, after forming the first passivation layer 6 and before etching the middle portion 31, the preparation method further includes using the first passivation layer 6 as a mask to oxidize the surface of the middle portion 31 to form a surface oxide layer. Etching the middle portion 31 also includes using the first passivation layer 6 as a mask to etch the surface oxide layer using a wet etching process.

[0072] For example, after forming the ohmic contact layer 5, Fig. 9 As shown, a first passivation layer 6 is formed and patterned so that the first passivation layer 6 covers the peripheral portion 32 and exposes at least a portion of the ohmic contact layer 5 for subsequent electrode connection. In addition, the first passivation layer 6 also exposes a surface P3 of the middle portion 31 away from the substrate, which is convenient for subsequent etching processes.

[0073] Then, taking the inductively coupled plasma process as an example, oxygen is injected into the surface P3 of the middle part 31, so that the surface layer of the middle part 31 is oxidized to form an oxide layer. Exemplarily, the thickness of the oxidation can be determined by adjusting the process equipment. For example, in some equipment, the oxidation thickness adjustment range is 2nm to 30nm, and this thickness is also the oxide layer thickness. According to needs, the oxidation thickness can be set to 5nm, 7nm, 10nm, etc.

[0074] Next, a wet etching process is used to remove the oxide layer. Through the wet etching process, the oxide layer can be accurately removed by utilizing the chemical reaction between the etching solution and the oxide layer, and the material of the original middle part 31 that has not undergone oxidation reaction will not be corroded. That is, through the wet etching process, the upper surface P1 of the middle part 31 that has not undergone oxidation reaction can be exposed.

[0075] like Fig.10 As shown, after the wet etching process is completed, the thickness of the middle portion 31 is finally smaller than the thickness of the peripheral portion 32 .

[0076] During the above oxidation and etching process, the thickness of the oxide layer formed during the oxidation process is equal to the difference in thickness between the peripheral portion 32 and the middle portion 31 after etching. After the above oxidation and etching process, a relatively uniform oxide layer can be formed, and the thickness of the oxide layer can be adjusted as needed, which is conducive to accurately grasping the etching thickness. After wet etching, the thickness of the remaining middle portion 31 after etching can be accurately grasped, for example, the thickness of the remaining middle portion 31 is any target value between 7nm and 20nm, which is conducive to adjusting the sensitivity of the Hall sensor 100.

[0077] Step S30: Fig.11As shown, a first electrode 11, a second electrode 12, a third electrode 13 and a fourth electrode 14 are formed. For example, the metal layer may be deposited by electron beam evaporation or magnetron sputtering, and the metal types include but are not limited to gold, silver, aluminum, copper, platinum, palladium, titanium and the like.

[0078] by Fig.11 Take the perspective shown as an example. Fig.11 Only the first electrode 11 and the second electrode 12 are schematically shown. The first electrode 11 and the second electrode 12 are located on a side of the ohmic contact layer 5 away from the substrate 1 . Along a first direction F1 parallel to the substrate 1 , the first electrode 11 and the second electrode 12 are arranged opposite to each other and are located on both sides of the middle portion 31 .

[0079] Similarly, the third electrode 13 and the fourth electrode 14 are located on the side of the ohmic contact layer 5 away from the substrate 1, and along the second direction F2 parallel to the substrate 1, the third electrode 13 and the fourth electrode 14 are arranged opposite to each other and located on both sides of the middle part 31. The second direction F2 intersects with the first direction F1.

[0080] Finally, if Fig.12 As shown, a second passivation layer 7 is formed and a pad hole is formed on the second passivation layer 7. The "pad hole" here refers to a via hole exposing the first electrode 11, the second electrode 12, the third electrode 13 and the fourth electrode 14, which is convenient for subsequent electrical connection with an external chip or circuit.

[0081] At this point, the Hall sensor 100 is completed.

[0082] In the embodiment of the present application, by adding a process of "thinning the middle part 31" during the preparation process, the thickness of the middle part 31 is made smaller than the thickness of the peripheral part 32, thereby reducing the carrier concentration of the Hall sensor 100 and improving the device sensitivity. In addition, during the thinning process, by the method of "first injecting oxygen for oxidation using an inductively coupled plasma process and then wet etching the oxide layer", the etching thickness and etching uniformity can be accurately controlled, so that the thickness of the middle part 31 after etching can be accurately controlled.

[0083] In some other embodiments, after thinning the middle portion 31 and before forming the first electrode 11 , the second electrode 12 , the third electrode 13 and the fourth electrode 14 , the preparation method further includes forming a gate 10 , wherein the gate 10 is located on a side of the middle portion 31 away from the substrate 1 .

[0084] Specifically, Figure 13 to Figure 17 As shown, Figure 13 to Figure 17 A diagram of the steps for preparing a Hall sensor provided in an embodiment of the present application.

[0085] In this preparation method, Fig. 9In the process of forming and patterning the first passivation layer 6, the first passivation layer 6 no longer exposes the ohmic contact layer 5. That is, the first passivation layer 6 only exposes the surface P3 of the middle portion 31 away from the substrate for subsequent etching process of thinning the middle portion 31.

[0086] In such Fig.10 After the step of thinning the middle portion 31 is completed, as shown in Fig.13 As shown, a first dielectric layer 8 is formed, and then, as Fig.14 As shown, a gate 10 is formed. The first dielectric layer 8 is used to separate the gate 10 from the middle portion 31 , and plays a role in protecting and isolating the gate 10 .

[0087] Exemplarily, the first dielectric layer 8 may be formed by plasma enhanced chemical vapor deposition process, the thickness of the first dielectric layer 8 is 5nm to 20nm, and the material may be silicon oxide, aluminum oxide or silicon nitride, etc. The gate 10 may be formed by electron beam evaporation or magnetron sputtering to deposit a metal layer, and the metal type of the gate 10 includes but is not limited to gold, silver, aluminum, copper, platinum, palladium, titanium, etc., and the thickness ranges from 50nm to 500nm.

[0088] Afterwards, if Fig.15 As shown, a second dielectric layer 9 is formed and an etching process is performed to etch the second dielectric layer 9, the first dielectric layer 8, and the first passivation layer 6 to expose at least a portion of the ohmic contact layer 5.

[0089] Then, if Fig.16 As shown, a first electrode 11, a second electrode 12, a third electrode 13 and a fourth electrode 14 are formed. The first electrode 11, the second electrode 12, the third electrode 13 and the fourth electrode 14 are electrically connected to the exposed ohmic contact layer 5 respectively. Exemplarily, the metal layer can be deposited by electron beam evaporation or magnetron sputtering, and the metal type includes but is not limited to gold, silver, aluminum, copper, platinum, palladium, titanium, etc., with a thickness ranging from 50nm to 500nm. Fig.16 Take the perspective shown as an example. Fig.16 Only the third electrode 13 and the fourth electrode 14 are illustrated. The third electrode 13 and the fourth electrode 14 are located on the side of the ohmic contact layer 5 away from the substrate 1 . Along the second direction F2 parallel to the substrate 1 , the third electrode 13 and the fourth electrode 14 are arranged opposite to each other and are located on both sides of the middle part 31 .

[0090] Similarly, the first electrode 11 and the second electrode 12 are located on the side of the ohmic contact layer 5 away from the substrate 1, and along the first direction F1 parallel to the substrate 1, the first electrode 11 and the second electrode 12 are arranged opposite to each other and located on both sides of the middle part 31. The second direction F2 intersects the first direction F1.

[0091] Finally, if Fig.17 As shown, a second passivation layer 7 is formed, and a pad hole is formed. The "pad hole" here refers to a via hole that exposes the first electrode 11, the second electrode 12, the third electrode 13, the fourth electrode 14 and the gate 10, which is convenient for subsequent electrical connection with an external chip or circuit.

[0092] At this point, the Hall sensor 100 is completed.

[0093] In this embodiment, by adding a process of "forming the gate 10" during the preparation process, the Hall sensor 100 can adjust the carrier concentration in the Hall sensor 100 by adjusting the voltage applied to the gate 10, thereby making the sensitivity of the Hall sensor 100 adjustable.

[0094] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can think of within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A Hall sensor, characterized in that: include: substrate; A channel layer is disposed on the substrate; A barrier layer is arranged on a side of the channel layer away from the substrate; the barrier layer comprises a middle portion and a peripheral portion, the peripheral portion is located around the middle portion; along a direction perpendicular to the substrate, the thickness of the middle portion is less than the thickness of the peripheral portion; A first electrode and a second electrode are arranged on a side of the peripheral portion away from the substrate; along a first direction parallel to the substrate, the first electrode and the second electrode are arranged opposite to each other and are located on both sides of the middle portion; A third electrode and a fourth electrode are arranged on a side of the peripheral portion away from the substrate; along a second direction parallel to the substrate, the third electrode and the fourth electrode are arranged opposite to each other and located on both sides of the middle portion, and the second direction intersects with the first direction; A portion of the first electrode and a portion of the second electrode are embedded in the peripheral portion; And / or, a portion of the third electrode and a portion of the fourth electrode are embedded in the peripheral portion.

2. The Hall sensor according to claim 1, characterized in that: The middle portion includes a first surface away from the substrate, and the peripheral portion includes a second surface away from the substrate; The first surface is located on a side of the second surface close to the substrate.

3. The Hall sensor according to claim 1, characterized in that: A ratio of a thickness of the middle portion to a thickness of the peripheral portion is greater than or equal to 0.23 and less than 1.

4. The Hall sensor according to claim 3, characterized in that: The thickness of the middle portion is in the range of 7 nm to 20 nm, and the thickness of the peripheral portion is in the range of 15 nm to 30 nm.

5. The Hall sensor according to claim 1, characterized in that: The material of the channel layer includes at least one of gallium nitride, gallium arsenide or indium gallium arsenide, and the material of the barrier layer includes at least one of indium gallium nitride, aluminum gallium nitride, indium phosphide, aluminum gallium arsenide or indium aluminum arsenide.

6. The Hall sensor according to claim 1, characterized in that: A gate is also included, and the gate is arranged on a side of the middle portion away from the substrate.

7. A method for preparing a Hall sensor, characterized in that: include: A stacked channel layer, a barrier layer and an ohmic contact layer are sequentially formed on a substrate, wherein the barrier layer includes a middle portion and a peripheral portion, wherein the peripheral portion is located around the middle portion, the ohmic contact layer is located on a side of the peripheral portion away from the channel layer, and a portion of the ohmic contact layer is embedded in the peripheral portion; Thinning the middle portion in a direction perpendicular to the substrate so that the thickness of the middle portion is smaller than the thickness of the peripheral portion; A first electrode, a second electrode, a third electrode and a fourth electrode are formed, wherein the first electrode and the second electrode are located on a side of the ohmic contact layer away from the substrate; along a first direction parallel to the substrate, the first electrode and the second electrode are arranged opposite to each other and are located on both sides of the middle portion; the third electrode and the fourth electrode are located on a side of the ohmic contact layer away from the substrate; along a second direction parallel to the substrate, the third electrode and the fourth electrode are arranged opposite to each other and are located on both sides of the middle portion, and the second direction intersects with the first direction.

8. The preparation method according to claim 7, characterized in that: Thinning the middle portion, comprising: forming a first passivation layer, wherein the first passivation layer covers the peripheral portion and exposes the middle portion; The middle portion is etched using the first passivation layer as a mask.

9. The preparation method according to claim 8, characterized in that: After forming the first passivation layer and before etching the middle portion, the preparation method further includes: Using the first passivation layer as a mask, oxidizing the surface of the middle portion to form a surface oxide layer; Etching the middle portion, comprising: The surface oxide layer is etched using the first passivation layer as a mask and a wet etching process.

10. The preparation method according to claim 7, characterized in that: After thinning the middle portion and before forming the first electrode, the second electrode, the third electrode and the fourth electrode, the method further includes: A gate is formed, the gate being located at a side of the middle portion away from the substrate.

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