Instruction processing method and device, processor, storage medium and program product

Abstract

The invention provides an instruction processing method and device, a processor, a storage medium and a computer program product, the instruction processing method is applied to the processor, the processor comprises a plurality of instruction execution ports, and each instruction execution port transmits an execution instruction in a clock period or is in an idle state. The instruction processing method comprises the following steps: respectively assigning corresponding register units for each execution instruction in a plurality of execution instructions which are transmitted in parallel and need to process the same input parameters; storing input parameters in the register unit; and when the plurality of execution instructions are transmitted in parallel, controlling each execution instruction in the plurality of execution instructions, and respectively acquiring the input parameters from the corresponding register units and processing the input parameters. According to the method and the device, parallel emission of multiple execution instructions can be realized, the concurrency characteristic is better utilized, the instruction parallel performance is improved, the overall consumed time of instruction operation is short, and the efficiency is high.

Description

Technical Field

[0001] The present application relates to the field of processor technology, and in particular to an instruction processing method, device, processor, storage medium and computer program product. Background Art

[0002] At present, in order to improve the performance of the processor, the processor can adopt a multi-issue micro-architecture to issue two instructions, four instructions and other instructions in parallel in one clock cycle. The processor core of the multi-issue micro-architecture has multiple instruction execution ports (Ports), which can issue multiple pipeline instructions in parallel on the basis of pipeline instructions. Multiple instruction execution ports can issue multiple execution instructions in parallel in one clock cycle, and the execution instructions can be data encryption execution instructions, etc. Multiple execution instructions issued in parallel in one clock cycle need to process the same input parameters. Since this input function only stores one copy of data (transferred from the memory to a register unit for storage), when one of the multiple execution instructions issued in parallel is executed, this register unit is occupied by this execution instruction, and this execution instruction obtains this input function and processes it; and before this execution instruction is executed, the other execution instructions in the multiple execution instructions issued in parallel are in a waiting state; after this execution instruction is executed, one of the other execution instructions in the multiple execution instructions issued in parallel can obtain this input parameter from this register unit and process it. Therefore, the parallel issuance of multiple execution instructions is actually part or all of the serial issuance, which increases the time consumption of the execution instruction and reduces the operation efficiency, thereby reducing the performance of the processor. Summary of the invention

[0003] The present disclosure provides an instruction processing method, apparatus, processor, storage medium and computer program product.

[0004] According to a first aspect of the present disclosure, there is provided an instruction processing method, which is applied to a processor, wherein the processor comprises a plurality of instruction execution ports, each of which transmits an execution instruction within a clock cycle or is in an idle state, and the instruction processing method comprises: for each of a plurality of execution instructions that are transmitted in parallel and need to process the same input parameters, respectively specifying a corresponding register unit; storing the input parameters in the register unit; and when transmitting the plurality of execution instructions in parallel, controlling each of the plurality of execution instructions to obtain the input parameters from the corresponding register unit and process them.

[0005] Optionally, the input parameters include processing results of the issued execution instructions, and for each execution instruction among multiple execution instructions that are issued in parallel and need to process the same input parameters, respectively specifying corresponding register units includes: after the issued execution instructions are executed, respectively specifying corresponding register units for each execution instruction among the multiple execution instructions.

[0006] Optionally, the register unit includes a second variable register unit and a first variable register unit corresponding to the issued execution instruction, and specifying a corresponding register unit for each of the multiple execution instructions includes: specifying the first variable register unit for one of the multiple execution instructions, and specifying a corresponding second variable register unit for each other execution instruction in the multiple execution instructions.

[0007] Optionally, storing the input parameter in the register unit includes: storing the processing result in the first variable register unit and the second variable register unit.

[0008] Optionally, storing the processing result in the first variable register unit and the second variable register unit includes: storing the processing result in the first variable register unit through the issued execution instruction; and after the issued execution instruction is executed, issuing a first copy execution instruction to store the processing result in the second variable register unit.

[0009] Optionally, the first copy execution instruction is issued in a next clock cycle after the clock cycle corresponding to the issued execution instruction.

[0010] Optionally, the input parameters include parameters that have not been processed by the issued execution instructions, the register unit includes a third variable register unit, and for each execution instruction of a plurality of execution instructions that are issued in parallel and need to process the same input parameters, respectively specifying a corresponding register unit includes: respectively specifying a corresponding third variable register unit for each execution instruction of the plurality of execution instructions.

[0011] Optionally, storing the input parameter in the register unit includes: storing the initial parameter in the third variable register unit.

[0012] Optionally, storing the initial parameters in the third variable register unit includes: before the multiple execution instructions are issued in parallel, issuing a second copy execution instruction to store the parameters that have not been processed by the issued execution instructions in the third variable register unit.

[0013] Optionally, the execution instruction includes an algorithm execution instruction for performing elliptic curve encryption, wherein the algorithm includes a Montgomery gradient algorithm.

[0014] Optionally, the number of the instruction execution ports includes four, and the instruction processing method includes: respectively allocating the algorithm execution instructions to be transmitted to the four instruction execution ports; respectively allocating encryption processing data to the four instruction execution ports, wherein the encryption processing data includes the first coordinate and the second coordinate of the first point on the elliptic curve in the projective coordinate system, and the first coordinate and the second coordinate of the second point on the elliptic curve in the projective coordinate system.

[0015] According to a second aspect of the present disclosure, there is provided an instruction processing device, which is applied to a processor, wherein the processor comprises a plurality of instruction execution ports, wherein the instruction execution ports transmit an execution instruction in one clock cycle or are in an idle state, and the instruction processing device comprises: an allocation module, which is used to specify a corresponding register unit for each of a plurality of execution instructions that are transmitted in parallel and need to process the same input parameters; a storage module, which is used to store the input parameters in the register unit; and an execution module, which is used to control each of the plurality of execution instructions, when the plurality of execution instructions are transmitted in parallel, to obtain the input parameters from the corresponding register unit and process them.

[0016] According to a third aspect of the present disclosure, a processor includes the instruction processing device as described above.

[0017] According to a fourth aspect of the present disclosure, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the instructions are executed by a processor as described above.

[0018] According to a fifth aspect of the present disclosure, a computer program product is provided, wherein the computer program product stores computer instructions, and the instructions are executed by a processor according to the method described above.

[0019] The instruction processing method, device, processor, storage medium and computer program product disclosed in the present invention respectively specify register units for multiple execution instructions that are issued in parallel and need to process the same input parameters, store the input parameters in the register units, and when multiple execution instructions are issued in parallel, control each execution instruction to obtain the input parameters from the corresponding register unit and process them; it is possible to realize the parallel issuance of multiple execution instructions, better utilize the concurrency characteristics, improve the instruction parallel performance, and the overall time consumption and efficiency of instruction execution are short. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] By describing the embodiments of the present disclosure in more detail in conjunction with the accompanying drawings, the above and other purposes, features and advantages of the present disclosure will become more apparent. The accompanying drawings are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other purposes and advantages of the present disclosure will be further described below in conjunction with specific embodiments and with reference to the accompanying drawings. In the accompanying drawings, the same or corresponding technical features or components will be represented by the same or corresponding figure marks.

[0021] Figure 1 is a flowchart of some embodiments of the instruction processing method according to the present disclosure;

[0022] Figure 2 A schematic diagram of a flow chart of storing processing results in some embodiments of the instruction processing method according to the present disclosure;

[0023] Figure 3 A flowchart of implementing the Montgomery gradient algorithm in some embodiments of the instruction processing method according to the present disclosure;

[0024] Figure 4 It is a module diagram of some embodiments of the instruction processing device according to the present disclosure. DETAILED DESCRIPTION

[0025] Exemplary embodiments of the present disclosure will be described below in conjunction with the accompanying drawings. For the sake of clarity and conciseness, not all features of the embodiments are described in the specification. However, it should be understood that many implementation-specific settings must be made in the process of implementing the embodiments in order to achieve the specific goals of the developer, for example, to meet those restrictions related to the device and the service, and these restrictions may vary depending on the implementation. In addition, it should be understood that although the development work may be very complex and time-consuming, it is only a routine task for those skilled in the art who benefit from the content of this disclosure.

[0026] It should be noted that the relative arrangement of components and steps, the numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.

[0027] Those skilled in the art can understand that the terms "first" and "second" in the embodiments of the present disclosure are only used to distinguish different steps, devices or modules, etc., and neither represent any specific technical meaning nor indicate the necessary logical order between them.

[0028] It should also be understood that in the embodiments of the present disclosure, “plurality” may refer to two or more than two, and “at least one” may refer to one, two, or more than two.

[0029] It should also be understood that any component, data or structure mentioned in the embodiments of the present disclosure can generally be understood as one or more, unless explicitly limited or otherwise indicated in the context.

[0030] In addition, the term "and / or" in the present disclosure is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in the present disclosure generally indicates that the associated objects before and after are in an "or" relationship.

[0031] It should also be understood that the description of the various embodiments in the present disclosure focuses on the differences between the various embodiments, and the same or similar aspects thereof can be referenced to each other, and for the sake of brevity, they will not be described one by one.

[0032] At the same time, it should be understood that for the convenience of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship.

[0033] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the present disclosure, its application, or uses.

[0034] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered part of the specification.

[0035] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0036] In addition, in order to avoid obscuring the present disclosure due to unnecessary details, only the processing steps and / or device structures closely related to at least the scheme according to the present disclosure are shown in the drawings, and other details that are not closely related to the present disclosure are omitted. It should also be noted that similar reference numerals and letters in the drawings indicate similar items, and therefore once an item is defined in one drawing, it does not need to be discussed again for subsequent drawings.

[0037] Figure 1 is a flowchart of some embodiments of the instruction processing method according to the present disclosure, Figure 1 The instruction processing method shown is applied to a processor, the processor includes multiple instruction execution ports, each instruction execution port sends an execution instruction in one clock cycle or is in an idle state. Figure 1 As shown, the instruction processing method includes steps S101 to S103.

[0038] Step S101 , for each execution instruction of a plurality of execution instructions issued in parallel and requiring processing of the same input parameter, specify a corresponding register unit respectively.

[0039] In some embodiments, the processor may be a variety of processors using a multi-issue micro-architecture. For example, the processor may be a processor with a four-issue micro-architecture, and four of the multiple ports of the processor may be used as instruction execution ports. Since one instruction execution port issues one execution instruction or is idle in the same clock cycle, a maximum of four instruction issuances may be completed in one clock cycle, reflecting a four-way pipeline.

[0040] The execution instruction is an instruction of the execution stage in the pipeline, and the execution instruction can be a variety of instructions, such as function operation instructions, etc. The execution instruction is transmitted through the instruction execution port, and the execution instruction can be processed accordingly after being transmitted to obtain corresponding execution and processing results. When the input parameters of multiple execution instructions transmitted in parallel are the same, a corresponding register unit is specified for each execution instruction in the multiple execution instructions, and the register unit can be a variety of registers, register groups, etc.

[0041] Step S102, storing input parameters in a register unit.

[0042] After specifying corresponding register units for each of the multiple execution instructions issued in parallel and requiring processing of the same input parameters, a variety of methods can be used to store the input parameters in the corresponding registers. The time consumption of storing the input parameters in the register units is relatively short, usually much less than the time consumption of executing the instructions.

[0043] For example, multiple execution instructions issued in parallel within a clock cycle are instruction 1 and instruction 2, the input parameters of instruction 1 are parameter a and parameter b, and the input parameters of instruction 2 are parameter a and parameter c. Instruction 1 and instruction 2 need to process the same input parameter, which is parameter a. Corresponding register units are specified for instruction 1 and instruction 2, respectively, where the register unit can store at least one parameter.

[0044] When instruction 1 and instruction 2 need to process the same input parameter, which is parameter a, corresponding register unit a and register unit b are respectively specified for instruction 1 and instruction 2. Parameter a is stored in register unit a and register unit b, so that parameter a can be saved in two copies.

[0045] Step S103, when multiple execution instructions are issued in parallel, each of the multiple execution instructions is controlled to obtain input parameters from the corresponding register unit and process them.

[0046] For example, the input parameters of instruction 1 are parameter a and parameter b, and the input parameters of instruction 2 are parameter a and parameter c; when instruction 1 and instruction 2 are issued in parallel, control instruction 1 and instruction 2 obtain parameter a from the corresponding register unit a and register unit b respectively, and at the same time, control instruction 1 and instruction 2 obtain parameter b and parameter c from the register units storing parameter b and parameter c respectively, instruction 1 performs corresponding processing based on parameter a and parameter b, and instruction 2 performs corresponding processing based on parameter a and parameter c.

[0047] Since parameter a is stored in register unit a and register unit b respectively, parameter a has two copies of data, and parameter b and parameter c are stored in corresponding registers, then instruction 1 and instruction 2 can obtain parameter a from register unit a and register unit b in parallel when obtaining parameter a, without the need for one of instruction 1 and instruction 2 to obtain parameter a and its parameter number and execute before the other instruction can obtain parameter a, so that instruction 1 and instruction 2 can be truly issued in parallel, better utilizing the concurrency characteristics, making the instruction execution time short and efficient, and improving the performance of the processor.

[0048] In the existing technical solutions for executing instructions in parallel using a processor with a multi-issue microarchitecture, it is often the case that multiple execution instructions issued in parallel have the same input parameters within the same clock cycle, and the same input parameters are only stored in a set of registers. At this time, other execution instructions will wait for an execution instruction to obtain the parameters in the register and complete the calculation before they can call the parameters in the register for calculation, resulting in low efficiency of serial operation.

[0049] The instruction processing method disclosed in the present invention specifies register units for multiple execution instructions that are issued in parallel and need to process the same input parameters, stores the input parameters in the register units, and when multiple execution instructions are issued in parallel, controls each execution instruction to obtain the input parameters from the corresponding register unit and process them. It can realize the parallel issuance of multiple execution instructions that need to process the same input parameters, better utilize the concurrency characteristics, improve the parallel performance, shorten the overall time consumption of instruction execution, increase the efficiency, and improve the performance of the processor.

[0050] In some embodiments, the same input parameters that need to be processed by multiple execution instructions include the processing results of the issued execution instructions. After the issued execution instructions are executed, corresponding register units can be respectively specified for each of the multiple execution instructions. The register units include a second variable register unit, a first variable register unit corresponding to the issued execution instruction, etc. The first variable register unit can be specified for one of the multiple execution instructions, and the corresponding second variable register unit can be specified for each of the other execution instructions in the multiple execution instructions, and the processing results are stored in the second variable register unit and the first variable register unit.

[0051] For example, instruction 1 and instruction 2 need to process the same input parameter, parameter a, which is the processing result of instruction 3 that has been issued before instruction 1 and instruction 2 are issued in parallel. After instruction 3 is issued, corresponding register units can be specified for instruction 1 and instruction 2 respectively. A first variable register unit corresponding to the issued instruction 3 can be specified for instruction 1, and a corresponding second variable register unit can be specified for instruction 2, and parameter a is stored in the second variable register unit and the first variable register unit.

[0052] Figure 2 FIG. 1 is a flow chart of storing processing results in some embodiments of the instruction processing method disclosed in the present invention. Figure 2 As shown, the instruction processing method includes step S201 and step S202.

[0053] Step S201, storing the processing result in the first variable register unit through the issued execution instruction. The processing result is the processing result of the issued execution instruction.

[0054] Step S202, after the issued execution instruction is executed, issue a first copy execution instruction to store the processing result in the second variable register unit.

[0055] The first duplicate execution instruction may be issued in a next clock cycle after the clock cycle corresponding to the issued execution instruction.

[0056] The same input parameters that need to be processed by multiple execution instructions include parameters that have not been processed by the issued execution instructions, etc. The parameters that have not been processed by the issued execution instructions may be initial parameters that have not been processed by the issued execution instructions. The register unit includes a third variable register unit, and a corresponding third variable register unit can be specified for each of the multiple execution instructions, and the initial parameters are stored in the third variable register unit. Before the multiple execution instructions are issued in parallel, a second copy execution instruction can be issued to store the parameters that have not been processed by the issued execution instructions in the third variable register unit.

[0057] For example, instruction 1 and instruction 2 need to process the same input parameter, parameter a, which is an initial parameter that has not been processed by the issued execution instruction. Before instruction 1 and instruction 2, corresponding third variable register unit 1 and third variable register unit 2 can be specified for instruction 1 and instruction 2, respectively. Before instruction 1 and instruction 2 are issued in parallel, a second copy execution instruction can be issued to store parameter a in third variable register unit 1 and third variable register unit 2.

[0058] In some embodiments, the execution instruction includes an algorithm execution instruction for performing elliptic curve encryption, and the algorithm includes the Montgomery gradient algorithm (also known as the Montgomery ladder algorithm), etc. Elliptic curve encryption has a large number of applications in technologies such as digital certificates, network communications, data security, blockchain, and privacy computing. The elliptic curve encryption algorithm can be elliptic curve random point scalar multiplication, which is the operator with the highest computational complexity in elliptic curve encryption. The algorithm for implementing elliptic curve random point scalar multiplication includes the Montgomery gradient algorithm (Montgomery Ladder Algorithm), etc. The Montgomery gradient algorithm has good performance.

[0059] The Montgomery gradient algorithm can be used in elliptic curve cryptography (ECC) to perform scalar multiplication of points on an elliptic curve, i.e., to calculate Q = k × P, where k is an integer (scalar) and P is a point on the curve. Scalar multiplication is the process of adding a point P to itself k times, and is the basis for encryption, decryption, and digital signatures. In the Montgomery gradient algorithm, the point addition and point multiplication operations are kept consistent regardless of the value of k, which enhances the security of the scalar multiplication operation.

[0060] Each processor core of a multi-issue micro-architecture processor has multiple instruction execution ports, and a multi-way pipeline can be used to implement the Montgomery gradient algorithm. By using the multi-issue micro-architecture processor to issue algorithm execution instructions in parallel, better performance can be achieved.

[0061] For example, the number of instruction execution ports of a processor with a multi-issue microarchitecture is four, and the algorithm execution instructions of the Montgomery gradient algorithm that need to be issued are respectively allocated to the four instruction execution ports; the encryption processing data are respectively allocated to the four instruction execution ports, and the encryption processing data includes the first coordinate and the second coordinate of the first point on the elliptic curve in the projective coordinate system, and the first coordinate and the second coordinate of the second point on the elliptic curve in the projective coordinate system, etc.

[0062] like Figure 3As shown, the processor of the quad-issue microarchitecture includes four instruction execution ports, namely instruction execution port 1, instruction execution port 2, instruction execution port 3 and instruction execution port 4; instruction execution port 1, instruction execution port 2, instruction execution port 3 and instruction execution port 4 emit an algorithm execution instruction of the Montgomery gradient algorithm in one clock cycle or are in an idle state.

[0063] The algorithm execution instructions of the Montgomery gradient algorithm are assigned to four instruction execution ports for emission, and multiple groups of register units are added. In the initialization process of the Montgomery gradient algorithm, two points can be set, R0 and R1, and the values ​​of these two points are continuously updated in the subsequent n cycles. Since R0 and R1 are two points on the elliptic curve (the first point and the second point on the elliptic curve), these two points can be represented by affine coordinates (i.e., plane Cartesian coordinate system): R0 = (X2, Y2), R1 = (X3, Y3).

[0064] Since performing elliptic curve point operations in affine coordinates will introduce too many finite field divisions (the computation time of one finite field division is more than 200 times that of one finite field multiplication), projective coordinates are used in the Montgomery gradient algorithm to represent points on the elliptic curve, namely: R0 = (x2, y2, z2), R1 = (x3, y3, z3), where: i=2,3.

[0065] Since the Montgomery gradient algorithm only uses the horizontal coordinates of the elliptic curve points, the y value can be ignored in the algorithm. Figure 3 This is the specific calculation process and algorithm execution instructions in one cycle of the Montgomery gradient algorithm. By continuously updating the values ​​of x2, z2, x3, and z3, the values ​​of R0 and R1 can be continuously updated, and finally the horizontal coordinate of R0 = k×P is obtained:

[0066] like Figure 3 As shown, encrypted processing data x2, z2, x3, z3 can be allocated to four instruction execution ports respectively, wherein x2, z2 are the first coordinate and the second coordinate of the first point on the elliptic curve in the projective coordinate system, x3, z3 are the first coordinate and the second coordinate of the second point on the elliptic curve in the projective coordinate system, and x2, z2, x3, z3 represent two points of the elliptic curve. In each loop of the Montgomery gradient algorithm, x1 is a fixed parameter, and x2, z2, x3, z3 are the input and output of each loop.

[0067] The finite field of the elliptic curve is usually a 256-bit large integer, and the register size of the four-issue CPU microarchitecture is usually 64 bits. Therefore, each finite field large integer needs to be stored in four 64-bit registers, and the four 64-bit registers can be a register group. For each instruction, the corresponding register is configured to store the processing result of the instruction; t0, t1, t2, t3, r0, r1, r2, r3, a total of eight groups of registers are configured to store the same input parameters that need to be processed by multiple execution instructions.

[0068] Each loop of the Montgomery gradient algorithm is set with 9 layers of instructions, and the instructions of each layer can be sent in the same clock cycle. There are multiple functions executed by each layer of instructions, among which fe_mul() is a finite field multiplication function, fe_sqr() is a finite field square function, fe_const_mul() is a finite field constant multiplication function, fe_add() is a finite field addition function, fe_sub() is a finite field subtraction function, and fe_copy() is a finite field copy function.

[0069] like Figure 3 As shown, the first layer of instructions includes instructions E11, E12, E13 and E14; instruction E11 is t0=fe_copy(x2), instruction E12 is t1=fe_copy(z2), instruction E13 is t2=fe_copy(x3), and instruction E12 is t3=fe_copy(z3).

[0070] The second layer of instructions includes instructions E21, E22, E23 and E24; instruction E21 is x2=fe_add(x2,z2), instruction E21 is t0=fe_sub(t0,t1), instruction E21 is x3=fe_add(x3,z3), instruction E21 is t2=fe_sub(t2,t3).

[0071] Among them, E21 and E22 need to process the same input parameters x2 and z2, which are parameters that have not been processed by the issued execution instruction. Corresponding register group 1 storing x2 and register group 2 storing z2 are specified for E21 (register group 1 and register group 2 are third variable register units), and before E21 and E22 are issued in parallel, a (second) copy execution instruction can be issued to store x2 in register group 1 and store z2 in register group 1.

[0072] For E22, the corresponding register group t0 storing x2 and register group t1 storing z2 (register group 1 and register group 2 are the third variable register unit) are specified. Before E21 and E22 are issued in parallel, (second) copy execution instructions E11 and E12 can be issued to store x2 in register group t0 and store z2 in register group t1. E21 and E22 can obtain the same input parameters from different register groups.

[0073] E23 and E24 need to process the same input parameters x3 and z3, which are parameters that have not been processed by the issued execution instructions. A similar method can be used to allocate a third variable register unit for E23 and E24. Before E23 and E24 are issued in parallel, a second copy execution instruction is issued to store the parameters x3 and z3 in the third variable register unit.

[0074] The third layer of instructions includes instructions E31 and E32; instruction E31 is r0=fe_copy(x2), and instruction E32 is r1=fe_copy(t0); instruction execution port 3 and instruction execution port 4 are in idle state.

[0075] The fourth level instructions include instructions E41, E42, E43 and E44; instruction E41 is z2=fe_sqr(x2), instruction E42 is t1=fe_sqr(t0), instruction E41 is t3=fe_mul(r1,x3), and instruction E44 is z3=fe_mul(r0,t2).

[0076] Among them, E41 and E44 need to process the same input parameter x2, x2 is the processing result of the issued execution instruction E21, register unit 3 (the first variable register unit corresponding to the issued execution instruction E21) is specified for E41, and register unit r0 (the second variable register unit) is specified for E42. The input parameter x2 is stored in register unit 3 through the issued execution instruction E31; after the issued execution instruction E21 is executed, the (first) copy execution instruction E31 is issued to store the input parameter x2 in register unit r0. E41 and E44 can obtain the same input parameters from different register groups.

[0077] The fifth layer of instructions includes instructions E51, E52, E53 and E54; instruction E51 is r2=fe_copy(z2), instruction E52 is r3=fe_copy(t1), instruction E53 is x3=fe_copy(t3), and instruction E54 is t2=fe_copy(z3).

[0078] The sixth level instructions include instructions E61, E62, E63 and E64; instruction E61 is x2=fe_mul(z2,t1), instruction E62 is r3=fe_sub(r2,r3), instruction E63 is t3=fe_add(t3,t2), and instruction E64 is z3=fe_sub(x3,z3).

[0079] The seventh layer instructions include instructions E71, E72, and E73; instruction E71 is t1=fe_const_mul(121666,r3), instruction E72 is x3=fe_sqr(t3), and instruction E73 is t2=fe_sqr(z3); instruction execution port 1 is in an idle state.

[0080] The eighth layer instructions include instructions E81 and E82; instruction E81 is r2=fe_add(r2,t1), or r2=fe_add(x2,t1), and instruction E82 is z3=fe_mul(t2,x1); instruction execution ports 1 and 3 are in idle state.

[0081] The ninth layer of instructions includes instruction E91; instruction E91 is z2=fe_mul(r2,r3); instruction execution ports 1, 3 and 4 are in idle state.

[0082] For finite field operators, in terms of computational time, finite field multiplication > finite field square > finite field constant multiplication >> finite field addition = finite field subtraction > finite field copy, that is, in terms of computational time, fe_mul > fe_sqr > fe_const_mul >> fe_add = fe_sub > fe_copy.

[0083] like Figure 3 As shown in the figure, the four instruction execution ports in the first-level instructions and the second-level instructions have basically the same time consumption; although the third-level instructions only have two instruction execution ports for copy operations, since each operator in the fourth level depends on all the parameters in the third level, the two idle instruction execution ports also need to wait for the execution time of the third-level copy operations; the first two instruction execution ports of the fourth-level instructions perform finite field square operations, and the last two instruction execution ports perform finite field multiplication operations. The first two instruction execution ports will be executed first and enter the fifth-level copy operation. At this time, all other register groups are occupied. Therefore, the last two register groups r2 and r3 are introduced here to perform the fifth-level copy operations of the first two ports in advance.

[0084] For the fifth-level instructions, the data between the first two instruction execution ports and the last two instruction execution ports no longer interact and are isolated; for the first and last two groups of ports, this level is a copy operation. Since the finite field multiplication time is greater than the finite field square time + the finite field copy time, after the fifth-level copy operation of the first two instruction execution ports is completed, the last two instruction execution ports are still executing the fourth-level finite field multiplication operation.

[0085] In the sixth level of instructions, the first instruction execution port performs finite field multiplication and generates x2, and the second, third, and fourth instruction execution ports all perform finite field addition or subtraction. In the seventh level of instructions, the first instruction execution port is idle, the second instruction execution port performs finite field constant multiplication, the last two instruction execution ports perform finite field square operations, and the third instruction execution port generates x3 after execution.

[0086] In the eighth level instruction, the first instruction execution port is idle, the second instruction execution port performs a finite field addition operation using the copied result in the fifth level, the third instruction execution port is idle, and the fourth instruction execution port performs a finite field multiplication operation and generates z3. In the ninth level instruction, the second instruction execution port performs a finite field multiplication operation and generates z2.

[0087] By setting the input and output assignment paths of the register groups in the Montgomery gradient algorithm, when each instruction is executed, there will be no situation where the relevant register groups are occupied by other instructions, thereby maximizing the parallelism of instruction execution.

[0088] like Figure 3 As shown in the figure, starting from the fourth level of instructions, the execution time of each instruction execution port is not synchronized, and the number of levels does not completely determine the final execution time. However, the second and fourth instruction execution ports become the key points to determine the performance: the second instruction execution port (instruction execution port 2) executes a total of 1 finite field multiplication, 1 finite field square, 1 finite field constant multiplication, 1 finite field addition, 1 finite field subtraction, and 1 finite field copy from the fourth level of instructions to the end; the fourth instruction execution port (instruction execution port 4) executes a total of 2 finite field multiplications, 1 finite field square, 1 finite field subtraction, and 1 finite field copy from the fourth level of instructions to the end. The time consumption of 1 finite field constant multiplication + 1 finite field addition is similar to that of 1 finite field multiplication, and the latter consumes slightly more time. Therefore, the operation speed of the fourth instruction execution port determines the operation performance of the entire algorithm.

[0089] The instruction processing method in the above embodiment can improve the execution performance of the Montgomery gradient algorithm and reduce the clock cycle of the algorithm (through relevant experiments, the execution performance of the Montgomery gradient algorithm can be improved by 15% by applying this application); it can better utilize the concurrency characteristics, improve the parallel performance, and the overall time consumption of instruction operation is short and efficient, which improves the performance of the processor. The present disclosure can be implemented using computer programming languages ​​such as assembly language.

[0090] In some embodiments, the present disclosure provides an instruction processing device, which is applied to a processor, wherein the processor includes a plurality of instruction execution ports, each of which transmits an execution instruction in one clock cycle or is in an idle state. Figure 4 As shown, the instruction processing device 40 includes an allocation module 41 , a storage module 42 and an execution module 43 .

[0091] The allocation module 41 specifies corresponding register units for each of the multiple execution instructions that need to process the same input parameters and are issued in parallel. The storage module 42 stores the input parameters in the register units. When issuing multiple execution instructions in parallel, the execution module 43 controls each of the multiple execution instructions to obtain the input parameters from the corresponding register units and process them.

[0092] In some embodiments, the input parameters include processing results of issued execution instructions, etc. After the issued execution instructions are executed, the allocation module 41 specifies corresponding register units for each of the multiple execution instructions.

[0093] The register unit includes a second variable register unit, a first variable register unit corresponding to the issued execution instruction, etc.; the allocation module 41 specifies the first variable register unit for one execution instruction among multiple execution instructions, and specifies the corresponding second variable register unit for each other execution instruction among the multiple execution instructions.

[0094] The storage module 42 stores the processing results in the first variable register unit and the second variable register unit. For example, the storage module 42 stores the input parameters in the first variable register unit through the issued execution instruction; after the issued execution instruction is executed, the storage module 42 issues a first copy execution instruction to store the input parameters in the second variable register unit. The storage module 42 may issue the first copy execution instruction in the next clock cycle after the clock cycle corresponding to the issued execution instruction.

[0095] In some embodiments, the input parameter includes a parameter that has not been processed by the issued execution instruction, the register unit includes a third variable register unit, and the allocation module 41 specifies a corresponding third variable register unit for each execution instruction in the multiple execution instructions. The storage module 42 stores the initial parameter in the third variable register unit. For example, before the multiple execution instructions are issued in parallel, the storage module 42 issues a second copy execution instruction to store the parameter that has not been processed by the issued execution instruction in the third variable register unit.

[0096] In some embodiments, the execution instruction includes an algorithm execution instruction for performing elliptic curve encryption, and the algorithm includes a Montgomery gradient algorithm, etc. The number of instruction execution ports includes four, and the allocation module 41 allocates the algorithm execution instructions to be transmitted to the four instruction execution ports respectively; the allocation module 41 allocates encryption processing data to the four instruction execution ports respectively, wherein the encryption processing data includes the first coordinate and the second coordinate of the first point on the elliptic curve in the projective coordinate system, and the first coordinate and the second coordinate of the second point on the elliptic curve in the projective coordinate system.

[0097] In some embodiments, the present disclosure provides a processor, comprising the instruction processing device in any of the above embodiments.

[0098] In some embodiments, the present disclosure provides a computer-readable storage medium storing computer instructions, which implement the methods in any of the above embodiments when the instructions are executed by a processor.

[0099] Computer readable storage media can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium can include, for example, but is not limited to, a system, device or device of electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination of the above. More specific examples (non-exhaustive enumeration) of readable storage media can include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0100] The embodiments of the present disclosure may also be a computer program product, which includes computer program instructions. When the computer program instructions are executed by a processor, the processor executes the steps of the method according to various embodiments of the present disclosure described in the above “Exemplary Method” section of this specification.

[0101] The instruction processing method, device, processor, storage medium and computer program product in the above-mentioned embodiments specify register units for multiple execution instructions that are issued in parallel and need to process the same input parameters, store the input parameters in the register units, and when multiple execution instructions are issued in parallel, control each execution instruction to obtain the input parameters from the corresponding register unit and process them; it is possible to realize the parallel issuance of multiple execution instructions, better utilize the concurrency characteristics, improve the instruction parallel performance, shorten the overall time consumption and increase the efficiency of instruction execution, improve the performance of the processor, and improve the user experience.

[0102] The basic principles of the present disclosure are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present disclosure are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present disclosure. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, and are not limitations. The above details do not limit the present disclosure to the necessity of adopting the above specific details to be implemented.

[0103] Each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the system embodiment, since it basically corresponds to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0104] The block diagrams of the devices, apparatuses, equipment, and systems involved in this disclosure are only illustrative examples and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. As will be appreciated by those skilled in the art, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including," "comprising," "having," and the like are open words, referring to "including but not limited to," and can be used interchangeably therewith. The words "or" and "and" used herein refer to the words "and / or," and can be used interchangeably therewith, unless the context clearly indicates otherwise. The word "such as" used herein refers to the phrase "such as but not limited to," and can be used interchangeably therewith.

[0105] It should also be noted that in the apparatus, device and method of the present disclosure, each component or each step can be decomposed and / or recombined. Such decomposition and / or recombination should be regarded as equivalent solutions of the present disclosure.

[0106] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the aspects shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

[0107] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present disclosure to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, it will be appreciated by those skilled in the art that the above embodiments are merely illustrative and do not limit the scope of the present disclosure. It will be appreciated by those skilled in the art that the above embodiments may be combined, modified or replaced without departing from the scope and essence of the present disclosure.

Claims

1. An instruction processing method, applied to a processor, wherein the processor includes a plurality of instruction execution ports, each of which transmits an execution instruction in one clock cycle or is in an idle state, wherein the instruction processing method include: For each of a plurality of execution instructions issued in parallel and requiring processing of the same input parameter, specify a corresponding register unit; storing the input parameter in the register unit; When the multiple execution instructions are issued in parallel, each of the multiple execution instructions is controlled to obtain the input parameter from the corresponding register unit and process it.

2. The instruction processing method according to claim 1, in, The input parameter includes the processing result of the issued execution instruction, and the corresponding register units are respectively specified for each execution instruction of multiple execution instructions issued in parallel and needing to process the same input parameter, including: After the issued execution instruction is executed, a corresponding register unit is respectively designated for each execution instruction of the plurality of execution instructions.

3. The instruction processing method according to claim 2, in, The register unit includes a second variable register unit and a first variable register unit corresponding to the issued execution instruction, and the specifying of a corresponding register unit for each execution instruction in the plurality of execution instructions includes: The first variable register unit is specified for one execution instruction among the multiple execution instructions, and the corresponding second variable register unit is specified for each other execution instruction among the multiple execution instructions.

4. The instruction processing method according to claim 3, in, The storing of the input parameter in the register unit comprises: The processing result is stored in the first variable register unit and the second variable register unit.

5. The instruction processing method according to claim 4, in, The storing the processing result in the first variable register unit and the second variable register unit comprises: By means of the issued execution instruction, the processing result is stored in the first variable register unit; After the issued execution instruction is executed, a first copy execution instruction is issued to store the processing result in the second variable register unit.

6. The instruction processing method according to claim 5, in, The first copy execution instruction is issued in a next clock cycle after the clock cycle corresponding to the issued execution instruction.

7. The instruction processing method according to claim 2, in, The input parameters include parameters that have not been processed by the issued execution instructions, the register unit includes a third variable register unit, and the corresponding register units are respectively specified for each of the multiple execution instructions issued in parallel and needing to process the same input parameters, including: A corresponding third variable register unit is respectively specified for each execution instruction of the plurality of execution instructions.

8. The instruction processing method according to claim 7, in, The storing of the input parameter in the register unit comprises: The initial parameters are stored in the third variable register unit.

9. The instruction processing method according to claim 8, in, The storing of the initial parameters in the third variable register unit comprises: Before the multiple execution instructions are issued in parallel, a second copy execution instruction is issued to store the parameters that have not been processed by the issued execution instructions in the third variable register unit.

10. The instruction processing method according to any one of claims 1 to 9, in, The execution instructions include algorithm execution instructions for performing elliptic curve encryption, wherein the algorithm includes a Montgomery gradient algorithm.

11. The instruction processing method according to claim 10, in, The number of the instruction execution ports includes four, and the instruction processing method includes: Allocating the algorithm execution instructions to be transmitted to four instruction execution ports respectively; Encrypted processing data are respectively allocated to the four instruction execution ports, wherein the encrypted processing data includes a first coordinate and a second coordinate of a first point on the elliptic curve in a projective coordinate system, and a first coordinate and a second coordinate of a second point on the elliptic curve in a projective coordinate system.

12. An instruction processing device, applied to a processor, the processor comprising a plurality of instruction execution ports, the instruction execution ports transmitting an execution instruction in one clock cycle or being in an idle state, the instruction processing device include: An allocation module, used for respectively specifying corresponding register units for each of a plurality of execution instructions issued in parallel and requiring processing of the same input parameters; A storage module, used for storing the input parameters in the register unit; The execution module is used to control each of the multiple execution instructions when the multiple execution instructions are issued in parallel, and obtain the input parameters from the corresponding register units and process them respectively.

13. A processor, include: The instruction processing apparatus as claimed in claim 12.

14. A computer-readable storage medium storing computer instructions, wherein the instructions are executed by a processor to execute the method according to any one of claims 1 to 11.

15. A computer program product, wherein the computer program product stores computer instructions, wherein the instructions are executed by a processor to execute the method according to any one of claims 1 to 11.

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