Software control system of chip flow and chip flow control method

Abstract

The invention provides a software control system for chip flow and a chip flow control method. The software control system comprises an application layer, an SDK layer and a drive adaptation layer, the SDK layer registers a flow table data structure and a flow table rule of each sub-module of the application layer to the drive adaptation layer, and associates configuration of each sub-module of the application layer with a flow table in the drive adaptation layer, and the flow table data structure comprises each sub-module name, each flow table name, an API handle operated by the flow table and a register corresponding to the flow table; driving the adaptation layer to obtain a flow table message of each sub-module according to a query instruction issued by the application layer, and returning a chip flow carried in the flow table message to the application layer; and the application layer and the drive adaptation layer read and write the flow table or the corresponding register through a control mechanism so as to realize the process control of the chip flow. According to the invention, a universal chip flow query mode is realized, and the difference between chip manufacturers is eliminated.

Description

Technical Field

[0001] The present invention relates to the technical field of network communication, and in particular to a chip pipeline software control system and a chip pipeline control method. Background Art

[0002] With the advancement of technology, embedded devices are increasingly used in industries, consumer electronics, defense, and other fields. However, the following problems often occur during product use:

[0003] 1) Business congestion problems occur from time to time, and it is necessary to troubleshoot packet loss during data transmission. However, different chip manufacturers have different degrees of openness to customers. Some chip manufacturers are not open to customers and cannot view chip flow. Therefore, troubleshooting such packet loss problems becomes very difficult.

[0004] 2) Due to business problems, the table lookup process of the message flow needs to be modified. Since the chip flow cannot be viewed, or even if it can be viewed, the table lookup process cannot be modified, such business problems cannot be solved in time; if the version is upgraded again by modifying the code, this will cause timeliness issues.

[0005] 3) The sub-modules of the application layer usually do not care about which flow tables of the chip the business data is sent to. However, sometimes when packet loss occurs, it is difficult to analyze which sub-module caused it by only checking the location of the packet loss in the pipeline. In addition, sometimes the application layer wants to intuitively understand whether there are conflicts among the flow tables sent to the chip. For example, when various functions of the application layer are superimposed and configured, the sending may fail. At this time, it is necessary to understand the resource usage, remaining status, memory resource ratio, etc. of each flow table to avoid conflicts. Summary of the invention

[0006] The present invention provides a chip pipeline software control system and a chip pipeline control method, aiming to uniformly realize chip pipeline query and eliminate the differences among chip manufacturers.

[0007] The purpose of the present invention is achieved by the following technical solutions:

[0008] In a first aspect, the present invention provides a software control system for chip pipeline, the software control system comprising: an application layer, an SDK layer and a driver adaptation layer;

[0009] The SDK layer registers the flow table data structure and flow table rules of each submodule of the application layer with the driver adaptation layer, and associates the configuration of each submodule of the application layer with the flow table in the driver adaptation layer, wherein the flow table data structure includes: each submodule name, each flow table name, an API handle for flow table operation, and a register corresponding to the flow table, and the flow table rules include: the order of querying submodules and the order of querying flow tables within submodules;

[0010] The driver adaptation layer obtains the flow table message of each submodule according to the query instruction issued by the application layer, and returns the chip flow carried in the flow table message to the application layer;

[0011] The application layer and the driver adaptation layer read and write the flow table or the corresponding register through a control mechanism to achieve process control of the chip pipeline.

[0012] According to a chip pipeline software control system provided by the present invention, the driver adaptation layer registers a callback function with the SDK layer, so that when the SDK layer registers the flow table data structure of each sub-module of the application layer with the driver adaptation layer, the data of the flow table data structure is stored in a preset storage table by calling the callback function, and the table structure of the storage table is a two-dimensional data table, the first dimension data is the sub-module to which each flow table belongs, and the second dimension data is the flow table.

[0013] According to a software control system of a chip pipeline provided by the present invention, the driver adaptation layer associates the flow table rules with the flow table operations, traverses the sub-modules of the storage table and the flow tables in the sub-modules through the read operations in the flow table operations, and queries the query results of all flow tables and the associated field values ​​of the registers according to the query instructions in the network data packets as the query results of the chip pipeline.

[0014] According to a chip pipeline software control system provided by the present invention, the driver adaptation layer obtains the query results of all flow tables through the read operation in the flow table operation, and counts the usage and remaining status of each flow table according to the query results, and calculates the memory occupancy ratio.

[0015] According to a chip pipeline software control system provided by the present invention, the driver adaptation layer obtains the flow table name sent by the application layer, obtains the flow table used by the submodule according to the flow table name, and queries other submodules associated with the flow table.

[0016] According to a chip pipeline software control system provided by the present invention, a feedback mechanism is triggered when packet loss occurs in the flow table. The feedback mechanism searches for the submodule that causes packet loss from the submodules associated with the flow table and feeds back to the application layer.

[0017] According to a software control system of a chip pipeline provided by the present invention, the driver adaptation layer operates on the data of the flow table or the corresponding register through add, delete, read and write operations in the flow table operation, changes the execution conditions of the chip pipeline, so as to realize the control of the chip pipeline.

[0018] According to a chip pipeline software control system provided by the present invention, the driver adaptation layer includes: a packet filtering module, a flow table resource management module, an associated flow table visualization module and a chip pipeline control module;

[0019] The application layer sends a query instruction to the packet filtering module to filter the flow table message to check the chip flow process in the flow table message;

[0020] The application layer sends a resource management instruction to the flow table resource management module to obtain resource usage of each flow table;

[0021] The application layer sends an associated flow table visualization instruction to the associated flow table visualization module to visualize the associated flow table status of each submodule and the data of the associated flow table;

[0022] The application layer sends a chip flow control instruction to the chip flow control module to control the chip flow.

[0023] In a second aspect, the present invention further provides a chip flow control method based on any of the above chip flow software control systems, comprising:

[0024] The driver adaptation layer registers the callback function with the SDK layer;

[0025] The SDK layer registers the flow table data structure of each sub-module of the application layer with the driver adaptation layer, triggers the call back function, and stores the data of the flow table data structure as the data returned by the call back function in a preset storage table, wherein the flow table data structure includes: the name of each sub-module, the name of each flow table, the API handle of the flow table operation, and the register corresponding to the flow table;

[0026] Associating the configuration of each submodule of the application layer with the flow table in the driver adaptation layer;

[0027] The SDK layer registers flow table rules with the driver adaptation layer, wherein the flow table rules include: an order of querying submodules and an order of querying flow tables within submodules.

[0028] A chip flow control method according to the present invention further includes:

[0029] The application layer sends a query instruction to the driver adaptation layer to query the chip pipeline;

[0030] The application layer sends resource management instructions to the driver adaptation layer to manage the resources of each flow table;

[0031] The application layer sends an associated flow table visualization instruction to the driver adaptation layer to visualize the associated flow table of each submodule and the data of the associated flow table;

[0032] The application layer sends chip pipeline control instructions to the driver adaptation layer to manage the chip pipeline.

[0033] The present invention provides a software control system for chip flow and a chip flow control method. The software control system comprises: an application layer, an SDK layer and a driver adaptation layer; the SDK layer registers the flow table data structure and flow table rules of each submodule of the application layer with the driver adaptation layer, and associates the configuration of each submodule of the application layer with the flow table in the driver adaptation layer, wherein the flow table data structure comprises: each submodule name, each flow table name, an API handle for flow table operation and a register corresponding to the flow table, and the flow table rule comprises: an order for querying submodules and an order for querying flow tables in submodules; the driver adaptation layer obtains flow table messages of each submodule according to a query instruction issued by the application layer, and returns the chip flow carried in the flow table message to the application layer; the application layer and the driver adaptation layer read and write the flow table or the corresponding register through a control mechanism to realize process control of the chip flow. Regardless of whether the chip itself supports chip flow viewing, the present invention implements a universal chip flow query method, eliminating the differences between chip manufacturers, facilitating users to access and analyze the flow data of these chips, and helping users to troubleshoot packet loss. By controlling the chip flow process, "programmable flow" becomes possible, and for business conflict problems in some usage scenarios, changing the chip flow can achieve the expected results, improving timeliness. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other implementation methods can be obtained based on these drawings without paying any creative work.

[0035] Figure 1 It is a structural schematic diagram of a software control system for chip pipeline provided by an embodiment of the present invention;

[0036] Figure 2 It is a schematic diagram of the internal logic of the software control system of the chip pipeline provided by an embodiment of the present invention;

[0037] Figure 3 It is one of the flow charts of the chip flow control method provided by the embodiment of the present invention;

[0038] Figure 4 This is the second flow chart of the chip flow control method provided in the embodiment of the present invention. DETAILED DESCRIPTION

[0039] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the following specifically cites a preferred embodiment and describes it in detail with the accompanying drawings as follows.

[0040] It should be noted that it is explicitly and implicitly understood by those of ordinary skill in the art that the embodiments described in the present invention can be combined with other embodiments without conflict. Unless otherwise defined, the technical terms or scientific terms involved in the present invention should be the usual meanings understood by people with ordinary skills in the technical field to which the present invention belongs. The words "one", "a", "a", "the" and the like involved in the present invention do not indicate a quantitative limitation and may represent the singular or plural. The terms "including", "comprising", "having" and any of their variations involved in the present invention are intended to cover non-exclusive inclusions; the terms "first", "second", "third", etc. involved in the present invention are merely to distinguish similar objects and do not represent a specific ordering of objects.

[0041] Reference Figure 1 As shown, an embodiment of the present invention provides a chip pipeline software control system, the software control system includes: an application layer, an SDK layer and a driver adaptation layer;

[0042] The SDK layer registers the flow table data structure and flow table rules of each sub-module of the application layer with the driver adaptation layer, and associates the configuration of each sub-module of the application layer with the flow table in the driver adaptation layer, wherein the flow table data structure includes: the name of each sub-module, the name of each flow table, the API handle of the flow table operation and the register corresponding to the flow table, and the flow table rules include: the order of querying the sub-modules and the order of querying the flow table in the sub-module;

[0043] The driver adaptation layer obtains the flow table message of each submodule according to the query instruction issued by the application layer, and returns the chip flow carried in the flow table message to the application layer;

[0044] The application layer and the driver adaptation layer read and write the flow table or the corresponding register through a control mechanism to achieve process control of the chip pipeline.

[0045] The whole solution of the present invention is implemented by SDK layer API, driver adaptation layer PIPELINE and application layer APP:

[0046] The submodules of the application layer refer to independent functional components served by the API (Application Programming Interface) of the SDK layer (Software Development Kit layer, a set of tools and interfaces for software development). These submodules can be software units responsible for handling specific tasks or functions, such as data processing, network communication, user interaction, etc. Each submodule has associated flow tables (table structures used to control data flow) and registers (small data storage units used to store configuration information or status).

[0047] Pipeline usually refers to a processing mode at the software level, especially common in processor design and embedded system software development. It involves breaking down complex processes (such as instruction processing or data processing tasks) into a series of discrete stages that can be executed in parallel or serially to improve overall processing efficiency. Each stage is usually responsible for processing a part of the work and then passing the results to the next stage. The driver adaptation layer is the software component layer that implements the pipeline processing mode, responsible for managing and optimizing the various stages of the processing flow.

[0048] The SDK layer API registers the flow tables and registers related to each sub-module of the application layer APP with the driver adaptation layer PIPELINE; the driver adaptation layer PIPELINE queries the flow table messages of each sub-module according to the query instructions of the application layer APP, obtains the relevant flow table information (such as: packet loss location) and returns it to the application layer APP, so that the application layer APP can know the entire chip pipeline process of the flow table message and the packet loss location in the flow table message.

[0049] The flow table is used to record the processing rules of data packets in network processing or data flow control. Add, delete or change the rules in the flow table, and then observe whether the data packet is processed correctly according to the new rules to verify the correctness of the flow table function. Or observe whether the chip responds correctly to the change of the register by modifying the field value of the register to verify whether the register is working properly. Therefore, the application layer APP and the driver adaptation layer PIPELINE read and write the data of the flow table or register through a control mechanism to rewrite the chip pipeline. The application layer APP can solve specific engineering problems based on this control mechanism, such as network processing behaviors related to forwarding, filtering, modification or monitoring of network data packets. The system provides an interface for modifying flow tables or registers, allowing users or developers to customize network processing behaviors according to actual needs to meet different application scenarios or security requirements, with a certain degree of flexibility.

[0050] The functional configuration of each sub-module of the application layer APP is associated with the flow table of each sub-module registered in the driver adaptation layer PIPELINE. Through this association, combined with the filter function of the driver adaptation layer PIPELINE, the chip flow of each sub-module is queried. If packet loss occurs, it can quickly and accurately locate which sub-module of the application layer APP the packet loss belongs to.

[0051] The driver adaptation layer PIPELINE collects the usage information of each sub-module on the flow table and the usage of resources such as memory, and feeds it back to the application layer APP, providing a basis for the allocation and use of resources by each sub-module of the application layer.

[0052] The present invention provides chip restriction conditions for demand design in the product development stage, such as flow table usage, conflict conditions, etc.; in the product debugging and operation stage, checks the chip flow of flow table messages and provides a packet loss troubleshooting method; in the product commercial stage, modifies the chip flow table lookup process to provide a modification path for specific functions.

[0053] Therefore, regardless of whether the chip itself supports chip flow viewing, the present invention implements a universal chip flow query method, eliminating the differences between chip manufacturers, facilitating users to access and analyze the flow data of these chips, and helping users to troubleshoot packet loss. By controlling the chip flow process, "programmable flow" becomes possible, and for business conflict problems in some usage scenarios, changing the chip flow can achieve the expected results, improving timeliness.

[0054] In this embodiment, the driver adaptation layer registers a callback function with the SDK layer, so that when the SDK layer registers the flow table data structure of each sub-module of the application layer with the driver adaptation layer, the data of the flow table data structure is stored in a preset storage table by calling the callback function. The table structure of the storage table is a two-dimensional data table, the first dimension data is the sub-module to which each flow table belongs, and the second dimension data is the flow table.

[0055] Specifically, refer to Figure 2 As shown, in the system initialization phase, the driver adaptation layer registers the callback function callback with the SDK layer. When the SDK layer registers the flow table data structure of each submodule with the driver adaptation layer, the callback function is triggered. By calling the callback function, the data of the flow table data structure is stored in the preset storage table store_tbl. The table structure of the storage table store_tbl is a two-dimensional data table. The first dimension data is the submodule to which each flow table belongs, and the second dimension data is the flow table. The flow table data structure includes: the name of each submodule, the name of each flow table, the API handle of the flow table operation, and the register corresponding to the flow table.

[0056] The SDK layer registers the flow table rule tbl_rule with the driver adaptation layer, that is, the order of querying sub-modules and the order of querying flow tables within sub-modules.

[0057] The driver adaptation layer includes: packet filtering module, flow table resource management module, associated flow table visualization module and chip pipeline control module, so as to respectively realize the chip pipeline query function, flow table resource management function, associated flow table management function of each sub-module of the application layer and chip pipeline management function of the driver adaptation layer.

[0058] In this embodiment, the application layer sends a query instruction to the packet filtering module to view the chip flow process in the flow table message by filtering the flow table message.

[0059] The driver adaptation layer associates the flow table rules with the flow table operations, and traverses the sub-modules of the storage table store_tbl and the flow tables in the sub-modules through the read operation read in the flow table operation. According to the query instructions in the network data packet, the query results of all flow tables and the field values ​​of the associated registers are queried to feed back to the application layer as the query results of the chip pipeline, thereby realizing the chip pipeline query function.

[0060] In this embodiment, the application layer sends a resource management instruction to the flow table resource management module to obtain the resource usage of each flow table.

[0061] The driver adaptation layer obtains the query results of all flow tables through the read operation in the flow table operation, counts the usage and remaining status of each flow table according to the query results, and calculates the memory occupancy ratio, and feeds the results back to the application layer, thereby realizing the flow table resource management function.

[0062] In this embodiment, the application layer sends an associated flow table visualization instruction to the associated flow table visualization module to visualize the associated flow table status of each submodule and the data of the associated flow table.

[0063] The driver adaptation layer obtains the flow table name sent by the application layer, obtains the flow table used by the sub-module according to the flow table name, and queries other sub-modules associated with the flow table.

[0064] The flow table used by each sub-module of the application layer is sent down to the driver adaptation layer. According to the sent flow table name and the flow table name registered to the driver adaptation layer by the associated SDK layer, the flow table used by the sub-module is obtained; and the associated sub-module can be queried based on the flow table. If packet loss occurs in the flow table, the feedback mechanism is triggered. The feedback mechanism searches for the sub-module that causes packet loss from the sub-modules associated with the flow table and feeds back to the application layer, thereby realizing the management function of the associated flow tables of each sub-module of the application layer.

[0065] Coupling the sub-module with the flow table enables the application layer to visualize the usage of the flow table and provide important SDK information for the functional requirement design of the sub-module. The sub-module uses this information to analyze whether the requirements can be met, whether there will be conflicts, and whether the performance requirements during design are met.

[0066] In this embodiment, the application layer sends a chip pipeline control instruction to the chip pipeline control module to implement chip pipeline control.

[0067] The driver adaptation layer operates on the data of the flow table or the corresponding registers through add, delete, read, and write operations in the flow table operation, and changes the execution conditions of the chip pipeline to achieve control of the chip pipeline. For example, if the mac address query and the acl (access control list) table items are both hit, because the chip pipeline rule is that the acl is executed later, then the acl decision will take effect in the end and overwrite the previous mac address hit result. The previous mac address will not take effect even if it hits; if for some specific business needs or security policies, the mac address is expected to take effect at this time, but the acl is not effective, the data in the flow table can be changed and rewritten so that the acl rule is not hit, so that the mac address hit can take effect. Therefore, the driver adaptation layer provides an interface for adding, deleting, modifying and checking the chip pipeline. The application layer modifies the data in the flow table or the corresponding register through such an interface to change the execution conditions of the network chip pipeline, thereby controlling the chip pipeline and allowing users or developers to customize network processing behaviors according to actual needs to meet different application scenarios or security requirements. In addition, by verifying or modifying the table lookup process by modifying the flow table or register, the expected effect is achieved and timeliness is improved.

[0068] Reference Figure 3 As shown, an embodiment of the present invention further provides a chip flow control method based on any of the above chip flow software control systems, including:

[0069] Step S101: the driver adaptation layer registers a callback function with the SDK layer;

[0070] Step S102: The SDK layer registers the flow table data structure of each sub-module of the application layer with the driver adaptation layer, triggers the call back function, and stores the data of the flow table data structure as the data returned by the call back function in a preset storage table, wherein the flow table data structure includes: the name of each sub-module, the name of each flow table, the API handle of the flow table operation, and the register corresponding to the flow table;

[0071] Step S103: Associating the configuration of each submodule of the application layer with the flow table in the driver adaptation layer;

[0072] Step S104: The SDK layer registers the flow table rules with the driver adaptation layer, where the flow table rules include:

[0073] The order in which submodules are queried and the order in which flow tables are queried within submodules.

[0074] Reference Figure 4As shown, a chip flow control method provided by the present invention further includes:

[0075] Step S201: the application layer sends a query instruction to the driver adaptation layer to query the chip pipeline;

[0076] Step S202: The application layer sends a resource management instruction to the driver adaptation layer to manage the resources of each flow table;

[0077] Step S203: the application layer sends an associated flow table visualization instruction to the driver adaptation layer to visualize the associated flow table of each submodule and the data of the associated flow table;

[0078] Step S204: the application layer sends a chip pipeline control instruction to the driver adaptation layer to manage the chip pipeline.

[0079] The implementation process of the above method is detailed in the implementation process of the system, which will not be repeated here.

[0080] Those skilled in the art will appreciate that, in the above method of specific implementation, the order in which the steps are written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of the steps should be determined by their functions and possible internal logic.

[0081] In summary, the present invention provides a software control system for chip flow and a chip flow control method, the software control system includes: an application layer, an SDK layer and a driver adaptation layer; the SDK layer registers the flow table data structure and flow table rules of each sub-module of the application layer to the driver adaptation layer, and associates the configuration of each sub-module of the application layer with the flow table in the driver adaptation layer, wherein the flow table data structure includes: the name of each sub-module, the name of each flow table, the API handle of the flow table operation and the register corresponding to the flow table, and the flow table rule includes: the order of querying the sub-modules and the order of querying the flow table in the sub-module; the driver adaptation layer obtains the flow table message of each sub-module according to the query instruction issued by the application layer, and returns the chip flow carried in the flow table message to the application layer; the application layer and the driver adaptation layer read and write the flow table or the corresponding register through a control mechanism to realize the process control of the chip flow. Regardless of whether the chip itself supports chip flow viewing, the present invention implements a universal chip flow query method, eliminating the differences between chip manufacturers, facilitating users to access and analyze the flow data of these chips, and helping users to troubleshoot packet loss. By controlling the chip flow process, "programmable flow" becomes possible, and for business conflict problems in some usage scenarios, changing the chip flow can achieve the expected results, improving timeliness.

[0082] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0083] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A software control system for chip pipeline, characterized in that: The software control system includes: an application layer, an SDK layer and a driver adaptation layer; The SDK layer registers the flow table data structure and flow table rules of each submodule of the application layer with the driver adaptation layer, and associates the configuration of each submodule of the application layer with the flow table in the driver adaptation layer, wherein the flow table data structure includes: each submodule name, each flow table name, an API handle for flow table operation, and a register corresponding to the flow table, and the flow table rules include: the order of querying submodules and the order of querying flow tables within submodules; The driver adaptation layer obtains the flow table message of each submodule according to the query instruction issued by the application layer, and returns the chip flow carried in the flow table message to the application layer; The application layer and the driver adaptation layer read and write the flow table or the corresponding register through a control mechanism to achieve process control of the chip pipeline.

2. The chip pipeline software control system according to claim 1, characterized in that: The driver adaptation layer registers a callback function with the SDK layer, so that when the SDK layer registers the flow table data structure of each sub-module of the application layer with the driver adaptation layer, the data of the flow table data structure is stored in a preset storage table by calling the callback function. The table structure of the storage table is a two-dimensional data table, the first dimension data is the sub-module to which each flow table belongs, and the second dimension data is the flow table.

3. The chip pipeline software control system according to claim 2, characterized in that: The driver adaptation layer associates the flow table rules with the flow table operations, traverses the sub-modules of the storage table and the flow tables in the sub-modules through the read operations in the flow table operations, and queries the query results of all flow tables and the associated field values ​​of the registers according to the query instructions in the network data packets as the query results of the chip pipeline.

4. The chip pipeline software control system according to claim 3, characterized in that: The driver adaptation layer obtains the query results of all flow tables through the read operation in the flow table operation, and counts the usage and remaining status of each flow table according to the query results, and calculates the memory occupancy ratio.

5. The chip pipeline software control system according to claim 3, characterized in that: The driver adaptation layer obtains the flow table name sent by the application layer, obtains the flow table used by the submodule according to the flow table name, and queries other submodules associated with the flow table.

6. The chip pipeline software control system according to claim 5, characterized in that: When packet loss occurs in the flow table, a feedback mechanism is triggered. The feedback mechanism searches for the submodule that causes the packet loss from the submodules associated with the flow table and feeds back to the application layer.

7. The chip pipeline software control system according to claim 3, characterized in that: The driver adaptation layer operates on the data of the flow table or the corresponding register through add, delete, read and write operations in the flow table operation, changes the execution conditions of the chip pipeline, so as to realize the control of the chip pipeline.

8. The chip pipeline software control system according to claim 1, characterized in that: The driver adaptation layer includes: a packet filtering module, a flow table resource management module, an associated flow table visualization module and a chip flow control module; The application layer sends a query instruction to the packet filtering module to filter the flow table message to check the chip flow process in the flow table message; The application layer sends a resource management instruction to the flow table resource management module to obtain resource usage of each flow table; The application layer sends an associated flow table visualization instruction to the associated flow table visualization module to visualize the associated flow table status of each submodule and the data of the associated flow table; The application layer sends a chip flow control instruction to the chip flow control module to control the chip flow.

9. A chip pipeline control method based on the chip pipeline software control system according to any one of claims 1 to 8, characterized in that: include: The driver adaptation layer registers the callback function with the SDK layer; The SDK layer registers the flow table data structure of each sub-module of the application layer with the driver adaptation layer, triggers the call back function, and stores the data of the flow table data structure as the data returned by the call back function in a preset storage table, wherein the flow table data structure includes: the name of each sub-module, the name of each flow table, the API handle of the flow table operation, and the register corresponding to the flow table; Associating the configuration of each submodule of the application layer with the flow table in the driver adaptation layer; The SDK layer registers flow table rules with the driver adaptation layer, wherein the flow table rules include: an order of querying submodules and an order of querying flow tables within submodules.

10. The chip flow control method according to claim 9, characterized in that: Also includes: The application layer sends a query instruction to the driver adaptation layer to query the chip pipeline; The application layer sends resource management instructions to the driver adaptation layer to manage the resources of each flow table; The application layer sends an associated flow table visualization instruction to the driver adaptation layer to visualize the associated flow table of each submodule and the data of the associated flow table; The application layer sends chip pipeline control instructions to the driver adaptation layer to manage the chip pipeline.

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