Server

Abstract

The invention relates to the technical field of servers, and discloses a server, which comprises a BMC (Baseboard Management Controller), an FPGA (Field Programmable Gate Array), a multiplexer, a first memory and a second memory, the BMC is used for loading the BMC firmware in the first memory, generating an initialization completion signal after initialization is completed, and sending the initialization completion signal to the FPGA, so that the FPGA sends a first signal to the BMC; the BMC is used for sending a pulse signal to the FPGA in response to the received first signal; the FPGA is used for determining that BMC firmware in the first memory is abnormal and sending a reset signal to the BMC if the pulse signal is not received, so that the BMC is reset; and the FPGA is used for sending a first chip selection signal to the multiplexer and sending a reset signal to the BMC if the BMC is reset abnormally, so that the BMC is connected with the second memory through the multiplexer and loads and runs the BMC firmware in the second memory. The server can monitor whether the BMC firmware is abnormal or not and perform exception processing.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of servers, and in particular to a server. Background Art

[0002] The server includes a baseboard management controller (BMC). As the management and control core of the server, the BMC is mainly responsible for various monitoring, control and configuration functions of the server. During the operation of the server, the BMC firmware may fail due to various reasons such as system power failure, abnormal reset, interruption of write operation, etc., resulting in configuration data corruption, thus affecting the normal startup and operation of the BMC. This failure will not only affect the stability and reliability of the server, but may also cause data loss and business interruption. Currently, existing servers cannot monitor whether the BMC firmware is abnormal. Summary of the invention

[0003] In view of the above problems, an embodiment of the present application provides a server for solving the problem in the prior art that the server cannot monitor whether the BMC firmware is abnormal.

[0004] According to one aspect of an embodiment of the present application, a server is provided, the server comprising a baseboard management controller BMC, a field programmable gate array FPGA, a multiplexer, a first memory and a second memory, wherein the first memory and the second memory store BMC firmware; the FPGA comprises a first signal receiving pin, a pulse signal receiving pin, a reset signal sending pin and a first signal sending pin, which are respectively connected to the second signal sending pin, the pulse signal sending pin, the reset signal receiving pin and the second signal receiving pin of the BMC in a one-to-one correspondence; the FPGA further comprises a chip select pin, which is connected to the control pin of the multiplexer; the BMC is used to connect to the first memory or the second memory through the multiplexer; wherein, when the BMC is connected to the first memory through the multiplexer, the BMC is used to load the BMC firmware in the first memory and generate an initialization completion signal after completing initialization, and send the initialization completion signal to the F through the second signal sending pin PGA; the FPGA is used to send a first signal to the BMC through the first signal sending pin in response to receiving the initialization completion signal; the BMC is used to send a pulse signal to the FPGA through the pulse signal sending pin in response to receiving the first signal; the FPGA is used to determine that the BMC firmware in the first memory is abnormal if the pulse signal is not received through the pulse signal receiving pin, and send a reset signal to the BMC through the reset signal sending pin; the BMC is used to receive the reset signal and reset; the FPGA is used to send a first chip select signal to the multiplexer through the chip select pin if the BMC reset is abnormal, and send a reset signal to the BMC through the reset signal sending pin; the multiplexer is used to switch the BMC from connecting to the first memory to connecting to the second memory in response to receiving the first chip select signal; the BMC is used to load and run the BMC firmware in the second memory in response to receiving the reset signal.

[0005] In an optional manner, the BMC is used to generate a second signal after loading and running the BMC firmware in the second memory and completing the restart, and send the second signal to the FPGA through the second signal sending pin; the FPGA is used to determine that the BMC firmware in the second memory is abnormal if the second signal is not received through the first signal receiving pin, send a second chip select signal to the multiplexer through the chip select pin, and send a reset signal to the BMC through the reset signal sending pin; the multiplexer is used to switch the BMC from connecting to the second memory to connecting to the first memory in response to receiving the second chip select signal; the BMC is used to load and run the BMC firmware in the first memory in response to receiving the reset signal.

[0006] In an optional manner, the FPGA is used to send the first signal to the BMC through the first signal sending pin in response to receiving the second signal through the first signal receiving pin; the BMC is used to send a pulse signal to the FPGA through the pulse signal sending pin in response to receiving the first signal; and the FPGA is used to determine that the BMC firmware in the second memory is abnormal if the pulse signal is not received through the pulse signal receiving pin.

[0007] In an optional manner, the FPGA also includes a first register, and the FPGA is also used to: add 1 to a first count value in the first register after each execution of the step of sending a first chip select signal to the multiplexer through the chip select pin, wherein the initial value of the first count value is 0; add 1 to the first count value after each execution of the step of sending a second chip select signal to the multiplexer through the chip select pin; if the first count value is greater than a preset threshold, stop executing the step of sending the first chip select signal to the multiplexer through the chip select pin and the step of sending the second chip select signal to the multiplexer through the chip select pin.

[0008] In an optional manner, the FPGA further includes a second register, and the FPGA is further used to: after executing the step of sending the first chip select signal to the multiplexer through the chip select pin, store the first value in the second register.

[0009] In an optional manner, the FPGA also includes a first data transmission pin, which is connected to a second data transmission pin of the BMC; the BMC is used to: when the BMC firmware stored in any one of the first memory and the second memory is normally operated, obtain the value in the second register through the second data transmission pin, if the obtained value is the first value, generate a first event log and send it to an electronic device that can receive BMC alarm information, and update the first value to an initial value through the second data pin, wherein the first event log is that the BMC firmware fails and the memory has been switched.

[0010] In an optional manner, the FPGA also includes a third register, and the FPGA is further used to add 1 to the second count value in the third register after each execution of the step of sending a reset signal to the BMC through the reset signal sending pin, wherein the initial value of the second count value is 0.

[0011] In an optional manner, the FPGA also includes a first data transmission pin, which is connected to a second data transmission pin of the BMC; the BMC is used to: when normally operating the BMC firmware stored in any one of the first memory and the second memory, obtain the second count value in the third register through the second data transmission pin, if the second count value currently obtained is greater than the second count value obtained last time, generate a second event log and send it to an electronic device that can receive BMC alarm information, wherein the second event log is the FPGA resetting the BMC.

[0012] In an optional manner, the memory currently connected to the BMC is the current memory, wherein the current memory is the first memory or the second memory; the pulse signal sent by the BMC is a periodic pulse signal, the FPGA also includes a first counter for recording duration, and the FPGA is also used to: after sending the first signal to the BMC, control the first counter to start timing; when the duration recorded by the first counter does not reach the first duration, if the pulse signal is received, clear the first counter and go to the step of controlling the first counter to start timing, wherein the first duration is greater than or equal to the period of the periodic pulse signal; when the duration recorded by the first counter reaches the first duration, if the pulse signal is not received, determine that the BMC firmware in the current memory is abnormal.

[0013] In an optional manner, the memory currently connected to the BMC is the current memory, wherein the current memory is the first memory or the second memory; the FPGA also includes a second counter for recording duration, and the FPGA is also used to: after sending the reset signal to the BMC, control the second counter to start timing; when the duration recorded by the second counter reaches the second duration, if the restart completion signal sent by the BMC is not received, determine that the BMC firmware in the current memory is abnormal, wherein the restart completion signal is a signal generated after the BMC loads the BMC firmware in the current memory and completes the restart.

[0014] In the embodiment of the present application, when the BMC is connected to the first memory through the multiplexer, if the BMC firmware in the first memory is normal, the BMC can run the BMC firmware in the first memory normally, and the BMC can send a pulse signal to the FPAG normally. If the BMC firmware in the first memory is abnormal, the BMC cannot run the BMC firmware in the first memory normally, and the BMC cannot send a pulse signal to the FPAG. Therefore, if the FPGA does not receive the pulse signal sent by the BMC, it can accurately determine that the BMC firmware in the first memory is abnormal.

[0015] After the FPGA determines that the BMC firmware in the first memory is abnormal, in order to perform abnormal processing and reduce losses, it controls the BMC to reset to achieve abnormal processing. If the reset fails, the BMC is controlled to connect to the second memory through the multiplexer so that the BMC loads and runs the BMC firmware in the second memory, thereby achieving abnormal processing.

[0016] Furthermore, in the embodiment of the present application, the BMC can be reset by sending a reset signal via the FPGA to the BMC, without requiring maintenance personnel to go to the computer room and perform a reset operation on the reset button on the server, thereby bringing convenience to users.

[0017] The above description is only an overview of the technical solution of the embodiment of the present application. In order to more clearly understand the technical means of the embodiment of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the embodiment of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings are only used to illustrate the embodiments and are not to be considered as limiting the present application. In addition, the same reference symbols are used to represent the same components throughout the accompanying drawings. In the accompanying drawings:

[0019] Figure 1 A schematic diagram of a server provided in an embodiment of the present application is shown;

[0020] Figure 2 A schematic diagram of a process of monitoring whether the BMC firmware is abnormal by a server provided in an embodiment of the present application is shown;

[0021] Figure 3 A schematic diagram of a process in which a server provided in an embodiment of the present application generates a first event log and a second event log and sends them to an electronic device is shown. DETAILED DESCRIPTION

[0022] The exemplary embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments set forth herein.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by technicians in the technical field to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" in the specification and claims of this application and the above-mentioned figure descriptions and any variations thereof are intended to cover non-exclusive inclusions.

[0024] In the description of the embodiments of the present application, the technical terms "first", "second", etc. are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features. In the description of the embodiments of the present application, the meaning of "multiple" is more than two, unless otherwise clearly and specifically defined.

[0025] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0026] In the description of the embodiments of the present application, the term "and / or" is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists, A and B exist at the same time, and B exists. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0027] In the description of the embodiments of the present application, the term "multiple" refers to more than two (including two). Similarly, "multiple groups" refers to more than two groups (including two groups), and "multiple pieces" refers to more than two pieces (including two pieces).

[0028] In the description of the embodiments of the present application, the technical terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, which are only for the convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the embodiments of the present application.

[0029] In the description of the embodiments of the present application, unless otherwise clearly specified and limited, technical terms such as "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be the internal connection of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0030] When the server is in operation, it is usually impossible to accurately know whether the BMC firmware is abnormal. It is necessary to regularly perform health checks on the server hardware to determine whether the BMC firmware is abnormal, or to determine that the BMC firmware is abnormal when access to the IP address fails or other problems occur during the server operation. If the BMC firmware is abnormal, if you want to restart the BMC, maintenance personnel need to go to the computer room and reset the reset button on the server, which is less convenient.

[0031] Based on the above considerations, the present application proposes a server, including a BMC, a field programmable gate array (FPGA), a multiplexer, a first memory and a second memory, wherein the BMC firmware is stored in the first memory and the second memory, and the BMC is connected to the first memory or the second memory through the multiplexer. In the present application, when the BMC firmware in the first memory or the second memory is set to run normally, a pulse signal is sent to the FPGA. If the FPGA does not receive the pulse signal sent by the BMC, it can be determined that the BMC firmware in the memory currently connected to the BMC is abnormal, and then a reset signal is sent to the BMC through the FPGA to reset the BMC. If the BMC reset is abnormal, the FPGA sends a chip select signal to the multiplexer so that the BMC is connected to another memory through the multiplexer, and loads and runs the BMC firmware in the memory.

[0032] Figure 1FIG. 1 shows a schematic diagram of a server provided in an embodiment of the present application. Figure 1 As shown, the server includes a BMC, an FPGA, a multiplexer, a first memory, and a second memory. The first memory and the second memory both store BMC firmware. The multiplexer can be a Multiplexer (MUX) selector.

[0033] The FPGA includes a first signal receiving pin, a pulse signal receiving pin, a reset signal sending pin and a first signal sending pin, which are respectively connected to the second signal sending pin, the pulse signal sending pin, the reset signal receiving pin and the second signal receiving pin of the BMC in a one-to-one correspondence. The FPGA also includes a chip select pin, which is connected to the control pin of the multiplexer.

[0034] The BMC is connected to the first memory or the second memory through a multiplexer. Specifically, the 1B1 pin and the 1B2 pin in the multiplexer are connected to the CS chip select pin of the first memory and the CS chip select pin of the second memory in a one-to-one correspondence. When the 1B1 pin in the multiplexer is connected to the CS chip select pin in the first memory, the BMC is connected to the first memory through the multiplexer. When the 1B2 pin in the multiplexer is connected to the CS chip select pin in the second memory, the BMC is connected to the second memory through the multiplexer.

[0035] The BMC also includes a #CS0 chip select pin, which is connected to the 1A pin of the multiplexer. When the BMC is in normal working state, it can send a signal to the 1A pin of the multiplexer through the #CS0 chip select pin to control the 1B1 pin in the multiplexer to be turned on with the CS chip select pin in the first memory, so that the BMC is connected to the first memory through the multiplexer; or control the 1B1 pin in the multiplexer to be turned on with the CS chip select pin in the second memory, so that the BMC is connected to the second memory through the multiplexer.

[0036] The 2B1 pin and 3B1 pin of the multiplexer are respectively connected to the DI pin (data input pin) and DO pin (data output pin) of the first memory, and the multiplexer can read the BMC firmware stored in the first memory through the 2B1 pin and 3B1 pin. Similarly, the 2B2 pin and 3B2 pin of the multiplexer are respectively connected to the DI pin (data input pin) and DO pin (data output pin) of the second memory, and the multiplexer can read the BMC firmware stored in the second memory through the 2B2 pin and 3B2 pin. The OE pin (output enable pin) in the multiplexer is grounded so that the multiplexer can work normally.

[0037] BMC includes a MISO pin (data output pin) and a MOSI pin (data input pin) for transmitting data, which are respectively connected to the 3A pin and the 2A pin of the multiplexer. After the 1B1 pin of the multiplexer and the CS chip select pin of the first memory are turned on, the multiplexer obtains the BMC firmware stored in the first memory through the 2B1 pin and the 3B1 pin, and transmits it to the BMC through the 2A pin and the 3A pin, so that the BMC can load and run the BMC firmware stored in the first memory. Similarly, after the 1B2 pin of the multiplexer and the CS chip select pin of the second memory are turned on, the multiplexer obtains the BMC firmware stored in the second memory through the 2B2 pin and the 3B2 pin, and transmits it to the BMC through the 2A pin and the 3A pin, so that the BMC can load and run the BMC firmware stored in the second memory.

[0038] When the BMC is connected to the first memory through the multiplexer, the BMC generates an initialization completion signal after loading the BMC firmware in the first memory and completing the initialization, and sends the initialization completion signal to the FPGA through the second signal sending pin. In response to receiving the initialization completion signal, the FPGA sends the first signal to the BMC through the first signal sending pin. In response to receiving the first signal, the BMC sends a pulse signal to the FPGA through the pulse signal sending pin.

[0039] After the server is connected to the power supply and powered on, the BMC starts to power on and start. If the BMC is connected to the first memory through the multiplexer, the BMC loads and runs the BMC firmware stored in the first memory and completes the initialization. After the BMC completes the initialization, it continues to run the BMC firmware stored in the first memory. After the BMC initialization is completed, an initialization completion signal is generated and sent to the FPGA.

[0040] After receiving the initialization completion signal sent by the BMC, the FPGA sends a first signal to the BMC through the first signal sending pin in order to monitor whether the BMC firmware stored in the first memory is abnormal. In response to receiving the first signal, the BMC sends a pulse signal to the FPGA through the pulse signal sending pin, so that the FPGA can determine whether the BMC firmware in the first memory is abnormal based on the pulse signal. If the FPGA does not receive the pulse signal through the pulse signal receiving pin, it determines that the BMC firmware in the first memory is abnormal, and sends a reset signal to the BMC through the reset signal sending pin. The BMC receives the reset signal and resets.

[0041] Specifically, if the BMC firmware in the first memory is normal, the BMC can run the BMC firmware in the first memory normally, and the BMC can normally send pulse signals to the FPGA through the pulse signal sending pin, so if the FPGA receives the pulse signal sent by the BMC, it can be determined that the BMC firmware in the first memory is normal. Conversely, if the BMC firmware in the first memory is abnormal, the BMC cannot run the BMC firmware in the first memory normally, and the BMC cannot send pulse signals to the FPGA through the pulse signal sending pin, so if the FPGA does not receive the pulse signal sent by the BMC, it can be determined that the BMC firmware in the first memory is abnormal.

[0042] After the FPGA determines that the BMC firmware in the first memory is abnormal, it sends a reset signal to the BMC through the reset pin to reset the BMC. If the BMC cannot normally run the BMC firmware in the first memory due to an abnormality such as a temporary error, the BMC can be restored to normal by resetting the BMC. Therefore, in the embodiment of the present application, the FPGA performs abnormal processing by sending a reset signal to the BMC to reset the BMC.

[0043] If the BMC firmware in the first memory is abnormal and cannot be resolved by resetting, then in the embodiment of the present application, if the BMC reset is abnormal, the FPGA sends a first chip select signal to the multiplexer through the chip select pin, and sends a reset signal to the BMC through the reset signal sending pin. In response to receiving the first chip select signal, the multiplexer switches the BMC from connecting to the first memory to connecting to the second memory. In response to receiving the reset signal, the BMC loads and runs the BMC firmware in the second memory.

[0044] Specifically, the FPGA sends a first chip select signal (e.g., a low level signal) to the multiplexer through the chip select pin, so that the 1B1 pin of the multiplexer and the CS chip select pin of the first memory are disconnected from the communication connection, and the 1B2 pin of the multiplexer and the CS chip select pin of the second memory are turned on, so that the BMC is connected to the second memory through the multiplexer. After receiving the reset signal sent by the FPGA, the BMC loads and runs the BMC firmware in the second memory.

[0045] In the embodiment of the present application, when the BMC is connected to the first memory through the multiplexer, if the BMC firmware in the first memory is normal, the BMC can run the BMC firmware in the first memory normally, and the BMC can send a pulse signal to the FPAG normally. If the BMC firmware in the first memory is abnormal, the BMC cannot run the BMC firmware in the first memory normally, and the BMC cannot send a pulse signal to the FPAG. Therefore, if the FPGA does not receive the pulse signal sent by the BMC, it can accurately determine that the BMC firmware in the first memory is abnormal.

[0046] After the FPGA determines that the BMC firmware in the first memory is abnormal, in order to perform abnormal processing and reduce losses, it controls the BMC to reset to achieve abnormal processing. If the reset fails, the BMC is controlled to connect to the second memory through the multiplexer so that the BMC loads and runs the BMC firmware in the second memory, thereby achieving abnormal processing.

[0047] Furthermore, in the embodiment of the present application, the BMC can be reset by sending a reset signal via the FPGA to the BMC, without requiring maintenance personnel to go to the computer room and perform a reset operation on the reset button on the server, thereby bringing convenience to users.

[0048] It should be noted that Figure 1 Where VDD represents the power supply, the resistance value of the pull-up resistor can be 4.7KΩ, and the resistance value of the pull-down resistor can be 100KΩ.

[0049] In some embodiments, the BMC generates a second signal after loading and running the BMC firmware in the second memory and completing the restart, and sends the second signal to the FPGA through the second signal sending pin. The second signal is a signal generated after the BMC firmware in the second memory is normal and the BMC loads and runs the BMC firmware in the second memory normally.

[0050] If the FPGA does not receive the second signal through the first signal receiving pin, it determines that the BMC firmware in the second memory is abnormal, sends the second chip select signal to the multiplexer through the chip select pin, and sends a reset signal to the BMC through the reset signal sending pin. In response to receiving the second chip select signal, the multiplexer switches the BMC from connecting to the second memory to connecting to the first memory. In response to receiving the reset signal, the BMC loads and runs the BMC firmware in the first memory.

[0051] Specifically, if the BMC firmware in the second memory is abnormal, the BMC cannot normally load and run the BMC firmware in the second memory, and the BMC cannot generate the second signal and send it to the FPGA. Therefore, if the FPGA does not receive the second signal, it can be determined that the BMC firmware in the second memory is abnormal. In order to handle the exception, the FPGA sends a second chip select signal (such as a high-level signal) to the multiplexer through the chip select pin to disconnect the communication connection between the 1B2 pin of the multiplexer and the CS chip select pin of the second memory, and the 1B1 pin of the multiplexer and the CS chip select pin of the first memory are turned on, so that the BMC is connected to the first memory through the multiplexer. After receiving the reset signal sent by the FPGA, the BMC loads and runs the BMC firmware in the first memory.

[0052] If the first memory, the second memory and the multiplexer have poor contact, the BMC will be unable to load and run the BMC firmware in the memory through the multiplexer normally. Therefore, in the embodiment of the present application, if it is determined that the BMC cannot normally run the BMC firmware in the first memory, the BMC is controlled to switch to run the BMC firmware in the second memory. If the BMC cannot normally run the BMC firmware in the second memory, the BMC is controlled to switch to run the BMC firmware in the first memory. Through the above operation, at a certain moment, after a certain memory and the multiplexer are in normal contact, the BMC can load and run the BMC firmware in the memory, thereby realizing exception handling.

[0053] On the basis of the above-mentioned embodiment, in the embodiment of the present application, the FPGA responds to receiving the second signal through the first signal receiving pin and sends the first signal to the BMC through the first signal sending pin. The BMC responds to receiving the first signal and sends a pulse signal to the FPGA through the pulse signal sending pin. If the FPGA does not receive the pulse signal through the pulse signal receiving pin, it determines that the BMC firmware in the second memory is abnormal.

[0054] Specifically, if the BMC firmware in the second memory is normal, the BMC can run the BMC firmware in the second memory normally, and the BMC can normally send pulse signals to the FPGA through the pulse signal sending pin. Therefore, if the FPGA receives the pulse signal sent by the BMC, it can be determined that the BMC firmware in the second memory is normal. On the contrary, if the BMC firmware in the second memory is abnormal, the BMC cannot run the BMC firmware in the second memory normally, and the BMC cannot send pulse signals to the FPGA through the pulse signal sending pin. Therefore, if the FPGA does not receive the pulse signal sent by the BMC, it can be determined that the BMC firmware in the second memory is abnormal. Therefore, in the embodiment of the present application, through the above settings, it can be accurately determined whether the BMC firmware in the second memory is abnormal.

[0055] In order to reduce power consumption, in an embodiment of the present application, the FPGA also includes a first register. After each time the FPGA executes the step of sending a first chip select signal to the multiplexer through a chip select pin, the FPGA adds 1 to the first count value in the first register, wherein the initial value of the first count value is 0; after each time the step of sending a second chip select signal to the multiplexer through the chip select pin is executed, the first count value is added 1; if the first count value is greater than a preset threshold, the step of sending the first chip select signal to the multiplexer through the chip select pin and the step of sending the second chip select signal to the multiplexer through the chip select pin are stopped.

[0056] As mentioned above, if the first memory, the second memory and the multiplexer have poor contact, the BMC will not be able to load and run the BMC firmware in the memory through the multiplexer. By controlling the alternating connection between the BMC and the first memory and the second memory, the BMC can load and run the BMC firmware in a certain memory after the contact between the memory and the multiplexer is restored to normal at a certain moment, thereby realizing exception handling.

[0057] However, if the BMC firmware abnormality in the first memory and the second memory is not caused by poor contact between the memory and the multiplexer, then the abnormality cannot be solved by controlling the alternating connection between the BMC and the first memory and the second memory, and switching the connection between the BMC and the first memory and the second memory back and forth will increase the power consumption of the server.

[0058] Therefore, in the embodiment of the present application, the first register is used to record the number of times the BMC is switched back and forth to connect to the first memory and the second memory through the multiplexer. If the number of times the BMC is switched back and forth to connect to the first memory and the second memory reaches a preset threshold, the switching of the BMC to connect to the first memory and the second memory is stopped, thereby reducing the power consumption of the server. The preset threshold can be set as needed, such as 5, 7 or 10.

[0059] In some embodiments, the FPGA further includes a second register, and after the FPGA executes the step of sending the first chip select signal to the multiplexer through the chip select pin, the first value is stored in the second register. The first value can be set as needed, for example, 0x1.

[0060] In the embodiment of the present application, if the FPAG sends the first chip select signal to the multiplexer, it indicates that an abnormality has occurred in the BMC firmware in the first memory, and an event has occurred in which the BMC switches from being connected to the first memory to being connected to the second memory. Therefore, subsequent maintenance personnel can directly and quickly determine whether an abnormality has occurred in the BMC firmware in the first memory based on whether the value in the second register is the first value.

[0061] In order to facilitate maintenance personnel to conduct abnormality inspection, in the embodiment of the present application, the FPGA also includes a first data transmission pin, and the first data transmission pin is connected to the second data transmission pin of the BMC. Figure 1 As shown, the first data transmission pin and the second data transmission pin are connected to form an inter-integrated circuit (I2C) serial bus, and the I2C bus includes a serial data line SDA and a serial clock line SCL. Among them, data transmission through the I2C bus belongs to the prior art and will not be described in detail here.

[0062] When the BMC normally operates the BMC firmware stored in any of the first memory and the second memory, the value in the second register is obtained through the second data transmission pin. If the obtained value is the first value, a first event log is generated and sent to an electronic device that can receive BMC alarm information, and the first value is updated to an initial value through the second data pin, wherein the first event log is that the BMC firmware fails and the memory has been switched. Among them, the electronic device can be a mobile phone, a laptop computer, etc. Specifically, the BMC can send the first event log to the electronic device through the Simple Network Management Protocol (snmp) or the Simple Mail Transfer Protocol (smtp).

[0063] In an embodiment of the present application, when the BMC is in a normal working state, by obtaining the value in the second register, if it is the first value, it means that the BMC has switched from being connected to the first memory to being connected to the second memory, or the BMC has switched from being connected to the second memory to being connected to the first memory, then a first event log is generated and sent to an electronic device that can receive BMC alarm information, so that maintenance personnel can promptly obtain abnormal information through the electronic device. In addition, after the first event log is generated, the first value is updated to the initial value in a timely manner to avoid repeatedly generating the same first event log. Among them, the initial value and the first value are two different values, and the initial value can be set as needed, such as 0.

[0064] In some embodiments, the FPGA further includes a third register. Each time the FPGA executes the step of sending a reset signal to the BMC via the reset signal sending pin, the second count value in the third register is increased by 1, wherein the initial value of the second count value is 0.

[0065] Since the FPGA sends a reset signal to the BMC only when the BMC firmware in the memory is abnormal, in the embodiment of the present application, after the FPGA executes the step of sending a reset signal to the BMC each time, the second count value in the third register is increased by 1, so that the total number of times the BMC is reset can be determined according to the second count value in the third register, so that the user can perform exception processing according to the total number of BMC resets.

[0066] In some embodiments, the FPGA also includes a first data transmission pin, and the first data transmission pin is connected to the second data transmission pin of the BMC. When the BMC normally operates the BMC firmware stored in any of the first memory and the second memory, the second count value in the third register is obtained through the second data transmission pin. If the second count value currently obtained is greater than the second count value obtained last time, a second event log is generated and sent to an electronic device that can receive BMC alarm information, wherein the second event log is the FPGA resetting the BMC. Each time the BMC reloads the BMC firmware in the first memory or the second memory for startup, the BMC obtains the second count value in the third register once. The electronic device can be a mobile phone, a laptop computer, etc. Specifically, the BMC can send the second event log to the electronic device through snmp or smtp.

[0067] In the embodiment of the present application, the BMC obtains the second count value and determines the size relationship between the second count value currently obtained and the second count value last obtained. If the second count value currently obtained is greater than the second count value last obtained, it indicates that an event has occurred in which the FPGA sends a reset signal to the BMC to reset the BMC, thereby generating a second event log and sending it to an electronic device that can receive BMC alarm information, so that maintenance personnel can perform exception processing according to the second event log.

[0068] Since the second count value is the number of times the FPGA resets the BMC, in some embodiments, the second event log also includes the second count value so that maintenance personnel can directly know the total number of times the FPGA resets the BMC based on the second count value, thereby facilitating exception handling.

[0069] In order to determine whether the BMC firmware is abnormal in a more timely manner, in the embodiment of the present application, for the convenience of description, the memory currently connected to the BMC is defined as the "current memory", where the current memory is the first memory or the second memory.

[0070] The pulse signal sent by the BMC is a periodic pulse signal. The FPGA also includes a first counter for recording duration. After the FPGA sends the first signal to the BMC, the first counter is controlled to start timing. When the duration recorded by the first counter does not reach the first duration, if a pulse signal is received, the first counter is cleared and the process proceeds to the step of controlling the first counter to start timing, wherein the first duration is greater than or equal to the period of the periodic pulse signal. When the duration recorded by the first counter reaches the first duration, if no pulse signal is received, it is determined that the BMC firmware in the current memory is abnormal.

[0071] In the embodiment of the present application, during the BMC running the BMC firmware, if the BMC firmware is normal, the BMC sends a pulse to the FPGA every cycle of the periodic pulse signal. If the FPGA can receive the pulse sent by the BMC within the first time period, it can be determined that the BMC firmware in the memory currently connected to the BMC is normal, otherwise, the BMC firmware is abnormal. Therefore, through the above settings, the BMC firmware can be fully monitored during the BMC running the BMC firmware.

[0072] Moreover, in the embodiment of the present application, by setting the first counter to record the duration, after the duration recorded by the first counter reaches the first duration, if the FPGA still has not received the pulse signal sent by the BMC, it is possible to promptly determine that the BMC firmware is abnormal, thereby improving the efficiency of determining the BMC firmware abnormality.

[0073] It should be noted that the first duration can be determined according to the period of the periodic pulse signal. For example, if the period of the periodic pulse signal is 10 seconds, the first duration can be set to 10 seconds, 11 seconds or 13 seconds.

[0074] In some embodiments, the FPGA also includes a second counter for recording duration. After the FPGA sends a reset signal to the BMC, the second counter is controlled to start timing. When the duration recorded by the second counter reaches the second duration, if the restart completion signal sent by the BMC is not received, it is determined that the BMC firmware in the current memory is abnormal, wherein the restart completion signal is a signal generated after the BMC loads the BMC firmware in the current memory and completes the restart.

[0075] Among them, after the BMC receives the reset signal, if the BMC firmware in the memory connected to the BMC is abnormal, the BMC may fail to restart. At this time, the BMC cannot generate a restart completion signal and send the restart completion signal to the FPGA through the second signal sending pin. If the BMC firmware in the memory connected to the BMC is normal, the BMC can successfully restart in a short time after receiving the reset signal, and send a restart completion signal to the FPGA through the second signal sending pin.

[0076] Therefore, in the embodiment of the present application, by setting a second counter for timing, when the duration recorded by the second counter reaches the second duration, if the FPGA does not receive the restart completion signal sent by the BMC, it is promptly determined that the BMC firmware in the memory connected to the BMC is abnormal, thereby improving the efficiency of determining the BMC firmware abnormality. The second duration can be set as needed, such as 120 seconds, 130 seconds or 150 seconds.

[0077] In order to better describe how the server provided in the embodiment of the present application monitors whether the BMC firmware is abnormal, Figure 2The following is a flow chart showing the process of the server monitoring whether the BMC firmware is abnormal according to the embodiment of the present application. Figure 2 As shown in the figure, the process of the server monitoring whether the BMC firmware is abnormal includes the following steps:

[0078] Step 101: The BMC loads and runs the BMC firmware in the first memory and performs initialization.

[0079] Step 102: The BMC determines whether initialization is completed. If not, go to step 101; if so, go to step 103.

[0080] Step 103: The BMC sends an initialization completion signal to the FPGA.

[0081] Step 104: The FPGA receives an initialization completion signal and waits for 30 seconds.

[0082] Step 105: The FPGA pulls down the reset signal sending pin (ie, sends a first signal to the BMC via the reset signal sending pin), and controls the first counter to start timing for 10 seconds.

[0083] Step 106: The BMC detects that the reset signal pin is at a low level.

[0084] Step 107: The BMC sends a pulse signal with a cycle of 10 seconds to the FPGA.

[0085] Step 108: FPGA determines whether a pulse signal is received within 10 seconds. If yes, go to step 109; if no, go to step 110.

[0086] Step 109: FPGA clears the first counter and then goes to step 105.

[0087] Step 110: The FPGA determines that the BMC firmware in the memory currently connected to the BMC is abnormal.

[0088] Step 111: The FPGA clears the first counter and sends a reset signal to the BMC, adds 1 to the second count value in the third register, and controls the second counter to start timing for 120 seconds.

[0089] Step 112: The BMC receives the reset signal and performs a reset.

[0090] Step 113: The BMC reset is completed and a restart completion signal is sent to the FPGA.

[0091] Step 114: FPGA determines whether it receives the restart completion signal within 120 seconds. If yes, go to step 115; if no, go to step 116.

[0092] Step 115: FPGA clears the second counter and the first register, and goes to step 106.

[0093] Step 116: The FPGA determines whether the first count value in the first register is less than a preset threshold value. If yes, go to step 117; if no, end this process.

[0094] Step 117: The FPGA determines that the BMC firmware in the current memory is abnormal, clears the second counter, sends a signal to the multiplexer, switches the BMC to connect with another memory, adds 1 to the second count value in the third register, sends a reset signal to the BMC, and goes to step 112.

[0095] Figure 3 The schematic diagram of the process of generating a first event log and a second event log provided by the server in the embodiment of the present application and sending the logs to the electronic device is shown. Figure 3 As shown, the process includes the following steps:

[0096] Step 201: BMC starts.

[0097] Step 202: BMC determines whether the startup is complete. If yes, go to step 203; if not, go to step 201.

[0098] Step 203: The BMC operates normally.

[0099] Step 204: The BMC determines whether the value in the second register is 0x1. If so, go to step 205; if not, go to step 206.

[0100] Step 205 : the BMC generates a first event log and clears the second register, wherein the first event log is that the BMC firmware fails and the memory is switched, and the process goes to step 211 .

[0101] Step 206: Determine whether the value in the third register is 0. If yes, go to step 208; if no, go to step 207.

[0102] Step 207: Record the value in the third register.

[0103] Step 208: The BMC obtains the value in the current third register through I2C.

[0104] Step 209: Determine whether the value in the third register currently obtained is increased compared with the value obtained last time. If yes, go to step 210, if no, end this process.

[0105] Step 210: The BMC generates a second event log according to the value in the third register, wherein the second event log is that the FPGA resets the BMC.

[0106] Step 211: The BMC sends the log to an electronic device that can receive BMC alarm information.

[0107] In the description provided herein, a large number of specific details are described. However, it is understood that the embodiments of the present application can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

[0108] Similarly, it should be understood that in order to streamline the present application and aid in understanding one or more of the various inventive aspects, in the above description of the exemplary embodiments of the present application, the various features of the embodiments of the present application are sometimes grouped together into a single embodiment, figure, or description thereof. However, this disclosed method should not be interpreted as reflecting the following intention: that the claimed application requires more features than those explicitly recited in each claim.

[0109] Those skilled in the art will appreciate that the modules in the devices in the embodiments may be adaptively changed and arranged in one or more devices different from the embodiments. The modules or units or components in the embodiments may be combined into one module or unit or component, and may be divided into a plurality of submodules or subunits or subcomponents. Except that at least some of such features and / or processes or units are mutually exclusive, all features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device disclosed in this manner may be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) may be replaced by an alternative feature providing the same, equivalent or similar purpose.

[0110] It should be noted that the above embodiments illustrate the present application rather than limit the present application, and that those skilled in the art may design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference symbol between brackets should not be constructed as a limitation to the claims. The word "comprising" does not exclude the presence of elements not listed in the claims. The word "one" or "an" preceding an element does not exclude the presence of multiple such elements. The present application may be implemented by means of hardware including several different elements and by means of a suitably programmed computer. In a unit claim that lists several devices, several of these devices may be embodied by the same hardware item. The use of the words first, second, and third, etc. does not indicate any order. These words may be interpreted as names.

Claims

1. A server, characterized in that: It includes a baseboard management controller BMC, a field programmable gate array FPGA, a multiplexer, a first memory and a second memory, wherein the first memory and the second memory store BMC firmware; The FPGA includes a first signal receiving pin, a pulse signal receiving pin, a reset signal sending pin and a first signal sending pin, which are respectively connected to the second signal sending pin, the pulse signal sending pin, the reset signal receiving pin and the second signal receiving pin of the BMC in a one-to-one correspondence; The FPGA also includes a chip select pin, and the chip select pin is connected to the control pin of the multiplexer; The BMC is used to connect to the first memory or the second memory through the multiplexer; wherein, When the BMC is connected to the first memory through the multiplexer, the BMC is used to load the BMC firmware in the first memory and generate an initialization completion signal after completing initialization, and send the initialization completion signal to the FPGA through the second signal sending pin; The FPGA is used for sending a first signal to the BMC through the first signal sending pin in response to receiving the initialization completion signal; The BMC is used for sending a pulse signal to the FPGA through the pulse signal sending pin in response to receiving the first signal; The FPGA is used to determine that the BMC firmware in the first memory is abnormal if the pulse signal is not received through the pulse signal receiving pin, and send a reset signal to the BMC through the reset signal sending pin; The BMC is used to receive the reset signal and perform a reset; The FPGA is used to send a first chip select signal to the multiplexer through the chip select pin if the BMC is reset abnormally, and send a reset signal to the BMC through the reset signal sending pin; The multiplexer is used for switching the BMC from being connected to the first memory to being connected to the second memory in response to receiving the first chip selection signal; The BMC is used to load and run the BMC firmware in the second memory in response to receiving the reset signal.

2. The server according to claim 1, characterized in that: The BMC is used to generate a second signal after loading and running the BMC firmware in the second memory and completing the restart, and send the second signal to the FPGA through the second signal sending pin; The FPGA is used to determine that the BMC firmware in the second memory is abnormal if the second signal is not received through the first signal receiving pin, send the second chip select signal to the multiplexer through the chip select pin, and send a reset signal to the BMC through the reset signal sending pin; The multiplexer is used for switching the BMC from being connected to the second memory to being connected to the first memory in response to receiving the second chip selection signal; The BMC is used to load and run the BMC firmware in the first memory in response to receiving the reset signal.

3. The server according to claim 2, characterized in that: The FPGA is configured to send the first signal to the BMC through the first signal sending pin in response to receiving the second signal through the first signal receiving pin; The BMC is used for sending a pulse signal to the FPGA through the pulse signal sending pin in response to receiving the first signal; The FPGA is used to determine that the BMC firmware in the second memory is abnormal if the pulse signal is not received through the pulse signal receiving pin.

4. The server according to claim 2, characterized in that: The FPGA further includes a first register, and the FPGA is further used for: After each execution of the step of sending the first chip select signal to the multiplexer through the chip select pin, adding 1 to the first count value in the first register, wherein the initial value of the first count value is 0; After each execution of the step of sending the second chip select signal to the multiplexer through the chip select pin, adding 1 to the first count value; If the first count value is greater than a preset threshold, the steps of sending the first chip select signal to the multiplexer through the chip select pin and sending the second chip select signal to the multiplexer through the chip select pin are stopped.

5. The server according to claim 1, characterized in that: The FPGA also includes a second register, and the FPGA is further used to: after executing the step of sending the first chip select signal to the multiplexer through the chip select pin, store the first value in the second register.

6. The server according to claim 5, characterized in that: The FPGA further includes a first data transmission pin, wherein the first data transmission pin is connected to a second data transmission pin of the BMC; The BMC is used to: when the BMC firmware stored in any one of the first memory and the second memory is normally operated, obtain the value in the second register through the second data transmission pin, if the obtained value is the first value, generate a first event log and send it to an electronic device that can receive BMC alarm information, and update the first value to an initial value through the second data pin, wherein the first event log indicates that the BMC firmware is invalid and the memory has been switched.

7. The server according to claim 2, characterized in that: The FPGA also includes a third register, and the FPGA is further used to add 1 to the second count value in the third register after executing the step of sending a reset signal to the BMC through the reset signal sending pin each time, wherein the initial value of the second count value is 0.

8. The server according to claim 7, characterized in that: The FPGA further includes a first data transmission pin, wherein the first data transmission pin is connected to a second data transmission pin of the BMC; The BMC is used to: when the BMC firmware stored in any one of the first memory and the second memory is normally operated, obtain the second count value in the third register through the second data transmission pin, and if the second count value currently obtained is greater than the second count value obtained last time, generate a second event log and send it to an electronic device that can receive BMC alarm information, wherein the second event log is the FPGA resetting the BMC.

9. The server according to claim 3, characterized in that: The memory currently connected to the BMC is a current memory, wherein the current memory is the first memory or the second memory; The pulse signal sent by the BMC is a periodic pulse signal, the FPGA further includes a first counter for recording duration, and the FPGA is further used for: After sending the first signal to the BMC, controlling the first counter to start timing; When the duration recorded by the first counter does not reach the first duration, if the pulse signal is received, the first counter is cleared and the process proceeds to the step of controlling the first counter to start timing, wherein the first duration is greater than or equal to the period of the periodic pulse signal; When the time length recorded by the first counter reaches the first time length, if the pulse signal is not received, it is determined that the BMC firmware in the current memory is abnormal.

10. The server according to claim 2, characterized in that: The memory currently connected to the BMC is a current memory, wherein the current memory is the first memory or the second memory; The FPGA also includes a second counter for recording duration, and the FPGA is further used for: After sending the reset signal to the BMC, controlling the second counter to start timing; When the duration recorded by the second counter reaches a second duration, if a restart completion signal sent by the BMC is not received, it is determined that the BMC firmware in the current memory is abnormal, wherein the restart completion signal is a signal generated after the BMC loads the BMC firmware in the current memory and completes the restart.

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