Detection device and method, processor and electronic equipment

Abstract

The embodiment of the invention discloses a detection device and method, a processor and electronic equipment, relates to the technical field of computers, and can effectively reduce the debugging cost of the processor and improve the debugging effect. The device comprises at least one state obtaining module, each state obtaining module is arranged in a processor core and corresponds to different functional parts in the processor core, and each state obtaining module is configured to obtain a preset part state signal in the corresponding functional part, the component state signal is sent to an error detection module; and the error detection module is arranged in the processor core, is respectively coupled with each state acquisition module, and is configured to receive each component state signal sent by each state acquisition module and perform error detection on the processor core according to each component state signal. The method can be used for processor debugging.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a detection device, method, processor and electronic equipment. Background Art

[0002] Currently, debugging of processor chips mostly requires the use of software or a debug bus, which is heavily dependent on the experience of debugging engineers and requires repeated iterations to determine the operating errors in the processor. In some cases, it is difficult to locate the errors. Therefore, the debugging cost of the processor is high, and the debugging effect is not ideal. Summary of the invention

[0003] In view of this, the embodiments of the present invention provide a detection device, method, processor and electronic device, which can effectively reduce the debugging cost of the processor and improve the debugging effect.

[0004] In a first aspect, an embodiment of the present invention provides a detection device, comprising: at least one state acquisition module, each of the state acquisition modules is arranged in a processor core and corresponds to a different functional component in the processor core, each of the state acquisition modules is configured to obtain a component state signal preset in the functional component corresponding to itself, and send the component state signal to an error detection module; the error detection module is arranged in the processor core and is respectively coupled to each of the state acquisition modules, and is configured to receive each of the component state signals sent by each of the state acquisition modules, and perform error detection on the processor core according to each of the component state signals.

[0005] In one embodiment, the functional components include one type of components, two types of components and three types of components; the error detection module includes: a first analysis submodule, a second analysis submodule, a third analysis submodule and a summary analysis submodule; the first analysis submodule is coupled with each of the state acquisition modules corresponding to the one type of components at one end and coupled with the summary analysis module at the other end, and is configured to perform a comprehensive analysis on each of the first state signals in the one type of components acquired by each of the state acquisition modules to obtain a first analysis result; wherein the one type of components includes at least one of the following: an instruction fetch unit, an instruction decoding unit and an instruction distribution unit; the second analysis submodule is coupled with each of the state acquisition modules corresponding to the two types of components at one end and coupled with the summary analysis module at the other end, and is configured to perform a comprehensive analysis on each of the first state signals in the one type of components acquired by each of the state acquisition modules to obtain a first analysis result. to perform a comprehensive analysis on each second state signal in the three types of components to obtain a second analysis result; wherein the two types of components include at least one of the following: a fixed-point execution unit, a floating-point execution unit, and an instruction release unit; the third analysis submodule is coupled at one end to each of the state acquisition modules corresponding to the three types of components, and is coupled at the other end to the summary analysis module, and is configured to perform a comprehensive analysis on each third state signal in the three types of components acquired by each of the state acquisition modules to obtain a third analysis result; wherein the three types of components include at least one of the following: a memory access execution unit, and a cache storage unit; the summary analysis submodule is coupled to the first analysis submodule, the second analysis submodule, and the third analysis submodule, respectively, and is configured to perform error detection on the processor core according to the first analysis result, the second analysis result, and the third analysis result.

[0006] In one embodiment, each first status signal in the first category of components includes at least one of the following: an error signal in the first category of components, a cache memory exception signal, an instruction fetch congestion signal, a pipeline status signal in the first category of components, an instruction decoding exception signal, a queue status signal in the first category of components, and a pointer status signal of the instruction distribution unit; each second status signal in the second category of components includes at least one of the following: an error signal in the second category of components, a queue status signal in the second category of components, a pipeline status signal in the second category of components, a pointer status signal of the instruction release unit, and a physical register stack status signal; each third status signal in the third category of components includes at least one of the following: an error signal in the third category of components, a cache memory exception signal, a data sending status signal of a peripheral device, a queue status signal of the memory access execution unit, and a pipeline status signal of the memory access execution unit.

[0007] In one embodiment, the first analysis submodule is further configured to, in response to the first analysis result indicating that the first category of components has an operation error, obtain first operation data of the first category of components, the first operation data including the virtual address of the operation instruction related to the operation error; and / or, the second analysis submodule is further configured to, in response to the second analysis result indicating that the second category of components has an operation error, obtain second operation data of the second category of components, the second operation data including the virtual address of the operation instruction related to the operation error; and / or, the third analysis submodule is further configured to, in response to the third analysis result indicating that the third category of components has an operation error, obtain third operation data of the third category of components, the third operation data including the virtual address of the operation instruction related to the operation error; the summary analysis submodule is configured to perform error detection on the processor core according to the first analysis result, the second analysis result, the third analysis result and the target operation data, wherein the target operation data includes at least one of the first operation data, the second operation data and the third operation data.

[0008] In one embodiment, the summary and analysis submodule is configured to: determine whether there is an operation error in the processor core based on the first analysis result, the second analysis result, the third analysis result and the target operation data; if there is an operation error in the processor core, determine the error information corresponding to the operation error, and the error information includes at least one of the following: the error type of the operation error, the functional component where the operation error is located, and the virtual address of the operation instruction related to the operation error.

[0009] In one embodiment, the summary and analysis submodule is configured to perform at least one of the following: determine the error type of the operation error based on the first analysis result, the second analysis result, and the third analysis result; determine the functional component where the operation error is located based on the source of each component status signal; determine the virtual address of the operation instruction related to the operation error based on the target operation data.

[0010] In one embodiment, the error detection module is configured to: determine whether there is an operation error in the processor core based on the status signals of each component; and when there is an operation error in the processor core, determine error information corresponding to the operation error, and the error information includes at least one of the following: the error type of the operation error and the functional component where the operation error is located.

[0011] In one embodiment, the detection device further includes: a repair control module, coupled to the error detection module, and configured to determine whether to perform error repair according to a preset control strategy in response to a detection result of the error detection module indicating that an error exists.

[0012] In one embodiment, the repair control module is also coupled to the instruction release unit in the functional component, and is configured to determine whether to instruct the instruction release unit to redirect the erroneous running instruction according to a preset control strategy in response to the detection result of the error detection module indicating the existence of an error.

[0013] In one embodiment, the control strategy includes: determining whether the number of error repairs for the current error is less than a preset number threshold; if the number of error repairs is less than the preset number threshold, determining to perform error repair; if the number of error repairs is greater than or equal to the preset number threshold, determining not to perform error repair.

[0014] In one embodiment, the repair control module is further configured to determine that the repair is successful and set the error repair count to 0 in response to the detection result of the error detection module being that there is no error.

[0015] In one embodiment, the repair control module is further configured to shut down the clock of the processor core without performing error repair, and report the detection result of the error detection and the repair status of the detection result.

[0016] In one embodiment, the repair control module is also configured to send an invalidation indication to the functional component corresponding to the register and / or the cache memory in response to the detection result of the error detection module that a bad point exists in the register and / or the cache memory, so that the functional component invalidates the register and / or cache line where the bad point is located.

[0017] In a second aspect, an embodiment of the present invention further provides a detection method applied to a processor core, the method comprising: respectively acquiring component status signals preset in different functional components in the processor core; and performing error detection on the processor core according to each of the component status signals.

[0018] In one embodiment, the functional components include one type of components, two types of components and three types of components; the error detection of the processor core according to the status signals of each of the components includes: comprehensively analyzing each first status signal in the one type of components to obtain a first analysis result; wherein the one type of components includes at least one of the following: an instruction fetch unit, an instruction decoding unit, and an instruction distribution unit; comprehensively analyzing each second status signal in the two types of components to obtain a second analysis result; wherein the two types of components include at least one of the following: a fixed-point execution unit, a floating-point execution unit, and an instruction release unit; comprehensively analyzing each third status signal in the three types of components to obtain a third analysis result; wherein the three types of components include at least one of the following: a memory access execution unit and a cache storage unit; based on the first analysis result, the second analysis result and the third analysis result, error detection is performed on the processor core.

[0019] In one embodiment, each first status signal in the first category of components includes at least one of the following: an error signal in the first category of components, a cache memory exception signal, an instruction fetch congestion signal, a pipeline status signal in the first category of components, an instruction decoding exception signal, a queue status signal in the first category of components, and a pointer status signal of the instruction distribution unit; each second status signal in the second category of components includes at least one of the following: an error signal in the second category of components, a queue status signal in the second category of components, a pipeline status signal in the second category of components, a pointer status signal of the instruction release unit, and a physical register stack status signal; each third status signal in the third category of components includes at least one of the following: an error signal in the third category of components, a cache memory exception signal, a data sending status signal of a peripheral device, a queue status signal of the memory access execution unit, and a pipeline status signal of the memory access execution unit.

[0020] In one embodiment, the method further includes: in response to the first analysis result being that the first type of component has an operation error, obtaining first operation data of the first type of component, the first operation data including the virtual address of the operation instruction related to the operation error; and / or, in response to the second analysis result being that the second type of component has an operation error, obtaining second operation data of the second type of component, the second operation data including the virtual address of the operation instruction related to the operation error; and / or, in response to the third analysis result being that the third type of component has an operation error, obtaining third operation data of the third type of component, the third operation data including the virtual address of the operation instruction related to the operation error; performing error detection on the processor core according to the first analysis result, the second analysis result and the third analysis result includes: performing error detection on the processor core according to the first analysis result, the second analysis result, the third analysis result and the target operation data, wherein the target operation data includes at least one of the first operation data, the second operation data and the third operation data.

[0021] In one embodiment, the error detection on the processor core based on the first analysis result, the second analysis result, the third analysis result and the target operation data includes: determining whether there is an operation error in the processor core based on the first analysis result, the second analysis result, the third analysis result and the target operation data; when there is an operation error in the processor core, determining error information corresponding to the operation error, the error information including at least one of the following: the error type of the operation error, the functional component where the operation error is located, and the virtual address of the operation instruction related to the operation error.

[0022] In one embodiment, when a runtime error exists in the processor core, determining the error information corresponding to the runtime error includes at least one of the following: determining the error type of the runtime error based on the first analysis result, the second analysis result, and the third analysis result; determining the functional component where the runtime error is located based on the source of each component status signal; and determining the virtual address of the runtime instruction related to the runtime error based on the target runtime data.

[0023] In one embodiment, the error detection of the processor core according to the component status signals includes: determining whether the processor core has an operation error according to the component status signals; and in the case that the processor core has an operation error, determining error information corresponding to the operation error, the error information including at least one of the following: the error type of the operation error and the functional component where the operation error is located.

[0024] In one embodiment, after performing error detection on the processor core according to each of the component status signals, the method further includes: in response to the detection result indicating that an error exists, determining whether to perform error repair according to a preset control strategy.

[0025] In one embodiment, in response to the detection result being an error, determining whether to perform error repair according to a preset control strategy includes: in response to the detection result being an error, determining whether to instruct a release unit in the functional component to redirect the operating instruction in which the error occurred according to a preset control strategy.

[0026] In one embodiment, the control strategy includes: determining whether the number of error repairs for the current error is less than a preset number threshold; if the number of error repairs is less than the preset number threshold, determining to perform error repair; if the number of error repairs is greater than or equal to the preset number threshold, determining not to perform error repair.

[0027] In one embodiment, the method further includes: in response to the detection result being that there is no error, determining that the repair is successful and setting the error repair count to 0.

[0028] In one embodiment, the method includes: when it is determined that no error repair is to be performed, shutting down the clock of the processor core, and reporting the detection result of the error and the repair status of the detection result.

[0029] In one embodiment, the method further includes: in response to the detection result that a bad pixel exists in the register and / or cache memory, sending an invalidation indication to the functional component corresponding to the register and / or the cache memory, so that the functional component invalidates the register and / or cache line where the bad pixel is located.

[0030] In a third aspect, an embodiment of the present invention further provides a processor, comprising: a detection device and at least one functional component, each of the functional components being respectively coupled to the detection device, wherein the detection device is any detection device provided by an embodiment of the present invention.

[0031] In a fourth aspect, an embodiment of the present invention further provides an electronic device, comprising a circuit board and a processor, wherein the processor is disposed on the circuit board, wherein the processor is any one of the processors provided in the embodiments of the present invention.

[0032] The detection device, method, processor and electronic device provided by the embodiment of the present invention include at least one state acquisition module, each state acquisition module is arranged in the processor core, and corresponds to different functional components in the processor core respectively, each state acquisition module is configured to acquire the component state signal preset in the functional component corresponding to itself, and send the component state signal to the error detection module; the error detection module is arranged in the processor core, coupled with each state acquisition module respectively, and configured to receive each component state signal sent by each state acquisition module, and perform error detection on the processor core according to each component state signal. Since the state acquisition module and the error detection module are both located in the processor core, the state signal acquisition and error detection can be automatically performed as the processor runs without manual debugging, so the debugging cost of the processor can be effectively reduced. In addition, since each state acquisition module corresponds to different functional components in the processor core respectively, in this way, after each state acquisition module acquires the component state signal preset in the corresponding functional component and sends it to the error detection module, the error detection module can distinguish which functional component each component state signal comes from, so as to facilitate the location of the detected error, so as to effectively improve the debugging effect while reducing the debugging cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0034] Figure 1 A schematic diagram of the structure of a detection device provided by an embodiment of the present invention; Figure 2 Another schematic diagram of the structure of a detection device provided by an embodiment of the present invention; Figure 3 A schematic diagram of another structure of a detection device provided by an embodiment of the present invention; Figure 4 A working flow chart of a detection device provided by an embodiment of the present invention; Figure 5 A flow chart of a detection method provided by an embodiment of the present invention; Figure 6 A schematic diagram of the structure of a processor provided by an embodiment of the present invention; Figure 7 A schematic structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0035] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0036] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0037] The technical solutions provided by the embodiments of the present invention are described in detail below.

[0038] In a first aspect, an embodiment of the present invention provides a detection device that can effectively reduce the debugging cost of a processor and improve the debugging effect.

[0039] like Figure 1 As shown, an embodiment of the present invention provides a detection device 1, comprising: At least one state acquisition module 11, each state acquisition module 11 is arranged in the processor core, and corresponds to different functional components 2 in the processor core respectively, each state acquisition module 11 is configured to obtain a component state signal preset in the functional component 2 corresponding to itself, and send the component state signal to the error detection module 12; The error detection module 12 is disposed in the processor core and is coupled to each state acquisition module 11 respectively. The error detection module 12 is configured to receive each component state signal sent by each state acquisition module 11 and perform error detection on the processor core according to each component state signal.

[0040] The detection device 1 provided in the embodiment of the present invention includes at least one state acquisition module 11, each state acquisition module 11 is arranged in the processor core, and corresponds to different functional components 2 in the processor core respectively, each state acquisition module 11 is configured to obtain the component state signal preset in the functional component 2 corresponding to itself, and send the component state signal to the error detection module 12; the error detection module 12 is arranged in the processor core, coupled with each state acquisition module 11 respectively, and is configured to receive each component state signal sent by each state acquisition module 11, and perform error detection on the processor core according to each component state signal. Since both the state acquisition module 11 and the error detection module 12 are located in the processor core, the state signal acquisition and error detection can be automatically performed as the processor runs without manual debugging, so the debugging cost of the processor can be effectively reduced. Furthermore, since each status acquisition module 11 corresponds to a different functional component 2 in the processor core, after each status acquisition module 11 obtains the preset component status signal in the corresponding functional component 2 and sends it to the error detection module 12, the error detection module 12 can distinguish which functional component 2 each component status signal comes from, thereby facilitating the positioning of the detected errors, and thus can effectively improve the debugging effect while reducing the debugging cost.

[0041] It should be noted that the error detection mentioned in the embodiments of the present invention is a broad term, which can include detecting errors as well as detecting abnormalities or situations worthy of attention, such as the pipeline executing instructions being in a livelock state, a deadlock state, etc.

[0042] In the embodiment of the present invention, each state acquisition module 11 corresponds to a different functional component 2 in the processor core, but the specific physical location of each state acquisition module 11 is not limited. For example, some state acquisition modules 11 can be set in the corresponding functional component 2, other state acquisition modules 11 can be set near the corresponding functional component 2, and some state acquisition modules 11 can be set at a position far away from the corresponding functional component 2, as long as the state acquisition module 11 can more conveniently obtain the component state signal of the corresponding functional component 2, for example, the state acquisition module 11 can be electrically connected to the corresponding functional component 2. Exemplarily, in one example, each state acquisition module 11 can be set in the corresponding functional component 2.

[0043] In one implementation, the detection device provided by the embodiment of the present invention can be set in the processor core and implemented by hardware. Specifically, the processor core may include a variety of functional components, and each functional component cooperates with each other to complete various processing operations. These functional components may include, for example: instruction fetch unit (IFU, Instruction Fetch Unit), instruction decoding unit (IDU, Instruction Decode Unit), instruction distribution unit (ISU, Instruction Issue Unit), fixed-point execution unit (EXU, Execute Unit), floating-point execution unit (FPU, Float Point Unit), instruction release unit (RTU, retire unit), memory access execution unit (LSU, Load Store Unit), cache storage unit (Cache), etc. Among them, the cache storage unit may include one or more levels, such as L1, L2, L3, etc.

[0044] In one embodiment of the present invention, the detection device 1 may include one or more state acquisition modules 11, and each state acquisition module 11 may be respectively set on different functional components 2 of the processor core. According to different specific detection requirements, for each functional component 2, one state acquisition module 11 may be set, or no state acquisition module 11 may be set. The embodiment of the present invention is not limited to this.

[0045] In a specific implementation, the state acquisition module 11 can collect the preset component state signals in the functional component 2 corresponding to itself. Since different functional components 2 have different structures and are used to implement different functions, they will have different component state signals. Based on this, the component state signals collected by each state acquisition module 11 are also different. For example, in one example, if the functional component 2 is an instruction fetch unit, the corresponding state acquisition module 11 can collect instruction fetch blocking signals, etc. In another example, if the functional component 2 is an instruction decoding unit, the corresponding state acquisition module 11 can collect instruction decoding exception signals, etc.

[0046] After each state acquisition module 11 acquires the component state signal, it can send the component state signal to the error detection module 12, so that the error detection module 12 uses the component state signal to perform error detection on the processor core. Specifically, in one embodiment of the present invention, the error detection module 12 can be configured to: determine whether the processor core has an operation error according to each component state signal; if the processor core has an operation error, determine the error information corresponding to the operation error, and the error information may include at least one of the following: the error type of the operation error, and the functional component 2 where the operation error is located. Among them, the error type of the operation error can be determined according to the signal value of each component state signal. For example, if the signal value corresponding to the instruction fetch blocking signal is "1" (high level), it can be determined that the processor core cannot fetch instructions continuously in the instruction fetch operation, and if the signal value of the instruction decoding exception signal is "1", it can be determined that the processor core may have a decoding error, etc. The functional component 2 where the operation error is located can be determined by the source of each component state signal. For example, if it is known that the instruction decoding exception signal comes from the instruction decoding unit, then if the signal value of the known instruction decoding exception signal is "1", it can be determined that the functional component 2 where the operation error is located is the instruction decoding unit.

[0047] Specifically, in one embodiment of the present invention, the functional components 2 in the processor core can be further classified according to different processing objects. For example, in one example, the functional components 2 can include one type of component, two type of component and three type of component. Among them, the one type of component can include various functional components that provide services for instruction content acquisition, such as instruction fetch unit, instruction decoding unit, instruction distribution unit, etc. The two type of components can include various functional components that provide services for instruction calculation, such as fixed-point execution unit, floating-point execution unit, instruction release unit, etc. The three type of components can include various functional components that provide services for memory access operations, such as memory access execution unit, cache storage unit, etc.

[0048] Corresponding to the classification of the first-class components, second-class components, third-class components, etc. included in each functional component 2, such as Figure 2 As shown, in one embodiment of the present invention, the error detection module 12 may include: a first analysis submodule 121, a second analysis submodule 122, a third analysis submodule 123, and a summary analysis submodule 124; the first analysis submodule 121 is coupled to each state acquisition module 11 corresponding to a type of component at one end, and is coupled to the summary analysis module 124 at the other end, and is configured to perform a comprehensive analysis on each first state signal in the type of component acquired by each state acquisition module 11 to obtain a first analysis result; wherein the type of component may include at least one of the following: an instruction fetch unit, an instruction decoding unit, and an instruction distribution unit; The second analysis submodule 122 is coupled at one end to each state acquisition module 11 corresponding to the second type of components, and at the other end to the summary analysis module 124, and is configured to perform a comprehensive analysis on each second state signal in the second type of components acquired by each state acquisition module 11 to obtain a second analysis result; wherein the second type of components includes at least one of the following: a fixed-point execution unit, a floating-point execution unit, and an instruction release unit; The third analysis submodule 123 is coupled at one end to the state acquisition modules 11 corresponding to the three types of components, and at the other end to the summary analysis module 124, and is configured to perform a comprehensive analysis on the third state signals of the three types of components acquired by the state acquisition modules 11 to obtain a third analysis result; wherein the three types of components include at least one of the following: a memory access execution unit, a cache storage unit; The summary analysis submodule 124 is coupled to the first analysis submodule 121, the second analysis submodule 122, and the third analysis submodule 123 respectively, and is configured to perform error detection on the processor core according to the first analysis result, the second analysis result, and the third analysis result.

[0049] It should be noted that, in the embodiment of the present invention, the first state signal, the second state signal and the third state signal are all component state signals preset in the functional component 2, wherein the first state signal is a component state signal generated by a type one component, the second state signal is a component state signal generated by a type two component, and the third state signal is a component state signal generated by a type three component.

[0050] In an embodiment of the present invention, since a class of components may include various functional components that provide services for instruction content acquisition, the first status signals generated by this class of components also mostly involve some hardware states in the instruction content acquisition process. For example, in one example, each first status signal in a class of components may include one or more of the following: an error signal in a class of components, a cache memory exception signal, an instruction fetch congestion signal, a pipeline status signal in a class of components, an instruction decoding exception signal, a queue status signal in a class of components, a pointer status signal of an instruction distribution unit, etc.

[0051] Similarly, since the second category components may include various functional components that provide services for instruction operations, the second status signals generated by this category of components also mostly involve some hardware states in the instruction operation process. For example, in one example, each second status signal in the second category components may include one or more of the following: an error signal in the second category component, a queue status signal in the second category component, a pipeline status signal in the second category component, a pointer status signal of the instruction release unit, a physical register stack status signal, etc.

[0052] By the same token, since the three categories of components may include various functional components that provide services for memory access operations, the third state signals generated by this type of components also mostly involve some hardware states in memory access operations. For example, in one example, each third state signal in the three categories of components may include one or more of the following: error signals in the three categories of components, cache memory exception signals, data transmission status signals of peripheral devices, queue status signals of memory access execution units, pipeline status signals of memory access execution units, etc.

[0053] Of course, according to debugging requirements, in other embodiments of the present invention, the first state signal, the second state signal and the third state signal may also include other signals, which is not limited in the embodiments of the present invention.

[0054] In the embodiment of the present invention, after the first analysis submodule 121 obtains the first state signal, it can analyze the first state signal to obtain the first analysis result. After the second analysis submodule 122 obtains the second state signal, it can analyze the second state signal to obtain the second analysis result. After the third analysis submodule 123 obtains the third state signal, it can analyze the third state signal to obtain the third analysis result. The summary analysis submodule 124 is coupled with the first analysis submodule 121, the second analysis submodule 122, and the third analysis submodule 123 respectively, so it can receive the first analysis result, the second analysis result, and the third analysis result respectively, and perform error detection on the processor core according to the first analysis result, the second analysis result, and the third analysis result. That is to say, the first analysis submodule 121, the second analysis submodule 122, and the third analysis submodule 123 can respectively use the signals obtained by themselves to perform preliminary analysis to obtain preliminary analysis results, and the summary analysis submodule 124 can summarize and analyze the analysis results obtained by the above preliminary analysis, so as to perform error detection on the processor core. Among them, the analysis results of each analysis submodule can preliminarily indicate whether there are errors in the component category corresponding to the analysis submodule. For example, the first analysis result can indicate whether there are errors in a type of component. The summary analysis submodule 124 can combine the first analysis result, the second analysis result and the third analysis result to perform error detection on the processor core. Since the processor core can run instructions based on the pipeline, and the type of component is generally located upstream of the pipeline, the type of component is generally located in the middle of the pipeline, and the type of component is generally located downstream of the pipeline, the instruction execution of these three types of components will affect each other, and any error in any type of component may affect the other two types of components. Therefore, error detection based on the first analysis result, the second analysis result and the third analysis result can make the detection conclusion more accurate and comprehensive.

[0055] In this embodiment, each analysis submodule can obtain its own analysis results, and the summary analysis submodule 124 can perform error detection on the processor core in combination with the analysis results, but the embodiments of the present invention are not limited to this. In other embodiments of the present invention, the summary analysis submodule 124 can also perform error detection in other ways.

[0056] For example, in one embodiment of the present invention, the first analysis submodule 121 can also be configured to obtain first operation data of the first category of components in response to the first analysis result that the first category of components has an operation error, the first operation data including the virtual address of the operation instruction related to the operation error; and / or, the second analysis submodule 122 can also be configured to obtain second operation data of the second category of components in response to the second analysis result that the second category of components has an operation error, the second operation data including the virtual address of the operation instruction related to the operation error; and / or, the third analysis submodule 123 can also be configured to obtain third operation data of the third category of components in response to the third analysis result that the third category of components has an operation error, the third operation data including the virtual address of the operation instruction related to the operation error. In one embodiment of the present invention, during the instruction execution process, once a certain functional component has an operation error, the corresponding analysis submodule can add a label to the erroneous instruction and obtain the virtual address of the instruction from the pipeline that executes the instruction.

[0057] Based on this, in one embodiment of the present invention, the summary analysis submodule 124 can be configured to perform error detection on the processor core according to the first analysis result, the second analysis result, the third analysis result and the target operation data, wherein the target operation data includes at least one of the first operation data, the second operation data and the third operation data. In this way, when performing error detection, the summary analysis submodule 124 can not only use the analysis results of each analysis submodule, but also use the virtual address of the operation instruction related to the operation error, so as to obtain a more accurate and specific detection conclusion. Among them, the operation instruction related to the operation error can refer to the instruction with operation error, that is, when processing which instruction, the pipeline has a processing error, for example, when fetching which instruction, the pipeline has an instruction fetch error, when decoding which instruction, the pipeline has a decoding error, when fetching which instruction, the pipeline has an operation error, etc.

[0058] Specifically, in one embodiment of the present invention, the summary and analysis submodule 124 can be configured to: determine whether there is an operation error in the processor core based on the first analysis result, the second analysis result, the third analysis result and the target operation data; when there is an operation error in the processor core, determine the error information corresponding to the operation error, and the error information includes at least one of the following: the error type of the operation error, the functional component where the operation error is located, and the virtual address of the operation instruction related to the operation error.

[0059] In one implementation, when there is an operation error in the processor core, the summary analysis submodule 124 may be configured to perform one or more of the following to determine error information corresponding to the operation error: The error type of the operation error is determined based on the first analysis result, the second analysis result, and the third analysis result; for example, if the first analysis result is an instruction decoding error, the second analysis result is no error, and the third analysis result is no error, then it can be determined that the error type of the operation error of the processor core is an instruction decoding error.

[0060] According to the source of each component status signal, the functional component where the operation error is located is determined; for example, if the component status signal where the error occurs is an instruction decoding error signal, and the instruction decoding error signal comes from the instruction decoding unit, then it can be determined that the functional component 2 where the operation error is located is the instruction decoding unit.

[0061] According to the target operation data, the virtual address of the operation instruction related to the operation error is determined. For example, if the target operation data is A, it can be determined that the virtual address of the operation instruction related to the operation error is also A.

[0062] In the aforementioned embodiment, the detection device provided by the embodiment of the present invention can detect whether there is an operation error in the processor core, but the embodiment of the present invention is not limited to this. In another embodiment of the present invention, the detection device can also attempt to repair the detected operation error.

[0063] Specifically, if Figure 3As shown, in one embodiment, the detection device provided by the embodiment of the present invention may also include: a repair control module 13, coupled with the error detection module 12, configured to determine whether to perform error repair according to a preset control strategy in response to the detection result of the error detection module 12 that there is an error. In a specific implementation, the repair control module 13 is also coupled with the instruction release unit in the functional component 2, and is configured to determine whether to instruct the instruction release unit to redirect the running instruction in which the error occurs according to a preset control strategy in response to the detection result of the error detection module 12 that there is an error. In the case of redirecting the running instruction in which the error occurs, the virtual address of the running instruction in which the error occurs can be obtained from the instruction release unit, and the virtual address can be reloaded into the program counter (PC, program counter) so as to re-execute the running instruction in which the error occurs. During the redirection process, the data in the internal pipeline of the processor will be flushed, and the processor can restart to try to execute the instruction in which the error occurs (i.e., the instruction in the PC). Since the circuit state may change when the instruction is re-executed, the circuit state that once caused the error is likely to no longer exist, so the instruction can be executed correctly, thereby achieving the effect of repairing the error. After the repair is successful, the processor can return to the normal processing flow and continue to work. By repairing the operation error, the detection device provided by the embodiment of the present invention can effectively improve the fault tolerance and reliability of the processor core and greatly improve the post-silicon yield of the processor.

[0064] Exemplarily, in one example, the control strategy may include: determining whether the number of error repairs for the current error is less than a preset number threshold; determining to perform error repair if the number of error repairs is less than the preset number threshold; determining not to perform error repair if the number of error repairs is greater than or equal to the preset number threshold. The preset number threshold may be set or adjusted as needed, for example, 5 times, 10 times, 20 times, etc. That is, an upper limit may be set for the number of repairs. If the number of repairs has not reached the upper limit, it means that the number of attempts to repair is not enough, so the repair may continue to be attempted. If the number of repairs has reached the upper limit, it means that the error is difficult to be successfully repaired in this way, so the repair may be abandoned. In one example, a repair permission flag may be set to indicate whether error repair is allowed. For example, the repair permission flag is 1, indicating that error repair is allowed, and the repair permission flag is 0, indicating that error repair is not allowed. In the case of allowing error repair, an error repair may be performed each time an error occurs, and the number of repairs is increased by 1. In the case of not allowing error repair, even if an error occurs, error repair is not performed. If no error occurs, the status detection of each functional component 2 may continue.

[0065] In a specific implementation, the repair control module 13 is also configured to turn off the clock of the processor core without performing error repair, and report the detection result of the error detection and the repair of the detection result. Among them, the detection result and the repair of the detection result can be saved in advance through a register or static memory. In this way, after turning off the clock of the processor core, the error scene is retained for subsequent viewing. Reporting the detection result of the error detection and the repair of the detection result can provide valuable debugging information for engineers, which is conducive to the repair of errors.

[0066] After the error repair, the execution of the instruction no longer has a running error. Based on this, in one embodiment, the repair control module 13 can also be configured to determine that the repair is successful and set the error repair count to 0 in response to the detection result of the error detection module 12 that there is no error. In this way, if a running error occurs again when other instructions are subsequently executed, the error repair count can be re-counted for the other instructions instead of accumulating the error repair counts of different instructions, thereby ensuring the correctness and rationality of the repair decision.

[0067] Furthermore, in an embodiment of the present invention, in addition to performing error repair through instruction redirection, the repair control module 13 can also be implemented in other ways. For example, in one embodiment, the repair control module 13 can also be configured to respond to the detection result of the error detection module 12 that there is a bad point in the register and / or cache memory, and send an invalidation indication to the functional component corresponding to the register and / or the cache memory (such as a static random access memory), so that the functional component invalidates the register and / or cache line where the bad point is located. For example, in one example, the cache line in the cache memory can be invalidated through a special register bus (SRB). In this way, the register and / or cache line where the bad point is located will no longer be used when subsequent instructions are executed, thereby effectively avoiding the resulting operation errors.

[0068] Exemplarily, a workflow of a detection device can be as follows Figure 4 shown.

[0069] In a second aspect, corresponding to the aforementioned detection device, an embodiment of the present invention further provides a detection method, which can effectively reduce the debugging cost of the processor and improve the debugging effect.

[0070] like Figure 5 As shown, the detection method provided by the embodiment of the present invention is applied to a processor core, and the method may include: S31, respectively obtaining component status signals preset in different functional components in the processor core; S32, performing error detection on the processor core according to each of the component status signals.

[0071] The detection method provided by the embodiment of the present invention is applied to the processor core, and can respectively obtain the component status signals preset in different functional components in the processor core, and perform error detection on the processor core according to each of the component status signals. Since the method is applied to the processor core, the status signal acquisition and error detection can be automatically performed as the processor runs without manual debugging, so the debugging cost of the processor can be effectively reduced. Since the component status signals preset in each functional component in the processor core can be obtained respectively, it is possible to distinguish which functional component each component status signal comes from, so as to facilitate the location of the detected error, so that the debugging effect can be effectively improved while reducing the debugging cost.

[0072] In one embodiment, the functional components include one type of components, two types of components and three types of components; the error detection of the processor core according to the status signals of each of the components includes: comprehensively analyzing each first status signal in the one type of components to obtain a first analysis result; wherein the one type of components includes at least one of the following: an instruction fetch unit, an instruction decoding unit, and an instruction distribution unit; comprehensively analyzing each second status signal in the two types of components to obtain a second analysis result; wherein the two types of components include at least one of the following: a fixed-point execution unit, a floating-point execution unit, and an instruction release unit; comprehensively analyzing each third status signal in the three types of components to obtain a third analysis result; wherein the three types of components include at least one of the following: a memory access execution unit and a cache storage unit; based on the first analysis result, the second analysis result and the third analysis result, error detection is performed on the processor core.

[0073] In one embodiment, each first status signal in the first category of components includes at least one of the following: an error signal in the first category of components, a cache memory exception signal, an instruction fetch congestion signal, a pipeline status signal in the first category of components, an instruction decoding exception signal, a queue status signal in the first category of components, and a pointer status signal of the instruction distribution unit; each second status signal in the second category of components includes at least one of the following: an error signal in the second category of components, a queue status signal in the second category of components, a pipeline status signal in the second category of components, a pointer status signal of the instruction release unit, and a physical register stack status signal; each third status signal in the third category of components includes at least one of the following: an error signal in the third category of components, a cache memory exception signal, a data sending status signal of a peripheral device, a queue status signal of the memory access execution unit, and a pipeline status signal of the memory access execution unit.

[0074] In one embodiment, the method further includes: in response to the first analysis result being that the first type of component has an operation error, obtaining first operation data of the first type of component, the first operation data including the virtual address of the operation instruction related to the operation error; and / or, in response to the second analysis result being that the second type of component has an operation error, obtaining second operation data of the second type of component, the second operation data including the virtual address of the operation instruction related to the operation error; and / or, in response to the third analysis result being that the third type of component has an operation error, obtaining third operation data of the third type of component, the third operation data including the virtual address of the operation instruction related to the operation error; performing error detection on the processor core according to the first analysis result, the second analysis result and the third analysis result includes: performing error detection on the processor core according to the first analysis result, the second analysis result, the third analysis result and the target operation data, wherein the target operation data includes at least one of the first operation data, the second operation data and the third operation data.

[0075] In one embodiment, the error detection on the processor core based on the first analysis result, the second analysis result, the third analysis result and the target operation data includes: determining whether there is an operation error in the processor core based on the first analysis result, the second analysis result, the third analysis result and the target operation data; when there is an operation error in the processor core, determining error information corresponding to the operation error, the error information including at least one of the following: the error type of the operation error, the functional component where the operation error is located, and the virtual address of the operation instruction related to the operation error.

[0076] In one embodiment, when a runtime error exists in the processor core, determining the error information corresponding to the runtime error includes at least one of the following: determining the error type of the runtime error based on the first analysis result, the second analysis result, and the third analysis result; determining the functional component where the runtime error is located based on the source of each component status signal; and determining the virtual address of the runtime instruction related to the runtime error based on the target runtime data.

[0077] In one embodiment, the error detection of the processor core according to the component status signals includes: determining whether the processor core has an operation error according to the component status signals; and in the case that the processor core has an operation error, determining error information corresponding to the operation error, the error information including at least one of the following: the error type of the operation error and the functional component where the operation error is located.

[0078] In one embodiment, after performing error detection on the processor core according to each of the component status signals, the method further includes: in response to the detection result indicating that an error exists, determining whether to perform error repair according to a preset control strategy.

[0079] In one embodiment, in response to the detection result being an error, determining whether to perform error repair according to a preset control strategy includes: in response to the detection result being an error, determining whether to instruct a release unit in the functional component to redirect the operating instruction in which the error occurred according to a preset control strategy.

[0080] In one embodiment, the control strategy includes: determining whether the number of error repairs for the current error is less than a preset number threshold; if the number of error repairs is less than the preset number threshold, determining to perform error repair; if the number of error repairs is greater than or equal to the preset number threshold, determining not to perform error repair.

[0081] In one embodiment, the method further includes: in response to the detection result being that there is no error, determining that the repair is successful and setting the error repair count to 0.

[0082] In one embodiment, the method includes: when it is determined that no error repair is to be performed, shutting down the clock of the processor core, and reporting the detection result of the error and the repair status of the detection result.

[0083] In one embodiment, the method further includes: in response to the detection result that a bad pixel exists in the register and / or cache memory, sending an invalidation indication to the functional component corresponding to the register and / or the cache memory, so that the functional component invalidates the register and / or cache line where the bad pixel is located.

[0084] Thirdly, Figure 6 As shown, an embodiment of the present invention further provides a processor 62, the processor 62 includes: a detection device 1 and at least one functional component 2, each functional component 2 is coupled to the detection device 1, wherein the detection device 1 is any one of the detection devices 1 provided in the above embodiments. Since the processor provided in the embodiment of the present invention includes any one of the detection devices 1 provided in the above embodiments, the corresponding beneficial technical effects can also be achieved, which have been described in detail above and will not be repeated here.

[0085] Fourthly, Figure 7As shown, an embodiment of the present invention further provides an electronic device 6, which includes a circuit board 61 and a processor 62. The processor 62 is arranged on the circuit board 61. The processor 62 is any processor 62 provided in the aforementioned embodiments, and therefore can also achieve corresponding beneficial technical effects, which have been described in detail above and will not be repeated here.

[0086] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0087] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0088] In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0089] For the convenience of description, the above device is described by dividing the functions into various units / modules. Of course, when implementing the present invention, the functions of each unit / module can be implemented in the same or multiple software and / or hardware.

[0090] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. The storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0091] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A detection device, It is characterized in that include: at least one state acquisition module, each of which is arranged in the processor core and corresponds to a different functional component in the processor core, each of which is configured to acquire a component state signal preset in the functional component corresponding to itself and send the component state signal to the error detection module; The error detection module is arranged in the processor core, coupled with each of the status acquisition modules respectively, and configured to receive each of the component status signals sent by each of the status acquisition modules, and perform error detection on the processor core according to each of the component status signals.

2. The detection device according to claim 1, It is characterized in that The functional components include first-class components, second-class components and third-class components; the error detection module includes: a first analysis submodule, a second analysis submodule, a third analysis submodule and a summary analysis submodule; The first analysis submodule is coupled at one end to each of the state acquisition modules corresponding to the first type of components, and at the other end to the summary analysis module, and is configured to perform a comprehensive analysis on each of the first state signals in the first type of components acquired by each of the state acquisition modules to obtain a first analysis result; wherein the first type of components includes at least one of the following: an instruction fetch unit, an instruction decoding unit, and an instruction distribution unit; The second analysis submodule is coupled at one end to each of the state acquisition modules corresponding to the two types of components, and at the other end to the summary analysis module, and is configured to perform a comprehensive analysis on each of the second state signals in the two types of components acquired by each of the state acquisition modules to obtain a second analysis result; wherein the two types of components include at least one of the following: a fixed-point execution unit, a floating-point execution unit, and an instruction release unit; The third analysis submodule is coupled with each of the state acquisition modules corresponding to the three types of components at one end and coupled with the summary analysis module at the other end, and is configured to comprehensively analyze each of the third state signals in the three types of components acquired by each of the state acquisition modules to obtain a third analysis result; wherein the three types of components include at least one of the following: a memory access execution unit and a cache storage unit; The summary analysis submodule is coupled to the first analysis submodule, the second analysis submodule, and the third analysis submodule respectively, and is configured to perform error detection on the processor core according to the first analysis result, the second analysis result, and the third analysis result.

3. The detection device according to claim 2, It is characterized in that Each first status signal in the type of components includes at least one of the following: Error signal in the said type of component, cache memory abnormality signal, instruction fetch blocking signal, pipeline status signal in the said type of component, instruction decoding abnormality signal, queue status signal in the said type of component, pointer status signal of the said instruction dispatch unit; Each second state signal in the second type of components includes at least one of the following: The error signal in the second type of component, the queue status signal in the second type of component, the pipeline status signal in the second type of component, the pointer status signal of the instruction release unit, and the physical register stack status signal; Each third status signal in the three types of components includes at least one of the following: The three types of components include error signals, cache memory exception signals, data transmission status signals of peripheral devices, queue status signals of the memory access execution unit, and pipeline status signals of the memory access execution unit.

4. The detection device according to claim 2, It is characterized in that The first analysis submodule is further configured to, in response to the first analysis result indicating that the first type of component has an operation error, obtain first operation data of the first type of component, wherein the first operation data includes a virtual address of an operation instruction related to the operation error; and / or, The second analysis submodule is further configured to, in response to the second analysis result indicating that the second type of component has an operation error, obtain second operation data of the second type of component, wherein the second operation data includes a virtual address of an operation instruction related to the operation error; and / or, The third analysis submodule is further configured to, in response to the third analysis result indicating that the three types of components have operation errors, obtain third operation data of the three types of components, wherein the third operation data includes a virtual address of an operation instruction related to the operation error; The summary analysis submodule is configured to perform error detection on the processor core based on the first analysis result, the second analysis result, the third analysis result and target operation data, wherein the target operation data includes at least one of the first operation data, the second operation data and the third operation data.

5. The detection device according to claim 4, It is characterized in that The summary analysis submodule is configured as follows: Determining whether the processor core has an operation error according to the first analysis result, the second analysis result, the third analysis result and the target operation data; In the event that a running error exists in the processor core, error information corresponding to the running error is determined, the error information including at least one of the following: an error type of the running error, the functional component where the running error is located, and a virtual address of a running instruction related to the running error.

6. The detection device according to claim 5, It is characterized in that The summary analysis submodule is configured to perform at least one of the following: Determining an error type of the operation error according to the first analysis result, the second analysis result, and the third analysis result; Determining the functional component where the operation error is located according to the source of each component status signal; A virtual address of an operation instruction related to the operation error is determined according to the target operation data.

7. The detection device according to claim 1, It is characterized in that The error detection module is configured as follows: determining, according to each of the component status signals, whether the processor core has an operation error; In the case that an operation error occurs in the processor core, error information corresponding to the operation error is determined, where the error information includes at least one of the following: an error type of the operation error and the functional component where the operation error occurs.

8. The detection device according to any one of claims 1 to 7, It is characterized in that The detection device also includes: The repair control module is coupled to the error detection module and is configured to determine whether to perform error repair according to a preset control strategy in response to a detection result of the error detection module indicating that an error exists.

9. The detection device according to claim 8, It is characterized in that The repair control module is also coupled to the instruction release unit in the functional component, and is configured to determine whether to instruct the instruction release unit to redirect the running instruction in which the error occurs according to a preset control strategy in response to the detection result of the error detection module indicating that an error exists.

10. The detection device according to claim 8, It is characterized in that The control strategy includes: Determine whether the number of error repairs for the current error is less than a preset number threshold; When the number of error repairs is less than the preset number threshold, determining to perform error repair; When the number of error repairs is greater than or equal to the preset number threshold, it is determined not to perform error repair.

11. The detection device according to claim 10, It is characterized in that The repair control module is further configured to determine that the repair is successful and set the error repair times to 0 in response to the detection result of the error detection module that there is no error.

12. The detection device according to claim 10, It is characterized in that The repair control module is further configured to shut down the clock of the processor core without performing error repair, and report the detection result of the error detection and the repair status of the detection result.

13. The detection device according to claim 8, It is characterized in that The repair control module is also configured to send an invalidation indication to the functional component corresponding to the register and / or the cache memory in response to the detection result of the error detection module that a bad point exists in the register and / or the cache memory, so that the functional component invalidates the register and / or cache line where the bad point is located.

14. A detection method, It is characterized in that Applied to a processor core, the method comprises: Respectively obtaining component status signals preset in different functional components in the processor core; Error detection is performed on the processor core according to each of the component status signals.

15. The detection method according to claim 14, It is characterized in that The functional components include first-class components, second-class components and third-class components; The performing error detection on the processor core according to each of the component status signals comprises: Performing a comprehensive analysis on each first state signal in the first type of components to obtain a first analysis result; wherein the first type of components includes at least one of the following: an instruction fetch unit, an instruction decoding unit, and an instruction dispatch unit; Performing a comprehensive analysis on each second state signal in the two types of components to obtain a second analysis result; wherein the two types of components include at least one of the following: a fixed-point execution unit, a floating-point execution unit, and an instruction release unit; Performing a comprehensive analysis on each third state signal in the three types of components to obtain a third analysis result; wherein the three types of components include at least one of the following: a memory access execution unit, a cache storage unit; Error detection is performed on the processor core according to the first analysis result, the second analysis result, and the third analysis result.

16. The detection method according to claim 15, It is characterized in that Each first status signal in the type of components includes at least one of the following: Error signal in the said type of component, cache memory abnormality signal, instruction fetch blocking signal, pipeline status signal in the said type of component, instruction decoding abnormality signal, queue status signal in the said type of component, pointer status signal of the said instruction dispatch unit; Each second state signal in the second type of components includes at least one of the following: The error signal in the second type of component, the queue status signal in the second type of component, the pipeline status signal in the second type of component, the pointer status signal of the instruction release unit, and the physical register stack status signal; Each third status signal in the three types of components includes at least one of the following: The three types of components include error signals, cache memory exception signals, data transmission status signals of peripheral devices, queue status signals of the memory access execution unit, and pipeline status signals of the memory access execution unit.

17. The detection method according to claim 15, It is characterized in that The method further comprises: In response to the first analysis result indicating that the first type of component has an operation error, acquiring first operation data of the first type of component, wherein the first operation data includes a virtual address of an operation instruction related to the operation error; and / or, In response to the second analysis result indicating that the second type of component has an operation error, obtaining second operation data of the second type of component, wherein the second operation data includes a virtual address of an operation instruction related to the operation error; and / or, In response to the third analysis result indicating that the three types of components have operation errors, obtaining third operation data of the three types of components, wherein the third operation data includes virtual addresses of operation instructions related to the operation errors; The performing error detection on the processor core according to the first analysis result, the second analysis result and the third analysis result comprises: Error detection is performed on the processor core according to the first analysis result, the second analysis result, the third analysis result and target operation data, wherein the target operation data includes at least one of the first operation data, the second operation data and the third operation data.

18. The detection method according to claim 17, It is characterized in that The performing error detection on the processor core according to the first analysis result, the second analysis result, the third analysis result and the target operation data comprises: Determining whether the processor core has an operation error according to the first analysis result, the second analysis result, the third analysis result and the target operation data; In the event that a running error exists in the processor core, error information corresponding to the running error is determined, the error information including at least one of the following: an error type of the running error, the functional component where the running error is located, and a virtual address of a running instruction related to the running error.

19. The detection method according to claim 18, It is characterized in that When there is an operation error in the processor core, determining error information corresponding to the operation error includes at least one of the following: Determining an error type of the operation error according to the first analysis result, the second analysis result, and the third analysis result; Determining the functional component where the operation error is located according to the source of each component status signal; A virtual address of an operation instruction related to the operation error is determined according to the target operation data.

20. The detection method according to claim 14, It is characterized in that The performing error detection on the processor core according to each of the component status signals comprises: determining, according to each of the component status signals, whether the processor core has an operation error; In the case that an operation error occurs in the processor core, error information corresponding to the operation error is determined, where the error information includes at least one of the following: an error type of the operation error and the functional component where the operation error occurs.

21. The detection method according to any one of claims 14 to 20, It is characterized in that After performing error detection on the processor core according to the component status signals, the method further includes: in response to the detection result indicating that an error exists, determining whether to perform error repair according to a preset control strategy.

22. The detection method according to claim 21, It is characterized in that In response to the detection result being an error, determining whether to perform error repair according to a preset control strategy includes: in response to the detection result being an error, determining whether to instruct a release unit in the functional component to redirect the operating instruction in which the error occurred according to a preset control strategy.

23. The detection method according to claim 21, It is characterized in that The control strategy includes: Determine whether the number of error repairs for the current error is less than a preset number threshold; When the number of error repairs is less than the preset number threshold, determining to perform error repair; When the number of error repairs is greater than or equal to the preset number threshold, it is determined not to perform error repair.

24. The detection method according to claim 23, It is characterized in that The method further includes: in response to the detection result being that there is no error, determining that the repair is successful and setting the error repair count to 0.

25. The detection method according to claim 23, It is characterized in that The method comprises: when it is determined that no error repair is to be performed, shutting down the clock of the processor core, and reporting the detection result of the error detection and the repair status of the detection result.

26. The detection method according to claim 21, It is characterized in that The method further includes: in response to the detection result that a bad pixel exists in the register and / or cache memory, sending an invalidation indication to the functional component corresponding to the register and / or cache memory, so that the functional component invalidates the register and / or cache line where the bad pixel is located.

27. A processor, It is characterized in that The processor comprises: a detection device and at least one functional component, each of the functional components is respectively coupled to the detection device, wherein the detection device is the detection device according to any one of claims 1 to 13.

28. An electronic device, It is characterized in that The electronic device includes a circuit board and a processor, and the processor is arranged on the circuit board, wherein the processor is the processor described in claim 27.

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