Fingerprint chip and function implementation method thereof

Abstract

The invention relates to the technical field of chips, in particular to a fingerprint chip and a function implementation method thereof.The fingerprint chip reads a register through an SPI interface, receives a scanning instruction sent by an upper computer and conducts scanning based on the scanning instruction, and the fingerprint chip further outputs touch picture data generated through scanning through the SPI interface or a DSPI interface; the SPI interface and the DSPI interface are distinguished according to different communication protocols; and reading and writing the AFE register by using 16-bit data with a 16-bit address or acquiring picture data through an SPI (Serial Peripheral Interface), and reading and writing the SFR general register by using 8-bit data with a 8-bit address. The upper computer sends a control instruction through the SPI interface to start scanning, touch picture data are generated, and corresponding picture data are output through the SPI interface or the DSPI interface based on different communication protocols, so that fingerprint images are quickly and accurately acquired.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a fingerprint chip and a method for realizing its functions. Background Art

[0002] With the continuous development of communication technology and electronic technology, more and more terminal devices have added fingerprint recognition functions. The fingerprint recognition function is realized by adding a fingerprint chip and a fingerprint recognition program matching the fingerprint chip to the terminal device. In the terminal device, the fingerprint chip needs to be initialized to realize the fingerprint recognition function. With the large increase in the demand for fingerprint recognition chips in mobile devices, the demand for the production and testing capacity of fingerprint recognition chips has also increased significantly. Fingerprint chips from different manufacturers are different, and the current fingerprint chips have low accuracy and are prone to errors in fingerprint image recognition. Summary of the invention

[0003] In view of this, an object of the present invention is to provide a fingerprint chip and a method for realizing its functions.

[0004] In the first aspect, an embodiment of the present invention provides a fingerprint chip, which reads a register through an SPI interface, receives a scanning instruction sent by a host computer and scans based on the scanning instruction, and the fingerprint chip also outputs touch image data generated by the scan through an SPI interface or a DSPI interface; the communication protocol corresponding to the SPI interface and the DSPI interface is different; the AFE register is read and written with 16-bit address and 16-bit data or the image data is obtained through the SPI interface, and the SFR general register is read and written with 8-bit address and 8-bit data.

[0005] In combination with the first aspect, the fingerprint chip also includes:

[0006] A timing generator is used to generate the timing instructions required for the operation of the analog dfe_ctrl AFE module;

[0007] ADC module, used to obtain the analog signal of the scanned fingerprint chip according to the timing instruction and convert the analog signal into a digital signal. There are multiple ADC modules;

[0008] dfe_ctrl AFE control module, used to receive digital signals input by multiple ADC modules and perform data processing according to timing instructions;

[0009] The FIFO unit is used to store processed fingerprint data.

[0010] In combination with the first aspect, it also includes:

[0011] The data processing module is connected to the dfe_ctrl AFE control module and the timing generator. The data processing module is used to process the data of the dfe_ctrl AFE control module and transmit it to the dp_ctrl display processing module for further processing according to preset rules and feedback to the timing generator.

[0012] In combination with the first aspect, it also includes:

[0013] The lp_controller low-power control module enters the FP_STOPPED state and then the FP_IDLE state after receiving the scan_end scan end signal from the dp_ctrl display processing module; after receiving the low-power sleep signal set by the register, it enters the FP_LOW_SLEEP / FP_DEEP_SLEEP state.

[0014] In a second aspect, the present application provides a method for realizing the functions of a fingerprint chip, which is applied to the fingerprint chip as described above; the method comprises:

[0015] The timing generator generates the timing required for the dfe_ctrl AFE control module to work;

[0016] Based on the timing, the dfe_ctrl AFE control module collects the data sent by multiple ADC modules one by one and stores them in the FIFO unit after data processing for acquisition by the SPI interface or DSPI interface.

[0017] In combination with the second aspect, based on the timing, the dfe_ctrl AFE control module collects the data sent by the multiple ADC modules one by one and stores them in the FIFO unit after data processing for the SPI interface or the DSPI interface to obtain the step, which also includes:

[0018] According to the preset enabling rule, an adc_en ADC enabling control signal is generated to determine the target ADC module to be enabled;

[0019] Based on the timing, adc_en ADC enable control signal and preset data reading rules, the dp_ctrl display processing module receives the data sent by the target ADC module and processes the data;

[0020] Send the scanned data processed by the dfe_ctrl AFE control module to the dp_ctrl display processing module for further processing;

[0021] The scanned data processed by the dp_ctrl display processing module is sorted, transmitted and stored in the FIFO unit.

[0022] In combination with the second aspect, the step of sending the scanned data processed by the dfe_ctrl AFE control module to the dp_ctrl display processing module for reprocessing includes:

[0023] Get the preset cumulative number of times;

[0024] Based on the cumulative number of times, the data processing volume of the cumulative processing is calculated;

[0025] After reaching the cumulative number of times, the cumulative average and base subtraction processing are performed.

[0026] In combination with the second aspect, the step of sorting and transmitting the processed scan data to the FIFO unit and storing the processed scan data includes:

[0027] Controlling the sortable FIFO unit to determine a read processing mode according to the ADC module range and the RX_SEL range; the read processing mode includes sorted storage reading or unsorted storage reading;

[0028] Get the speed at which the host computer reads data, based on whether the FIFO is full;

[0029] If the speed is less than the data generation speed of the FIFO unit;

[0030] The control timing generator generates a pause timing instruction to send a pause instruction to the dfe_ctrl AFE control module until the data in the FIFO unit is read out.

[0031] In conjunction with the second aspect, the method further includes:

[0032] In the default FP_IDLE idle state, if the dp_ctrl display processing module receives the scan_start scan start signal, it enters the FP_RUNNING scanning state;

[0033] If the scan_end scan end signal is received, the scan stop state is entered. At the same time, the host computer reads the data in the FIFO unit through the SPI interface or DSPI interface.

[0034] In conjunction with the second aspect, the method includes:

[0035] In the FP_IDLE idle state, if the dp_ctrl display processing module receives a low-power sleep signal, it enters the FP_LOW_SLEEP state and turns off the main clock of CLK_24M.

[0036] After that, if a wake-up signal or a reset signal is received, the FP_IDLE idle state is restored;

[0037] If the host computer (MCU) also sets the clk_32koff instruction signal through the SPI when entering sleep mode, the FP_DEEP_SLEEP state is entered and the 32KHz clock is turned off.

[0038] The embodiments of the present invention bring the following beneficial effects: the fingerprint chip and its implementation method provided by the present application, the fingerprint chip reads the register through the SPI interface, receives the scanning instruction sent by the host computer and scans based on the scanning instruction, and the fingerprint chip also outputs the touch image data generated by the scan through the SPI interface or the DSPI interface; the communication protocols corresponding to the SPI interface and the DSPI interface are different; the AFE register is read and written with 16-bit address and 16-bit data or the image data is obtained through the SPI interface, and the SFR general register is read and written with 8-bit address and 8-bit data.

[0039] During the actual application of the fingerprint chip provided in this application, the host computer sends a control instruction through the SPI interface to start scanning, generates touch image data, and outputs the corresponding image data through the SPI interface or the DSPI interface based on different communication protocols, thereby realizing fast and accurate acquisition of fingerprint images.

[0040] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention are realized and obtained by the structures particularly pointed out in the description, claims and drawings.

[0041] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.

[0043] Figure 1 A schematic diagram of the structure of a fingerprint chip provided by an embodiment of the present invention;

[0044] Figure 2 ADC data returned by the dfe_ctrl AFE control module obtained in the fingerprint chip provided in the embodiment of the present invention;

[0045] Figure 3 A schematic diagram of the actual line sequence of the fingerprint chip after the fingerprint line sequence is disrupted provided by an embodiment of the present invention;

[0046] Figure 4 A schematic diagram of the line sequence of the fingerprint chip provided by the embodiment of the present invention after sorting the disrupted fingerprint line sequence;

[0047] Figure 5 This is a flow chart of the low power consumption control state machine transfer in the fingerprint chip provided by the embodiment of the present invention. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0049] In order to facilitate the understanding of this embodiment, the technical terms designed in this application are briefly introduced below.

[0050] DSPI is the abbreviation of Dual SPI, which means 2-wire SPI. Based on the SPI protocol, Motorola has enhanced its functions, added a queue transmission mechanism, and launched the queue serial peripheral interface protocol. Using this interface, users can transmit a transmission queue containing 2 bits of data at a time, doubling the transmission efficiency.

[0051] CLK: The master device provides the clock to the slave device, thereby triggering the transmission of communication data.

[0052] CS: When QSPI is connected to multiple peripheral devices, the CS pin can be used to determine which peripheral device to communicate with the host.

[0053] IO0: For the host, when only IO0 is set as the data input and output interface, it is considered to be in 3-wire mode; if IO0 is used as the data output interface, it is called Single Write mode, and if it is used as the data input mode, it is called Single Read mode.

[0054] IO1: For the host, only IO0 is set as the data output interface, and IO1 is set as the data input mode, which is considered to be a 2-wire mode; if IO0 is used as a data output interface, it is called Single Write mode, and if it is used as a data input mode, it is called Single Read mode. If both IO0 and IO1 are used as data input interfaces, it is called DualRead mode.

[0055] AFE (Analog Front end), analog front end.

[0056] After introducing the technical terms involved in this application, the application scenarios and design concepts of the embodiments of this application are briefly introduced.

[0057] In the terminal device, the fingerprint chip needs to be initialized to realize the fingerprint recognition function. The fingerprint chips of different manufacturers are different, and the current fingerprint chips have low accuracy and are prone to errors in fingerprint image recognition.

[0058] Based on this, an embodiment of the present application provides a fingerprint chip and a method for realizing its functions.

[0059] Example 1

[0060] The present application provides a fingerprint chip, which reads registers through an SPI interface, receives scanning instructions sent by a host computer and scans based on the scanning instructions. The fingerprint chip also outputs touch image data generated by the scan through an SPI interface or a DSPI interface; the communication protocols corresponding to the SPI interface and the DSPI interface are different; the AFE register is read and written with 16-bit address and 16-bit data or the image data is obtained through the SPI interface, and the SFR general register is read and written with 8-bit address and 8-bit data.

[0061] The capacitive fingerprint chip uses the state of the finger sliding over the sensor, and uses the ups and downs of the fingerprint to cause different changes in the pressure difference between the two, thereby obtaining the fingerprint image of the finger. The resolution of the image here is calculated as follows: RX (Receive array) crosses horizontally and TX (transfer, transmit array) vertically to form an image. RX consists of 32 ADCs in RX_SEL, and RX_SEL has a total of 8 channels, that is, the maximum resolution of RX is RX_SEL×32=256. TX is composed of TX_SELNO, TX_SELLR (TX_SELNO, TX_SELLR select the left half and right half of the transmit channel respectively) to select TX_SEL L (left) and TX_SEL R (right). TX_SELNO has a maximum of 180 channels, that is, the maximum resolution of TX is TX_SELNO×2=360. Therefore, the maximum resolution of the fingerprint image is 256x360.

[0062] In this embodiment, the fingerprint chip itself implements a SPI / DSPI slave interface. The SPI interface here is the main channel for the chip to interact with the outside world. The host computer (external CPU / MCU) communicates with the fingerprint chip through the built-in or external SPIMaster interface, sets the value of the built-in register on the fingerprint chip and starts 1 / N scans. N≤8 means that at most 8 scans are started once. The 8 scanned areas can be the same, or 8 different areas can be scanned at the same time, that is, the 256x360 image area is divided into 8 blocks and scanned separately. The image data is also obtained from the chip through this SPI interface. When the SPI interface is used to obtain image data, the SPI can be in the form of SPI / DSPI, and in other cases the SPI interface can only be used as SPI.

[0063] In this embodiment, a simple protocol is used inside the fingerprint chip to distinguish SPI read and write control registers, SPI read image data or DSPI read image data, and read FIFO image data in the form of 16-bit address 16-bit data. At the same time, the registers include AFE registers with 16-bit address 16-bit data and SFR general register operations with 8-bit address 8-bit data.

[0064] In combination with the first aspect, the fingerprint chip further includes: a timing generator, an ADC module, a dfe_ctrl AFE control module and a FIFO unit (such as Figure 1 shown).

[0065] The timing generator is used to generate the timing instructions required for the operation of the analog dfe_ctrl AFE module.

[0066] The timing generator also generates the timing required for the analog AFE ADC module to work, mainly some control and clock input to the analog AFE module. Figure 2 As shown, the timing generator generates the timing instructions required for the analog AFE ADC to work, such as RX_RST, RX_VB, ISO...ADC_CLK; the dfe_ctrl AFE control module also needs to obtain the 32-channel ADC data returned by the analog AFE ADC according to the timing of the Timing Generator: ADC_DATA1~ADC_DATA32.

[0067] in addition Figure 2 The ADC_Valid signal (ADC data valid indication signal) shown is also generated by the timing generator. Generally, ADC_DATA, that is, the data on the ADC channel, is obtained when ADC_Valid is valid.

[0068] The ADC module (analog to digital converter module) is used to obtain the analog signal of the scanned fingerprint chip according to the timing instructions and convert the analog signal into a digital signal. There are multiple ADC modules.

[0069] The dfe_ctrl AFE control module is used to receive digital signals input from multiple ADC modules and perform data processing according to timing instructions.

[0070] The dfe_ctrl AFE control module receives the data of ADC_DATA1~ADC_DATA32 according to the timing of the Timing Generator, and outputs 32 afe_adcdata to the dp_ctrl module after processing, and generates the adc_en ADC enable control signal. Furthermore, it determines which ADC_DATA of the 32 ADCs to enable. Here, you can set the ADC sequence number from adc_start to adc_end, and set whether to enable interleave (i.e. enable every other ADC). For example, adc_start=1, adc_end=24, and adc_interleave=1, then ADC_DATA1, ADC_DATA3…ADC_DATA23, a total of 12 ADC data, are enabled. In addition, RX_SEL here can also be cross-processed in a similar way, for example, rxsel_start=1, rxsel_end=8, and rxsel_interleave=1, then a total of 4 rxsels are enabled. Therefore, the RX resolution in the horizontal direction is 12x4=48.

[0071] Correspondingly, the settings that can be made in the TX direction are: tx arrange left and right order.

[0072] As an practicable manner, tx arrange=1 is set, and the TX direction is first the right side and then the left side; as another practicable manner, tx arrange=0 is set, and the TX direction is first the left side and then the right side. The above manners are all practicable and are not limited here.

[0073] In addition, you can also set the counting order of tx sequence TX_SELNO. For example:

[0074] tx sequence = 0, TX_SELNO counts sequentially from 1 to 180.

[0075] tx sequence = 1, TX_SELNO counts in reverse order from 180 to 1.

[0076] tx interleave cross processing, tx sequence (whether TX_SELNO count is reversed), tx interleave (TX send channel cross processing) cross can be set to 0~3, that is, no skip, skip 1, skip 2, skip 4, up to 3 types of cross skip processing.

[0077] For example, if tx_start=1,tx_end=200,tx arrange=1,tx sequence=1,tx interleave=2,then the output of TX is:TX_SELLR,TX_SELNO=1,100,0,100,1,97,0,97…1,1,0,1。The resolution of TX in the vertical direction is (33+1)x2=68。Among them, tx_start and tx_end are the starting sequence number and the ending sequence number of TX channel respectively.

[0078] In addition, ADC_DATA can be calibrated or not, inverted or not.

[0079] The FIFO unit (First In Fist Out) is used to store the processed fingerprint data.

[0080] The sortable FIFO unit can sort a row of data, up to 256 bytes (32x8) of data. Generally, for the convenience of wiring on the glass, our fingerprint line sequence will be shuffled. The actual line sequence is as follows Figure 3 As shown, the line sequence after sorting is as follows Figure 4 shown.

[0081] The 32-channel ADC data is divided into 8 times (after 8 CLK_24M clocks) according to the CLK_24M clock, and the data of 4 ADC channels are processed each time. The processing here refers to the cumulative processing. In addition, this processing is similar to pipeline processing, which is implemented according to the clock timing method. The step-by-step pipeline processing is a common method for digital logic to increase the reliability of mathematical calculations and reduce resource occupation. After the cumulative count is reached, the average and cut_base (minus base) are calculated. Generally, it is calculated like this: cumulative value ÷ cumulative number of times - cut_base. Then the 32-channel ADC data is sent to the sortable FIFO unit here for processing and storage.

[0082] The sortable FIFO unit can also perform selective sorting / unsorting storage and reading processing according to the ADC range (specified by adc_start, adc_end, where adc_start and adc_end are the start and end numbers of the ADC channel respectively) and the RX_SEL range (specified by rxsel_start, rxsel_end, where rxsel_start and rxsel_end are the start and end numbers of the receiving channel respectively), which is also achieved through register settings. In addition, the data is cached to the FIFO unit by reading 1 line and writing 1 line, ensuring efficient and reliable writing and reading of data.

[0083] The host computer (MCU, micro-controller unit, micro-control unit. For example, microprocessor, single-chip microcomputer) reads the data of the FIFO unit in this way: the data can be read at any time. If the data is not ready (there is no data in the FIFO unit), then all the data read is 0xFF empty data. If there is data in the FIFO unit, then non-empty data can be read. Non-empty data is other 8-bit data values ​​other than 0xFF (i.e. 0x0~0xFE). You can also enable the FIFO unit data interrupt by setting the register. At this time, when the gpio_irq interrupt output pin is pulled high, it means that there is data available for reading. The MCU can read the data through SPI or DSPI. At this time, it can be guaranteed that the data read is non-empty data.

[0084] In addition, when the data reading speed is slower than the data generation speed, the FIFO unit is in full state. In order to avoid overflow of the full state, the dfe_ctrl AFE control module will be paused. At this time, the dfe_ctrl AFE control module is in a paused state until the data in the FIFO unit is read out and the full state is cancelled.

[0085] In combination with the first aspect, the fingerprint chip further includes:

[0086] The data processing module is connected to the dfe_ctrl AFE control module and the timing generator. The data processing module is used to process the data of the dfe_ctrl AFE control module, process it again according to preset rules, and feed it back to the timing generator.

[0087] Data processing module (dp_ctrl display processing module), dp stands for data processing, dfe_ctrl AFE control module sends the initially processed afe_adcdata (32 ADC channel data transmitted to dp_ctrl display processing module after processing by dfe_ctrl AFE control module), which is 32 channels of 8-bit ADC data (adc_start and adc_end are obtained according to the number of enabled ADCs, and some ADC channel data may be useless). 32 channels of ADC data need to be accumulated and processed, and the accumulation times can be set through registers.

[0088] In combination with the first aspect, the fingerprint chip further includes: an lp_controller low power consumption control module.

[0089] After receiving the scan_end scan end signal from the dp_ctrl display processing module, the lp_controller low power control module enters the FP_STOPPED (scan stop) state, and then enters the FP_IDLE idle state; then after receiving the low power sleep signal set by the register, it will enter the FP_LOW_SLEEP / FP_DEEP_SLEEP (low / deep sleep) state.

[0090] Combination Figure 5 As shown, first, in the default FP_IDLE idle state, if the scan_start scan start signal is set and initiated through the register, it will enter the FP_RUNNING scanning state.

[0091] At this time, if the dfe_ctrl AFE control module sends a scan_end scan end signal, it will enter the FP_STOPPED scan stop state, otherwise it will stay in the FP_RUNNING state. At the same time, the host computer (external MCU) must read the data in the sortable FIFO unit through the SPI interface or DSPI, otherwise it will cause the dfe_ctrl module to pause as before. Then in the FP_STOPPED state, if the last row of data in the FIFO unit is read, the sortable FIFO unit is empty, and then it will eventually return to the FP_IDLE idle state, otherwise it will stay in the FP_STOPPED state.

[0092] Second, if you set low-power sleep by setting registers in FP_IDLE idle state, you will enter FP_LOW_SLEEP low-power sleep state, and the CLK_24M24MHZ master clock will be turned off. Except for the lp_controller low-power control module, which is still working because CLK_32K (32KHZ clock) still exists, the SPI interface can receive the wake-up data of 0xD5, and all other modules stop working because there is no 24MHZ master clock. At this time, the power consumption is very low. Then if the wake-up signal (SPI module receives 0xD5 data) or reset signal is received, the chip will return to FP_IDLE state.

[0093] If clk_32koff (whether to turn off the 32k clock when entering low power consumption) has been set through the SPI interface at this time, it will further enter the FP_DEEP_SLEEP deep sleep state. At this time, the 32KHZ clock will also be turned off, and all modules of the chip will stop working. At this time, the chip power consumption is extremely low, and the current is only a few uA (microampere level). At this time, the chip cannot be awakened by the wake-up signal (SPI module receives 0xD5 data), and the SPI module receiving 0xD5 data cannot make the chip return to the FP_IDLE state. The chip can only be reset by the reset signal.

[0094] If scan_start is started, but the state machine has not returned to FP_IDLE, the chip will not immediately enter the low power state even if the request to enter the sleep state is set. It will have to wait until the chip scan completes scan_end and the data in the fifo_empty sortable FIFO unit is read empty, and the chip returns to the FP_IDLE idle state, and then enters the FP_LOW_SLEEP or further enters the FP_DEEP_SLEEP state.

[0095] In addition, when the CLK_32K and CLK_24M clocks are turned off, they are not turned off immediately, but remain on for a short period of time (about 3 milliseconds), and then the PLL (phase-locked loop clock generation unit) is notified to actually turn off the corresponding clock. This ensures that the relevant modules can smoothly enter the stop state.

[0096] The clock and reset units generate the clock and reset signals for the chip to work. The register file module generates a series of corresponding control (write) registers required by the chip, as well as the status registers for reading, which is achieved through the SPI interface and the custom simple protocol.

[0097] In a second aspect, the present application provides a method for realizing the functions of a fingerprint chip, which is applied to the above-mentioned fingerprint chip. The method comprises:

[0098] S110, the timing generator generates the timing required for the dfe_ctrl AFE control module to work;

[0099] S120, based on the timing, the dfe_ctrl AFE control module collects the data sent by the multiple ADC modules one by one and stores them in the FIFO unit after processing the data, so as to be acquired by the SPI interface or the DSPI interface.

[0100] In this embodiment, the timing generator generates the timing required for the operation of the dfe_ctrl AFE control module. The dfe_ctrlAFE control module performs data acquisition according to the timing instructions to read and process the data sent by the ADC module according to the preconfigured data reading rules (data reading range, whether to cross, jump, sequential reading, etc.), and then stores it in the FIFO unit for the host computer (external MCU) to read the data in the FIFO unit through the SPI interface and the DSPI interface.

[0101] Step S120 also includes:

[0102] S121, generating an adc_en ADC enable control signal according to a preset enable rule to determine a target ADC module to be enabled.

[0103] S122, based on the timing, adc_en ADC enable control signal and preset data reading rules, the dp_ctrl display processing module receives the data sent by the target ADC module and performs data processing.

[0104] According to the adc_en (adc enable, ADC enable signal) ADC enable control signal, the target ADC module corresponding to each timing is determined, and based on the dp_ctrl display processing module and the configured data reading rules, the sequential or reverse reading of the image data, as well as the horizontal and vertical interleaving / non-interleaving (interlaced rows / interlaced columns) processing of the image data, etc. can be realized. Among them, sorting / non-sorting processing can also be selected when reading data.

[0105] S123, sending the scan data processed by the dfe_ctrl AFE control module to the dp_ctrl display processing module for further processing.

[0106] S124, sorting and transmitting the scanned data processed by the dp_ctrl display processing module to the FIFO unit and storing the same.

[0107] The dfe_ctrl AFE control module sends the initially processed afe_adcdata, which is 32-channel 8-bit ADC data, to the dp_ctrl display processing module. The dp_ctrl display processing module accumulates the received data and then calculates the average minus the base. The sortable FIFO unit sorts / unsorts the access data according to the ADC range.

[0108] When the reading speed of the host computer (external MCU) through the SPI interface is slower than the data generation speed of the chip, let dfe_ctrl pause pause the data generation to prevent data overflow.

[0109] In combination with the first aspect, step S123 includes:

[0110] S1231, obtaining a preset cumulative number of times.

[0111] S1232, based on the accumulated number of times, calculate the data processing amount of the cumulative processing.

[0112] S1233, after reaching the cumulative number of times, perform cumulative averaging and base subtraction processing.

[0113] In combination with the second aspect, step S124 includes:

[0114] S1241, controlling the sortable FIFO unit to determine a read processing mode according to the ADC module range and the RX_SEL range; the read processing mode includes sorted storage reading or unsorted storage reading.

[0115] S1242, obtaining the speed at which the host computer reads data, based on whether the FIFO is full.

[0116] S1243, if the speed is lower than the data generation speed of the FIFO unit.

[0117] S1244, the control timing generator generates a pause timing instruction to send a pause instruction to the dfe_ctrl module until the data in the FIFO unit is read out.

[0118] In this embodiment, the ADC range (adc_start, adc_end are both specified), the RX_SEL range (i.e., rxsel_start, rxsel_end are both specified), and the preset data reading rules are determined based on the register settings, so as to selectively sort or not sort the data storage and reading processing. Under the control of the timing instruction, the host computer reads the data in the FIFO unit through the SPI interface or the DSPI interface according to the timing. In this process, by comparing the speed at which the host computer reads data with the speed at which the data in the FIFO unit is generated, when the reading speed is less than the data generation speed of the FIFO unit, it means that the data of a certain row in the FIFO unit has not been read yet and new data is written. In this way, when the new data is written to the row, the newly written data will be read when the host computer reads the data, resulting in the read data not being consistent with the actual scanned data, resulting in data confusion. Therefore, in such a case, the timing generator generates a pause timing instruction to send a pause instruction to the dfe_ctrl AFE control module to stop storing the data processed by the dfe_ctrl AFE control module into the FIFO unit until the data in the FIFO unit is read out. The dfe_ctrl AFE control module then stores the data into the FIFO unit, and the cycle repeats until all the data is completely read.

[0119] In combination with the first aspect, the method further includes:

[0120] S210, in the default FP_IDLE idle state, if the dp_ctrl display processing module receives the scan_start scan start signal, the lp_controller low power consumption processing module enters the FP_RUNNING scanning state.

[0121] S220, if the scan_end scan end signal is received, the FP_STOPPED scan stop state is entered, and at the same time, the host computer reads the data in the FIFO unit through the SPI interface or the DSPI interface. If the host computer does not read the data in the FIFO unit, resulting in the FIFO being in a full state, the dfe_ctrl module will suspend its work.

[0122] In the actual working process, if a scan start signal is received in the default idle state, the command of the control signal is executed to scan to obtain the scan data, and the scan is stopped immediately after the dp_ctrl AFE control module receives the scan end signal. In the stop scanning state, if the host computer needs to read the data of the FIFO unit, the data in the FIFO unit is read by the host computer through the SPI interface or the DSPI interface. Among them, FP (Finger Pprint, i.e. fingerprint sensor).

[0123] It can be understood that if the host computer does not read the data in the FIFO unit when the FIFO is full, the dfe_ctrl AFE control module is controlled to suspend operation to stop writing processed data to the FIFO unit to prevent the host computer from reading erroneous data.

[0124] In conjunction with the second aspect, the method includes:

[0125] S310, in the FP_IDLE idle state, if the dp_ctrl display processing module receives a low power sleep signal, it enters the FP_LOW_SLEEP state, and at the same time, turns off the main clock of CLK_24M.

[0126] S310: If a wake-up signal or a reset signal is received, the FP_IDLE idle state is restored.

[0127] In this embodiment, the low power sleep signal is set through the register, and the FP_LOW_SLEEP state is entered. At this time, the CLK_24M_24MHz main clock is turned off. In addition to the lp_controller still working because the CLK_32K_32KHz clock still exists, the SPI interface can receive the 0xD5 wake-up signal or reset signal. If the signal is received, the chip will return to the FP_IDLE state.

[0128] S310, if the host computer (MCU) also sets the clk_32koff instruction signal through the SPI when entering sleep mode, the FP_DEEP_SLEEP state is entered and the 32KHz clock is turned off.

[0129] In this embodiment, if clk_32koff has been set through the SPI interface, it will further enter the FP_DEEP_SLEEP (deep sleep) state, then the 32KHz clock will also be turned off, all modules of the chip will stop working, and the chip power consumption is extremely low at this time, with a current of only a few microamperes.

[0130] Finally, the touch control unit (combined with Figure 1 The touch_ctrl liveness recognition module shown in FIG. 1 is a liveness recognition unit external to the chip. When there is liveness touch, it can output a reset signal to the chip, and can wake up the chip when the chip is in FP_LOW_SLEEP / FP_DEEP_SLEEP.

[0131] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the system and device described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0132] In addition, in the description of the embodiments of the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be the internal communication of two components. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0133] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0134] Finally, it should be noted that the above embodiments are only specific implementations of the present invention, which are used to illustrate the technical solutions of the present invention, rather than to limit them. The protection scope of the present invention is not limited thereto. Although the present invention is described in detail with reference to the above embodiments, those skilled in the art should understand that any person skilled in the art can still modify the technical solutions recorded in the above embodiments within the technical scope disclosed by the present invention, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A fingerprint chip, characterized in that: The fingerprint chip reads registers through the SPI interface, receives scanning instructions sent by the host computer and scans based on the scanning instructions. The fingerprint chip also outputs touch image data generated by the scan through the SPI interface or the DSPI interface; the communication protocols corresponding to the SPI interface and the DSPI interface are different; the AFE register is read and written with 16-bit address and 16-bit data or the image data is obtained through the SPI interface, and the SFR general register is read and written with 8-bit address and 8-bit data.

2. The fingerprint chip according to claim 1, characterized in that: The fingerprint chip also includes: A timing generator is used to generate the timing instructions required for the operation of the analog dfe_ctrl AFE module; An ADC module, used for acquiring an analog signal of scanning the fingerprint chip according to the timing instruction and converting the analog signal into a digital signal, and there are multiple ADC modules; dfe_ctrl AFE control module, used for receiving digital signals input by a plurality of ADC modules and performing data processing according to the timing instruction; The FIFO unit is used to store processed fingerprint data.

3. The fingerprint chip according to claim 2, characterized in that: Also includes: A data processing module is connected to the dfe_ctrl AFE control module and the timing generator. The data processing module is used to process the data of the dfe_ctrl AFE control module and transmit it to the dp_ctrl display processing module for further processing according to preset rules and feedback to the timing generator.

4. The fingerprint chip according to claim 3, characterized in that: Also includes: The lp_controller low power control module enters the FP_STOPPED state after receiving the scan_end scan end signal of the dp_ctrl display processing module; and enters the FP_LOW_SLEEP / FP_DEEP_SLEEP state after receiving the low power sleep signal set by the register.

5. A method for realizing the function of a fingerprint chip, characterized in that: The method is applied to the fingerprint chip according to any one of claims 1 to 4; the method comprises: The timing generator generates the timing required for the dfe_ctrl AFE control module to work; Based on the timing, the dfe_ctrl AFE control module collects the data sent by multiple ADC modules one by one and stores them in the FIFO unit after data processing, so that the MCU can obtain them through the SPI interface or the DSPI interface.

6. The method according to claim 5, characterized in that Based on the timing, the dfe_ctrl AFE control module collects the data sent by the multiple ADC modules one by one and stores them in the FIFO unit after data processing for the SPI interface or the DSPI interface to obtain, and also includes: According to the preset enabling rule, an adc_en ADC enabling control signal is generated to determine the target ADC module to be enabled; Based on the timing, the adc_en ADC enable control signal and the preset data reading rule, the dp_ctrl display processing module receives the data sent by the target ADC module and performs data processing; Sending the scanned data processed by the dfe_ctrl AFE control module to the dp_ctrl display processing module for further processing; The scanned data processed by the dp_ctrl display processing module is sorted, transmitted and stored in the FIFO unit.

7. The method according to claim 5, characterized in that The step of sending the scanned data processed by the dfe_ctrl AFE control module to the dp_ctrl display processing module for further processing includes: Get the preset cumulative number of times; Based on the accumulated times, calculating the data processing amount of the cumulative processing; After reaching the cumulative number, the cumulative average and base subtraction processing are performed.

8. The method according to claim 5, characterized in that The step of sorting and transmitting the processed scan data to the FIFO unit and storing the processed scan data in the FIFO unit comprises: Controlling the sortable FIFO unit to determine a read processing mode according to the ADC module range and the RX_SEL range; the read processing mode at least includes sorted storage reading or random storage reading; Get the speed at which the host computer reads data, which is determined by whether the FIFO is full; If the speed is less than the data generation speed of the FIFO unit; The timing generator is controlled to generate a pause timing instruction to send a pause instruction to a dfe_ctrl AFE control module until the data in the FIFO unit is read out.

9. The method according to claim 6, characterized in that The method further comprises: In the default FP_IDLE idle state, if the dp_ctrl display processing module receives the scan_start scan start signal, it enters the FP_RUNNING scanning state; If the scan_end scan end signal is received, the FP_STOPPED scan stop state is entered, and at the same time, the host computer reads the data in the FIFO unit through the SPI interface or the DSPI interface.

10. The method according to claim 6, characterized in that The method comprises: In the FP_IDLE idle state, if the dp_ctrl display processing module receives a low-power sleep signal sent by the MCU, it enters the FP_LOW_SLEEP state and turns off the main clock of CLK_24M. If a wake-up signal or a reset signal is received afterwards, the FP_IDLE idle state is restored; If the host computer (MCU) also sets the clk_32koff instruction signal through the SPI when entering sleep mode, the FP_DEEP_SLEEP state is entered, and the 32KHz clock is turned off.

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