Software and hardware collaborative NVME SSD log analysis system based on FPGA

Abstract

The invention provides a software and hardware collaborative NVME SSD log analysis system based on an FPGA. The system comprises an on-chip processor, a data buffer area, an on-chip interface controller and an on-chip interface. The on-chip processor is connected with the on-chip interface controller, the logic end block storage controller and the processor end block storage controller, and the on-chip processor receives an NVME I / O command of a host and transmits the NVME I / O command to the logic end block storage controller; the logic end block storage controller reads log data from the storage simulation system and then transmits the log data to the data buffer area; the processor end block storage controller reads the log data from the data buffer area and then sends the log data to the on-chip processor, and the on-chip processor analyzes the log data to obtain a log analysis result and transmits the log analysis result to the on-chip interface controller; the on-chip interface controller is connected with the on-chip interface, and the on-chip interface controller transmits a log analysis result to the host and the SD memory card through the on-chip interface. The log analysis system provided by the invention can provide more detailed and fine-grained access records.

Description

Technical Field

[0001] The present invention belongs to the technical field of log analysis, and specifically discloses an NVME SSD log analysis system based on software and hardware collaboration of FPGA. Background Art

[0002] NVME solid state drive (SSD) is the most popular large-capacity storage device currently, and is widely used in emerging industries such as interactive AI, cloud storage, and intelligent networks. Since SSDs store massive amounts of data information, errors in the operation of SSDs may lead to inestimable cost losses. Therefore, the industry is paying more and more attention to the detailed analysis of NVME I / O logs to grasp the working status of SSDs, but the detailed information of NVME I / O commands is often difficult to obtain directly from the host. In addition, due to the performance limitations of traditional flash memory for write and erase operations, new solid state drive storage devices are using heterogeneous storage media to form storage devices. In order to study the impact of different storage media on the I / O performance of solid state drives, the existing technology needs to classify and collect NVME I / O log information and debug the access of NVME I / O operations sent by the host to different storage media. Therefore, a log analysis system dedicated to NVME solid state drives is needed, which can parse the field information of NVME I / O commands in detail and distinguish the access information of NVME I / O to heterogeneous storage media.

[0003] Field Programming Gate Array, FPGA, is a semi-customized circuit in the field of application-specific integrated circuits. It has rich wiring resources, the advantages of re-programmability and high integration, which not only solves the shortcomings of fully customized circuits, but also overcomes the shortcomings of the limited number of gate circuits of the original programmable logic device. The existing FPGA board also integrates an on-chip processor, so that FPGA can design System-on-chip, SoC system. The on-chip processor can use software code to assist the hardware circuit to complete the processing of complex data structures, and can use the driver software to call the on-chip interface more conveniently. There are some patents for collecting NVME solid-state drive logs. The Chinese patent "CN114661502A A SSD log management system" proposes a system structure for lightweight update of solid-state drive logs, including information collection modules and information cache modules, etc., which can pre-cache the system's log information for SSD operations and use event-driven methods to update the log cache, but only focuses on the way to collect solid-state drive logs, and does not focus on the analysis of the collected log data. The Chinese patent "CN112631819 Method, device, computer equipment and storage medium for collecting SSD error logs" proposes a simple method for collecting SSD error logs, using the tool USB flash drive of the WINPE system to obtain the error information of the SSD and analyze and warn the error information. The logs are collected through the tools in the WINPE system, but only part of the error information is judged, and no more detailed analysis of the SSD log information is performed. At present, there is no work on the collection of log information for heterogeneous storage media of solid-state drives. In view of the above-mentioned problems, it is very necessary to study and design a new NVME SSD log parsing system based on FPGA and hardware collaboration to overcome the problems existing in the existing technology for collecting NVME solid-state drive logs. Summary of the invention

[0004] In order to solve the problems in the existing NVME solid state drive log parsing technology that it is difficult to complete fine-grained recording of NVME logs and lack of parsing process for the recorded logs, the present invention proposes an NVME SSD log parsing system based on FPGA and hardware collaboration.

[0005] The present invention provides a FPGA-based soft-hard collaborative NVME SSD log parsing system, including an on-chip processor, a logic-end block storage controller, a data buffer, a processor-end block storage controller, an on-chip interface controller, and an on-chip interface;

[0006] The on-chip processor is connected to the on-chip interface controller, the logic end block storage controller and the processor end block storage controller, and the on-chip processor receives the NVME I / O command of the host through the on-chip interface controller, and transmits the NVME I / O command to the logic end block storage controller;

[0007] One end of the logic end block storage controller is connected to the storage simulation system, and the other end is connected to the data buffer. The logic end block storage controller is used to read log data from the storage simulation system after receiving the NVME I / O command of the host, and transmit the log data to the data buffer. After the log data transmission is completed, the logic end block storage controller generates an interrupt signal, and transmits the interrupt signal to the on-chip processor;

[0008] The data buffer is connected to the processor-side block storage controller, and the data buffer is used to store the log data and for the processor-side block storage controller to read the log data;

[0009] The processor-side block storage controller is connected to the on-chip processor, the on-chip processor sends a read signal to the processor-side block storage controller according to the interrupt signal, the processor-side block storage controller is used to read the log data from the data buffer according to the read signal, and send the log data to the on-chip processor, the on-chip processor parses the log data, obtains a log parsing result, and transmits the log parsing result to the on-chip interface controller;

[0010] The on-chip interface controller is connected to the on-chip interface, and the on-chip interface controller transmits the log analysis result to the host and the SD memory card through the on-chip interface;

[0011] The on-chip interface is connected to a host and an SD memory card.

[0012] According to an FPGA-based soft-hard collaborative NVME SSD log parsing system according to some embodiments of the present application, the on-chip processor includes a communication module, a log data parsing module, an access count counter and a driver module;

[0013] The communication module is respectively connected to the on-chip interface controller, the logic end block storage controller, the processor end block storage controller, the log data parsing module, the access times counter and the driving module. The communication module is used to receive the NVME I / O command from the host of the on-chip interface controller, and transmit the NVME I / O command to the logic end block storage controller. The communication module is also used to receive an interrupt signal from the logic end block storage controller, and transmit the interrupt signal to the driving module. The driving module generates a read signal according to the interrupt signal and transmits it to the communication module. The communication module transmits the read signal to the processor end block storage controller. The communication module is also used to receive log data from the processor end block storage controller, and transmit the log data to the log data parsing module and the access times counter. The log data parsing module and the access times counter parse the log data to obtain the log parsing result, and transmit the log parsing result to the communication module. The communication module transmits the log parsing result to the on-chip interface controller;

[0014] The log data parsing module is connected to the access count counter. After receiving the log data, the log data parsing module parses the fields in the log data according to the log data structure of the log data to obtain the ID of the current NVME I / O access, the address of the current NVME I / O access, the data of the current NVME I / O access, the operation type of the current NVME I / O access, the status of the current NVME I / O access, the target medium of the current NVME I / O access, and the I / O classification of the target device accessed, and the log data parsing module transmits the target medium of the current NVME I / O access to the access count counter;

[0015] The access count counter determines the target medium type according to the target medium accessed by the current NVME I / O, adds one to the access count of the target medium type that has been accessed, obtains the access count of each target medium type, and sends the access count of each target medium type to the communication module;

[0016] The driving module also transmits a driving signal for driving the on-chip interface controller to work to the communication module, and the communication module transmits the driving signal to the on-chip interface controller.

[0017] According to some embodiments of the present application, an FPGA-based soft-hard collaborative NVME SSD log parsing system, the log parsing result includes the ID of the current NVME I / O access, the address of the current NVME I / O access, the data of the current NVME I / O access, the operation type of the current NVME I / O access, the status of the current NVME I / O access, the target medium of the current NVME I / O access, the I / O classification of the accessed target device and the I / O count of the accessed target device.

[0018] According to an FPGA-based software-hardware collaborative NVME SSD log parsing system of some embodiments of the present application, the logic end block storage controller includes a logic end bus interface module and a logic end block storage interface module connected to each other;

[0019] The logic end bus interface module is connected to the communication module through a processor bus, and the logic end bus interface module is used to receive the NVME I / O command and transmit the NVME I / O command to the logic end block storage interface module;

[0020] The logical end block storage interface module is also connected to the storage simulation system and the data buffer. The logical end block storage interface module reads the log data from the storage simulation system according to the NVME I / O command and transmits the log data to the data buffer. After the log data is written into the data buffer, the logical end block storage interface module generates an interrupt signal and transmits the interrupt signal to the logical end bus interface module, and the logical end bus interface module transmits the interrupt signal to the communication module.

[0021] According to some embodiments of the present application, an FPGA-based soft-hard collaborative NVME SSD log parsing system, the data buffer includes a logic end block storage controller port and a processor block storage controller port, the logic end block storage controller port is used to connect to the logic end block storage interface module, and the processor block storage controller port is used to connect to the processor block storage controller.

[0022] According to an FPGA-based soft-hard collaborative NVME SSD log parsing system of some embodiments of the present application, the processor-side block storage controller includes a processor-side bus interface module and a processor-side block storage interface module connected to each other;

[0023] The processor-side bus interface module is connected to the communication module via a processor bus, and the processor-side bus interface module is used to receive the read signal and transmit the read signal to the processor-side block storage interface module;

[0024] The processor-side block storage interface module is also connected to the data buffer. The processor-side block storage interface module reads the log data from the data buffer according to the read signal and transmits the log data to the processor-side bus interface module. The processor-side bus interface module transmits the log data to the communication module.

[0025] According to some embodiments of the present application, a FPGA-based soft-hard collaborative NVME SSD log parsing system, the on-chip interface includes a UART interface and an SD card interface, the UART interface is used to connect to the host and transmit the log parsing results to the host, the SD card interface is used to connect to the SD memory card and transmit the log parsing results to the SD memory card.

[0026] According to some embodiments of the present application, an FPGA-based soft-hard collaborative NVME SSD log parsing system, the on-chip interface controller includes a UART interface control module and an SD card interface control module, the UART interface control module is used to control the transmission of the UART interface, and the SD card interface control module is used to control the transmission of the SD card interface.

[0027] According to an FPGA-based soft-hard collaborative NVME SSD log parsing system in some embodiments of the present application, the on-chip interface controller is connected to the on-chip processor via a processor bus.

[0028] According to an FPGA-based software-hardware collaborative NVME SSD log parsing system in some embodiments of the present application, the bus architecture of the processor bus is the AMBA4 bus architecture, and the interface specification of the processor bus is AXI4.

[0029] The present invention proposes a NVME SSD log parsing system based on FPGA and software-hard collaboration, which improves the troubleshooting efficiency of NVMe solid-state hard disks. Compared with the prior art, the log parsing system of the present invention can provide more detailed and fine-grained NVMe I / O access records, so as to quickly locate the I / O requests of the solid-state hard disk access errors, and quickly analyze the causes of the errors according to the log parsing results. The present invention has a variety of log recording methods, and the log parsing results can be reported to the host in a timely manner through the on-chip interface, or can be saved in the SD memory card. When the present invention uses an on-chip processor to analyze the NMVE I / O log, the target medium type is determined according to the target medium accessed by the current NVME I / O, and the number of accesses of each target medium type is determined, which provides a debugging platform for studying the access of NVME I / O to heterogeneous storage media of solid-state hard disks. In addition, the present invention is convenient for functional expansion, the present invention uses FPGA for development, and utilizes its reprogrammable flexibility to facilitate the optimization and decoupling of hardware paths, introduces an on-chip processor to parse log data, and can optimize the cache design of the processor, store more NVME I / O logs, and adapt to larger-scale NVME I / O log recording situations. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 This is a schematic diagram of the overall structure of the NVME SSD log parsing system based on FPGA software and hardware collaboration according to an embodiment of the present invention;

[0031] Figure 2 It is a structural diagram of a logical end block storage controller according to an embodiment of the present invention;

[0032] Figure 3 The figure is a schematic diagram of the structure of a processor-side block storage controller according to an embodiment of the present invention. DETAILED DESCRIPTION

[0033] The following embodiments of the present invention are described in further detail in conjunction with the accompanying drawings and examples. The following examples are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

[0034] This embodiment provides an NVME SSD log parsing system based on FPGA and software-hard collaboration, wherein FPGA, i.e., field programmable gate array, is a semi-custom circuit widely used in the field of application-specific integrated circuits. It has abundant wiring resources, supports repeated programming, and has high integration. FPGA not only makes up for the limitations of fully customized circuits, but also overcomes the limitations of traditional programmable logic devices on the number of gate circuits. NVME, which refers to the non-volatile memory specification, is an efficient and scalable interface that allows host software to communicate with non-volatile memory through the PCI Express bus. A major highlight of NVME is its multi-queue mechanism, which supports up to 64,000 I / O queues, and each queue can have up to 64,000 commands. The instruction set structure adopted by NVME is simple. These advantages enable the NVME protocol to give full play to the performance of solid-state hard disks represented by Flash storage as permanent storage media. At present, NVME has widely replaced the traditional SATA protocol in SSD applications.

[0035] This embodiment provides an NVME SSD log parsing system based on FPGA software and hardware collaboration. Figure 1 As shown, it includes an on-chip processor, a logic-end block storage controller, a data buffer, a processor-end block storage controller, an on-chip interface controller and an on-chip interface; the on-chip processor is connected to the on-chip interface controller, the logic-end block storage controller and the processor-end block storage controller, the on-chip processor receives the NVME I / O command of the host through the on-chip interface controller, and transmits the NVME I / O command to the logic-end block storage controller; one end of the logic-end block storage controller is connected to the storage simulation system, and the other end is connected to the data buffer, and the logic-end block storage controller is used to receive the NVME After the I / O command is executed, the log data is read from the storage simulation system and transmitted to the data buffer. The logic-side block storage controller generates an interrupt signal after the log data transmission is completed, and transmits the interrupt signal to the on-chip processor; the data buffer is connected to the processor-side block storage controller, the data buffer is used to store the log data, and the processor-side block storage controller reads the log data; the processor-side block storage controller is connected to the on-chip processor, the on-chip processor sends a read signal to the processor-side block storage controller according to the interrupt signal, the processor-side block storage controller is used to read the log data from the data buffer according to the read signal, and send the log data to the on-chip processor, the on-chip processor parses the log data, obtains the log parsing result and transmits the log parsing result to the on-chip interface controller; the on-chip interface controller is connected to the on-chip interface, the on-chip interface controller transmits the log parsing result to the host and the SD memory card through the on-chip interface; the on-chip interface is connected to the host and the SD memory card.

[0036] It should be noted that, as a preferred embodiment of the present invention, the on-chip processor includes a communication module, a log data parsing module, an access count counter and a driver module; the communication module is respectively connected to the on-chip interface controller, the logic end block storage controller, the processor end block storage controller, the log data parsing module, the access count counter and the driver module, and the communication module is used to receive the NVME I / O command of the host from the on-chip interface controller and convert the NVME The I / O command is transmitted to the logical end block storage controller, the communication module is also used to receive an interrupt signal from the logical end block storage controller, and transmit the interrupt signal to the driver module, the driver module generates a read signal according to the interrupt signal and transmits it to the communication module, the communication module transmits the read signal to the processor end block storage controller, the communication module is also used to receive log data from the processor end block storage controller, and transmit the log data to the log data parsing module and the access count counter, the log data parsing module and the access count counter parse the log data to obtain a log parsing result, and transmit the log parsing result to the communication module, the communication module transmits the log parsing result to the on-chip interface controller; the log data parsing module is connected to the access count counter, after receiving the log data, the log data parsing module parses the fields in the log data according to the log data structure of the log data, the parsed fields may include the address accessed by the NVME command, the data accessed by the NVME command, the queue number accessed by the NVME command, the namespace configuration accessed by the NVME command, the important status information accessed by the NVME command, the command specific field accessed by the NVME command, the target medium accessed by the NVME I / O command, and the target device information accessed by the NVME I / O command, and obtain the current NVME The ID of the I / O access, the address of the current NVME I / O access, the data of the current NVME I / O access, the operation type of the current NVME I / O access, the state of the current NVME I / O access, the target medium of the current NVME I / O access, and the I / O classification of the target device accessed, and the log data parsing module transmits the target medium of the current NVME I / O access to the access count counter; the access count counter determines the target medium type according to the target medium accessed by the current NVME I / O, adds one to the number of accesses of the target medium type that has been accessed, obtains the number of accesses of each target medium type, and sends the number of accesses of each target medium type to the communication module, and the number of accesses of each target medium type can analyze the access proportion of heterogeneous media; the driving module also transmits a driving signal for driving the on-chip interface controller to the communication module, and the communication module transmits the driving signal to the on-chip interface controller. As the preferred embodiment of this embodiment, the driving module includes Xilinx UART driver software and FatFS driver software, and FatFS driver software is a micro file system designed for embedded storage devices and microprocessors. The frequency of the on-chip processor can be 1.5GHz.

[0037] In the storage simulation system used in the present embodiment, different I / O access address ranges are allocated to different storage media. In the log parsing system of the present embodiment, the target media accessed by the NVME command are distinguished according to different I / O address ranges. In order to make up for the difficulty in capturing NVME command log records or the lack of log content parsing in the current NVME SSD log recording work, the present embodiment records more detailed NVME command fields in the storage simulation system, such as the physical address area PRP (Physical Region Page) describing the physical address used for data transmission, the starting logical block address SLBA (Starting LBA) for starting to read or write data, and the number of logical blocks NLB (Number of Logical Blocks) specifying the number of logical blocks to be read or written. Blocks), etc. These fields are used in the NVME protocol for the transmission and execution of read and write commands, helping the log parsing system and the host to exchange data correctly and efficiently. In the storage simulation system, these fields are assembled into a new format according to the log data structure. In addition, the log parsing system also records the information of a group of registers in NVME, which are essential for the normal operation of NVME devices. For example, the register group CAP (Capabilities) is the switch for some important functions of NVME devices, and the register group CC (Controller Configuration) is used to configure the key information of the controller. Through command fields and registers, the NVME protocol realizes efficient storage device management and data operations.

[0038] It should be noted that, as a preferred embodiment of the present invention, the log parsing result includes the ID of the current NVME I / O access, the address of the current NVME I / O access, the data of the current NVME I / O access, the operation type of the current NVME I / O access, the status of the current NVME I / O access, the target medium of the current NVME I / O access, the I / O classification of the target device accessed, and the I / O count of the target device accessed.

[0039] It should be noted that, as a preferred embodiment of this embodiment, Figure 2As shown, the logic end block storage controller includes a logic end bus interface module and a logic end block storage interface module that are interconnected; the logic end bus interface module is connected to the communication module through the processor bus, and the logic end bus interface module is used to receive NVME I / O commands and transmit the NVME I / O commands to the logic end block storage interface module; the logic end block storage interface module is also connected to the storage simulation system and the data buffer, the logic end block storage interface module reads log data from the storage simulation system according to the NVME I / O commands, and transmits the log data to the data buffer, after the log data is written into the data buffer, the logic end block storage interface module generates an interrupt signal, and transmits the interrupt signal to the logic end bus interface module, and the logic end bus interface module transmits the interrupt signal to the communication module. More preferably, the logic end bus interface module signal is consistent with the bus standard used by the on-chip processor, and is used for the transmission of on-chip processor clock synchronization data, and uses registers to transmit the host's log request. The logic end block storage controller defines signals that comply with the read and write FPGABRAM specifications, and can directly receive the log data output by the storage simulation system. As shown Figure 3 As shown, the processor-side block storage controller includes a processor-side bus interface module and a processor-side block storage interface module that are connected to each other; the processor-side bus interface module is connected to the communication module through the processor bus, and the processor-side bus interface module is used to receive a read signal and transmit the read signal to the processor-side block storage interface module; the processor-side block storage interface module is also connected to the data buffer, and the processor-side block storage interface module reads log data from the data buffer according to the read signal and transmits the log data to the processor-side bus interface module, and the processor-side bus interface module transmits the log data to the communication module. The data buffer includes a logic-side block storage controller port and a processor block storage controller port, the logic-side block storage controller port is used to connect to the logic-side block storage interface module, and the processor block storage controller port is used to connect to the processor block storage controller.

[0040] It should be noted that, as preferred in this embodiment, the on-chip interface includes a UART interface and an SD card interface, the UART interface is used to connect to the host and transmit the log parsing result to the host, and output and display it on the serial port debugging software of the host. The SD card interface is used to connect to the SD memory card and transmit the log parsing result to the SD memory card, and the SD saves the parsing result into the SD memory card to save the complete parsing result, and can continue to analyze the log after the board is powered off. The on-chip interface controller includes a UART interface control module and an SD card interface control module, the UART interface control module is used to control the transmission of the UART interface, and the SD card interface control module is used to control the transmission of the SD card interface. The on-chip interface controller is connected to the on-chip processor through a processor bus, the bus architecture of the processor bus is the AMBA4 bus architecture, and the interface specification of the processor bus is AXI4.

[0041] This embodiment also provides an FPGA-based soft-hard collaborative NVME SSD log parsing method, using the above-mentioned log parsing system, including the following steps:

[0042] S1. Host request log: The host sends an NVME I / O command to the log parsing system. The on-chip processor of the log parsing system receives the NVME I / O command from the host through the on-chip interface controller and transmits the NVME I / O command to the logical end block storage controller;

[0043] S2. The logical end block storage controller reads the log data: After receiving the NVME I / O command from the host, the logical end block storage controller in the log parsing system starts the write data logic in the logical end block storage interface module, receives the log data transmitted from the storage simulation system, and stores it in the data buffer;

[0044] S3. The on-chip processor obtains log data: After completing a batch of log data writing, the logic-side block storage controller feeds back an interrupt signal to the on-chip processor through the logic-side block storage interface module. After receiving the interrupt signal, the on-chip processor drives the processor-side block storage controller to read the log data from the data buffer to the on-chip processor;

[0045] S4. The on-chip processor parses the log data: The on-chip processor parses the log data in detail to obtain the ID of the current NVME I / O access, the address of the current NVME I / O access, the data of the current NVME I / O access, the operation type of the current NVME I / O access, the status of the current NVME I / O access, the target medium of the current NVME I / O access and the I / O classification of the target device accessed, and obtain the number of accesses of each target medium type;

[0046] S5. The on-chip processor controller outputs the log analysis result: The on-chip processor calls the driver software to output the log analysis result obtained in step S4 to the host through the UART interface, and backs it up in the SD memory card through the SD card interface.

[0047] This embodiment proposes a log parsing system that can parse the NVME I / O log of the solid-state drive in detail and can distinguish the access information of NVME I / O to heterogeneous storage media. The work of the present invention is based on the NVME SSD storage simulation system of FPGA, and a NVME SSD log parsing system based on FPGA and hardware collaboration is designed. The on-chip processor is used to parse the NVME I / O log generated by the storage simulation system in detail according to a certain data structure, and can distinguish the access information of NVME I / O to heterogeneous storage media, thereby improving the problem of insufficient analysis of solid-state drive log information in existing work and filling the gap in the analysis of heterogeneous storage media I / O logs in solid-state drives. Finally, the results parsed from the log information are transmitted to the host in real time through the on-chip interface, and the results can also be written to the SD memory card. In this embodiment, the data bit width of the log is set to the maximum length of 64Byte commonly used by NVME I / O commands to leave sufficient space for flexible configuration of the structure of the log data. The log parsing system of this embodiment can record the content of NVME I / O commands completely and finely, and can perform detailed parsing of the field content of NVME I / O in a certain format, and also supports offline reading and analysis of logs, which improves the problem of insufficient log recording and insufficient analysis of NVME solid-state hard disks in previous work. In the logs recorded in this embodiment, according to the address division of different storage media, the access records of NVME I / O to different storage media can be distinguished, and the number of I / Os received by different media is given to debug the access proportion of NVME I / O to different storage media, and study the impact of different storage media on the overall performance of solid-state hard disks.

[0048] The embodiments of the present invention are given for the purpose of illustration and description, and are not intended to be exhaustive or to limit the invention to the disclosed forms. Many modifications and variations will be apparent to those of ordinary skill in the art. The embodiments are selected and described in order to better illustrate the principles and practical applications of the present invention and to enable those of ordinary skill in the art to understand the present invention and thereby design various embodiments with various modifications suitable for specific uses.

Claims

1. An NVME SSD log parsing system based on FPGA and software-hardware collaboration, characterized in that: It includes an on-chip processor, a logic-side block storage controller, a data buffer, a processor-side block storage controller, an on-chip interface controller, and an on-chip interface; The on-chip processor is connected to the on-chip interface controller, the logic end block storage controller and the processor end block storage controller, and the on-chip processor receives the NVME I / O command of the host through the on-chip interface controller, and transmits the NVME I / O command to the logic end block storage controller; One end of the logic end block storage controller is connected to the storage simulation system, and the other end is connected to the data buffer. The logic end block storage controller is used to read log data from the storage simulation system after receiving the NVME I / O command of the host, and transmit the log data to the data buffer. After the log data transmission is completed, the logic end block storage controller generates an interrupt signal, and transmits the interrupt signal to the on-chip processor; The data buffer is connected to the processor-side block storage controller, and the data buffer is used to store the log data and for the processor-side block storage controller to read the log data; The processor-side block storage controller is connected to the on-chip processor, the on-chip processor sends a read signal to the processor-side block storage controller according to the interrupt signal, the processor-side block storage controller is used to read the log data from the data buffer according to the read signal, and send the log data to the on-chip processor, the on-chip processor parses the log data, obtains a log parsing result, and transmits the log parsing result to the on-chip interface controller; The on-chip interface controller is connected to the on-chip interface, and the on-chip interface controller transmits the log analysis result to the host and the SD memory card through the on-chip interface; The on-chip interface is connected to a host and an SD memory card.

2. According to claim 1, a NVME SSD log parsing system based on FPGA and hardware collaboration, characterized in that: The on-chip processor includes a communication module, a log data parsing module, an access times counter and a driving module; The communication module is respectively connected to the on-chip interface controller, the logic end block storage controller, the processor end block storage controller, the log data parsing module, the access times counter and the driving module. The communication module is used to receive the NVME I / O command from the host of the on-chip interface controller, and transmit the NVME I / O command to the logic end block storage controller. The communication module is also used to receive an interrupt signal from the logic end block storage controller, and transmit the interrupt signal to the driving module. The driving module generates a read signal according to the interrupt signal and transmits it to the communication module. The communication module transmits the read signal to the processor end block storage controller. The communication module is also used to receive log data from the processor end block storage controller, and transmit the log data to the log data parsing module and the access times counter. The log data parsing module and the access times counter parse the log data to obtain the log parsing result, and transmit the log parsing result to the communication module. The communication module transmits the log parsing result to the on-chip interface controller; The log data parsing module is connected to the access count counter. After receiving the log data, the log data parsing module parses the fields in the log data according to the log data structure of the log data to obtain the ID of the current NVME I / O access, the address of the current NVME I / O access, the data of the current NVME I / O access, the operation type of the current NVME I / O access, the status of the current NVME I / O access, the target medium of the current NVME I / O access, and the I / O classification of the target device accessed, and the log data parsing module transmits the target medium of the current NVME I / O access to the access count counter; The access count counter determines the target medium type according to the target medium accessed by the current NVME I / O, adds one to the access count of the target medium type that has been accessed, obtains the access count of each target medium type, and sends the access count of each target medium type to the communication module; The driving module also transmits a driving signal for driving the on-chip interface controller to work to the communication module, and the communication module transmits the driving signal to the on-chip interface controller.

3. According to claim 2, a NVME SSD log parsing system based on FPGA and hardware collaboration, characterized in that: The log parsing result includes the ID of the current NVME I / O access, the address of the current NVME I / O access, the data of the current NVME I / O access, the operation type of the current NVME I / O access, the status of the current NVME I / O access, the target medium of the current NVME I / O access, the I / O classification of the accessed target device, and the I / O count of the accessed target device.

4. According to claim 2, a NVME SSD log parsing system based on FPGA and software-hardware collaboration, characterized in that: The logic end block storage controller includes a logic end bus interface module and a logic end block storage interface module connected to each other; The logic end bus interface module is connected to the communication module through a processor bus, and the logic end bus interface module is used to receive the NVME I / O command and transmit the NVME I / O command to the logic end block storage interface module; The logical end block storage interface module is also connected to the storage simulation system and the data buffer. The logical end block storage interface module reads the log data from the storage simulation system according to the NVME I / O command and transmits the log data to the data buffer. After the log data is written into the data buffer, the logical end block storage interface module generates an interrupt signal and transmits the interrupt signal to the logical end bus interface module, and the logical end bus interface module transmits the interrupt signal to the communication module.

5. According to claim 4, a NVME SSD log parsing system based on FPGA and software-hardware collaboration, characterized in that: The data buffer includes a logic end block storage controller port and a processor block storage controller port, the logic end block storage controller port is used to connect to the logic end block storage interface module, and the processor block storage controller port is used to connect to the processor block storage controller.

6. According to claim 5, the NVME SSD log parsing system based on FPGA and hardware collaboration is characterized in that: The processor-side block storage controller includes a processor-side bus interface module and a processor-side block storage interface module connected to each other; The processor-side bus interface module is connected to the communication module via a processor bus, and the processor-side bus interface module is used to receive the read signal and transmit the read signal to the processor-side block storage interface module; The processor-side block storage interface module is also connected to the data buffer. The processor-side block storage interface module reads the log data from the data buffer according to the read signal and transmits the log data to the processor-side bus interface module. The processor-side bus interface module transmits the log data to the communication module.

7. The NVME SSD log parsing system based on FPGA and software-hardware collaboration according to claim 1, characterized in that: The on-chip interface includes a UART interface and an SD card interface, the UART interface is used to connect to a host and transmit the log analysis result to the host, and the SD card interface is used to connect to an SD memory card and transmit the log analysis result to the SD memory card.

8. The NVME SSD log parsing system based on FPGA and software-hardware collaboration according to claim 7, characterized in that: The on-chip interface controller comprises a UART interface control module and an SD card interface control module, wherein the UART interface control module is used to control the transmission of the UART interface, and the SD card interface control module is used to control the transmission of the SD card interface.

9. The NVME SSD log parsing system based on FPGA and software-hardware collaboration according to claim 8, characterized in that: The on-chip interface controller is connected to the on-chip processor via a processor bus.

10. The NVME SSD log parsing system based on FPGA and software-hardware collaboration according to claim 9, characterized in that: The bus architecture of the processor bus is the AMBA4 bus architecture, and the interface specification of the processor bus is AXI4.

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