Layout legalization inspection and filling unit insertion method and device, equipment and medium

Abstract

The invention provides a layout legalization checking and filling unit insertion method and device, equipment and a medium, is applied to the technical field of integrated circuit design automation, simulates filling unit insertion in the legalization stage of integrated circuit design, detects potential violation problems in advance before the filling unit is actually inserted, and improves the accuracy of layout legalization checking and filling unit insertion. The legalization stage and the filling unit insertion stage cooperate with each other through unit movement to ensure that the physical circuit design does not violate the constraint of the ion implantation layer after the filling unit insertion stage, so that the compliance of the overall design is remarkably improved, and the layout design is enabled to meet the complicated process requirements and to be more convenient to use. And the design period is effectively shortened.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit design automation, and in particular to a layout legalization check and filling unit insertion method and device, equipment, and medium that consider ion implantation layer constraints in integrated circuit design. Background Art

[0002] In the physical implementation of integrated circuits, ion implantation layer technology plays a vital role. By dividing the layout into different areas and injecting different doses of ions, the threshold voltage of transistors in each area can be set. Especially in the design of integrated circuits at process nodes of 28 nanometers and below, ion implantation layer technology is widely used in multi-threshold voltage design to achieve a balance between power consumption and timing.

[0003] However, as the feature size of integrated circuits continues to decrease, the design rules of the implant layer have become more stringent. During the legalization stage and the filling cell insertion stage, it is necessary to check whether the design meets the process rules such as the minimum width and spacing within and between rows.

[0004] At present, among the existing schemes, some only consider the intra-row constraint rules, such as references [1-2]; some consider the inter-row constraint rules, but the consideration is not comprehensive, lacking the consideration of the minimum spacing constraint between rows, and most of them rely on heuristic algorithms, such as references [3-5]; some consider more comprehensive rules, but are only based on simple examples, and do not consider problems such as macro blocks in industrial examples, resulting in the final design being unable to meet the requirements of high performance and high reliability, such as reference [6].

[0005] In addition, existing schemes often only consider the constraints during legalization, but do not consider the requirements for inserting filler units.

[0006] Therefore, existing practices cannot fully comply with intra-industry and inter-industry constraints, resulting in the inability to meet the needs when the process node is reduced to 28nm and below.

[0007] Based on this, a new integrated circuit design method is needed.

[0008] References:

[0009] [1]Kahng AB,Lee H.Minimum implant area-aware gate sizing and placement[C] / / Proceedings of the 24th Edition of the Great Lakes Symposium onVLSI.2014:57-62.

[0010] [2]Tseng K H,Chang Y W,Liu C C C.Minimum-implant-area-aware detailedplacement with spacing constraints[C] / / Proceedings of the 53rd Annual DesignAutomation Conference.2016:1-6.

[0011] [3]Han K,Kahng AB,Lee H.Scalabledetailed placement legalization forcomplex sub-14nm constraints[C] / / 2015IEEE / ACM International Conference onComputer-Aided Design(ICCAD).IEEE,2015:867-873.

[0012] [4]Mak W K,Kuo W S,Zhang S H,et al.Minimum implant area-awareplacement and threshold voltage refinement[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2017,36(7):1103-1112.

[0013] [5]Chen G,Zeng Z,Zhu B,et al.Mixed-cell-height Placement withMinimum-Implant-Area and Drain-to-Drain Abutment Constraints[C] / / 2023 60thACM / IEEE Design Automation Conference(DAC).IEEE,2023:1-6.

[0014] [6]Zou P, Chen G, Lin Z, et al. Toward Optimal Filler Cell Insertion with Complex Implant Layer Constraints[C] / / 2023 60th ACM / IEEE Design Automation Conference (DAC). IEEE, 2023:1-6. Summary of the invention

[0015] In view of this, the embodiments of the present specification provide a layout legalization check and filling unit insertion method and device, equipment, and medium. By considering the optimal insertion strategy of the filling unit in advance in the legalization stage, combined with the lookup table generated according to the constraint form of the process node in the preprocessing stage, violations in the design can be quickly and accurately identified and repaired, which not only speeds up the speed of violation detection and repair, but also ensures that the design meets the strict process requirements of the ion implantation layer, thereby achieving comprehensive legalization of the layout design.

[0016] The embodiments of this specification provide the following technical solutions:

[0017] The embodiment of this specification provides a method for checking the legalization of an integrated circuit layout, including:

[0018] According to the process node and the ion implantation layer constraint, the circuit design layout is generated into a corresponding lookup table through dynamic programming; wherein the ion implantation layer constraint at least includes: a minimum width constraint within a row, a minimum spacing constraint within a row, a minimum width constraint between rows, and a minimum spacing constraint between rows; the lookup table includes: an inference mode lookup table and a violation mode lookup table;

[0019] Perform the following traversal on each unit to be laid out and the placement position to obtain the legalized layout result:

[0020] Try to place the current unit to be laid out at the currently designated placement position, then take the current unit to be laid out as the center, generate the current processing window according to the preset optimal size of the recognition window, and give an ion implantation layer in the current processing window, then perform pre-filling inference of the ion implantation layer on the blank sites in the current processing window according to the inference pattern lookup table, until no further inference can be made, finally determine whether there is a violation in the current processing window according to the violation pattern lookup table, and determine the corresponding unit to be laid out and the placement position for the next round of traversal according to the violation situation and the placement situation of other units that have been placed;

[0021] The cells to be laid out include logic cells and filling cells to be laid out.

[0022] This specification also provides a method for inserting a fill cell in an integrated circuit layout, comprising:

[0023] Based on any one of the integrated circuit layout legalization checking methods, a filling position corresponding to the filling unit is obtained;

[0024] Performing a filling process at the filling position;

[0025] The illegal pattern lookup table is used to perform a legality check on the filled filling unit.

[0026] The embodiment of the present specification also provides an integrated circuit layout legalization checking device, the integrated circuit layout legalization checking device comprising: a lookup table generation module and a layout generation module;

[0027] The lookup table generation module is used to generate a corresponding lookup table from the circuit design layout through dynamic programming according to the process node and the ion implantation layer constraint; wherein the ion implantation layer constraint at least includes: a minimum width constraint within a row, a minimum spacing constraint within a row, a minimum width constraint between rows, and a minimum spacing constraint between rows; the lookup table includes: an inference mode lookup table and a violation mode lookup table;

[0028] The layout generation module is used to perform the following traversal on each unit to be laid out and the placement position to obtain a legalized layout result:

[0029] Try to place the current unit to be laid out at the currently designated placement position, then take the current unit to be laid out as the center, generate the current processing window according to the preset optimal size of the recognition window, and give an ion implantation layer in the current processing window, then perform pre-filling inference of the ion implantation layer on the blank sites in the current processing window according to the inference pattern lookup table, until no further inference can be made, finally determine whether there is a violation in the current processing window according to the violation pattern lookup table, and determine the corresponding unit to be laid out and the placement position for the next round of traversal according to the violation situation and the placement situation of other units that have been placed;

[0030] The cells to be laid out include logic cells and filling cells to be laid out.

[0031] The embodiment of the present specification also provides an electronic device, including:

[0032] At least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute: any one of the integrated circuit layout legalization checking methods or the integrated circuit layout filling unit insertion methods.

[0033] The embodiments of the present specification also provide a computer storage medium, wherein the computer storage medium stores computer executable instructions, and when the computer executable instructions are executed by a processor, they perform: any one of the integrated circuit layout legalization checking methods, or any one of the integrated circuit layout filling unit insertion methods.

[0034] Compared with the prior art, the at least one technical solution adopted in the embodiments of this specification can achieve the following beneficial effects:

[0035] The present application simulates the insertion of filling cells in the legalization stage of integrated circuit design, detects potential violations in advance before the actual insertion of the filling cells, and eliminates violations by moving cells, thereby achieving coordination between the legalization stage and the filling cell insertion stage, ensuring that after the filling cell insertion stage, the physical circuit design does not violate the ion implantation layer constraints, thereby significantly improving the compliance of the overall design, allowing the layout design to effectively shorten the design cycle while meeting complex process requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0037] Figure 1 It is a schematic diagram of the effect of inserting a filling unit in this application;

[0038] Figure 2 It is a schematic diagram of the reasoning mode of the lookup table content in this application;

[0039] Figure 3 It is a schematic diagram of the violation mode of the lookup table content in this application;

[0040] Figure 4 It is a flow chart of the integrated circuit layout legalization checking method in this application. DETAILED DESCRIPTION

[0041] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0042] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0043] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspect described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0044] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0045] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the examples can be practiced without these specific details.

[0046] In the physical implementation of integrated circuits, the design of the ion implantation layer plays a vital role in determining the precise setting of the threshold voltage of the transistor, which directly affects the switching speed, power consumption and performance of the transistor. With the advancement of technology, the feature size continues to decrease, especially at process nodes of 28nm and below, and the design rules of the implantation layer have become more stringent, which puts higher requirements on the violation detection in the legalization stage and the filling cell insertion stage. It is necessary to check whether the design meets a series of process constraints including the minimum width and spacing within and between rows.

[0047] However, the existing mainstream legalization violation detection methods have some obvious shortcomings. Some methods only consider intra-row constraints and ignore the importance of inter-row constraints, which leads to a large number of adjustments in the subsequent design stage, which not only increases the design cycle and cost, but also causes the design to fail to meet the complex requirements of the new process node.

[0048] Although other methods take into account the constraints between rows, their coverage is not comprehensive, especially the lack of consideration of the minimum spacing constraints between rows, and they rely on heuristic algorithms. As the process nodes shrink and the design scale increases, it is difficult for them to adapt to the increase in design scale and the complexity of constraints. They cannot guarantee to find the optimal solution or an effective solution in complex situations, thus affecting the overall performance and reliability of the design.

[0049] Some methods, although they theoretically consider more comprehensive rules, are based only on simple examples and do not fully consider issues such as macroblocks in industrial applications, resulting in the final design failing to meet the requirements of high performance and high reliability. In addition, existing solutions often only focus on the constraints during legalization, while ignoring the requirements of the padding cell insertion stage, resulting in the need for redesign and verification when padding cell problems are discovered later, which increases the difficulty and risk of correction and prolongs the entire design cycle.

[0050] In view of this, the inventors discovered through research and improvement exploration that the existing legalization violation detection method does not fully consider the complexity of integrated circuit design, especially the neglect of inter-row constraints and filling cell insertion requirements, resulting in the final design being unable to meet the requirements of high performance and high reliability.

[0051] Based on this, the embodiment of this specification proposes a method for checking the legalization of integrated circuit layout: the overall idea is: through the lookup table generated in the preprocessing stage, the need for filling unit insertion is considered simultaneously in the legalization stage (such as Figure 1 As shown in the figure, the potential placement position of each unit is checked for compliance, and the lookup table is used to effectively identify violations and adjust positions. Through an iterative process, it is ensured that all units meet the process constraints, which significantly improves the compliance of the overall design. This allows the layout design to meet complex process requirements while effectively shortening the design cycle and reducing costs.

[0052] The technical solutions provided by various embodiments of the present application are described below in conjunction with the accompanying drawings.

[0053] like Figure 4 As shown, the embodiment of this specification provides an integrated circuit layout legalization checking method, comprising the following steps:

[0054] According to the process nodes and ion implantation layer constraints, a corresponding lookup table is generated from the circuit design layout through dynamic programming; wherein the ion implantation layer constraints include at least: a minimum width constraint within a row, a minimum spacing constraint within a row, a minimum width constraint between rows, and a minimum spacing constraint between rows; the lookup table includes: an inference mode lookup table and a violation mode lookup table.

[0055] Specifically, in the preprocessing stage of integrated circuit design, according to the circuit design layout that needs to be legalized and the ion implantation layer constraints corresponding to the process node, a lookup table is generated, including an inference mode lookup table (see Figure 2 ) and the violation pattern lookup table (see Figure 3 ), generates the optimal size of the recognition window, ensuring that when checking whether the cell placement is compliant, it will neither miss important design rules due to a small window nor introduce unnecessary complexity due to a large window.

[0056] Proper window size helps ensure that the ion implantation layer information within the window is sufficient for comprehensive compliance checks, including minimum width and spacing constraints within and between rows.

[0057] In combination with the above embodiment, the following traversal is performed on each unit to be laid out and the placement position to obtain a legalized layout result:

[0058] Try to place the current unit to be placed at the currently specified placement position, then generate the current processing window based on the preset optimal size of the recognition window with the current unit to be placed as the center, and give an ion implantation layer in the current processing window, then perform pre-filling reasoning of the ion implantation layer on the blank sites in the current processing window according to the reasoning pattern lookup table until no further reasoning can be done, finally determine whether there is a violation in the current processing window according to the violation pattern lookup table, and determine the position of the unit to be placed corresponding to the next round of traversal according to the violation situation and the placement situation of other units that have been placed;

[0059] The cells to be laid out include logic cells and filling cells to be laid out.

[0060] Specifically, when the legalization engine attempts to place a unit at a certain position, it cuts out a local area from the layout according to the optimal size of the recognition window to form the current processing window. Within the current processing window, it collects the ion implantation layer information of all relevant units, including the type of unit, ion implantation dose, implantation depth, etc. The ion implantation layer information of the current processing window is passed as input data to the violation identifier.

[0061] According to the ion implantation layer information provided by the legalization engine, the violation identifier fills in the blank sites in the current processing window according to the inference pattern lookup table generated by the preprocessing until no further inference is possible. After completing the filling inference, the violation identifier checks whether there are any violations in the current processing window according to the violation pattern lookup table, such as whether the current placement is compliant, or what violations exist, and feeds back the results of the compliance analysis to the legalization engine.

[0062] The legalization engine determines whether the current position is legal based on the feedback from the ion implantation layer violation identifier. If it is legal, the legalization engine will continue to process the next unit. If it is illegal, the legalization engine will search for the next possible placement position of the current unit and iterate the legalization process until all units are legally placed and the entire layout design meets the constraints of all ion implantation layers.

[0063] After the pre-placement attempts of all cells are completed and the entire layout meets all process constraints in the simulation check, the legalization engine will generate a preliminary legalized layout design.

[0064] It should be noted that the legalization stage provides a layout framework that meets the process requirements for the subsequent filling cell insertion stage. During the filling cell insertion stage, necessary adjustments and confirmations are made to the pre-placed cells to ensure that the final layout design not only meets the constraints of the ion implantation layer, but also optimizes the layout of the filling cells, significantly improving the compliance of the overall design and effectively shortening the design cycle while ensuring that the design meets strict requirements.

[0065] In some embodiments, when generating a lookup table, the allocation of each unit site is first determined according to the pattern size, and then it is determined whether the unit site is assigned a pattern of a specified type according to the allocation of the unit site, and if so, the unit site is recorded in a first pattern set, wherein the unit sites in the first pattern set do not need to be inferred and only need to determine whether the pattern is in violation;

[0066] The allocation of each unit site is determined by the following formula: ImplantType*2+1, where ImplantType represents the number of implant types of the process node; multiplication by 2 indicates allocation as a logic unit or a fill unit; addition of 1 indicates allocation as a macro block or other non-placeable area.

[0067] Specifically, the pattern size can be determined based on the provided ion implantation layer constraints. In order to fully consider all possible process constraints and design options, each cell site has ImplantType*2+1 possible allocations. The number of implant types of the process node is ImplantType. Multiplying by 2 means that each cell site can be a logic cell or a fill cell, which increases the flexibility of the design and allows optimization while meeting process constraints; plus 1 means that in addition to logic cells and fill cells, macro blocks or other non-placeable areas need to be considered to ensure that these special cases are included in the design.

[0068] A reasonable distribution situation can optimize the efficiency of the algorithm, thereby ensuring fast and accurate violation detection and layout adjustment during the legalization process, reducing the need for later corrections.

[0069] In some embodiments, a pattern set corresponding to each unit site is determined according to the number of allocations and the pattern size of each unit site, so that the patterns corresponding to the unit site are divided into corresponding pattern sets according to the allocation of the unit site in dynamic programming;

[0070] The total number of pattern sets is expressed as: N=M+1, where N>=1 and M represents the corresponding pattern size;

[0071] The first pattern set is used to characterize patterns in which each unit site is assigned a specific type; the second pattern set is used to characterize patterns in which only one unit site is unassigned; and the Nth pattern set is used to characterize patterns in which N-1 unit sites are unassigned.

[0072] Specifically, the process parameters determine the size of the pattern, and the size of each pattern and the number of allocations to each unit site determine the pattern set of the unit site.

[0073] For example, at a certain process node, there are two pattern sizes corresponding to 2 rows * 5 columns and 3 rows * 3 columns. Under each pattern size, the pattern set is determined according to the number of allocated unit sites. 2 rows * 5 columns will have the first pattern set to the eleventh pattern set, and 3 rows * 3 columns will have another first pattern set to the tenth pattern set, such as Figure 2 As shown, the pattern has four unassigned cell sites, so the pattern is divided into the fifth pattern set. By processing each pattern set in a targeted manner, unnecessary calculations can be reduced, the accuracy and efficiency of violation detection can be improved, and by generating a comprehensive lookup table, it supports fast and accurate compliance evaluation of cell placement in the legalization stage, thereby optimizing the entire integrated circuit design automation process.

[0074] In some embodiments, dynamic programming is used to detect each pattern set in sequence starting from the first pattern set until the Nth pattern set;

[0075] For the first pattern set, determining whether a pattern in the first pattern set violates a rule, and if so, adding the pattern to a lookup table, and updating the lookup table;

[0076] For the second pattern set, according to the process node and the ion implantation layer constraints, an unallocated unit site is allocated by dynamic programming, converted into a pattern in the first pattern set, and the lookup table is updated according to the converted situation;

[0077] For the Nth pattern set, dynamic programming will allocate one of the unallocated unit sites to obtain the pattern in the N-1th pattern set, and update the lookup table according to the conversion result in the N-1th pattern set.

[0078] Specifically, in the dynamic programming algorithm, the first pattern set P1 to which each unit site is assigned is first detected. Since each site in this set is assigned a specific type (corresponding to each site being occupied), such patterns do not require reasoning, and it is possible to directly determine whether the pattern is in violation.

[0079] Then, when a second pattern set P2 is detected in which there is an unassigned unit site, the unassigned unit site can be assigned in the pattern p of the set so as to be converted into a pattern in the set P1.

[0080] Afterwards, for the third pattern set P3 with two unassigned unit sites, a pattern in the set P2 can also be obtained by transforming one of the unassigned unit sites, and the subsequent process is the same as the above.

[0081] During implementation, for example, if a pattern has four unallocated unit sites, the pattern is divided into the fifth pattern set. Subsequently, an allocation attempt is made to one of the unallocated unit sites. If a unit allocation is determined for one of the unallocated sites, the pattern is converted into a pattern in the fourth pattern set, and the lookup table is updated according to the conversion result in the fourth pattern set to support subsequent design decisions and compliance checks.

[0082] It should be noted that the generated violation patterns and reasoning patterns will finally be organized according to the pattern size.

[0083] In some embodiments, when converting a pattern in the Nth pattern set into a pattern in the N-1th pattern set, the situation after the unassigned unit sites are assigned is judged:

[0084] If the allocation mode of any unallocated unit site leads to a violation mode, the current mode is identified as a violation mode, and the current mode is added to the violation mode lookup table;

[0085] If there is only one allocation method of the unassigned sites that can transform the current mode into a non-violation mode in the N-1th mode set, then establish an inference mode from the current mode to the non-violation mode, and add the current mode to the inference mode lookup table;

[0086] If there are two or more cases where the unassigned sites can be converted into non-violating patterns in the N-1th pattern set after assignment, the current pattern is not added to the lookup table.

[0087] Specifically, taking the conversion of a pattern in the second pattern set into a pattern in the first pattern set as an example, in implementation, when a pattern set P2 with an unassigned unit site is detected, in the pattern p of the set, the unassigned unit site can be allocated to be converted into a pattern in the set P1. There are three possibilities for this process:

[0088] (1) If the corresponding transformed patterns are all illegal patterns in set P1 regardless of how the site is assigned, then the pattern p is also an illegal pattern and is added to the lookup table;

[0089] (2) If there is only one transformation that can transform pattern p into a non-violating pattern in set P1, then a reasoning model from pattern p to the non-violating pattern can be established and added to the lookup table;

[0090] (3) If there are two or more transformations that can transform pattern p into a non-violating pattern in set P1, then it is not added to the lookup table.

[0091] In some embodiments, performing pre-filling reasoning of the ion implantation layer on the blank sites in the current processing window according to the reasoning pattern lookup table until no further reasoning can be performed includes:

[0092] According to the inference pattern lookup table, determining whether there is a blank site in the current processing window that must be assigned a specific ion implantation type;

[0093] If there is, the blank site is marked; otherwise, the filling reasoning ends and the violation detection mode is entered.

[0094] Specifically, when entering the legalization process, the legalization engine will provide a unit and a placement position each time to query whether it is legal to place the unit at the position. First, with the current unit as the center, the legalization engine needs to give a local window of the ion implantation layer according to the current placement situation. Then, according to the ion implantation layer situation of the local window, the violation identifier can combine the reasoning pattern in the lookup table to know whether there are some empty sites that must be assigned a specific ion implantation type. If there is no new filling in the reasoning, it means that the remaining blank sites are uncertain, and the violation pattern can be used to identify whether there is a violation in the current window.

[0095] In combination with the above embodiment, the violation situation is fed back to the legalization engine, and the legalization engine determines the cells and placement positions to be provided in the next round based on the violation situation and the placement of other cells. The process is repeated until all cells are traversed, and the legalization considering the ion implantation layer constraints can be completed.

[0096] This application considers the insertion of filler units in advance during the legalization stage (e.g. Figure 1 As shown in Figure 2, the algorithm combines the logic cells and the padding cells to determine whether there are any violations in the layout, that is, whether there is a legal padding cell insertion scheme during the legalization stage. Combined with the legalization engine, the algorithm can quickly detect the violations corresponding to the example injection layer constraints and feed them back to the legalization engine for repair.

[0097] Based on the same inventive concept, the present application provides a method for inserting a filling cell in an integrated circuit layout, comprising:

[0098] Based on any one of the integrated circuit layout legalization checking methods, a filling position corresponding to the filling unit is obtained;

[0099] Performing a filling process at the filling position;

[0100] The illegal pattern lookup table is used to perform a legality check on the filled filling unit.

[0101] Based on the same inventive concept, the present application also provides an integrated circuit layout legalization checking device, the integrated circuit layout legalization checking device comprising: a lookup table generation module and a layout generation module;

[0102] The lookup table generation module is used to generate a corresponding lookup table from the circuit design layout through dynamic programming according to the process node and the ion implantation layer constraint; wherein the ion implantation layer constraint at least includes: a minimum width constraint within a row, a minimum spacing constraint within a row, a minimum width constraint between rows, and a minimum spacing constraint between rows; the lookup table includes: an inference mode lookup table and a violation mode lookup table;

[0103] The layout generation module is used to perform the following traversal on each unit to be laid out and the placement position to obtain a legalized layout result:

[0104] Try to place the current unit to be laid out at the currently designated placement position, then take the current unit to be laid out as the center, generate the current processing window according to the preset optimal size of the recognition window, and give an ion implantation layer in the current processing window, then perform pre-filling inference of the ion implantation layer on the blank sites in the current processing window according to the inference pattern lookup table, until no further inference can be made, finally determine whether there is a violation in the current processing window according to the violation pattern lookup table, and determine the corresponding unit to be laid out and the placement position for the next round of traversal according to the violation situation and the placement situation of other units that have been placed;

[0105] The cells to be laid out include logic cells and filling cells to be laid out.

[0106] Based on the same inventive concept, the present application also provides an electronic device based on an integrated circuit layout legalization checking method, or an electronic device based on an integrated circuit layout filling unit insertion method, the electronic device comprising: a processor, a memory and a computer program; wherein

[0107] The memory is used to store the computer program, and the memory may also be a flash memory. The computer program is, for example, an application program, a functional module, etc. for implementing the above method.

[0108] The processor is used to execute the computer program stored in the memory to implement each step performed by the device in the above method. For details, please refer to the relevant description in the above method embodiment.

[0109] Optionally, the memory can be independent or integrated with the processor.

[0110] When the memory is a device independent of the processor, the device may further include:

[0111] A bus is used to connect the memory and the processor.

[0112] Based on the same inventive concept, the present application also provides a computer storage medium, which stores computer executable instructions. When the computer executable instructions are executed by a processor, they execute: the integrated circuit layout legalization checking method as described in any embodiment of the present application, or the integrated circuit layout filling unit insertion method.

[0113] It should be noted that the computer storage medium may include but is not limited to: a portable disk, a hard disk, a random access memory, a read-only memory, an erasable programmable read-only memory, an optical storage device, a magnetic storage device or any suitable combination thereof.

[0114] In a possible implementation, the present invention may also provide a form of a program product that implements data processing, which includes program code. When the program product runs on a terminal device, the program code is used to enable the terminal device to execute several steps of the method described in any of the aforementioned embodiments.

[0115] The program code for executing the present invention may be written in any combination of one or more programming languages, and may be executed entirely on a user device, partially on a user device, as an independent software package, partially on a user device and partially on a remote device, or entirely on a remote device.

[0116] This application provides an ion implantation layer violation detection algorithm at advanced integrated circuit process nodes (28nm process and below), so as to consider the insertion of fill cells in the legalization stage of layout, detect the corresponding violations in advance, and eliminate the violations by cell movement. By coordinating with the fill cell insertion stage, the algorithm can ensure that the physical circuit design after the fill cell insertion stage does not violate the ion implantation layer constraints.

[0117] In this specification, the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the embodiments described later, the description is relatively simple, and the relevant parts can be referred to the partial description of the previous embodiments.

[0118] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A method for checking the legalization of an integrated circuit layout, characterized in that: include: According to the process node and the ion implantation layer constraint, the circuit design layout is generated into a corresponding lookup table through dynamic programming; wherein the ion implantation layer constraint at least includes: a minimum width constraint within a row, a minimum spacing constraint within a row, a minimum width constraint between rows, and a minimum spacing constraint between rows; the lookup table includes: an inference mode lookup table and a violation mode lookup table; Perform the following traversal on each unit to be laid out and the placement position to obtain the legalized layout result: Try to place the current unit to be laid out at the currently designated placement position, then take the current unit to be laid out as the center, generate the current processing window according to the preset optimal size of the recognition window, and give an ion implantation layer in the current processing window, then perform pre-filling inference of the ion implantation layer on the blank sites in the current processing window according to the inference pattern lookup table, until no further inference can be made, finally determine whether there is a violation in the current processing window according to the violation pattern lookup table, and determine the corresponding unit to be laid out and the placement position for the next round of traversal according to the violation situation and the placement situation of other units that have been placed; The cells to be laid out include logic cells and filling cells to be laid out.

2. The integrated circuit layout legalization checking method according to claim 1, characterized in that: When generating the lookup table, the allocation of each unit site is first determined according to the pattern size, and then it is determined whether the unit site is assigned a specified type of pattern according to the allocation of the unit site. If so, the unit site is recorded in the first pattern set, wherein the unit sites in the first pattern set do not need to be inferred and only need to determine whether the pattern is in violation; The allocation of each unit site is determined by the following formula: ImplantType*2+1, where ImplantType represents the number of implant types of the process node; multiplication by 2 indicates allocation as a logic unit or a fill unit; addition of 1 indicates allocation as a macro block or other non-placeable area.

3. The integrated circuit layout legalization checking method according to claim 2, characterized in that: Determine the pattern set corresponding to each unit site according to the number of allocations and the pattern size of each unit site, so as to divide the patterns corresponding to the unit site into corresponding pattern sets according to the allocation of the unit site in dynamic programming; The total number of pattern sets is expressed as: N=M+1, where N>=1 and M represents the corresponding pattern size; The first pattern set is used to characterize patterns in which each unit site is assigned a specific type; the second pattern set is used to characterize patterns in which only one unit site is unassigned; and the Nth pattern set is used to characterize patterns in which N-1 unit sites are unassigned.

4. The integrated circuit layout legalization checking method according to claim 3, characterized in that: Using dynamic programming, starting from the first pattern set, each pattern set is tested in turn until the Nth pattern set; For the first pattern set, determining whether a pattern in the first pattern set violates a rule, and if so, adding the pattern to a lookup table, and updating the lookup table; For the second pattern set, according to the process node and the ion implantation layer constraints, an unallocated unit site is allocated by dynamic programming, converted into a pattern in the first pattern set, and the lookup table is updated according to the converted situation; For the Nth pattern set, dynamic programming will allocate one of the unallocated unit sites to obtain the pattern in the N-1th pattern set, and update the lookup table according to the conversion result in the N-1th pattern set.

5. The integrated circuit layout legalization checking method according to claim 4, characterized in that: When converting the patterns in the Nth pattern set into the patterns in the N-1th pattern set, the situation after the unassigned unit sites are assigned is judged: If the allocation mode of any unallocated unit site leads to a violation mode, the current mode is identified as a violation mode, and the current mode is added to the violation mode lookup table; If there is only one allocation method of the unassigned sites that can transform the current mode into a non-violation mode in the N-1th mode set, then establish an inference mode from the current mode to the non-violation mode, and add the current mode to the inference mode lookup table; If there are two or more cases where the unassigned sites can be converted into non-violating patterns in the N-1th pattern set after assignment, the current pattern is not added to the lookup table.

6. The integrated circuit layout legalization checking method according to claim 1, characterized in that: The pre-filling reasoning of the ion implantation layer is performed on the blank sites in the current processing window according to the reasoning pattern lookup table until no further reasoning is possible, including: According to the inference pattern lookup table, determining whether there is a blank site in the current processing window that must be assigned a specific ion implantation type; If there is, the blank site is marked; otherwise, the filling reasoning ends and the violation detection mode is entered.

7. A method for inserting a filling cell in an integrated circuit layout, characterized in that: include: Based on the integrated circuit layout legalization checking method according to any one of claims 1 to 6, obtaining a filling position corresponding to the filling unit; Performing a filling process at the filling position; The illegal pattern lookup table is used to perform a legality check on the filled filling unit.

8. An integrated circuit layout legalization checking device, characterized in that: The integrated circuit layout legalization checking device comprises: a lookup table generation module and a layout generation module; The lookup table generation module is used to generate a corresponding lookup table from the circuit design layout through dynamic programming according to the process node and the ion implantation layer constraint; wherein the ion implantation layer constraint at least includes: a minimum width constraint within a row, a minimum spacing constraint within a row, a minimum width constraint between rows, and a minimum spacing constraint between rows; the lookup table includes: an inference mode lookup table and a violation mode lookup table; The layout generation module is used to perform the following traversal on each unit to be laid out and the placement position to obtain a legalized layout result: Try to place the current unit to be laid out at the currently designated placement position, then take the current unit to be laid out as the center, generate the current processing window according to the preset optimal size of the recognition window, and give an ion implantation layer in the current processing window, then perform pre-filling inference of the ion implantation layer on the blank sites in the current processing window according to the inference pattern lookup table, until no further inference can be made, finally determine whether there is a violation in the current processing window according to the violation pattern lookup table, and determine the corresponding unit to be laid out and the placement position for the next round of traversal according to the violation situation and the placement situation of other units that have been placed; The cells to be laid out include logic cells and filling cells to be laid out.

9. An electronic device, characterized in that: include: at least one processor; And, a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute: the integrated circuit layout legalization checking method as described in any one of claims 1-6, or the integrated circuit layout filling unit insertion method as described in claim 7.

10. A computer storage medium, characterized in that: The computer storage medium stores computer executable instructions, and when the computer executable instructions are executed by the processor, they perform: the integrated circuit layout legalization checking method according to any one of claims 1 to 6, or the integrated circuit layout filling unit insertion method according to claim 7.

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