Image distortion correction device and image distortion correction method

Abstract

The invention discloses an image distortion correction device and an image distortion correction method, and relates to the technical field of image processing. The image distortion correction device comprises an interpolation range preprocessing circuit, a memory, a first register group, a control circuit and a pixel processing circuit. The interpolation range preprocessing circuit obtains a plurality of first mapping points according to a mapping table, and determines a first pixel set according to the plurality of first mapping points. The memory stores input image data. The control circuit confirms whether the input image data in the memory includes a first set of data corresponding to the first set of pixels, and stores the first set of data to the first register group when the input image data includes the first set of data. The pixel processing circuit performs a distortion correction according to the first set data in the first register group to generate a plurality of output pixel data, and generates an output image data accordingly.

Description

Technical Field

[0001] The present application relates to the field of image processing technology, and in particular to an image distortion correction device and an image distortion correction method. Background Art

[0002] Existing image distortion correction devices usually perform correction pixel by pixel, that is, the image distortion correction device can only generate one corrected pixel data in each distortion correction, and a large amount of static random access memory is required to store the original image data during the distortion correction, or multiple reads are required to obtain sufficient original image data from the static random access memory. This will result in poor overall efficiency and a large circuit area. Summary of the invention

[0003] One of the purposes of the present application is to provide an image distortion correction device and an image distortion correction method that can improve processing efficiency, so as to improve the deficiencies of the prior art.

[0004] In some embodiments, an image distortion correction device includes an interpolation range preprocessing circuit, a memory, a first register group, a control circuit, and a pixel processing circuit. The interpolation range preprocessing circuit obtains a plurality of first mapping points according to a mapping table, and determines a first pixel set according to the plurality of first mapping points. The memory stores an input image data. The control circuit confirms whether the input image data in the memory includes a first set data corresponding to the first pixel set, and stores the first set data to the first register group when the input image data includes the first set data. The pixel processing circuit performs a distortion correction according to the first set data in the first register group to generate a plurality of output pixel data, and generates an output image data accordingly.

[0005] In some embodiments, an image distortion correction method performed by an image distortion correction device includes the following operations: obtaining multiple first mapping points according to a mapping table, and determining a first pixel set according to the multiple first mapping points; confirming whether an input image data in a memory of the image distortion correction device includes a first set of data corresponding to the first pixel set, and storing the first set of data in a first register group of the image distortion correction device when the input image data includes the first set of data; and performing a distortion correction according to the first set of data in the first register group to generate multiple output pixel data, and generating an output image data accordingly.

[0006] The features, implementation and effects of the present application are described in detail below with reference to the accompanying drawings for a preferred embodiment. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 A schematic diagram of an image distortion correction device is drawn according to some embodiments of the present application;

[0008] Figure 2 According to some embodiments of the present application, Figure 1 A schematic diagram of the corresponding relationship between the input image data, the mapping table and the output image data;

[0009] Figure 3 According to some embodiments of the present application, Figure 1 A main operation flow chart of the image distortion correction device;

[0010] Figure 4 According to some embodiments of the present application, Figure 1 An operation diagram of a pipeline operation of an image distortion correction device; and

[0011] Figure 5 An operation flow chart of an image distortion correction method is drawn according to some embodiments of the present application.

[0012] Reference numerals:

[0013] 100: image distortion correction device;

[0014] 101: Processor;

[0015] 102, 120, 150: memory;

[0016] 111: direct memory access circuit;

[0017] 113: controller;

[0018] 115: register;

[0019] 130: interpolation range preprocessing circuit;

[0020] 140: control circuit;

[0021] 160, 170: register group;

[0022] 180: pixel processing circuit;

[0023] 201: pixel set;

[0024] 500: Image distortion correction method;

[0025] A0, B0, C0, D0: pixels;

[0026] A1, B1, C1, D1: multiple mapping points;

[0027] A2, B2, C2, D2: output pixels;

[0028] CLK: clock signal;

[0029] CMD: calibration command;

[0030] DIN: input image data;

[0031] DO: output image data;

[0032] DS1, DS2: collection data;

[0033] MT: mapping table;

[0034] S310, S320, S330, S340, S350, S360, S370: operation;

[0035] S510, S520, S530: operation;

[0036] SS1, SS2, SS3, SS4: interpolation area;

[0037] T0, T1, T2, T3, T4: period;

[0038] X_low, X_high, Y_low, Y_high: coordinates. DETAILED DESCRIPTION

[0039] All words used herein have their ordinary meanings. The definitions of the above words in commonly used dictionaries, including any use examples of the words discussed herein in the content of this application are only examples and should not limit the scope and meaning of this application. Similarly, this application is not limited to the various embodiments shown in this specification.

[0040] As used herein, "coupled" or "connected" may refer to two or more elements making direct physical or electrical contact with each other, or making indirect physical or electrical contact with each other, or may refer to two or more elements operating or acting on each other. As used herein, the term "circuit" may refer to a device composed of at least one transistor and / or at least one active and passive element connected in a certain manner to process signals.

[0041] Figure 1 A schematic diagram of an image distortion correction device 100 is drawn according to some embodiments of the present application. The image distortion correction device 100 includes a direct memory access circuit 111, a controller 113, a register 115, a memory 120, an interpolation range preprocessing circuit 130, a control circuit 140, a memory 150, a register group 160, a register group 170 and a pixel processing circuit 180.

[0042] The processor 101 may execute the image processing software and issue a correction instruction CMD to the register 115 to configure one or more control parameters in the register 115, thereby starting the image distortion correction device 100. In response to the correction instruction CMD, the memory 150 may start to store the input image data DIN until the storage space of the memory 150 is used up. In some embodiments, the input image data DIN may come from a dynamic random access memory (not shown) or from an image processing circuit (not shown). In some embodiments, the memory 150 may be, but not limited to, a static random access memory. At the same time, the controller 113 may configure the direct memory access circuit 111 based on one or more control parameters in the register 115, so that the direct memory access circuit 111 may write the mapping table MT from the memory 102 to the memory 120. In some embodiments, the memory 102 may be, but not limited to, a dynamic random access memory. In some embodiments, the mapping table MT is used to indicate the pixel correspondence between the input image data DIN and the output image data DO. In some embodiments, the mapping table MT may be provided by the manufacturer of the lens that generates the input image data DIN, but the present application is not limited thereto. For further explanation of the mapping table MT, please refer to Figure 2 describe.

[0043] The interpolation range preprocessing circuit 130 obtains a plurality of first mapping points (for example, Figure 2 A1, B1, C1 and D1 in the first mapping points, and determine a first pixel set (for example, Figure 2 In some embodiments, the interpolation range preprocessing circuit 130 may determine the plurality of pixels in the input image data DIN used to generate the plurality of first mapping points according to the interpolation operation in the image distortion correction algorithm, and set the first pixel set according to the positions of the plurality of pixels. In some embodiments, the image distortion correction algorithm may be a lens distortion correction algorithm. In some embodiments, the interpolation operation may be, but is not limited to, a bicubic interpolation operation. Further description of the first mapping point and the pixel set will be described later. Figure 2 describe.

[0044] The control circuit 140 confirms whether the input image data DIN in the memory 150 includes the set data DS1 corresponding to the aforementioned first pixel set. In some embodiments, the set data DS1 includes image information of all pixels in the first pixel set. If the input image data DIN in the memory 150 includes the set data DS1, the control circuit 140 may store the set data DS1 from the memory 150 to the register set 160. If the input image data DIN in the memory 150 does not yet include the set data DS1, the control circuit 140 may wait until the memory 150 stores the set data DS1 before writing the set data DS1 from the memory 150 to the register set 160. In some embodiments, the control circuit 140 may be implemented by a microcontroller or a digital signal processing circuit, but the present application is not limited thereto.

[0045] The pixel processing circuit 180 performs distortion correction according to the set data DS1 of the register group 160 to generate a plurality of output pixel data (e.g. Figure 2 The pixel processing circuit 180 may be configured to generate the output image data DO based on the image information of the plurality of output pixels A2, B2, C2 and D2 in the pixel processing circuit 180. For example, after generating all the output pixel data in the output image data, the pixel processing circuit 180 may combine the plurality of output pixel data and output the combined plurality of output pixel data as the output image data DO. In some embodiments, the pixel processing circuit 180 may be implemented by a processing circuit that can execute an image distortion correction algorithm, but the present application is not limited thereto.

[0046] Figure 2 According to some embodiments of the present application, Figure 1 Schematic diagram of the corresponding relationship between the input image data DIN, the mapping table MT and the output image data DO. Figure 2 As shown, the input image data DIN is an image that may have image distortion, and the output image data DO is an output image after image distortion correction. Generally speaking, when the installation position and angle of the sensor and lens that generate the image are fixed, the image distortion degree of the input image data DIN generated by the sensor is substantially constant. Therefore, through pre-calculation and measurement, the relative relationship between the pixel position in the input image data DIN generated by the sensor and lens and the pixel position in the corrected output image data DO can be obtained.

[0047] For example, it is assumed that the pixel processing circuit 180 can generate 4 output pixel data by performing one distortion correction (i.e., the pixel processing circuit 180 can process 4 pixels at a time). The output pixels A2, B2, C2, and D2 in the output image data DO correspond to the mapping points A1, B1, C1, and D1 in the mapping table MT. Through the calculation of the interpolation range preprocessing circuit 130, it can be confirmed that the mapping points A1, B1, C1, and D1 correspond to the pixels A0, B0, C0, and D0 in the input image data DIN, and the interpolation regions SS1, SS2, SS3, and SS4 corresponding to the pixels A0, B0, C0, and D0 are confirmed. In the input image data DIN, a plurality of pixels (including pixel A0) in the interpolation area SS1 can be used to interpolate the image information of the output pixel A2 (i.e., a stroke of output pixel data). Similarly, in the input image data DIN, a plurality of pixels (including pixel B0) in the interpolation area SS2 can be used to interpolate the image information of the output pixel B2 (i.e., a stroke of output pixel data). By analogy, the corresponding relationship between the plurality of interpolation areas SS1 to SS4, the plurality of pixels A0, B0, C0 and D0, the plurality of mapping points A1, B1, C1 and D1, and the plurality of output pixels A2, B2, C2 and D2 can be known. In some embodiments, the number of pixels in each of the plurality of interpolation areas SS1, SS2, SS3 and SS4 is determined according to the number of original pixels required by the image distortion correction algorithm to correct one pixel. For example, the number of original pixels can be, but is not limited to, 4×4 pixels.

[0048] Therefore, the interpolation range preprocessing circuit 130 may obtain a plurality of mapping points from the mapping table MT in sequence (for example, but not limited to, row by row) and obtain a plurality of corresponding pixels in the input image data DIN and a plurality of interpolation regions corresponding thereto according to the mapping points. Then, the interpolation range preprocessing circuit 130 may set a pixel set 201 according to the interpolation regions. For example, the upper rightmost position of the plurality of interpolation regions SS1 to SS4 is the coordinate X_high, the lower rightmost position is the coordinate Y_high, the lower leftmost position is the coordinate Y_low, and the corresponding upper leftmost position is the coordinate X_low. The interpolation range preprocessing circuit 130 may set the region formed by the coordinate X_high, the coordinate X_low, the coordinate Y_high, and the coordinate Y_low as the pixel set 201 (which may cover the plurality of interpolation regions SS1 to SS4).

[0049] In some embodiments, the aforementioned aggregate data DS1 is the image information of all pixels in the pixel set 201 in the input image data DIN. The control circuit 140 can confirm whether the input image data DIN stored in the memory 150 includes the aggregate data DS1. If so, the control circuit 140 can write the aggregate data DS1 from the memory 150 to the register set 160, so that the pixel processing circuit 180 can obtain the aggregate data DS1 from the register set 160, and perform distortion correction according to the aggregate data DS1 to generate a plurality of output pixel data (i.e., image information of a plurality of output pixels A2, B2, C2, and D2).

[0050] In some embodiments, each of the register group 160 and the register group 170 includes a plurality of registers (not shown), and the number of the plurality of registers may be determined based on a first value and a second value, wherein the first value is the number of output pixel data that can be generated by the pixel processing circuit 180 performing one distortion correction (for example, in Figure 2 For example, the first value is 4), and the second value is the number of pixels in the input image data DIN used to generate one of the multiple output pixel data. For example, as mentioned above, the number of pixels in each of the multiple interpolation areas SS1, SS2, SS3 and SS4 can be 4×4 pixels, that is, the second value is 16 (4×4). Under this condition, the number of the multiple registers can be N×M, where the value N can be less than or equal to the product of a factor of the first value and the second value (i.e. 4×4), and the value M can be less than or equal to the product of another factor of the first value and the second value (i.e. 4×4). Through the setting of the above multiple registers, it can be ensured that the data capacity of each of the register group 160 and the register group 170 is sufficient to store the image information of all original pixels required for the pixel processing circuit 180 to perform a distortion correction. In this way, the pixel processing circuit 180 can quickly obtain all the image information required to perform distortion correction from the register group 160 (and / or the register group 170) to more efficiently generate multiple output pixel data.

[0051] On the other hand, since the pixel processing circuit 180 obtains the plurality of image information to be corrected (e.g., the aggregate data DS1) from the register set 160 (and / or the register set 170) instead of reading the aggregate data DS1 from the memory 150, the pixel processing circuit 180 can quickly obtain the aggregate data DS1 in a short time. For example, the register set 160 and the register set 170 are operated as a first-in-first-out data buffer according to the clock signal CLK, which can be triggered according to the clock signal CLK to receive and / or output data. In some embodiments, the pixel processing circuit 180 can obtain the aggregate data DS1 within one clock cycle of the clock signal CLK.

[0052] In some related technologies, the distortion correction circuit obtains the image data to be corrected from the static random access memory to generate a corrected output pixel data. Since the distortion correction algorithm needs to use multiple original pixel data to interpolate and generate the corrected output pixel data, the distortion correction circuit needs to read from the static random access memory for multiple times to obtain the multiple original pixel data, resulting in reduced processing efficiency. Alternatively, in some other related technologies, a larger number of static random access memories are used to store multiple original pixel data to improve the efficiency of data transmission. However, this approach will cause the circuit area to be too large and the overall manufacturing cost to increase. Different from the above-mentioned related art, in some embodiments of the present application, the interpolation range preprocessing circuit 130 can read out multiple mapping points according to the mapping table MT (that is, at least 2 output pixel data can be generated at one time), the register group 160 (and / or the register group 170) can store the corresponding set data in the input image data DIN in advance, and the pixel processing circuit 180 obtains multiple image information to be corrected (for example, the set data DS1) from the register group 160 (and / or the register group 170), wherein the data capacity of each of the register group 160 and the register group 170 is set based on the correction capability of the pixel processing circuit 180. In this way, the data transmission efficiency and the distortion correction efficiency can be improved under the use of a certain amount of registers, and the number of static random access memories used will not be increased, so the overall manufacturing cost can be relatively saved.

[0053] In some embodiments, the register set 170 can store the set data (such as the set data DS2) corresponding to other mapping points during different operation periods to perform pipelined continuous operations together with the register set 160. In this way, the overall processing efficiency can be improved. The configuration method here will be referred to later. Figure 4 illustrate.

[0054] In some embodiments, the control circuit 140 may further determine whether the data size of the aggregate data DS1 exceeds the data capacity of the register set 160. If so, the control circuit 140 may store part of the data in the aggregate data DS1 from the memory 150 to the register set 160, and the data size of the part of the data is less than or equal to the data capacity of the register set 160. In this way, the pixel processing circuit 180 may perform distortion correction according to the part of the data to generate part of the pixel data in the plurality of output pixel data. If not, the control circuit 140 may store the entire aggregate data DS1 from the memory 150 to the register set 160.

[0055] For example, when the data size of the aggregate data DS1 exceeds the data capacity of the register set 160, the control circuit 140 may configure the relevant parameters in the register set 160 to reduce the number of output pixel data generated by the distortion correction performed by the pixel processing circuit 180 this time (for example, reducing the multiple output pixels A2, B2, C2, and D2 to the multiple output pixels A2 and B2). At the same time, the control circuit 140 may output the pixel data in the interpolation areas SS1 and SS2 corresponding to the multiple output pixels A2 and B2 in the aggregate data DS1 from the memory 150 as the aforementioned partial data, and store the partial data in the register set 160. In this way, the pixel processing circuit 180 may obtain the partial data from the register set 160, and generate the multiple output pixel data corresponding to the multiple output pixels A2 and B2 accordingly.

[0056] In some embodiments, during the above process, the control circuit 140 may further configure the relevant parameters in the register set 160 (and / or the register set 170) to indicate the corresponding position of the output pixel currently being processed. In this way, in the next operation, the control circuit 140 may continue to process the output pixels that have not yet been generated, so as to continue to read out the remaining data in the set data DS1 from the memory 150 (or merge them into the next set data). In this way, the pixel processing circuit 180 may continue to generate the remaining plurality of output pixel data to generate the output image data DO.

[0057] Figure 3 According to some embodiments of the present application, Figure 1 The main operation flow chart of the image distortion correction device 100 is shown in FIG. 1 . In operation S310, the processor 101 issues a correction instruction CMD to the image distortion correction device 100. In operation S320, the direct memory access circuit 111 obtains the mapping table MT from the memory 102 in response to the correction instruction CMD, and stores the mapping table MT in the memory 120. In operation S330, the memory 150 stores the input image data DIN. In operation S340, the interpolation range preprocessing circuit 130 obtains a plurality of mapping points according to the mapping table MT, and determines a pixel set according to the plurality of mapping points. In operation S350, the control circuit 140 stores the set data corresponding to the pixel set in the input image data DIN from the memory 150 to a corresponding register group in the register group 160 and the register group 170. In operation S360, the pixel processing circuit 180 performs distortion correction according to the set data of the corresponding register group to generate a corresponding plurality of output pixel data. In operation S370, after all the output pixel data are generated, the pixel processing circuit 180 generates the output image data DO accordingly.

[0058] In the above process, operation S340, operation S350 and operation S360 are multiple operations that are performed in a pipelined manner. The image distortion correction device 100 can generate multiple output pixel data in sequence by repeatedly performing the above operations until all image distortions in the input image data DIN are corrected. The part about pipeline operation will be referred to later. Figure 4 illustrate.

[0059] Figure 4 According to some embodiments of the present application, Figure 1 As described above, the image distortion correction device 100 can implement pipeline operation by setting a plurality of register groups 160 and register groups 170, thereby further improving the overall processing efficiency. Figure 4 As shown, the multiple operations of the image distortion correction device 100 can be divided into multiple stages of operation.

[0060] In the first stage of operation, the image distortion correction device 100 may perform the following operations in the period T0, the period T1, and the period T2, respectively. Figure 3 Operation S340, operation S350 and operation S360, wherein these operations in the first stage are based on multiple first mapping points in the mapping table MT.

[0061] Similarly, in the second stage of operation, the image distortion correction device 100 may perform the operation again during the period T1, the period T2, and the period T3. Figure 3 The operations S340, S350 and S360 of the second stage are based on the plurality of second mapping points in the mapping table MT. That is, during the period T1, when the control circuit 140 writes the set data DS1 from the memory 150 to the register group 160 (i.e., the operation S350 in the first stage), the interpolation range preprocessing circuit 130 can simultaneously obtain the plurality of second mapping points according to the mapping table MT, and determine the second pixel set according to the second mapping points (i.e., the operation S340 in the second stage), wherein the second pixel set is different from the first pixel set corresponding to the plurality of first mapping points). Similarly, during period T2, when the pixel processing circuit 180 performs distortion correction according to the set data DS1 to generate corresponding multiple output pixel data (i.e., operation S360 in the first stage), the control circuit 140 can confirm whether the input image data DIN in the memory 150 includes second set data corresponding to the second pixel set, and store the second set data to another register group 170 when the input image data DIN includes the second set data (i.e., operation S350 in the second stage).

[0062] In the third stage of operation, the image distortion correction device 100 may perform the operation again in the period T2, the period T3 and the period T4 respectively. Figure 3 Similarly, during the period T2, the interpolation range preprocessing circuit 130 can also simultaneously obtain a plurality of third mapping points according to the mapping table MT, and determine a third pixel set according to the third mapping points (i.e., operation S340 in the third stage). During the period T3, when the pixel processing circuit 180 performs distortion correction according to the second set data to generate a plurality of corresponding output pixel data (i.e., operation S360 in the second stage), the control circuit 140 can also confirm whether the input image data DIN in the memory 150 includes the third set data corresponding to the third pixel set, and store the third set data in the register group 160 when the input image data DIN includes the third set data (i.e., operation S350 in the third stage). By analogy, it can be understood that each circuit in the image distortion correction device 100 can perform multi-stage operations in a pipeline manner according to the mapping table MT during multiple periods to continuously process the pixel data to be corrected in the input image data DIN, thereby efficiently generating the output image data DO.

[0063] Each of the above-mentioned raw pixel data, aggregate data and / or output pixel data may include brightness data (i.e., Y component data) and chrominance data (i.e., U component data and V component data). Depending on actual application requirements, in different embodiments, the brightness data and the chrominance data may be stored in different memories, or in different storage spaces of the same memory.

[0064] Figure 5 The following is a flowchart of an image distortion correction method 500 according to some embodiments of the present application. In some embodiments, the image distortion correction method 500 may include, but is not limited to, Figure 1 The image distortion correction device 100 is implemented.

[0065] In operation S510, a plurality of first mapping points are obtained according to a mapping table, and a first pixel set is determined according to the plurality of first mapping points. In operation S520, it is confirmed whether an input image data in a memory of an image distortion correction device includes a first set of data corresponding to the first pixel set, and when the input image data includes the first set of data, the first set of data is stored in a first register group of the image distortion correction device. In operation S530, a distortion correction is performed according to the first set of data in the first register group to generate a plurality of output pixel data, and an output image data is generated accordingly.

[0066] The description of the multiple operations of the above-mentioned image distortion correction method 500 can refer to the above-mentioned multiple embodiments, so it will not be repeated here. The above-mentioned multiple operations are only examples and are not limited to being performed in the order in this example. Without violating the operation mode and scope of each embodiment of the present application, the various operations under the image distortion correction method 500 can be appropriately added, replaced, omitted or performed in a different order. Alternatively, one or more operations under the image enhancement method 500 can be performed simultaneously or partially simultaneously.

[0067] In summary, the image distortion correction device and the image distortion correction method provided in some embodiments of the present application can generate multiple output pixel data in one distortion correction, and can read the original pixel data to be used from the memory in advance through a mapping table, and implement pipeline operation by using multiple register groups. In this way, the efficiency of the overall image distortion correction can be effectively improved and the overall cost can be saved without using too much static random access memory.

[0068] Although the embodiments of the present application are described above, these embodiments are not intended to limit the present application. Technicians in this technical field may change the technical features of the present application based on the explicit or implicit contents of the present application. All these changes may fall within the scope of patent protection sought by the present application. The scope of patent protection of the present application shall be based on the scope of the patent application of this specification.

Claims

1. An image distortion correction device, characterized in that: include: an interpolation range preprocessing circuit, which obtains a plurality of first mapping points according to a mapping table, and determines a first pixel set according to the plurality of first mapping points; A memory for storing input image data; a first register group; a control circuit, which confirms whether the input image data in the memory includes a first set of data corresponding to the first pixel set, and stores the first set of data in the first register group when the input image data includes the first set of data; and A pixel processing circuit performs a distortion correction according to the first set of data in the first register group to generate a plurality of output pixel data, and then generates an output image data.

2. The image distortion correction device according to claim 1, characterized in that: The control circuit also determines whether the data size of the first set data exceeds the data capacity of the first register group, and stores a portion of the first set data to the first register group when the data size of the first set data exceeds the data capacity of the first register group, and the data size of the portion of the data is less than or equal to the data capacity of the first register group.

3. The image distortion correction device according to claim 2, characterized in that: When the data size of the first set data exceeds the data capacity of the first register group, the pixel processing circuit further performs the distortion correction according to the partial data to generate a portion of the pixel data among the plurality of output pixel data.

4. The image distortion correction device according to claim 1, characterized in that: The first register group includes multiple registers, and the number of the multiple registers is based on a first value and a second value, the first value is the number of data of the multiple output pixel data generated by the pixel processing circuit performing the distortion correction once, and the second value is the number of pixels in the input image data used to generate one of the multiple output pixel data.

5. The image distortion correction device according to claim 1, characterized in that: The interpolation range preprocessing circuit finds a plurality of pixels in the input image data for interpolating the plurality of output pixel data according to the plurality of first mapping points, and sets the first pixel set according to positions of the plurality of pixels.

6. The image distortion correction device according to claim 1, characterized in that: The pixel processing circuit obtains the first set of data from the first register group within one clock cycle.

7. The image distortion correction device according to claim 1, characterized in that: When the control circuit writes the first set of data from the memory to the first register group, the interpolation range preprocessing circuit also obtains a plurality of second mapping points according to the mapping table, and determines a second pixel set according to the plurality of second mapping points.

8. The image distortion correction device according to claim 7, characterized in that: The first set of pixels is different from the second set of pixels.

9. The image distortion correction device according to claim 1, characterized in that: Also includes: a second register group, wherein when the pixel processing circuit performs the distortion correction according to the first set data to generate the plurality of output pixel data, the control circuit confirms whether the input image data in the memory includes a second set data corresponding to a second pixel set, and stores the second set data in the second register group when the input image data includes the second set data, wherein the second set data corresponds to the data of the second pixel set determined by the interpolation range preprocessing circuit obtaining a plurality of second mapping points according to the mapping table.

10. A method for image distortion correction, characterized in that: Executed by an image distortion correction device, the image distortion correction method comprises: Obtaining a plurality of first mapping points according to a mapping table, and determining a first pixel set according to the plurality of first mapping points; confirming whether an input image data in a memory of the image distortion correction device includes a first set of data corresponding to the first pixel set, and storing the first set of data in a first register group of the image distortion correction device when the input image data includes the first set of data; and A distortion correction is performed according to the first set of data in the first register group to generate a plurality of output pixel data, and then an output image data is generated accordingly.

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