Defect analysis method, storage medium and terminal
By conducting machine learning model training on the characteristic parameters and defect locations of historical wafers, we can quickly predict the defect locations of wafers to be detected, solving the problems of low defect detection efficiency and long-term manual chasing in the existing technology, and improving production efficiency and yield.
Patent Information
- Application Number
- CN202411139400.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-16
- Publication Date
- 2024-12-13
AI Technical Summary
In the prior art, defect detection efficiency is low, potential defects are easily ignored, resulting in yield loss, and manual traceability is not timely.
By training and testing machine learning models on the characteristic parameters, key defects and potential defect locations of various layers of historical wafers, we can quickly predict the locations of key defects and potential defects that may arise during the process of the wafer to be detected, and reduce human misjudgment and labor time-consuming.
It improves the accuracy and efficiency of defect detection, reduces rework caused by cross-layer defects, and achieves better rates in a shorter time.
Smart Images
Figure CN119130928A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a defect analysis method, a storage medium and a terminal. Background Art
[0002] Integrated circuits are an important part of modern information technology and the electronics industry. With the continuous development of integrated circuit technology and the continuous improvement of integration, the manufacturing difficulty and cost of integrated circuits have also continued to rise. Yield is the last test step in the semiconductor manufacturing process, and it is also directly related to the chip mass production cost and corporate profits. Therefore, as the complexity of chip manufacturing increases, the yield research of integrated circuits has also deepened.
[0003] From the time a wafer is produced off the production line to the time it is shipped, the entire manufacturing process is a continuous stacking of hundreds of process steps, and defects may occur in each step. The final yield of the wafer is composed of the product of the yield of each process step. The yield of each process is crucial, so detecting defects in each layer is an important part of corporate production.
[0004] However, there are still many problems in the defect detection in the existing technology. Summary of the invention
[0005] The technical problem solved by the present invention is to provide a defect analysis method, a storage medium and a terminal to improve the defect detection efficiency.
[0006] In order to solve the above problems, the present invention provides a defect analysis method, including: providing a plurality of historical wafers, wherein the historical wafers have a plurality of historical integrated circuit layers, wherein the plurality of historical integrated circuit layers include a critical defect historical integrated circuit layer with a critical defect, and a potential defect historical integrated circuit layer that causes a critical defect; collecting characteristic parameters of the historical integrated circuit layer of each layer of each historical wafer, the position of the critical defect historical integrated circuit layer, and the position of the potential defect historical integrated circuit layer; providing a machine learning model; inputting the characteristic parameters of the historical integrated circuit layer of each layer of the historical wafer, the position of the critical defect historical integrated circuit layer, and the position of the potential defect historical integrated circuit layer into the machine learning model for model training; after the model training, inputting the characteristic parameters of the historical integrated circuit layer of each layer of the historical wafer into the trained machine learning model Model testing is performed in the process, and the position of the key defect test integrated circuit layer with the key defect and the position of the potential defect test integrated circuit layer causing the key defect are output based on the machine learning model; the position of the key defect test integrated circuit layer and the position of the potential defect test integrated circuit layer are compared with the corresponding position of the key defect history integrated circuit layer and the position of the potential defect history integrated circuit layer until the test accuracy reaches the preset accuracy, thereby completing the model testing of the machine learning model; a wafer to be inspected is provided, and the wafer to be inspected has several integrated circuit layers to be inspected; the characteristic parameters of the integrated circuit layers to be inspected in each layer of the wafer to be inspected are input into the machine learning model that completes the model testing, and the position of the key defect integrated circuit layer with the key defect and the position of the potential defect integrated circuit layer causing the key defect are output based on the machine learning model.
[0007] Optionally, the plurality of historical wafers are divided into a plurality of training wafers and a plurality of testing wafers.
[0008] Optionally, the number of the test wafers is greater than the number of the training wafers.
[0009] Optionally, the characteristic parameters of the historical integrated circuit layers of each layer of the training wafer, the locations of the key defect historical integrated circuit layers, and the locations of the potential defect historical integrated circuit layers are input into the machine learning model for model training.
[0010] Optionally, the characteristic parameters of the historical integrated circuit layers in each layer of the test wafer are input into the trained machine learning model for model testing.
[0011] Optionally, the method of training until the test accuracy reaches a preset accuracy includes: when the test accuracy of the machine learning model does not reach the preset accuracy, increasing the number of model training of the machine learning model until the test accuracy of the machine learning model reaches the preset accuracy.
[0012] Optionally, the method for increasing the number of model training times of the machine learning model includes: inputting the characteristic parameters of the historical integrated circuit layers of each layer of the historical wafer that failed the test during the test, the location of the historical integrated circuit layers with key defects, and the location of the historical integrated circuit layers with potential defects into the machine learning model for model training.
[0013] Optionally, the characteristic parameters include: temperature, current and material integrity.
[0014] Optionally, the material integrity includes: the density of the current material layer and the bonding between the current material layer and adjacent material layers.
[0015] Optionally, the material integrity is input into the machine learning model in the form of an image.
[0016] Optionally, the machine learning model includes: a neural network model or a random forest model.
[0017] Correspondingly, the technical solution of the present invention also provides a storage medium on which computer instructions are stored, and when the computer instructions are executed, the steps of the method described in any one of the above technical solutions are executed.
[0018] Correspondingly, the technical solution of the present invention also provides a terminal, including a memory and a processor, wherein the memory stores computer instructions that can be executed on the processor, and when the processor executes the computer instructions, the steps of the method described in any one of the above technical solutions are executed.
[0019] Compared with the prior art, the technical solution of the present invention has the following advantages:
[0020] In the defect analysis method of the technical solution of the present invention, the machine learning model is trained and tested through the characteristic parameters of the historical integrated circuit layers of each layer, the position of the key defect historical integrated circuit layer, and the position of the potential defect historical integrated circuit layer. After the machine learning model passes the test, the position of the key defect integrated circuit layer that will produce key defects in the process of the wafer to be inspected, and the position of the potential defect integrated circuit layer that causes the key defects can be quickly predicted based on the machine learning model. Through artificial intelligence, the potential defects associated with cross-layers can be identified and predicted, which reduces human misjudgment and manual time consumption, improves production efficiency, and can obtain better quality rates in a shorter time, avoiding rework in subsequent wafer fabrication caused by cross-layer defects as much as possible. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] Figure 1 is a flow chart of a defect analysis method according to an embodiment of the present invention;
[0022] Figures 2 to 4 It is a structural schematic diagram of each step of the defect analysis method according to an embodiment of the present invention. DETAILED DESCRIPTION
[0023] As described in the background art, there are still many problems with defect detection in the prior art, which will be described in detail below.
[0024] Currently, defect detection is mainly done by engineers interspersed between process steps to find problems, relying on human experience to gradually dissect and refine the defects found in the current station and the previous layer, and trace the cause and effect. This model has the following problems: potential defects are ignored, and they are transmitted to other layers and become key defects, causing yield loss; manual tracing of the cause and effect of the previous layer defects takes a long time and is not timely.
[0025] On this basis, the present invention provides a defect analysis method, a storage medium and a terminal, which train and test a machine learning model through the characteristic parameters of the historical integrated circuit layers of each layer, the position of the key defect historical integrated circuit layer, and the position of the potential defect historical integrated circuit layer. After the machine learning model passes the test, the position of the key defect integrated circuit layer that will produce key defects in the process of the wafer to be inspected, and the position of the potential defect integrated circuit layer that causes the key defects can be quickly predicted based on the machine learning model. Through artificial intelligence, it is possible to identify and predict potential defects associated with cross-layers, reduce human misjudgment and manual time consumption, improve production efficiency, and obtain a better rate in a shorter time, thereby avoiding rework in subsequent wafer fabrication caused by cross-layer defects as much as possible.
[0026] Figure 1 : is a flow chart of a defect analysis method according to an embodiment of the present invention, comprising:
[0027] Step S101, providing a plurality of historical wafers, wherein the historical wafers have a plurality of historical integrated circuit layers, wherein the plurality of historical integrated circuit layers include critical defect historical integrated circuit layers having critical defects and potential defect historical integrated circuit layers causing critical defects;
[0028] Step S102, collecting characteristic parameters of the historical integrated circuit layer of each layer of each historical wafer, the location of the critical defective historical integrated circuit layer, and the location of the potential defective historical integrated circuit layer;
[0029] Step S103, providing a machine learning model;
[0030] Step S104, inputting the characteristic parameters of the historical integrated circuit layers of each layer of the historical wafer, the positions of the critical defective historical integrated circuit layers, and the positions of the potential defective historical integrated circuit layers into the machine learning model for model training;
[0031] Step S105, after model training, inputting the characteristic parameters of the historical integrated circuit layers of each layer of the historical wafer into the trained machine learning model for model testing, and outputting the position of the key defect test integrated circuit layer with the key defect and the position of the potential defect test integrated circuit layer causing the key defect based on the machine learning model;
[0032] Step S106, comparing the position of the key defect test integrated circuit layer and the position of the potential defect test integrated circuit layer with the corresponding position of the key defect history integrated circuit layer and the position of the potential defect history integrated circuit layer until the test accuracy reaches a preset accuracy, thereby completing the model test of the machine learning model;
[0033] Step S107, providing a wafer to be inspected, wherein the wafer to be inspected has a plurality of integrated circuit layers to be inspected;
[0034] Step S108, input the characteristic parameters of the integrated circuit layer to be inspected in each layer of the wafer to be inspected into the machine learning model that completes the model test, and output the location of the critical defect integrated circuit layer with the critical defect and the location of the potential defect integrated circuit layer that causes the critical defect based on the machine learning model.
[0035] The following will describe in detail the various steps of the defect analysis method in conjunction with the accompanying drawings.
[0036] Figures 2 to 4 It is a structural schematic diagram of each step of the defect analysis method according to an embodiment of the present invention.
[0037] In step S101 , a plurality of historical wafers are provided, wherein the historical wafers have a plurality of historical integrated circuit layers 100 (IC layers), wherein the plurality of historical integrated circuit layers 100 include a critical defect historical integrated circuit layer 1001 having a critical defect and a potential defect historical integrated circuit layer 1002 causing a critical defect.
[0038] It should be noted that the historical wafers are wafers that have completed the process, and the process steps of each of the historical wafers are the same.
[0039] In step S102 , characteristic parameters of the historical integrated circuit layer 100 of each layer of each historical wafer, the position of the critical defective historical integrated circuit layer 1001 , and the position of the potential defective historical integrated circuit layer 1002 are collected.
[0040] In this embodiment, by collecting data on the characteristic parameters of the historical integrated circuit layer 100 of each layer of the wafer that has completed the process, the location of the key defect historical integrated circuit layer 1001, and the location of the potential defect historical integrated circuit layer 1002, these data will provide support for subsequent training and testing of the machine learning model.
[0041] It should be noted that, during the process of each of the historical wafers, the characteristic parameters of each layer of the historical integrated circuit layer 100 will be detected and saved, so when these data are needed, they only need to be called. In addition, the critical defect historical integrated circuit layer 1001 and the potential defect historical integrated circuit layer 1002 are cross-layer relationships, that is, when the characteristic parameters in the potential defect historical integrated circuit layer 1002 are abnormal, the parameters will be critical defects in the subsequently formed critical defect historical integrated circuit layer 1001, and the abnormality of the characteristic parameters in the potential defect historical integrated circuit layer 1002 will not produce critical defects that affect the yield in the current layer.
[0042] In this embodiment, the characteristic parameters include: temperature, current and material integrity.
[0043] In this embodiment, the material integrity includes: the compactness of the current material layer and the bonding between the current material layer and the adjacent material layer.
[0044] It should be noted that, since the material integrity is difficult to quantify in specific values using measurement tools, the material integrity is input into the subsequent machine learning model in the form of an image.
[0045] In this embodiment, since a large amount of data is required to support both the training and testing phases of the machine learning model, the number of historical wafers cannot be only one. In addition, the historical wafers need to be divided into a number of training wafers and a number of test wafers. The data of the training wafers will be used in the training phase of the machine learning model, and the data of the test wafers will be used in the testing phase of the machine learning model.
[0046] It should be noted that the ratio between the number of the training wafers and the number of the test wafers is not fixed, and usually the number of the test wafers is greater than the number of the training wafers.
[0047] Please refer to Figure 3 , in step S103, a machine learning model 200 is provided.
[0048] In this embodiment, the machine learning model 200 includes: a neural network model or a random forest model.
[0049] In step S104, the characteristic parameters of the historical integrated circuit layer 100 of each layer of the historical wafer, the position of the key defect historical integrated circuit layer 1001, and the position of the potential defect historical integrated circuit layer 1002 are input into the machine learning model 200 for model training.
[0050] In this embodiment, the characteristic parameters of the historical integrated circuit layer 100 of each layer of the training wafer, the position of the key defect historical integrated circuit layer 1001, and the position of the potential defect historical integrated circuit layer 1002 are input into the machine learning model 200 for model training.
[0051] In this embodiment, during the model training stage, the characteristic parameters of each layer of the historical integrated circuit layer 100 are taken as conditions, and the position of the key defect historical integrated circuit layer 1001 and the position of the potential defect historical integrated circuit layer 1002 are taken as results. The conditions and results are simultaneously input into the machine learning model 200, and the machine learning model 200 learns and establishes a mapping relationship by itself.
[0052] Please continue to refer to Figure 3 In step S105, after model training, the characteristic parameters of the historical integrated circuit layer 100 of each layer of the historical wafer are input into the trained machine learning model 200 for model testing, and the location of the key defect test integrated circuit layer with the key defect and the location of the potential defect test integrated circuit layer causing the key defect are output based on the machine learning model 200.
[0053] In this embodiment, the characteristic parameters of the historical integrated circuit layer 100 of each layer of the test wafer are input into the trained machine learning model 200 for model testing.
[0054] Please continue to refer to Figure 3 In step S106, the position of the key defect test integrated circuit layer and the position of the potential defect test integrated circuit layer are compared with the corresponding position of the key defect history integrated circuit layer 1001 and the position of the potential defect history integrated circuit layer 1002 until the test accuracy reaches the preset accuracy, thereby completing the model test of the machine learning model 200.
[0055] In this embodiment, the method of training until the test accuracy reaches the preset accuracy includes: when the test accuracy of the machine learning model 200 does not reach the preset accuracy, increasing the number of model training of the machine learning model 200 until the test accuracy of the machine learning model 200 reaches the preset accuracy.
[0056] In this embodiment, the method for increasing the number of model training times of the machine learning model 200 includes: inputting the characteristic parameters of the historical integrated circuit layer 100 of each layer of the historical wafer that failed the test during the test, the location of the key defect historical integrated circuit layer 1001, and the location of the potential defect historical integrated circuit layer 1002 into the machine learning model 200 for model training.
[0057] Please refer to Figure 4 In step S107 , a wafer to be inspected is provided, wherein the wafer to be inspected has a plurality of integrated circuit layers 300 to be inspected.
[0058] In this embodiment, the process of the wafer to be inspected is the same as the process of each of the historical wafers.
[0059] Please continue to refer to Figure 4 In step S108, the characteristic parameters of the integrated circuit layer 300 to be inspected in each layer of the wafer to be inspected are input into the machine learning model 200 that completes the model test, and the position of the critical defect integrated circuit layer 3001 with the critical defect and the position of the potential defect integrated circuit layer 3002 causing the critical defect are output based on the machine learning model 200.
[0060] The machine learning model 200 is trained and tested through the characteristic parameters of the historical integrated circuit layer 100 of each layer, the position of the key defect historical integrated circuit layer 1001, and the position of the potential defect historical integrated circuit layer 1002. After the machine learning model 200 passes the test, the machine learning model 200 can quickly predict the position of the key defect integrated circuit layer 3001 that will produce key defects in the process of the wafer to be inspected, and the position of the potential defect integrated circuit layer 3002 that causes the key defects. Through artificial intelligence, it is possible to identify and predict potential defects associated with cross-layers, reduce human misjudgment and manual time consumption, improve production efficiency, and obtain better quality rates in a shorter time, thereby avoiding rework in subsequent wafer fabrication caused by cross-layer defects as much as possible.
[0061] It should be noted that the potential defective integrated circuit layer 3002 predicted by the machine learning model is a layer of the integrated circuit layer 300 to be detected that has been formed in the wafer to be detected, while the key defective integrated circuit layer 3001 predicted by the machine learning model has not yet been formed on the wafer to be detected, that is, the integrated circuit layer 300 to be detected will be formed in the subsequent process.
[0062] Correspondingly, an embodiment of the present invention further provides a storage medium on which computer instructions are stored. When the computer instructions are executed, the steps of any one of the above-mentioned embodiment methods are executed.
[0063] Correspondingly, an embodiment of the present invention further provides a terminal, including a memory and a processor, wherein the memory stores computer instructions that can be executed on the processor, and when the processor executes the computer instructions, the steps of any one of the above-mentioned embodiment methods are executed.
[0064] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A defect analysis method, characterized in that: include: Providing a plurality of historical wafers, wherein the historical wafers have a plurality of historical integrated circuit layers, wherein the plurality of historical integrated circuit layers include critical defect historical integrated circuit layers having critical defects and potential defect historical integrated circuit layers causing critical defects; Collecting characteristic parameters of the historical integrated circuit layer of each layer of each historical wafer, the location of the critical defective historical integrated circuit layer, and the location of the potential defective historical integrated circuit layer; Provide machine learning models; Inputting the characteristic parameters of the historical integrated circuit layers of each layer of the historical wafer, the positions of the critical defective historical integrated circuit layers, and the positions of the potential defective historical integrated circuit layers into the machine learning model for model training; After model training, the characteristic parameters of the historical integrated circuit layers of each layer of the historical wafer are input into the trained machine learning model for model testing, and the location of the key defect test integrated circuit layer with the key defect and the location of the potential defect test integrated circuit layer causing the key defect are output based on the machine learning model; Comparing the position of the key defect test integrated circuit layer and the position of the potential defect test integrated circuit layer with the corresponding position of the key defect history integrated circuit layer and the position of the potential defect history integrated circuit layer until the test accuracy reaches a preset accuracy, thereby completing the model test of the machine learning model; Providing a wafer to be inspected, wherein the wafer to be inspected has a plurality of integrated circuit layers to be inspected; The characteristic parameters of the integrated circuit layers to be inspected in each layer of the wafer to be inspected are input into the machine learning model that completes the model test, and the location of the critical defective integrated circuit layer with the critical defect and the location of the potential defective integrated circuit layer that causes the critical defect are output based on the machine learning model.
2. The defect analysis method according to claim 1, characterized in that: The plurality of historical wafers are divided into a plurality of training wafers and a plurality of testing wafers.
3. The defect analysis method according to claim 1, characterized in that: The number of the test wafers is greater than the number of the training wafers.
4. The defect analysis method according to claim 2, characterized in that: The characteristic parameters of the historical integrated circuit layers of each layer of the training wafer, the locations of the key defect historical integrated circuit layers, and the locations of the potential defect historical integrated circuit layers are input into the machine learning model for model training.
5. The defect analysis method according to claim 2, characterized in that: The characteristic parameters of the historical integrated circuit layers in each layer of the test wafer are input into the trained machine learning model for model testing.
6. The defect analysis method according to claim 1, characterized in that: The method for training the machine learning model until the test accuracy reaches the preset accuracy includes: when the test accuracy of the machine learning model does not reach the preset accuracy, increasing the number of model training times of the machine learning model until the test accuracy of the machine learning model reaches the preset accuracy.
7. The defect analysis method according to claim 6, characterized in that: The method for increasing the number of model training times of the machine learning model includes: inputting the characteristic parameters of the historical integrated circuit layers of each layer of the historical wafer that failed the test during the test, the location of the critical defect historical integrated circuit layer, and the location of the potential defect historical integrated circuit layer into the machine learning model for model training.
8. The defect analysis method according to claim 1, characterized in that: The characteristic parameters include: temperature, current and material integrity.
9. The defect analysis method according to claim 8, characterized in that: The material integrity includes: the compactness of the material layer and the bonding between the material layer and the adjacent material layer.
10. The defect analysis method according to claim 8, characterized in that: The material integrity is input into the machine learning model in the form of an image.
11. The defect analysis method according to claim 1, characterized in that: The machine learning model includes: a neural network model or a random forest model.
12. A storage medium having computer instructions stored thereon, characterized in that: When the computer instructions are executed, the steps of the method according to any one of claims 1 to 11 are executed.
13. A terminal comprising a memory and a processor, wherein the memory stores computer instructions that can be executed on the processor, characterized in that: When the processor runs the computer instructions, the steps of the method according to any one of claims 1 to 11 are performed.