Electron source device, manufacturing method thereof and integrated circuit

Abstract

The invention provides an electron source device, a manufacturing method thereof and an integrated circuit. The electron source device comprises a substrate 1; the electron emission unit comprises a low-potential source region 111, a channel region 222, a highly-doped drain region 333, a grid 6, an electron acceleration layer 9, an insulating film 10 and a high-potential electron emitter conductive film 14, the highly-doped drain region 333 is formed on the first main surface of the substrate 1, the channel region 222 is located on the lower side of the highly-doped drain region 333, and the grid 6 is located on the lower side of the highly-doped drain region 333. The electron acceleration layer 9 is located on the surface of the highly-doped drain region 333, an insulating film 10 is arranged between the electron acceleration layer 9 and the high-potential electron emitter conductive film 14, the grid 6 is located on the transverse outer side of the channel region 222, and the low-potential source region 111 is formed in the substrate 1 and at least partially located below the grid 6. The electron emission efficiency can be improved, the resistance of the channel region is reduced, the service life of the electron source device is prolonged, and the electron emission stability is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to an electron source device and a manufacturing method thereof, and an integrated circuit. Background Art

[0002] With the development of semiconductor micro-fabrication industry, the requirements for electron beam direct writing technology are getting higher and higher, including the guarantee of accuracy of fine graphics imaging and the substantial improvement of direct writing speed.

[0003] In response to this industry demand, multi-electron beam direct writing technology is developing rapidly and plays an irreplaceable role in the direct writing of fine graphics in the manufacturing process of integrated circuit chips. Specifically, in the manufacturing of semiconductor integrated circuit chips, the imaging of high-tech node graphics (including the graphics of photomasks and the structural graphics of each level of the device) requires more precise and accurate direct writing, and also requires high-speed direct writing when the amount of graphic data increases dramatically.

[0004] From the perspective of accurate direct writing of fine graphics, the electron beam spot needs to be made smaller for precise scanning. When the current density remains unchanged, making the electron beam spot smaller means reducing the current of the electron beam, which results in a longer direct writing time. On the other hand, when the size of the graphics to be written is less than tens of nanometers, the smaller the line width, the more significant the impact of shot noise, which seriously affects the uniformity of the critical dimension and the roughness of the line edge.

[0005] In order to ensure that the critical line width uniformity and line edge roughness of small line width graphics are sufficient to meet product performance requirements, when writing graphics directly, the smaller the line width, the lower the sensitivity of the electron beam photoresist. As a result, the smaller the line width graphics, the greater the direct writing exposure required. This means that when the current density remains unchanged, the smaller the line width, the longer the direct writing time required. In order to improve the production capacity of electron beam direct writing equipment per unit time, a multi-electron beam direct writing machine that uses multiple electron beams to write simultaneously has become a necessary tool. In order to meet actual needs, the number of direct writing electron beams of a multi-electron beam direct writing machine needs to be around hundreds of thousands.

[0006] At present, the practical multi-electron beam direct writing machine generally uses a single electron source, and splits a source electron beam emitted from a single electron source into multiple direct writing electron beams. In order to increase the current density of the direct writing electron beam, it is necessary to increase the total current of the source electron beam. However, it is difficult to increase the total current of the source electron beam, and the increase in the current density of each direct writing electron beam is relatively limited. The best solution to these problems is to use a multi-source multi-beam electron source device in which each beam current can be controlled.

[0007] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0008] Porous silicon prepared by photoelectrochemical etching can be applied to the preparation of electron sources. For example, single crystal silicon or columnar polycrystalline silicon materials can be used to prepare cold field emission electron sources. Figure 1 is a porous silicon electron source structure and a voltage V is applied across the porous silicon electron source structure PS Energy band diagram when .

[0009] like Figure 1 As shown in (a), when voltage Vps is applied to both ends of the electron source device, hot electrons are injected from the N-type silicon substrate into the broadband porous silicon region. The injected electrons are continuously accelerated by the electric field, reaching the top gold (Au) film by a quasi-ballistic transport mechanism, and penetrating the Au film by a tunneling mechanism to be emitted into the vacuum. This is the cold field electron emission current. Therefore, the porous silicon electron source device has the characteristics of high electron emission collimation, concentrated energy, and stable emission current. Using semiconductor integrated circuit process technology and micro-electromechanical system (MEMS) process technology, integrated porous silicon electron source devices can be prepared to achieve multi-source and multi-beam functions.

[0010] The inventors of the present application have found that the existing porous silicon electron source devices have the following problems: Figure 1 (b) shows the problem of large resistance of N-type silicon substrate. As the size of electron source devices becomes smaller, the resistance of N-type silicon substrate becomes larger and larger. When voltage Vps is applied to both ends of the electron source device, most of Vps falls on this large resistance, generating useless Joule heat, causing the degradation of the characteristics of the electron source device, leading to damage to the electron source device, and seriously affecting the life of the electron source device.

[0011] In order to solve the above problems or at least similar problems, the embodiments of the present application provide an electron source device and a manufacturing method thereof, and an integrated circuit. In the electron source device of the present application, when the metal oxide semiconductor (MOS) field effect transistor formed around the active area is turned on, electrons can be directly provided from the low potential source area to the electron acceleration layer, thereby improving the electron emission efficiency, reducing the resistance of the channel area, solving the heating problem caused by large resistance, and improving the life of the electron source device and the stability of electron emission. In addition, it is convenient to mass-produce electron source devices with good uniformity using advanced micro-electromechanical systems (MEMS) processes.

[0012] According to one aspect of an embodiment of the present application, an electron source device is provided, wherein the transistor device comprises:

[0013] a substrate 1; and

[0014] Electron emission unit,

[0015] The electron emission unit comprises:

[0016] The low potential source region 111, the channel region 222, the highly doped drain region 333, the gate 6, the electron acceleration layer 9, the insulating film 10 and the high potential electron emitter conductive film 14,

[0017] in,

[0018] The highly doped drain region 333 is formed on the first main surface of the substrate 1.

[0019] The channel region 222 is located at the lower side of the highly doped drain region 333.

[0020] The electron acceleration layer 9 is located on the surface of the highly doped drain region 333.

[0021] The insulating film 10 is disposed between the electron acceleration layer 9 and the high potential electron emitter conductive film 14.

[0022] The gate 6 is located laterally outside the channel region 222 , and the low potential source region 111 is formed in the substrate 1 and is at least partially located below the gate 6 .

[0023] According to another aspect of an embodiment of the present application, a method for manufacturing an electron source device is provided, for manufacturing the electron source device described in the above embodiment, the method comprising:

[0024] A highly doped drain region 333, a channel region 222 and a low potential source region 111 are formed in a substrate 1, wherein the highly doped drain region 333 is formed on the first main surface of the substrate 1, the channel region 222 is located at the lower side of the highly doped drain region 333, and the low potential source region 111 is at least partially located laterally outside the channel region 222 and at least partially located below the channel region 222;

[0025] Forming an electron acceleration layer 9 on the surface of the highly doped drain region 333;

[0026] A gate insulating film 4, 5 and a gate 6 are sequentially formed on the lateral outer side of the channel region 222; and

[0027] An insulating film 10 and a high potential electron emitter conductive film 14 are sequentially formed on the surface of the electron acceleration layer 9 .

[0028] The beneficial effect of the present application is that: in the electron source device of the present application, when the metal oxide semiconductor (MOS) field effect transistor formed around the active area is turned on, electrons can be directly provided from the low potential source area to the electron acceleration layer, thereby improving the electron emission efficiency, reducing the resistance of the channel area, solving the heating problem caused by large resistance, and improving the life of the electron source device and the stability of electron emission. In addition, it is convenient to mass-produce electron source devices with good uniformity using advanced micro-electromechanical system (MEMS) technology.

[0029] With reference to the following description and accompanying drawings, the specific embodiments of the present application are disclosed in detail, indicating the way in which the principles of the present application can be adopted. It should be understood that the embodiments of the present application are not limited in scope. Within the scope of the spirit and clauses of the appended claims, the embodiments of the present application include many changes, modifications and equivalents.

[0030] Features described and / or illustrated with respect to one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0031] It should be emphasized that the term “include / comprises” when used herein refers to the presence of features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps or components. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The included drawings are used to provide a further understanding of the embodiments of the present application, which constitute a part of the specification, are used to illustrate the implementation methods of the present application, and together with the text description, explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0033] Figure 1 is a porous silicon electron source structure and an energy band diagram when a voltage is applied across the porous silicon electron source structure;

[0034] Figure 2 is a schematic diagram of the electron source device of the present application;

[0035] Figure 3 is a schematic diagram of a method for manufacturing an electron source device of the present application;

[0036] Figures 4 to 26 1 is a schematic diagram of the device structure of each step of the manufacturing method of the electron source device 100. DETAILED DESCRIPTION

[0037] With reference to the accompanying drawings, the above and other features of the present application will become apparent through the following description. In the description and the accompanying drawings, specific embodiments of the present application are specifically disclosed, which show some embodiments in which the principles of the present application can be adopted. It should be understood that the present application is not limited to the described embodiments. On the contrary, the present application includes all modifications, variations and equivalents falling within the scope of the attached claims.

[0038] In the description of the various embodiments of the present application, for the convenience of description, the direction parallel to the first main surface of the substrate is called "lateral", the direction perpendicular to the first main surface of the substrate is called "longitudinal", and the dimension in the "longitudinal" direction can be called "height" or "thickness"; in the "longitudinal" direction, the direction from the first main surface of the first substrate to the channel region is called the "up" direction, and the opposite direction to the "up" direction is the "down" direction.

[0039] It should be noted that the above-mentioned “up” direction and “down” direction are only for the convenience of explanation and do not limit the orientation or posture of the electron source device of the present application during manufacture or use.

[0040] An embodiment of the present application provides an electron source device.

[0041] Figure 2 Schematic diagram of the electron source device of the present application. Figure 2 As shown, the electron source device 100 comprises: a substrate 1; and an electron emission unit. The electron source emission unit comprises: a low potential source region 111, a channel region 222, a highly doped drain region 333, a gate 6, an electron acceleration layer 9, an insulating film 10 and a high potential electron emitter conductive film 14.

[0042] like Figure 2 As shown, the highly doped drain region 333 is formed on the first surface (e.g., the upper surface) of the substrate 1; the channel region 222 is located at the lower side of the highly doped drain region 333, the electron acceleration layer 9 is located on the surface of the highly doped drain region 333, an insulating film 10 is provided between the electron acceleration layer 9 and the high potential electron emitter conductive film 14, and the gate 6 is located laterally outside the channel region 222. The low potential source region 111 is formed in the substrate 1, and is at least partially located below the gate 6, for example, the low potential source region 111 is located laterally outside the channel region 222 and below the gate 6.

[0043] like Figure 2 As shown, the electron source device 100 further includes: a low-voltage back metal electrode 12 , which is disposed on the second main surface (eg, the lower surface) of the substrate 1 .

[0044] In at least one embodiment, the substrate 1 may be, for example, an N-type silicon substrate. The channel region 222 may be, for example, an undoped silicon epitaxial layer or an undoped columnar polysilicon layer. The impurity concentration of the low potential source region 111 and / or the highly doped drain region 333 is 5×10 19 cm -3 The thickness of the high potential electron emitter conductive film 14 is 0.1-10 nm, and the material is one or more of metal, conductive compound, and conductive two-dimensional material. The thickness of the gate 6 is equal to or greater than the thickness of the channel region 222. The material of the gate 6 is a highly doped semiconductor material, or a metal material.

[0045] like Figure 2 As shown, there may be a gate insulating film between the channel region 222 and the gate 6, and the gate 6 is electrically connected to the gate electrode 11. The thickness of the gate insulating film is 1 to 30 nm. The material of the gate insulating film is silicon dioxide and / or silicon nitride. For example, the gate insulating film includes a silicon dioxide (SiO2) film 4 and a silicon nitride (Si3N4) film 5. In addition, the gate insulating film can also extend laterally between the low potential source region 111 and the gate 6.

[0046] The shape of the channel region 222 is a cylinder, a cube, or a cuboid. The lateral dimension of the channel region 222 (e.g., the diameter of the cylinder, the side length of the cube, or the short side length of the cuboid) is 0.05-30 μm; the longitudinal dimension of the channel region 222 (e.g., the height) is 0.5-7 μm.

[0047] In at least one embodiment, the material of the electron acceleration layer 9 may be porous silicon or porous polycrystalline silicon. The electron acceleration layer 9 may have a plurality of semiconductor grains independent of each other, and an insulating medium of a predetermined thickness is provided between adjacent semiconductor grains, and the insulating medium includes, for example, silicon oxide SiO2. The thickness of the electron acceleration layer 9 is 0.1 to 5 μm, and the characteristic size of the semiconductor grains is 1 to 50 nm; the predetermined thickness of the insulating medium is, for example, 0.3 to 2 nm. Under the isolation of the insulating medium, adjacent semiconductor grains are formed into a semiconductor grain chain structure with an insulating layer, and the direction of the semiconductor grain chain structure is perpendicular to the first main surface of the substrate 1.

[0048] like Figure 2 As shown, the electron source device 100 may also include a silicon dioxide (SiO2) film 7 and a silicon nitride (Si3N4) film 8. The silicon dioxide (SiO2) film 7 and the silicon nitride (Si3N4) film 8 are vertically stacked between the gate 6 and the electron emitter metal lead 13, wherein the electron emitter metal lead 13 is electrically connected to the high potential electron emitter conductive film 14.

[0049] In the present application, the channel region 222, the gate insulating film, the gate 6, the low potential source region 111, and the highly doped drain region 333 form a MOS field effect transistor with a vertical channel. The gate 6 is, for example, a gate all around (GAA) structure that surrounds the sidewall of the channel region 222 in the horizontal direction.

[0050] The working principle of the electron source device 100 of the present application is as follows.

[0051] When a voltage V is applied between the electron emitter metal lead 13 and the back metal electrode 12 PS When the electron emitter metal lead 13 is at a positive voltage and the back metal electrode 12 is at a ground or negative voltage, hot electrons are injected from the low potential source region 111 into the channel region 222, and the electrons are transferred to the highly doped drain region 333 (e.g., a highly doped N-type silicon drain region) under the action of the electric field, and injected into the electron acceleration layer 9, where the injected electrons are accelerated by the electric field and transferred to the high potential electron emitter conductive film 14 by a quasi-ballistic transport mechanism, and tunnel through the conductive film and are emitted into the surrounding space (e.g., vacuum). When a positive voltage VG is applied to the gate metal electrode 11, the gate 6 (e.g., n + By turning on (ON) the n-channel MOS field effect transistor on the side wall of the active area, electrons can be directly provided from the low potential source area 111 to the highly doped drain area 333, thereby reducing the resistance of the channel area 222 and allowing Vps to effectively fall on the electron acceleration layer 9, solving the heating problem, and improving the life of the electron source device and the electron emission efficiency. The emission current can also be controlled by adjusting VG.

[0052] Since the electron source device of the present application is based on the planar cold field electron emission mechanism and quasi-ballistic electron emission, the emitted electron energy has small chromatic aberration, stable performance and long service life. In addition, it is convenient to use MEMS technology for manufacturing, so the manufactured devices have good uniformity, small size, can be integrated, and can realize multi-source multi-beam electron source devices.

[0053] An embodiment of the present application further provides an integrated circuit, which may include at least one electron source device 100 .

[0054] The embodiment of the present application also provides a method for manufacturing an electron source device, which is used to manufacture the electron source device 100 .

[0055] Figure 3 is a schematic diagram of the manufacturing method of the electron source device, such as Figure 3 As shown, the manufacturing method includes:

[0056] 301, forming a highly doped drain region 333, a channel region 222 and a low potential source region 111, wherein the highly doped drain region 333 is formed on the first main surface of the substrate 1, the channel region 222 is located at the lower side of the highly doped drain region 333, and the low potential source region 111 is at least partially located laterally outside the channel region 222, and at least partially located below the channel region 222;

[0057] 302. Forming an electron acceleration layer 9 on the surface of the highly doped drain region 333;

[0058] 303 , forming a gate insulating film and a gate 6 in sequence on the lateral outer side of the channel region 222 ; and

[0059] 304 . An insulating film 10 and a high-potential electron emitter conductive film 14 are sequentially formed on the surface of the electron acceleration layer 9 .

[0060] In addition, the method also includes: vertically stacking a silicon dioxide (SiO2) film 7 and a silicon nitride (Si3N4) film 8 on the surface of the gate 6; forming an electron emitter metal lead 13 on the surface of the silicon nitride (Si3N4) film 8; forming a gate metal electrode 11 and a back metal electrode 12, etc.

[0061] For descriptions of materials and dimensions involved in each step, reference may be made to the related descriptions of the electron source device 100 .

[0062] In some embodiments of operation 302, the step of forming the electron acceleration layer 9 includes:

[0063] 3021. Growing an undoped silicon epitaxial layer on the surface of the substrate 1, and forming an N-type silicon region on the top of the undoped silicon epitaxial layer;

[0064] 3022. Perform photoelectrochemical etching on the N-type silicon region formed on the top to form porous silicon; and

[0065] 3023. Perform a passivation process on the porous silicon to form a nanocrystalline grain chain structure containing an insulating layer.

[0066] In some other embodiments of operation 302, the step of forming the electron acceleration layer 9 includes:

[0067] 3021a, growing an undoped columnar polysilicon layer on the surface of the substrate, and forming an N-type polysilicon region on the top of the columnar polysilicon layer;

[0068] 3022a, performing photoelectrochemical etching on the N-type polysilicon region formed on the top to form porous polysilicon; and

[0069] 3023a. Perform a passivation process on the porous polycrystalline silicon to form a nanocrystalline grain chain structure containing an insulating layer.

[0070] The following describes the method for manufacturing the electron source device according to the embodiment of the present application with reference to specific examples.

[0071] The specific process methods listed in the following examples are only examples, and the present application is not limited thereto.

[0072] Figures 4 to 26 Schematic diagram of the device structure of each step of the manufacturing method of the electron source device 100. Figures 4 to 26 As shown, the manufacturing method of the electron source device 100 includes the following steps (1) to (21):

[0073] (1) Figure 4 As shown, a P-type (100) silicon substrate is prepared as the substrate 1, and its resistivity is 0.01 to 0.5 Ωcm.

[0074] (2) Figure 5 As shown, an active area photoresist pattern 1000 is formed by photolithography, and the shape of the pattern is circular (with a diameter of 0.05 to 30 μm), or positive direction (with a side length of 0.05 to 30 μm), or rectangular (with a short side length of 0.05 to 30 μm). Figure 6 Schematic diagram of active area photoresist pattern 1000, showing examples of circle, square, rectangle, etc.

[0075] (3) Figure 7 As shown, the P-type silicon 1 around the active area photoresist pattern 100 is etched by reactive ion etching (RIE) and other methods to form a step structure 102. The height of the step 102 is 1 to 15 μm. After etching, the photoresist is removed by oxygen plasma or sulfuric acid plus hydrogen peroxide to form an island active area 101, which is in the shape of a cylinder, a cube, or a cuboid.

[0076] (4) Figure 8 As shown, a silicon dioxide (SiO2) film 103 is deposited by low pressure chemical vapor deposition (LPCVD) method, and the thickness thereof is 200 to 300 nm.

[0077] (5) Fig. 9 As shown, the silicon dioxide (SiO2) film 103 is etched by RIE method to form a sidewall SiO2 film 104 and bare silicon surfaces 105 and 106 at the same time.

[0078] (6) Fig.10 As shown, a highly doped N-type source region (ie, a low potential source region) 111 is prepared by ion implantation or thermal diffusion, and a highly doped N-type region 33 is formed on the top of the active region with a thickness of 0.1 to 3 μm, and a channel region 222 is formed at the same time.

[0079] The doping elements of the highly doped N-type source region 111 and the highly doped N-type region 33 are group V elements such as phosphorus, antimony, and arsenic, and the implantation dose is 2×10 15 cm 2 above.

[0080] If ion implantation is used for doping, an annealing process at a temperature above 600 degrees is performed after the ion implantation. The annealing atmosphere is a forming gas (a mixture of hydrogen and nitrogen) or 100% nitrogen. The thickness of the highly doped N-type source region 111 and the highly doped N-type region 33 can be controlled by adjusting the annealing temperature and time. If thermal diffusion is used for doping, the thickness of the highly doped N-type source region 111 and the highly doped N-type region 33 can be controlled by adjusting the diffusion temperature and time.

[0081] (7) Fig.11 As shown, after the annealing is completed, a wet etching method (for example, using an HF solution) is used to completely etch the SiO2 film on the side walls of the active area 101 and the back side of the P-type silicon substrate 1 to form bare silicon side walls 107 and a bare silicon substrate back side 108.

[0082] (8) Fig.12 As shown, a silicon dioxide (SiO2) film 4 is deposited by the LPCVD method with a thickness of 1 to 10 nm, followed by a silicon nitride (Si3N4) film 5 with a thickness of 1 to 10 nm.

[0083] (9) Fig.13 As shown, using the LPCVD method, n + The thickness of the polysilicon film must be greater than the height 101 of the active area.

[0084] Then, a chemical mechanical polishing (CMP) method is used to planarize the top nitride (Si3N4) silicon film 5 of the active area 101.

[0085] Then, the RIE method is used to etch n + Polysilicon, forming n + The polysilicon gate 6 also forms a step structure 109 with a depth of 0.03 to 2.8 μm.

[0086] n +The structure of the polysilicon gate 6 is a Gate all around (GAA) structure, and the top of the polysilicon gate 6 is higher than the bottom of the highly doped N-type silicon region 33 .

[0087] (10) Fig.14 As shown, a silicon dioxide (SiO2) film 7 is deposited by LPCVD method, and its thickness is greater than the height of the step 103. Then, CMP is used to planarize the silicon nitride film 5 on the top of the active area 101. Then, a silicon nitride (Si3N4) film 8 is deposited by LPCVD method, and its thickness is 20-50nm.

[0088] (11) Fig.15 As shown, a photoresist is used to protect the surface, and a multi-layer film such as a silicon nitride (Si3N4) film, a silicon dioxide (SiO2) film, and a polysilicon film on the back is removed by RIE method to form a bare silicon back 110. Then, an oxygen plasma method or a method such as sulfuric acid plus hydrogen peroxide is used to remove the surface photoresist.

[0089] (12) Fig.16 As shown, an opening pattern 111 is formed on the top of the active area 101 by a photolithography method, and other areas are protected by a photoresist 112.

[0090] (13) Fig.17 As shown, the silicon nitride (Si3N4) films 8 and 5 are etched to the surface of the silicon dioxide (SiO2) film 4 by RIE method. Then, the silicon dioxide (SiO2) film 4 is etched by diluted hydrofluoric acid (DHF, Diluted HF) solution to expose the highly doped N-type silicon surface 113. Then, the surface photoresist is removed by oxygen plasma method, sulfuric acid plus hydrogen peroxide method, etc.

[0091] (14) Fig.18 As shown, a porous silicon layer 114 is prepared by photoelectrochemical etching method, and its thickness is 0.01-2.7 μm. Under the porous silicon layer 114, a highly doped N-type silicon drain region 333 with a thickness of more than 50 nm is left.

[0092] (15) Fig.19As shown, thermal oxidation or electrochemical oxidation (ECO) is used to oxidize the nano-silicon grains in the porous silicon, so that a 1-2 nm thick oxide layer (SiO2) grows on the surface of the nano-silicon grains in the porous silicon. Then, high pressure water vapor annealing (HWA) and super critical rinsing and drying (SCRD) are immediately performed to form a porous silicon electron acceleration layer 9. The porous silicon electron acceleration layer 9 is composed of nano-silicon grain chains with a 1-2 nm thick oxide film (SiO2) formed on the surface, and the direction of the nano-silicon grain chain is perpendicular to the surface of the silicon substrate, as shown in FIG. Fig. 20 shown.

[0093] (16) Fig.21 As shown, an insulating film 10 with a thickness of 1 to 2 nm is deposited on the surface of the porous silicon electron acceleration layer 9 by an atomic layer deposition (ALD) method (if the oxide layer in step 15 is thick enough to be more than 2 nm, this insulating film may not be used). The insulating film material is at least one of the following materials: SiO2, ZrO2, Si3N4, HfO2, Al2O3, etc.

[0094] (17) Fig. 22 As shown, a contact hole pattern is formed by photolithography, a silicon nitride (Si3N4) film 8 is etched by RIE, and a silicon dioxide (SiO2) film 7 is etched by RIE or wet etching to expose n + The contact hole 115 is formed on the surface of the polysilicon. Then, the surface photoresist is removed by using an oxygen plasma method or a method such as sulfuric acid plus hydrogen peroxide.

[0095] (18) Fig.23 As shown, a sputtering method is used to deposit an Al metal film, the thickness of which is greater than the thickness of the silicon nitride (Si3N4) film 8 plus the thickness of the silicon dioxide (SiO2) film 7. Then, a photolithography method is used to form a gate lead electrode pattern, and a RIE method or a wet etching method is used to prepare a gate metal electrode 11. Then, an oxygen plasma method is used to remove the surface photoresist.

[0096] (19) Fig.24 As shown, the surface is protected by photoresist, and the back is etched by RIE and wet etching to form a bare silicon surface. Then, an Al metal film is deposited by sputtering to form a back metal electrode 12 with a thickness of 100 to 300 nm. Then, the surface photoresist is removed by oxygen plasma. Then, annealing is performed for 30 minutes in a forming gas (hydrogen and nitrogen mixed gas) atmosphere at 450 to 500°C to form an ohmic contact.

[0097] (20) Fig.25 As shown, photolithography, sputtering (or evaporation) and lift-off methods are used to prepare the electron emitter metal lead 13. The metal film material and its thickness are Au / Cr=200-300 / 10nm, or Au / Ti=200-300 / 10nm.

[0098] (21) Fig.26 As shown, photolithography, sputtering (or evaporation) and lift-off methods are used to prepare the high potential electron emitter conductive film 14. The high potential electron emitter conductive film material and its thickness are Au / Ti≦10 / 1nm, or Au / Cr≦10 / 1nm, or a single atomic layer graphene film.

[0099] The present application is described above in conjunction with specific implementation methods, but it should be clear to those skilled in the art that these descriptions are exemplary and are not intended to limit the scope of protection of the present application. Those skilled in the art can make various modifications and variations to the present application based on the spirit and principles of the present application, and these modifications and variations are also within the scope of the present application.

Claims

1. An electron source device, characterized in that: The electron source device comprises: a substrate (1); and Electron emission unit, The electron emission unit comprises: A low potential source region (111), a channel region (222), a highly doped drain region (333), a gate (6), an electron acceleration layer (9), an insulating film (10) and a high potential electron emitter conductive film (14), in, The highly doped drain region (333) is formed on the first main surface of the substrate (1), The channel region (222) is located at the lower side of the highly doped drain region (333), The electron acceleration layer (9) is located on the surface of the highly doped drain region (333), The insulating film (10) is arranged between the electron acceleration layer (9) and the high-potential electron emitter conductive film (14). The gate (6) is located laterally outside the channel region (222), The low potential source region (111) is formed in the substrate (1) and is at least partially located below the gate (6).

2. The electron source device according to claim 1, characterized in that The electron source device further comprises: A low-voltage back metal electrode (12) is arranged on the second main surface of the substrate (1).

3. The electron source device according to claim 1, characterized in that The electron acceleration layer (9) comprises a plurality of semiconductor crystal grains which are independent of each other, and an insulating medium of a predetermined thickness is provided between adjacent semiconductor crystal grains, wherein the insulating medium comprises silicon oxide (SiO2).

4. The electron source device according to claim 3, characterized in that The thickness of the electron acceleration layer (9) is 0.1 to 5 μm, and the characteristic size of the semiconductor grains is 1 to 50 nm.

5. The electron source device according to claim 3, characterized in that The predetermined thickness of the insulating medium is 0.3-2 nm. Under the isolation of the insulating medium, the adjacent semiconductor grains form a semiconductor grain chain structure with an insulating layer, and the direction of the semiconductor grain chain structure is perpendicular to the first main surface of the substrate.

6. The electron source device according to claim 1, characterized in that The thickness of the high potential electron emitter conductive film (14) is 0.1-10 nm, and the material is one or more of metal, conductive compound and conductive two-dimensional material.

7. The electron source device according to claim 1, characterized in that A gate insulating film (4, 5) is provided between the channel region (222) and the gate (6), Furthermore, the gate insulating film (4, 5) extends laterally between the low potential source region (111) and the gate (6). The gate (6) is electrically connected to the gate electrode (11).

8. The electron source device according to claim 7, characterized in that The shape of the channel region (222) is a cylinder, a cube, or a cuboid. The channel region (222) has a lateral dimension of 0.05 to 30 μm and a longitudinal dimension of 0.5 to 7 μm.

9. The electron source device according to claim 7, characterized in that The impurity concentration of the low potential source region (111) and / or the highly doped drain region (333) is 5×10 19 cm -3 above.

10. The electron source device according to claim 7, characterized in that The lateral dimension of the gate insulating film (4, 5) is 1 to 30 nm, The material of the gate insulating film (4, 5) is silicon dioxide and / or silicon nitride.

11. The electron source device according to claim 1, characterized in that The thickness of the gate (6) is equal to or greater than the thickness of the channel region (222), and the material of the gate (6) is a highly doped semiconductor material or a metal material.

12. An integrated circuit, characterized in that: The integrated circuit comprises at least one electron source device according to any one of claims 1 to 11.

13. A method for manufacturing an electron source device, for manufacturing the electron source device according to any one of claims 1 to 11, characterized in that: The method comprises: A highly doped drain region (333), a channel region (222) and a low potential source region (111) are formed in a substrate (1), wherein the highly doped drain region (333) is formed on a first main surface of the substrate (1), the channel region (222) is located below the highly doped drain region (333), and the low potential source region (111) is at least partially located laterally outside the channel region (222) and at least partially located below the channel region (222); forming an electron acceleration layer (9) on the surface of the highly doped drain region (333); forming a gate insulating film (4, 5) and a gate (6) in sequence on the lateral outer side of the channel region (222); and An insulating film (10) and a high-potential electron emitter conductive film (14) are sequentially formed on the surface of the electron acceleration layer (9).

14. The method for manufacturing an electron source device according to claim 13, wherein: The step of forming the electron acceleration layer (9) comprises: Growing an undoped silicon epitaxial layer on the surface of the substrate, and forming an N-type silicon region on the top of the undoped silicon epitaxial layer; Performing photoelectrochemical etching on the N-type silicon region formed on the top to form porous silicon; and A passivation process is performed on the porous silicon to form a nanocrystalline grain chain structure containing an insulating layer.

15. The method for manufacturing an electron source device according to claim 13, wherein: The step of forming the electron acceleration layer (9) comprises: Growing an undoped columnar polysilicon layer on the surface of the substrate, and forming an N-type polysilicon region on the top of the columnar polysilicon layer; Performing photoelectrochemical etching on the N-type polysilicon region formed on the top to form porous polysilicon; and A passivation process is performed on the porous polycrystalline silicon to form a nanocrystalline grain chain structure containing an insulating layer.

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