Method for improving reliability of device

Abstract

The invention provides a method for improving the reliability of a device, and the method comprises the steps: 1, providing a substrate, forming an interlayer dielectric layer on the substrate, forming a groove in the interlayer dielectric layer, and sequentially forming a high-K dielectric layer and a cap layer on the side wall and the bottom of the groove; 2, sequentially forming a barrier layer and a PMOS (P-channel Metal Oxide Semiconductor) work function metal layer on the cap layer, and then removing the PMOS work function metal layer in an NMOS (N-channel Metal Oxide Semiconductor) region; 3, reducing oxide layers formed on the surfaces of the barrier layer and the PMOS work function metal layer by using hydrogen; 4, nitriding the surface of the barrier layer and the surface of the PMOS work function metal layer by using ammonia gas; and 5, sequentially forming an NMOS (N-channel Metal Oxide Semiconductor) work function metal layer and a metal gate, and filling the groove. Before the NMOS work function metal layer is formed, the pretreatment procedures of hydrogen reduction and ammonia nitridation are added, the work function adjusting effect of the PMOS work function metal layer is achieved while the anti-etching capacity of the barrier layer is improved, and therefore the reliability of the device is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for improving device reliability. Background Art

[0002] In the high-K metal gate process, tantalum nitride (TaN) is often used as an etch barrier metal layer, titanium nitride (TiN) is used as a PMOS work function metal layer, and an NMOS work function metal layer TiAl is grown on them.

[0003] TaN / TiN metal layers are easily oxidized, and the oxidized TAN / TIN will have an adverse effect on the stability of the device. For TiN, the N in Ti-N will be replaced by O atoms due to oxidation to form TiO and TiON, and the work function adjustment ability of TiO and TiON is much worse than that of TiN. For TaN, since the oxidized part of Ta-N forms Ta-O, and the etching resistance of TaO is much worse than that of TaN, it cannot protect the high-K dielectric layer well, causing loss of electrical stability. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a method for improving device reliability, which is used to solve the problem in the prior art that the TaN / TiN metal layer is easily oxidized, resulting in poor device stability.

[0005] To achieve the above objectives and other related objectives, the present application provides a method for improving device reliability, comprising:

[0006] Step 1, providing a substrate, on which an interlayer dielectric layer is formed, a trench is formed in the interlayer dielectric layer, and a high-K dielectric layer and a cap layer are sequentially formed on the sidewall and bottom of the trench;

[0007] Step 2: forming a barrier layer and a PMOS work function metal layer on the cap layer in sequence, and then removing the PMOS work function metal layer located in the NMOS region;

[0008] Step 3, using hydrogen to reduce the oxide layer formed on the surface of the barrier layer and the PMOS work function metal layer;

[0009] Step 4, using ammonia gas to nitride the surfaces of the barrier layer and the PMOS work function metal layer;

[0010] Step 5: Form an NMOS work function metal layer and a metal gate in sequence to fill the trench.

[0011] Preferably, the process conditions for hydrogen reduction in step three include but are not limited to using plasma bombardment or pure chemical reduction at a temperature of 200°C to 450°C.

[0012] Preferably, the process conditions for ammonia nitridation in step 4 are: using chemical vapor reaction, a flow rate of 5slm to 25slm, and a temperature of 320°C to 800°C.

[0013] Preferably, the interlayer dielectric layer and the high-K dielectric layer are formed by chemical vapor deposition process.

[0014] Preferably, the capping layer is formed by an atomic layer deposition process or a chemical vapor deposition process.

[0015] Preferably, the barrier layer is formed by an atomic layer deposition process or a chemical vapor deposition process.

[0016] Preferably, the material of the barrier layer includes tantalum nitride.

[0017] Preferably, the PMOS work function metal layer is formed by an atomic layer deposition process.

[0018] Preferably, the material of the PMOS work function metal layer includes titanium nitride.

[0019] Preferably, the NMOS work function metal layer is formed by a physical magnetron sputtering process or an atomic layer deposition process.

[0020] As described above, the method for improving device reliability provided by the present application has the following beneficial effects: before forming the NMOS work function metal layer, adding hydrogen (H 2 ) reduction and ammonia (NH 3 ) The nitridation pretreatment process increases the etching resistance of the barrier layer while covering the work function adjustment effect of the PMOS work function metal layer, thereby improving device reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1 A flow chart showing a method for improving device reliability provided by an embodiment of the present application is shown. DETAILED DESCRIPTION

[0023] The following describes the implementation of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0024] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0025] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating directions or positional relationships, are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0026] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0027] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0028] See also Figure 1 , which shows a flow chart of a method for improving device reliability provided in an embodiment of the present application.

[0029] like Figure 1 As shown, the method for improving device reliability includes the following steps:

[0030] Step 1, providing a substrate, on which an interlayer dielectric layer is formed, a trench is formed in the interlayer dielectric layer, and a high-K dielectric layer and a cap layer are sequentially formed on the sidewall and bottom of the trench;

[0031] Step 2: forming a barrier layer and a PMOS work function metal layer on the cap layer in sequence, and then removing the PMOS work function metal layer located in the NMOS region;

[0032] Step 3, using hydrogen to reduce the oxide layer formed on the surface of the barrier layer and the PMOS work function metal layer;

[0033] Step 4, using ammonia gas to nitride the surfaces of the barrier layer and the PMOS work function metal layer;

[0034] Step 5: Form an NMOS work function metal layer and a metal gate in sequence to fill the trench.

[0035] In step 1, optionally, the substrate is a silicon substrate, a germanium substrate, or a silicon-on-insulator substrate, etc.; or the material of the substrate may also include other materials, such as III-V compounds such as gallium arsenide. Those skilled in the art can select the constituent material of the substrate according to the type of device structure formed on the substrate, so the type of the substrate should not limit the protection scope of the present invention.

[0036] Optionally, the material of the interlayer dielectric layer is, for example but not limited to: silicon nitride (Si 3 N 4 ), silicon oxide (SiO 2 ), fluorinated SiO 2 (FSG), hydrogenated silicon oxycarbide (SiCOH), porous SiCOH, borophosphosilicate glass (BPSG), silsesquioxane, carbon (C) doped oxides (i.e., organosilicates) including silicon (Si), carbon (C), oxygen (O) and / or hydrogen (H) atoms, thermosetting polyarylene ether, or other low dielectric constant (<3.9) materials.

[0037] Exemplarily, the interlayer dielectric layer is formed by a chemical vapor deposition process.

[0038] Exemplarily, the step of forming a groove in the interlayer dielectric layer includes: forming a photoresist layer on the interlayer dielectric layer by a coating process; exposing and developing the photoresist layer by a photolithography process to form a photoresist layer having a pseudo gate pattern; using the photoresist layer having the pseudo gate pattern as a mask, etching the exposed pseudo gate by a plasma etching process to form a groove in the interlayer dielectric layer; and removing the photoresist layer having the pseudo gate pattern by an ashing process.

[0039] For example, a high-K (dielectric constant) dielectric layer is formed by chemical vapor deposition. The high dielectric constant may be higher than 3.9, for example, and the material of the high-K dielectric layer may include hafnium oxide (HfO 2 ), alumina (Al 2 O 3 ), yttrium oxide (Y 2 O3 ), Tantalum Oxide (Ta 2 O 5 ), titanium dioxide (TiO 2 ), praseodymium oxide (Pr 2 O 3 )、ZrO 2 ), erbium oxide (ErOx), and other materials now known or later developed having similar properties.

[0040] Exemplarily, the capping layer is formed by an atomic layer deposition process or a chemical vapor deposition process, and the material of the capping layer includes titanium nitride.

[0041] In step two, illustratively, an atomic layer deposition process or a chemical vapor deposition process is used to form a barrier layer, and the material of the barrier layer includes tantalum nitride.

[0042] Exemplarily, the PMOS work function metal layer is formed by an atomic layer deposition process, and the material of the PMOS work function metal layer includes titanium nitride.

[0043] As an example, a mask layer covering only the PMOS region is first formed, and then the PMOS work function metal layer located in the NMOS region is removed by an etching process, and then the mask layer is removed.

[0044] In step three, hydrogen is used to reduce the oxide layer formed on the surface of the barrier layer and the PMOS work function metal layer, so that the oxidized Ta and Ti metals are reduced again.

[0045] As an example, the process conditions of the hydrogen reduction include but are not limited to using plasma bombardment or pure chemical reduction at a temperature of 200°C to 450°C.

[0046] In step 4, ammonia is used to nitride the surface of the barrier layer and the PMOS work function metal layer, so that the Ta and Ti metals reduced in step 3 are bonded with N in the ammonia to form stable Ta-N and Ti-N metal bonds.

[0047] As an example, the process conditions of the ammonia nitridation are: using chemical vapor reaction, a flow rate of 5slm to 25slm (standard liters per minute), and a temperature of 320°C to 800°C.

[0048] In step five, illustratively, a physical magnetron sputtering process or an atomic layer deposition process is used to form an NMOS work function metal layer, and the material of the NMOS work function metal layer includes titanium aluminum (TiAl) or titanium aluminum carbide (TiAlC).

[0049] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present application in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0050] In summary, the method for improving device reliability provided by the present application effectively overcomes various shortcomings of the prior art and has high industrial utilization value.

[0051] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present application.

Claims

1. A method for improving device reliability, It is characterized in that The method comprises: Step 1, providing a substrate, on which an interlayer dielectric layer is formed, a trench is formed in the interlayer dielectric layer, and a high-K dielectric layer and a cap layer are sequentially formed on the sidewall and bottom of the trench; Step 2, forming a barrier layer and a PMOS work function metal layer on the cap layer in sequence, and then removing the PMOS work function metal layer located in the NMOS region; Step 3, using hydrogen to reduce the oxide layer formed on the surface of the barrier layer and the PMOS work function metal layer; Step 4, using ammonia gas to nitride the surfaces of the barrier layer and the PMOS work function metal layer; Step 5: forming an NMOS work function metal layer and a metal gate in sequence to fill the trench.

2. The method according to claim 1, It is characterized in that The process conditions for hydrogen reduction in step three include but are not limited to plasma bombardment or pure chemical reduction at a temperature of 200° C. to 450° C.

3. The method according to claim 1, It is characterized in that The process conditions for ammonia nitridation in step 4 are: chemical vapor reaction, flow rate of 5slm to 25slm, and temperature of 320°C to 800°C.

4. The method according to claim 1, It is characterized in that The interlayer dielectric layer and the high-K dielectric layer are formed by chemical vapor deposition process.

5. The method according to claim 1, It is characterized in that The cap layer is formed by an atomic layer deposition process or a chemical vapor deposition process.

6. The method according to claim 1, It is characterized in that The barrier layer is formed by an atomic layer deposition process or a chemical vapor deposition process.

7. The method according to claim 1 or 6, It is characterized in that The material of the barrier layer includes tantalum nitride.

8. The method according to claim 1, It is characterized in that The PMOS work function metal layer is formed by an atomic layer deposition process.

9. The method according to claim 1 or 8, It is characterized in that The material of the PMOS work function metal layer includes titanium nitride.

10. The method according to claim 1, It is characterized in that The NMOS work function metal layer is formed by a physical magnetron sputtering process or an atomic layer deposition process.

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