Field effect transistor preparation method, field effect transistor and integrated circuit

Abstract

The invention discloses a field effect transistor preparation method, a field effect transistor and an integrated circuit. The method comprises the following steps: providing a silicon carbide substrate; the silicon carbide substrate comprises a silicon carbide substrate and a first silicon carbide epitaxial layer arranged on the silicon carbide substrate; forming a source shielding layer in the first silicon carbide epitaxial layer and forming a second silicon carbide epitaxial layer on the first silicon carbide epitaxial layer; forming a grid shielding layer in the second silicon carbide epitaxial layer and forming a third silicon carbide epitaxial layer on the second silicon carbide epitaxial layer; and forming a grid electrode and a source electrode on the silicon carbide epitaxial layer to obtain the target field effect transistor. The method can be widely applied to the technical field of semiconductors.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for preparing a field effect transistor, a field effect transistor and an integrated circuit. Background Art

[0002] In the case of a silicon carbide trench metal oxide semiconductor field effect tube under high voltage reverse bias conditions, the electric field tends to concentrate at the corner of the gate trench. According to Gauss's law, the electric field strength in the gate oxide of the metal oxide semiconductor device is higher than the peak electric field strength in the semiconductor, and the ratio is equal to the dielectric constant of the semiconductor divided by the SiO 2 The dielectric constant of SiO 2 The dielectric constant ratio of SiC to SiC is about 2.5, which means that the electric field strength inside the oxide layer of the device is 2.5 times the peak electric field strength inside SiC. Excessively high electric field strength of the device can easily lead to reduced reliability of the device. Therefore, there are still technical problems that need to be solved in the related art. Summary of the invention

[0003] The purpose of this application is to solve one of the technical problems existing in the prior art to at least a certain extent.

[0004] To this end, an object of an embodiment of the present application is to provide a method, system, device and storage medium for preparing a field effect transistor, which can reduce the concentration of the electric field at the corners of the gate trench and improve the reliability of the device.

[0005] In order to achieve the above technical objectives, the technical solution adopted in the embodiment of the present application includes: a method for preparing a field effect transistor, including: providing a silicon carbide substrate; the silicon carbide substrate includes a silicon carbide substrate and a first silicon carbide epitaxial layer arranged on the silicon carbide substrate; forming a source shielding layer in the first silicon carbide epitaxial layer and forming a second silicon carbide epitaxial layer on the first silicon carbide epitaxial layer; forming a gate shielding layer in the second silicon carbide epitaxial layer and forming a third silicon carbide epitaxial layer on the second silicon carbide epitaxial layer; forming a P-well layer in the third silicon carbide epitaxial layer and forming an N-type heavily doped layer in the P-well layer; forming a first trench in the third silicon carbide epitaxial layer; the first trench penetrates the P-well layer, the N-type heavily doped layer and the third silicon carbide epitaxial layer. an epitaxial layer, exposing the gate shielding layer; forming a first P+ injection layer and a second trench in the P-well layer; the second trench penetrates the P-well layer, the third silicon carbide epitaxial layer and the second silicon carbide epitaxial layer, exposing the source shielding layer; forming a second P-type doping layer on the inner wall of the second trench and forming a source in the second trench, so that the source forms an ohmic contact with the second P-type doping layer and the second P-type doping layer abuts the source shielding layer; forming a gate in the first trench and forming an oxide layer on the inner wall of the first trench; the oxide layer abuts the gate shielding layer; forming an insulating layer on the gate, and forming a metal layer on the source and the insulating layer, to obtain a silicon carbide trench metal oxide field effect transistor.

[0006] In addition, the method for preparing a field effect transistor according to the above embodiment of the present invention may also have the following additional technical features:

[0007] Furthermore, in an embodiment of the present application, forming a source shielding layer in the first silicon carbide epitaxial layer and forming a second silicon carbide epitaxial layer on the first silicon carbide epitaxial layer specifically includes: setting a hard mask on the first silicon carbide epitaxial layer and performing photolithography to form a notch on the hard mask; the notch exposes the first silicon carbide epitaxial layer; injecting P-type ions into the exposed first silicon carbide epitaxial layer to obtain a source shielding layer; removing the hard mask and forming a second silicon carbide epitaxial layer on the first silicon carbide epitaxial layer.

[0008] Furthermore, in an embodiment of the present application, the P-type ions include one or a combination of aluminum ions or boron ions.

[0009] Furthermore, in an embodiment of the present application, the forming of a gate shielding layer in the second silicon carbide epitaxial layer and a third silicon carbide epitaxial layer on the second silicon carbide epitaxial layer specifically includes: setting a hard mask on the second silicon carbide epitaxial layer and performing photolithography to form a notch on the hard mask to expose the second silicon carbide epitaxial layer; injecting aluminum ions or boron ions into the exposed second silicon carbide epitaxial layer to obtain a gate shielding layer; removing the hard mask and forming a third silicon carbide epitaxial layer on the second silicon carbide epitaxial layer.

[0010] Furthermore, in an embodiment of the present application, forming a P-well layer in the third silicon carbide epitaxial layer and forming an N-type heavily doped layer in the P-well layer specifically includes: setting a hard mask on the third silicon carbide epitaxial layer and performing photolithography to form a notch on the hard mask to expose the third silicon carbide epitaxial layer; performing a P-type ion implantation process on the exposed third silicon carbide epitaxial layer to obtain a P-well layer; and injecting N-type ions into the P-well layer to form an N-type heavily doped layer.

[0011] Furthermore, in an embodiment of the present application, forming a source in the second trench specifically includes: forming a second P-type doping layer of a preset thickness on an inner wall of the second trench by an ion implantation process; forming a source in the second trench, the source forming an ohmic contact with the second P-type doping layer.

[0012] Furthermore, in the embodiment of the present application, the doping ions of the gate shielding layer and the source shielding layer are aluminum ions or boron ions.

[0013] On the other hand, an embodiment of the present application also provides a field effect transistor, which is obtained by the field effect transistor preparation method described above, and the field effect transistor includes: a silicon carbide substrate, a first silicon carbide epitaxial layer, a second silicon carbide epitaxial layer, a third silicon carbide epitaxial layer, a gate shielding layer, a source shielding layer, a first P+ injection layer, a second P-type doped layer, a gate, a source, an insulating layer, an oxide layer and a metal layer; a P-well layer and an N-type heavily doped layer are provided in the third silicon carbide epitaxial layer; the gate passes through the P-well layer, the N-type heavily doped layer and the third silicon carbide epitaxial layer; the oxide layer covers the bottom wall and side wall of the gate; the oxide layer abuts the gate shielding layer; the first P+ injection layer and the source form an ohmic contact through the second P-type doped layer and the second P-type doped layer abuts the source shielding layer; the insulating layer is provided on the gate for electrically isolating the gate and the source; the metal layer is provided on the insulating layer.

[0014] Furthermore, in an embodiment of the present application, the width of the gate shielding layer is greater than the width of the gate, and the width of the source shielding layer is greater than the width of the source; or, the gate shielding layer completely covers the bottom of the oxide layer, and the side wall of the source facing the gate is at least partially covered by the source shielding layer.

[0015] In addition, the present application also provides an integrated circuit, including the field effect transistor described above.

[0016] The advantages and benefits of the present application will be partially given in the following description, and partially become apparent from the following description, or be understood through the practice of the present application:

[0017] The present application can set a gate shielding layer in contact with the oxide layer covering the gate, and set a shielding layer in contact with the second P-type doping layer below the source, which can effectively improve the defect of electric field concentration at the corner of the gate trench and improve the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a structural schematic diagram of a field effect tube in the prior art;

[0019] Figure 2 A schematic diagram of the steps of a method for preparing a field effect transistor in a specific embodiment of the present invention;

[0020] Figure 3 A schematic diagram of structural changes in a field effect transistor preparation process in a specific embodiment of the present invention;

[0021] Figure 4 It is a structural schematic diagram of a field effect transistor in a specific embodiment of the present invention;

[0022] Figure 5 It is a structural schematic diagram of a field effect transistor in another specific embodiment of the present invention;

[0023] Figure 6 It is a structural schematic diagram of a field effect transistor in another specific embodiment of the present invention;

[0024] Figure 7 It is a structural schematic diagram of a field effect transistor in another specific embodiment of the present invention;

[0025] Figure 8 It is a structural schematic diagram of a field effect transistor in another specific embodiment of the present invention;

[0026] Fig. 9 It is a schematic diagram of the structure of a field effect transistor in another specific embodiment of the present invention. DETAILED DESCRIPTION

[0027] The embodiments of the present invention are described in detail below in conjunction with the accompanying drawings to illustrate the principles and processes of the field effect transistor preparation method, the field effect transistor and the integrated circuit in the embodiments of the present invention.

[0028] First, the terms used in this application are explained:

[0029] MOSFET: Metal Oxide Field Effect Transistor.

[0030] In the related art, refer to Figure 1 , under high voltage reverse bias conditions, the electric field of MOSFET tends to concentrate at the corners of the gate trench (such as Figure 1 The position indicated by the arrow). Too high an electric field strength can easily lead to a decrease in the reliability of the device. Therefore, there are still technical problems that need to be solved in the related art.

[0031] For the above problems, refer to Figure 2 The present application provides a method for preparing a field effect transistor, which may include steps S101 to S109.

[0032] S101, providing a silicon carbide substrate; the silicon carbide substrate comprises a silicon carbide substrate and a first silicon carbide epitaxial layer disposed on the silicon carbide substrate.

[0033] S102 , forming a source shielding layer in the first silicon carbide epitaxial layer and forming a second silicon carbide epitaxial layer on the first silicon carbide epitaxial layer.

[0034] S103 , forming a gate shielding layer in the second silicon carbide epitaxial layer and forming a third silicon carbide epitaxial layer on the second silicon carbide epitaxial layer.

[0035] S104 , forming a P-well layer in the third silicon carbide epitaxial layer and forming an N-type heavily doped layer in the P-well layer.

[0036] S105, forming a first trench in the third silicon carbide epitaxial layer; the first trench penetrates the P-well layer, the N-type heavily doped layer and the third silicon carbide epitaxial layer, exposing the gate shielding layer.

[0037] S106, forming a first P+ injection layer and a second trench in the P well layer; the second trench penetrates the P well layer, the third silicon carbide epitaxial layer and the second silicon carbide epitaxial layer to expose the source shielding layer.

[0038] S107 , forming a second P-type doping layer on the inner wall of the second trench and forming a source in the second trench, so that the source forms an ohmic contact with the second P-type doping layer and the second P-type doping layer abuts against the source shielding layer.

[0039] S108, forming a gate in the first trench and forming an oxide layer on the inner wall of the first trench; the oxide layer abuts against the gate shielding layer.

[0040] S109, forming an insulating layer on the gate, and forming a metal layer on the source and the insulating layer to obtain a target field effect transistor.

[0041] Furthermore, in some feasible embodiments of the present application, the step of forming a source shielding layer in the first silicon carbide epitaxial layer and forming a second silicon carbide epitaxial layer on the first silicon carbide epitaxial layer specifically includes steps S201 to S203.

[0042] S201, setting a hard mask on the first silicon carbide epitaxial layer and performing photolithography to form a notch on the hard mask; the notch exposes the first silicon carbide epitaxial layer.

[0043] S202 , implanting P-type ions into the exposed first silicon carbide epitaxial layer to obtain a source shielding layer.

[0044] S203 , removing the hard mask and forming a second silicon carbide epitaxial layer on the first silicon carbide epitaxial layer.

[0045] Furthermore, in some feasible embodiments of the present application, the P-type ions include one or a combination of aluminum ions or boron ions.

[0046] Furthermore, in some feasible embodiments of the present application, the step of forming a gate shielding layer in the second silicon carbide epitaxial layer and forming a third silicon carbide epitaxial layer on the second silicon carbide epitaxial layer specifically includes steps S301 to S303.

[0047] S301, setting a hard mask on the second silicon carbide epitaxial layer and performing photolithography to form a gap in the hard mask to expose the second silicon carbide epitaxial layer.

[0048] S302 , implanting aluminum ions or boron ions into the exposed second silicon carbide epitaxial layer to obtain a gate shielding layer.

[0049] S303 , removing the hard mask and forming a third silicon carbide epitaxial layer on the second silicon carbide epitaxial layer.

[0050] Further, in some feasible embodiments of the present application, the process of forming a P-well layer in the third silicon carbide epitaxial layer and forming an N-type heavily doped layer in the P-well layer specifically includes steps S401 to S403.

[0051] S401, setting a hard mask on the third silicon carbide epitaxial layer and performing photolithography to form a notch on the hard mask to expose the third silicon carbide epitaxial layer.

[0052] S402 , performing a P-type ion implantation process on the exposed third silicon carbide epitaxial layer to obtain a P-well layer.

[0053] S403 , injecting N-type ions into the P-well layer to form an N-type heavily doped layer.

[0054] Furthermore, in some feasible embodiments of the present application, the process of forming a source in the second trench specifically includes step S501 - step S502.

[0055] S501 , forming a second P-type doping layer of a preset thickness on the inner wall of the second trench by an ion implantation process.

[0056] S502 , forming a source electrode in the second trench, wherein the source electrode forms an ohmic contact with the second P-type doping layer.

[0057] Furthermore, in some feasible embodiments of the present application, the doping ions of the gate shielding layer and the source shielding layer are aluminum ions or boron ions.

[0058] Specifically, refer to Figure 3In this embodiment, a first silicon carbide epitaxial layer 1002 can be formed by epitaxy on a silicon carbide substrate 1001. The epitaxy process adopts an existing commonly used process. A surface of the substrate that is not subjected to epitaxy can be used to make a drain. After the first silicon carbide epitaxial layer 1002 is formed, a hard mask 1003 can be formed on the first silicon carbide epitaxial layer 1002 and photolithography can be performed to form certain gaps on the hard mask 1003, and these gaps can expose the first silicon carbide epitaxial layer 1002. Then, P-type ions are injected into the exposed first silicon carbide epitaxial layer 1002 to obtain a source shielding layer 1004. After obtaining the source shielding layer 1004, the remaining hard mask 1003 can be removed, and epitaxy can be continued on the first silicon carbide epitaxial layer 1002 after the hard mask 1003 is removed to form a second silicon carbide epitaxial layer 1005. After obtaining the second silicon carbide epitaxial layer 1005, the hard mask 1003 may be covered on the second silicon carbide epitaxial layer and the hard mask 1003 may be photolithographically processed to form a certain gap. After obtaining the gap, P-type ions may be injected into the exposed second silicon carbide epitaxial layer 1005 along the gap to obtain the gate shielding layer 1006. After obtaining the gate shielding layer 1006, the present embodiment may continue to epitaxially form the third silicon carbide epitaxial layer 1007 on the second silicon carbide epitaxial layer 1005. After forming the third silicon carbide epitaxial layer 1007, the hard mask 1003 may be covered on the third silicon carbide epitaxial layer 1007 and the hard mask 1003 may be photolithographically processed to partially expose the third silicon carbide epitaxial layer 1007. After obtaining the partially exposed third silicon carbide epitaxial layer 1007, the present embodiment may perform a P-type ion implantation process on the partially exposed third silicon carbide epitaxial layer 1007 to obtain a P well layer 1008. After the P-well layer 1008 is obtained, a hard mask 1003 may be covered on the P-well layer 1008 and photolithography may be performed to partially expose the P-well layer 1008. N-type ions are injected into the partially exposed P-well layer 1008. In this embodiment, an N-type heavily doped layer 1009 may be formed in the P-well layer 1008. After the N-type heavily doped layer 1009 is obtained, a first trench 1010 may be formed in the third silicon carbide epitaxial layer 1007 by an etching process. Since the P-well layer 1008 and the N-type heavily doped layer 1009 are also disposed in the third silicon carbide epitaxial layer 1007, the first trench 1010 may penetrate the P-well layer 1008, the third silicon carbide epitaxial layer 1007 and the second silicon carbide epitaxial layer 1005, so that the gate shielding layer 1006 is exposed. After obtaining the first trench 1010, a hard mask 1003 may be covered on the third silicon carbide epitaxial layer 1007, and the hard mask 1003 may cover the first trench 1010. After obtaining the hard mask 1003, the hard mask 1003 is photolithographically processed to form a notch for forming the first P+ injection layer 1011. After obtaining the notch for forming the first P+ injection layer 1011, P-type ions are continuously injected into the P well layer 1008 along the notch to obtain the first P+ injection layer 1011.

[0059] After obtaining the first P+ injection layer 1011, the present embodiment can remove the hard mask 1003 remaining after photolithography, and then form a second trench 1012 in the third silicon carbide epitaxial layer 1007. The second trench 1012 penetrates the P well layer 1008, the third silicon carbide epitaxial layer 1007 and the second silicon carbide epitaxial layer 1005, so that the gate shielding layer 1006 is exposed, and then the second trench 1012 is subjected to an ion implantation process to implant P-type ions into the sidewall of the trench to obtain a second P-type doping layer 1013. After obtaining the second P-type doping layer 1013, a source of a field effect transistor can be formed in the second trench 1012. The source forms an ohmic contact with the second P-type doping layer 1013, and the second P-type doping layer 1013 abuts against the source shielding layer 1004. After obtaining the source of the field effect transistor, a gate can be formed in the first trench 1010 and the gate 1015 can be oxidized to obtain an oxide layer 1017 covering the gate 1015 of the field effect transistor. After obtaining the oxide layer 1017, an insulating layer 1016 can be formed on the gate 1015. After obtaining the insulating layer 1016, a metal layer 1018 can be formed on the insulating layer 1016, and the metal layer 1018 can connect the two source electrodes 1014, and the insulating layer 1016 can isolate the metal layer 1018 from the gate 1015, thereby isolating the gate 1015 from the source 1014.

[0060] In addition, refer to Figure 4 The application also provides a field effect transistor. The field effect transistor can be obtained by the above field effect transistor preparation method. The field effect transistor includes a silicon carbide substrate 1001, a first silicon carbide epitaxial layer 1002, a second silicon carbide epitaxial layer 1005, a third silicon carbide epitaxial layer 1007, a gate shielding layer 1004, a source shielding layer 1006, a first P+ injection layer 1011, a second P-type doped layer 1013, a gate 1015, a source 1014, an insulating layer 1016, an oxide layer 1017 and a metal layer 1018. A P-well layer 1009 and an N-type heavily doped layer 1008 are provided in the third silicon carbide epitaxial layer 1007. The gate penetrates the P-well layer 1009, the N-type heavily doped layer 1008 and the third silicon carbide epitaxial layer 1007. The oxide layer 1017 covers the bottom wall and side wall of the gate 1015. The oxide layer 1017 abuts against the gate shielding layer 1006. The first P+ injection layer 1011 forms an ohmic contact with the source 1014 through the second P-type doping layer 1013, and the second P-type doping layer 1013 abuts against the source shielding layer 1004. An insulating layer 1016 is disposed on the gate 1015, and the insulating layer 1016 can electrically isolate the gate 1015 and the source 1014. A metal layer 1018 is disposed on the insulating layer 1016, and the metal layer 1018 covers the insulating layer 1016 and enables the two sources 1014 to be electrically connected.

[0061] It is understandable that the source shielding layer and the gate shielding layer are both P+ shielding layers. The bottom of the first trench needs to be in effective contact with the bottom P+ shielding layer, and the bottom of the second trench needs to be in effective contact with the bottom P+ shielding layer.

[0062] Further, in some feasible embodiments of the present application, referring to Figure 5-Figure 9 , the width of the gate shielding layer 1006 may be greater than the width of the gate, and the width of the source shielding layer 1004 may be greater than the width of the source. Alternatively, in other feasible embodiments of the present application, the gate shielding layer 1006 completely covers the bottom of the oxide layer, and the sidewall of the source facing the gate is at least partially covered by the source shielding layer 1004.

[0063] It should be noted that the contents of the above-mentioned field effect tube preparation method embodiment are applicable to the present field effect tube preparation method embodiment. The functions specifically implemented by the present field effect tube embodiment are the same as those of the above-mentioned field effect tube preparation method embodiment, and the beneficial effects achieved are also the same as those achieved by the above-mentioned field effect tube preparation method embodiment.

[0064] In summary, this application has the following advantages:

[0065] 1. The present application can realize a P+ buried layer structure of required depth through multiple epitaxial and buried layer processes, which can improve the problem of insufficient injection depth in traditional injection processes (usually the injection depth is only about 1-1.5um), and can effectively reduce the electric field of the gate trench and provide shielding protection.

[0066] 2. The present application adopts multiple epitaxy and P+ buried layer processes, which can improve the problems of electric field concentration at the gate trench of traditional SiC trench MOSFET, easy gate oxide breakdown and poor reliability. The present application effectively reduces the electric field strength and concentration at the gate trench by introducing a P+ buried layer shielding layer, which can significantly reduce the electric field strength at the corner of the gate trench, reduce the risk of gate oxide breakdown, and improve the reliability of SiC trench MOSFET. The P+ shielding layer can protect the gate trench while taking into account the influence of the JFET effect. Through the design of different structures, the protection effect and the improvement of the influence of the JFET effect can be balanced. The present application can also adopt appropriate solutions according to different parameter design needs to improve the overall performance of the device.

[0067] and Figure 2 Corresponding to the method, an embodiment of the present application further provides an integrated circuit, including the above-mentioned field effect transistor.

[0068] It should be noted that the contents of the above method embodiments are all applicable to the present device embodiments, the functions specifically implemented by the present device embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0069] In some optional embodiments, the function / operation mentioned in the block diagram may not occur in the order mentioned in the operation diagram. For example, depending on the function / operation involved, the two boxes shown in succession can actually be executed substantially simultaneously or the boxes can sometimes be executed in reverse order. In addition, the embodiment presented and described in the flow chart of the application is provided by way of example, for the purpose of providing a more comprehensive understanding of technology. The disclosed method is not limited to the operation and logic flow presented herein. Optional embodiments are expected, wherein the order of various operations is changed and the sub-operation described as a part of a larger operation is performed independently.

[0070] In the above description of this specification, the description with reference to the terms "one embodiment / example", "another embodiment / example" or "certain embodiments / examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0071] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

[0072] The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the described embodiments. Technical personnel familiar with the field may make various equivalent modifications or substitutions without violating the spirit of the present application. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present application.

Claims

1. A method for preparing a field effect transistor, characterized in that: include: Providing a silicon carbide substrate; the silicon carbide substrate comprises a silicon carbide substrate and a first silicon carbide epitaxial layer disposed on the silicon carbide substrate; forming a source shield layer in the first silicon carbide epitaxial layer and forming a second silicon carbide epitaxial layer on the first silicon carbide epitaxial layer; forming a gate shielding layer in the second silicon carbide epitaxial layer and forming a third silicon carbide epitaxial layer on the second silicon carbide epitaxial layer; forming a P-well layer in the third silicon carbide epitaxial layer and forming an N-type heavily doped layer in the P-well layer; forming a first trench in the third silicon carbide epitaxial layer; The first trench penetrates the P-well layer, the N-type heavily doped layer and the third silicon carbide epitaxial layer, so that the gate shielding layer is exposed; forming a first P+ implantation layer and a second trench in the P well layer; The second trench penetrates the P-well layer, the third silicon carbide epitaxial layer and the second silicon carbide epitaxial layer to expose the source shielding layer; forming a second P-type doping layer on the inner wall of the second trench and forming a source electrode in the second trench, so that the source electrode forms an ohmic contact with the second P-type doping layer and the second P-type doping layer abuts against the source shielding layer; forming a gate in the first trench and forming an oxide layer on an inner wall of the first trench; the oxide layer abuts against the gate shielding layer; An insulating layer is formed on the gate, and a metal layer is formed on the source and the insulating layer to obtain a target field effect transistor.

2. A method for preparing a field effect transistor according to claim 1, characterized in that: The step of forming a source shielding layer in the first silicon carbide epitaxial layer and forming a second silicon carbide epitaxial layer on the first silicon carbide epitaxial layer specifically includes: Disposing a hard mask on the first silicon carbide epitaxial layer and performing photolithography to form a notch on the hard mask; the notch exposes the first silicon carbide epitaxial layer; Implanting P-type ions into the exposed first silicon carbide epitaxial layer to obtain a source shielding layer; The hard mask is removed and a second silicon carbide epitaxial layer is formed on the first silicon carbide epitaxial layer.

3. A method for preparing a field effect transistor according to claim 2, characterized in that: The P-type ions include aluminum ions or boron ions, or a combination of both.

4. A method for preparing a field effect transistor according to claim 1, characterized in that: The step of forming a gate shielding layer in the second silicon carbide epitaxial layer and forming a third silicon carbide epitaxial layer on the second silicon carbide epitaxial layer specifically includes: Disposing a hard mask on the second silicon carbide epitaxial layer and performing photolithography to form a notch on the hard mask to expose the second silicon carbide epitaxial layer; Implanting aluminum ions or boron ions into the exposed second silicon carbide epitaxial layer to obtain a gate shielding layer; The hard mask is removed and a third silicon carbide epitaxial layer is formed on the second silicon carbide epitaxial layer.

5. A method for preparing a field effect transistor according to claim 1, characterized in that: The forming of a P-well layer in the third silicon carbide epitaxial layer and forming an N-type heavily doped layer in the P-well layer specifically includes: Disposing a hard mask on the third silicon carbide epitaxial layer and performing photolithography to form a notch on the hard mask to expose the third silicon carbide epitaxial layer; Performing a P-type ion implantation process on the exposed third silicon carbide epitaxial layer to obtain a P-well layer; N-type ions are implanted into the P-well layer to form an N-type heavily doped layer.

6. A method for preparing a field effect transistor according to claim 1, characterized in that: The forming of a source in the second trench specifically includes: forming a second P-type doping layer of a preset thickness on the inner wall of the second trench by an ion implantation process; A source electrode is formed in the second trench, and the source electrode forms an ohmic contact with the second P-type doping layer.

7. A method for preparing a field effect transistor according to claim 1, characterized in that: The gate shielding layer and the source shielding layer are doped with aluminum ions or boron ions.

8. An effect tube, characterized in that: The field effect transistor is obtained by the method for preparing the field effect transistor according to any one of claims 1 to 7, wherein the field effect transistor comprises: Silicon carbide substrate, a first silicon carbide epitaxial layer, a second silicon carbide epitaxial layer, a third silicon carbide epitaxial layer, a gate shielding layer, a source shielding layer, a first P+ injection layer, a second P-type doping layer, a gate, a source, an insulating layer, an oxide layer and a metal layer; The third silicon carbide epitaxial layer is provided with a P-well layer and an N-type heavily doped layer; The gate penetrates the P-well layer, the N-type heavily doped layer and the third silicon carbide epitaxial layer; The oxide layer covers the bottom wall and the side wall of the gate; the oxide layer abuts against the gate shielding layer; The first P+ injection layer forms an ohmic contact with the source through the second P-type doping layer, and the second P-type doping layer abuts the source shielding layer; the insulating layer is arranged on the gate to electrically isolate the gate and the source; the metal layer is arranged on the insulating layer.

9. The field effect transistor according to claim 8, characterized in that: The width of the gate shielding layer is greater than the width of the gate, and the width of the source shielding layer is greater than the width of the source; or, the gate shielding layer completely covers the bottom of the oxide layer, and the side wall of the source facing the gate is at least partially covered by the source shielding layer.

10. An integrated circuit comprising the field effect transistor according to any one of claims 8 to 9.

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