A method for manufacturing a MOSFET structure and a MOSFET structure

Abstract

The present invention discloses a method for manufacturing a MOSFET structure and a MOSFET structure, the method comprising: performing ion implantation on a wafer to form a p-type shielding region, and etching a groove on the wafer, the wafer comprising a first current transmission layer and a second current transmission layer, the grooves being distributed on both sides of the second current transmission layer; forming a doped region on both sides of the second current transmission layer; growing a gate oxide layer and an eighth barrier layer on the doped region and the wafer, etching the eighth barrier layer through photoresist and depositing polysilicon to form two gate regions; forming an oxidized dielectric layer to wrap the gate region, depositing a source region and a Schottky contact region on the doped region, the oxidized dielectric layer and the second current transmission layer, and depositing a drain region at the bottom of the wafer to perform ohmic contact and Schottky contact. The present invention protects the gate oxide and the Schottky contact region through the p-type shielding region and the doped region, controls the width of the conductive current path, reduces the saturation current, and improves the short-circuit capability and reliability.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a MOSFET structure and a MOSFET structure. Background Art

[0002] As a third-generation wide bandgap semiconductor material, silicon carbide (SiC) has excellent properties such as high critical breakdown electric field strength, high electron saturation drift rate and high thermal conductivity, making it an ideal material for making high-power, high-temperature, high-frequency and radiation-resistant devices. Silicon carbide power devices have performance advantages such as low on-resistance, fast switching speed, high thermal conductivity, and the ability to withstand high voltage. They can significantly reduce energy loss and improve system efficiency during power conversion. They have been used in a certain range of applications in industrial automation, 5G communications, electric vehicle revolution, and renewable energy generation.

[0003] In practical applications, power equipment will inevitably work for a long time under overload, short circuit and other conditions. This requires that silicon carbide power devices, in addition to having a certain current-carrying capacity, also need to have good overload capacity, short-circuit capacity and reliability to ensure the long and stable service life of the device. However, in traditional cognition, the smaller the on-resistance of the silicon carbide power device, the stronger its current-carrying capacity, the worse the short-circuit capacity and the worse the reliability. Therefore, the more or less optimization of the short-circuit performance and reliability of most silicon carbide power devices will affect the current-carrying capacity of the device. The conventional integrated Schottky structure VDMOSFET structure has the advantages of high input impedance, fast switching speed, good thermal stability, low on-resistance, self-shutdown capability and easy parallel use. However, the short-circuit capacity and reliability capabilities of this structure are not high, which can easily affect the stability of the device. Summary of the invention

[0004] The object of the present invention is to provide a method for manufacturing a MOSFET structure and a MOSFET structure to solve the technical problem that the short-circuit capability and reliability capability in the prior art are not high, which easily affects the stability of the device. The preferred technical solutions among the many technical solutions provided by the present invention can produce many technical effects as described below.

[0005] To achieve the above object, the present invention provides the following technical solutions:

[0006] The present invention provides a method for manufacturing a MOSFET structure, comprising:

[0007] Manufacturing a wafer, performing ion implantation on the wafer to form a p-type shielding region, and etching grooves on the wafer, wherein the wafer comprises a first current transmission layer and a second current transmission layer, and the grooves are distributed on both sides of the second current transmission layer;

[0008] forming doped regions on both sides of the second current transport layer, wherein the doped regions include a first doped region and a second doped region, the first doped region is located below the trench, and the second doped region is located on both sides above the second current transport layer;

[0009] Growing a gate oxide layer and an eighth barrier layer on the doped region and the wafer, etching the eighth barrier layer by photoresist and depositing polysilicon to form two gate regions;

[0010] An oxide dielectric layer is formed to wrap the gate region, a source region and a Schottky contact region are deposited on the doped region, the oxide dielectric layer and the second current transmission layer, a drain region is deposited at the bottom of the wafer, ohmic contact and Schottky contact are made, and the MOSFET structure is completed.

[0011] Optionally, the manufacturing of the wafer includes:

[0012] After growing an N-epitaxial layer on the N+ substrate layer, growing a first current transport layer on the N-epitaxial layer;

[0013] After growing a first blocking layer on the first current transport layer, etching and N ion implantation are performed on the middle of the first blocking layer using photoresist to form a second current transport layer and removing the first blocking layer, thereby completing the manufacture of the wafer.

[0014] Optionally, the step of performing ion implantation on the wafer to form a p-type shielding region and etching a groove on the wafer comprises:

[0015] After growing a second blocking layer on the first current transport layer and the second current transport layer, etching both sides of the second blocking layer and implanting Al+ ions through photoresist to form a p-type shielding region and removing the second blocking layer;

[0016] Growing a third blocking layer on the second current transport layer of the wafer, and etching two sides of the third blocking layer by photoresist to form a groove area;

[0017] Then, etching is performed along the groove region into the wafer to form grooves on both sides of the wafer and remove the third barrier layer.

[0018] Optionally, forming doped regions on both sides of the second current transport layer includes:

[0019] Growing a fourth blocking layer on the groove and the second current transport layer, etching both sides of the fourth blocking layer by photoresist and implanting Al+ ions to form a Pwell region and removing the fourth blocking layer;

[0020] Growing a fifth blocking layer on the Pwell region, the trench and the second current transport layer, etching and N ion implanting on both sides of the fifth blocking layer by photoresist to form an N+ region and removing the fifth blocking layer;

[0021] Growing a sixth blocking layer on the N+ region, the Pwell region, the trench and the second current transport layer, etching both sides of the sixth blocking layer and implanting Al+ ions through photoresist to form a P+plus region and removing the sixth blocking layer;

[0022] A seventh blocking layer is grown on the P+plus region, the N+ region, the Pwell region, the trench and the second current transport layer, and the seventh blocking layer is etched and Al+ ion implanted by photoresist to form a P+ region and remove the seventh blocking layer.

[0023] Optionally, the step of growing a gate oxide layer and an eighth barrier layer on the doped region and the wafer, etching the eighth barrier layer by photoresist and depositing polysilicon to form gate regions on both sides includes:

[0024] growing a gate oxide layer on the P+plus region, the N+ region, the Pwell region, the trench, the P+ region and the second current transport layer;

[0025] The eighth barrier layer is grown on the gate oxide layer, the eighth barrier layer is etched by photoresist and polysilicon is deposited, two gate regions are formed on the trench and the eighth barrier layer is removed.

[0026] Optionally, the step of forming an oxide dielectric layer to wrap the gate region, depositing a source region and a Schottky contact region on the doped region, the oxide dielectric layer and the second current transmission layer, depositing a drain region at the bottom of the wafer, making ohmic contacts and Schottky contacts, and completing the manufacture of a MOSFET structure includes:

[0027] Depositing an isolation dielectric layer on the gate oxide layer and the gate region to form an oxide dielectric layer and wrapping the gate region in the oxide dielectric layer;

[0028] Growing a ninth barrier layer on the oxidized dielectric layer, etching the ninth barrier layer by photoresist and etching the oxidized dielectric layer through the ninth barrier layer to form a source metal deposition region and a Schottky contact electrode region, and removing the ninth barrier layer;

[0029] After depositing source metal in the source metal deposition area to form a source region, a drain metal is deposited at the bottom of the wafer to form a drain region to complete ohmic contact;

[0030] While depositing source metal in the source metal deposition area to form a source region, a Schottky contact electrode is deposited on the Schottky contact electrode area to form a Schottky contact area, completing the Schottky contact, thereby completing the manufacture of the MOSFET structure.

[0031] A MOSFET structure, comprising: a wafer, a doped region, a p-type shielding region, a trench, two gate regions, an oxide dielectric layer, a source region, a Schottky contact region and a drain region; the wafer comprises a first current transmission layer and a second current transmission layer, the first current transmission layer wraps the side surface of the second current transmission layer; the trench is arranged on both sides of the second current transmission layer, the doped region and the gate region are arranged on both sides of the second current transmission layer, the p-type shielding region is arranged in both sides of the wafer, and the p-type shielding region is located below the trench;

[0032] The source region, the oxide dielectric layer and the Schottky contact region are arranged in sequence from outside to inside on both sides above the doped region and the second current transmission layer, and the oxide dielectric layer wraps the gate region; the drain region is arranged at the bottom of the wafer.

[0033] Optionally, the width of the trench is in the range of 1um-1.4um, and the depth of the trench is in the range of 0.1um-0.5um; the depth of the p-type shielding region is in the range of 1um-1.5um, and the width of the p-type shielding region is in the range of 1.4um-2um.

[0034] Optionally, the wafer also includes an N+ substrate layer and an N-epitaxial layer, and the N+ substrate layer, the N-epitaxial layer, the first current transmission layer and the second current transmission layer are stacked in sequence from bottom to top, and the first current transmission layer wraps the side of the second current transmission layer; the thickness range of the first current transmission layer is 1.5um-3um; the width range of the second current transmission layer is 0.4um-1um, and the depth range of the second current transmission layer is 0um-2um.

[0035] Optionally, the doped region includes a first doped region and a second doped region, the first doped region includes a Pwell region, an N+ region and a P+plus region, the second doped region includes a P+ region, the P+ region and the p-type shielding region are arranged at the upper and lower ends of the second current transmission layer opposite to each other, the P+ region is arranged on both sides above the second current transmission layer, and the P+ region is in contact with the oxidized dielectric layer, and the p-type shielding region is arranged on both sides below the second current transmission layer; the Pwell region is arranged above the p-type shielding region, and the P+plus region and the N+ region are arranged on both sides above the Pwell region in sequence from outside to inside; the P+ region is arranged on both sides above the second current transmission layer;

[0036] The depth range of the Pwell region is 0.9um-1.2um, the depth range of the N+ region is 0.1um-0.4um, the depth range of the P+plus region is 0.2um-1um, the depth range of the P+ region is 0.1um-0.3um, and the width range of the P+ region is 0.1um-0.5um.

[0037] Implementing one of the above technical solutions of the present invention has the following advantages or beneficial effects:

[0038] The present invention uses the p-type shielding region and the P+ region of the doped region to work together, and the self-clamping structure controls the width of the conductive current path, thereby reducing the saturation current and improving the short-circuit capability. At the same time, the p-type shielding region shields the SiC-SiO2 interface, reducing the gate oxide electric field strength, and the p-type shielding region and the P+ region work together to protect the gate oxide and the Schottky contact region, preventing high electric fields from damaging the structure and improving the structural reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. It is obvious that the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0040] Figure 1 is a flow chart of an embodiment of the present invention;

[0041] Figure 2 is a schematic diagram of the overall structure of an embodiment of the present invention;

[0042] Figure 3 Schematic diagram of the structure of an N+ substrate layer and an N- epitaxial layer according to an embodiment of the present invention;

[0043] Figure 4 is a schematic diagram of the structure of growing and etching the first barrier layer according to an embodiment of the present invention;

[0044] Figure 5 is a schematic structural diagram of a manufactured wafer according to an embodiment of the present invention;

[0045] Figure 6 is a schematic diagram of the structure of growing and etching the second barrier layer according to an embodiment of the present invention;

[0046] Figure 7 is a schematic structural diagram of etching a p-type shielding region according to an embodiment of the present invention;

[0047] Figure 8is a schematic diagram of the structure of growing and etching the third barrier layer according to an embodiment of the present invention;

[0048] Fig. 9 is a schematic diagram of a structure for forming a groove according to an embodiment of the present invention;

[0049] Fig.10 is a schematic diagram of the structure of growing and etching a fourth barrier layer according to an embodiment of the present invention;

[0050] Fig.11 is a schematic diagram of a structure for forming a Pwell region according to an embodiment of the present invention;

[0051] Fig.12 is a schematic diagram of the structure of growing and etching the fifth barrier layer according to an embodiment of the present invention;

[0052] Fig.13 is a schematic diagram of a structure for forming an N+ region according to an embodiment of the present invention;

[0053] Fig.14 is a schematic diagram of the structure of growing and etching the sixth barrier layer according to an embodiment of the present invention;

[0054] Fig.15 is a schematic diagram of a structure for forming a P+plus region according to an embodiment of the present invention;

[0055] Fig.16 is a schematic diagram of the structure of growing and etching the seventh barrier layer according to an embodiment of the present invention;

[0056] Fig.17 is a schematic structural diagram of forming a P+ region according to an embodiment of the present invention;

[0057] Fig.18 is a schematic structural diagram of a growing gate oxide layer according to an embodiment of the present invention;

[0058] Fig.19 is a schematic structural diagram of growing and etching an eighth barrier layer according to an embodiment of the present invention;

[0059] Fig. 20 is a schematic structural diagram of forming a gate region according to an embodiment of the present invention;

[0060] Fig.21 is a schematic structural diagram of a deposited isolation dielectric layer according to an embodiment of the present invention;

[0061] Fig. 22 is a schematic diagram of the structure of growing and etching the ninth barrier layer according to an embodiment of the present invention;

[0062] Fig.23 is a schematic structural diagram of forming a source metal deposition region and a Schottky contact electrode region according to an embodiment of the present invention;

[0063] Fig.24is a schematic structural diagram of a deposited source region, a Schottky contact region, and a drain region according to an embodiment of the present invention;

[0064] Fig.25 It is a comparison diagram of output characteristic curves of a conventional planar MOSFET structure with integrated Schottky structure in an embodiment of the present invention and the MOSFET structure of the present invention under normal conduction conditions;

[0065] Fig.26 It is a comparison diagram of the gate oxygen strength of the planar MOSFET structure of the regular integrated Schottky structure of the embodiment of the present invention and the MOSFET structure of the present invention within a certain process window.

[0066] In the figure: 1. wafer; 11. N+ substrate layer; 12. N- epitaxial layer; 13. first current transmission layer; 14. second current transmission layer; 2. doping region; 21. Pwell region; 22. N+ region; 23. P+plus region; 24. P+ region; 3. p-type shielding region; 4. trench; 5. gate region; 6. oxide dielectric layer; 61. gate oxide layer; 62. isolation dielectric layer; 7. source region; 8. Schottky contact region; 9. drain region; 101. first blocking layer; 102. second blocking layer; 103. third blocking layer; 104. fourth blocking layer; 105. fifth blocking layer; 106. sixth blocking layer; 107. seventh blocking layer; 108. eighth blocking layer; 109. ninth blocking layer. DETAILED DESCRIPTION

[0067] In order to make the purpose, technical solutions and advantages of the present invention clearer, the various exemplary embodiments to be described below will refer to the corresponding drawings, which constitute a part of the exemplary embodiments, wherein various exemplary embodiments that may be used to implement the present invention are described. Unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation methods described in the following exemplary embodiments do not represent all implementation methods consistent with the present disclosure. It should be understood that they are only examples of processes, methods, devices, etc. that are consistent with some aspects of the present disclosure as detailed in the attached claims, and other embodiments may also be used, or the embodiments listed herein may be modified in structure and function without departing from the scope and essence of the present invention.

[0068] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", etc. indicate the orientation or positional relationship based on the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the elements referred to must have a specific orientation, be constructed and operated in a specific orientation. The terms "first", "second", etc. are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. The term "multiple" means two or more. The terms "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, an integral connection, a mechanical connection, an electrical connection, a communication connection, a direct connection, an indirect connection through an intermediate medium, and can be the internal connection of two elements or the interaction relationship between two elements. The term "and / or" includes any and all combinations of one or more related listed items. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances.

[0069] In order to illustrate the technical solution of the present invention, a specific embodiment is used below for description, and only the parts related to the embodiment of the present invention are shown.

[0070] Embodiment 1:

[0071] like Figure 1 As shown, the present invention provides a method for manufacturing a MOSFET structure, comprising:

[0072] S10, manufacturing a wafer, performing ion implantation on the wafer to form a p-type shielding region, and etching grooves on the wafer, wherein the wafer includes a first current transmission layer and a second current transmission layer, and the grooves are distributed on both sides of the second current transmission layer;

[0073] S20, forming doped regions on both sides of the second current transport layer, wherein the doped regions include a first doped region and a second doped region, the first doped region is located below the trench, and the second doped region is located on both sides above the second current transport layer;

[0074] S30, growing a gate oxide layer and an eighth barrier layer on the doped region and the wafer, etching the eighth barrier layer by photoresist and depositing polysilicon to form two gate regions;

[0075] S40, forming an oxide dielectric layer to wrap the gate region, depositing a source region and a Schottky contact region on the doped region, the oxide dielectric layer and the second current transfer layer, depositing a drain region at the bottom of the wafer, making ohmic contacts and Schottky contacts, and completing the manufacture of the MOSFET structure.

[0076] Specifically, making a wafer with a first current transmission layer and a second current transmission layer can increase the current path of the MOSFET structure and reduce the on-resistance, thereby ensuring the forward conduction capability of the MOSFET structure. Ion implantation is performed in the wafer to form a p-type shielding region and a p+ region, which can well protect the gate region and the Schottky contact region of the MOSFET structure, thereby improving the short-circuit capability and reliability capability of the MOSFET structure. Grooves are etched on both sides of the second current transmission layer of the wafer to facilitate the conduction of the current and the coupling of the p-type shielding region and the p+ region. The gate is deposited on the doped region and the groove, and the ohmic contact and Schottky contact of the MOSFET structure are completed by depositing the source region and the Schottky contact region above the wafer and the doped region, and the drain region is deposited below the wafer.

[0077] The present invention uses the p-type shielding region and the P+ region of the doped region to work together, and the self-clamping structure controls the width of the conductive current path, thereby reducing the saturation current and improving the short-circuit capability. At the same time, the p-type shielding region shields the SiC-SiO2 interface, reducing the gate oxide electric field strength, and the p-type shielding region and the P+ region work together to protect the gate oxide and the Schottky contact region, preventing high electric fields from damaging the structure and improving the structural reliability.

[0078] As an optional implementation, manufacturing a wafer includes: growing an N-epitaxial layer on an N+ substrate layer, and then growing a first current transmission layer on the N-epitaxial layer. After growing a first barrier layer on the first current transmission layer, etching the middle of the first barrier layer by photoresist and implanting N ions to form a second current transmission layer and removing the first barrier layer, thereby completing the manufacturing of the wafer. Specifically, as Figure 3 As shown, an N-epi layer (ie, N-epi: SiC low-doped N-type epitaxial layer) of appropriate concentration and thickness is grown on an N+ substrate layer (ie, N+sub, SiC high-doped N-type substrate); as shown Figure 4 As shown, a first current transmission layer (Csl, Current Spreading Layer) of appropriate concentration and thickness is grown on the N-epitaxial layer, and a first barrier layer is grown on the first current transmission layer. The middle of the first barrier layer is etched by photoresist to form an injection region of the second current transmission layer. The width range of the injection region of the etched second current transmission layer can be adaptively set according to actual needs, and can be selected as 0.4um-1um; as shown Figure 5 As shown, the injection angle is adjusted, and N ions are injected multiple times to form a second current transmission layer (i.e., Csl2) in the first current parameter layer. The injection depth range of the second current transmission layer can be selected to be 0um-2um, and the energy of the injected N ions is about 100keV-1100keV, and the dose is 1e12-1e14. Then, the first barrier layer forming the second current transmission layer is removed to complete the wafer production.

[0079] As an optional implementation, ion implantation is performed on a wafer to form a p-type shielding region, and a groove is etched on the wafer, including: after growing a second barrier layer on the first current transmission layer and the second current transmission layer, etching both sides of the second barrier layer through photoresist and implanting Al+ ions to form a p-type shielding region and remove the second barrier layer. A third barrier layer is grown on the second current transmission layer of the wafer, and both sides of the third barrier layer are etched through photoresist to form a groove region. Then, etching is performed into the wafer along the groove region to form grooves on both sides of the wafer and remove the third barrier layer.

[0080] Specifically, Figure 6 As shown, a second barrier layer is grown on the first current transport layer and the second current transport layer, and both sides of the second barrier layer are etched by photoresist to form an injection region of a p-type shielding region. The width range of the injection region of the etched p-type shielding region can be adaptively set according to actual needs, and can be selected to be 1.4um-2um. Figure 7 As shown, the injection angle is adjusted, and Al+ ions are injected into the injection area of ​​the p-type shielding area multiple times to form a p-type shielding area (i.e., p+ shielded area). When injecting Al+ ions, the energy of the injected Al+ ions is controlled to control the depth of the injected p-type shielding area. The greater the energy of the injected Al+ ions, the deeper the injection depth of the p-type shielding area. The injection depth of the p-type shielding area ranges from 1um to 1.5um, and the energy of the injected Al+ ions is about 800keV to 1500keV, with a dose of 1e13 to 1e15. After the Al+ ions are injected, some Al+ ions will remain in the upper part but will be compensated, so that the p-type shielding area is injected in the middle of the first current transmission layer and the second current transmission layer, and is located on both sides of the middle of the wafer.

[0081] like Figure 8 As shown, a third blocking layer is grown on the second current transport layer, and both sides of the third blocking layer are etched by photoresist to form a groove area. Fig. 9 As shown, etching continues downward along the trench area to form trenches, which are located on both sides of the wafer. Then, the third barrier layer forming the trenches is removed.

[0082] As an optional embodiment, a doped region is formed on both sides of the second current transport layer, including: growing a fourth barrier layer on the groove and the second current transport layer, etching both sides of the fourth barrier layer and implanting Al+ ions through photoresist to form a Pwell region and remove the fourth barrier layer. Growing a fifth barrier layer on the Pwell region, the groove and the second current transport layer, etching both sides of the fifth barrier layer and implanting N ions through photoresist to form an N+ region and remove the fifth barrier layer. Growing a sixth barrier layer on the N+ region, the Pwell region, the groove and the second current transport layer, etching both sides of the sixth barrier layer and implanting Al+ ions through photoresist to form a P+plus region and remove the sixth barrier layer. Growing a seventh barrier layer on the P+plus region, the N+ region, the Pwell region, the groove and the second current transport layer, etching and implanting Al+ ions through photoresist to form a P+ region and remove the seventh barrier layer.

[0083] Specifically, Fig.10 As shown, a fourth barrier layer is grown on the groove and the second current transmission layer, and both sides of the fourth barrier layer are etched by photoresist to form a Pwell injection region. The width of the etched Pwell injection region can be adaptively set according to actual needs. Fig.11 As shown, the injection angle is adjusted, and Al+ ions are injected into the Pwell injection area multiple times to form a Pwell area. The Pwell area is located above the p-type shielding area. The injection depth of the Pwell area ranges from 0.9um to 1.2um. The energy of the injected Al+ ions is about 100keV to 600keV, and the dose is 1e12 to 1e14. Then the fourth barrier layer is removed.

[0084] like Fig.12 As shown, a fifth barrier layer is grown on the Pwell region, the trench and the second current transport layer, and both sides of the fifth barrier layer are etched by photoresist to form an N ion implantation region. The width of the etched N ion implantation region can be adaptively set according to actual needs. Fig.13 As shown, the implantation angle is adjusted, and N ions are implanted into the N ion implantation area to form an N+ region, which is located above the Pwell region. The implantation depth of the N+ region ranges from 0.1um to 0.4um, and the energy of the implanted N ions is about 50keV to 150keV, with a dose of 5e14 to 1e15. Then the fifth barrier layer is removed.

[0085] like Fig.14 As shown, a sixth barrier layer is grown on the N+ region, the Pwell region, the trench, and the second current transmission layer, and both sides of the sixth barrier layer are etched by photoresist to form a P+plus injection region. The width of the etched P+plus injection region can be adaptively set according to actual needs. Fig.15 As shown, the implantation angle is adjusted, and Al+ ions are implanted into the P+plus implantation area to form a P+plus area. The P+plus area is located above the Pwell area and abuts against the N+ area, and is located outside the wafer. The implantation depth of Al+ ions ranges from 0.2um to 1um, and the energy of the implanted Al+ ions is about 50keV to 450keV, with a dose of 5e14 to 3e15. Then the sixth barrier layer forming the P+plus area is removed.

[0086] like Fig.16 As shown, the seventh barrier layer is grown on the P+plus region, N+ region, Pwell region, trench and second current transmission layer, and the seventh barrier layer is etched by photoresist (i.e., the seventh barrier layer on both sides above the second current transmission layer is etched) to form a P+ injection region. The width of the etched P+ injection region can be adaptively set according to actual needs, and the width range of the etched P+ injection region can be selected to be 0.1um-0.5um. Fig.17 As shown, the injection angle is adjusted, and Al+ ions are injected into the P+ injection area to form a P+ area, and the P+ area is located on both sides above the second current transmission layer. The injection depth of Al+ ions into the P+ injection area is in the range of 0.1um-0.3um, the energy of the injected Al+ ions is about 50keV-150keV, and the dose is 1e12-1e14. Then the seventh barrier layer forming the P+ area is removed.

[0087] As an optional implementation, a gate oxide layer and an eighth barrier layer are grown on the doped region and the wafer, the eighth barrier layer is etched by photoresist and polysilicon is deposited to form gate regions on both sides, including: growing a gate oxide layer on the P+plus region, the N+ region, the Pwell region, the trench, the P+ region and the second current transmission layer. An eighth barrier layer is grown on the gate oxide layer, the eighth barrier layer is etched by photoresist and polysilicon is deposited, two gate regions are formed on the trench and the eighth barrier layer is removed. Specifically, as Fig.18 As shown in FIG. 19 , a gate oxide layer is grown on the P+plus region, the N+ region, the Pwell region, the trench, the P+ region, and the second current transmission layer. As shown in FIG. 19 , an eighth barrier layer is grown on the gate oxide layer, and the eighth barrier layer is etched by photoresist to form a deposition area for a polysilicon gate. The width of the deposition area of ​​the etched polysilicon gate can be adaptively set according to actual needs. Fig. 20 As shown, polysilicon is deposited in the polysilicon gate deposition area to form two polysilicon gate regions, which are located on both sides of the second current transmission layer and above the gate oxide layer. Then the eighth barrier layer forming the gate region is removed.

[0088] As an optional implementation, an oxide dielectric layer is formed to wrap the gate region, a source region and a Schottky contact region are deposited on the doped region, the oxide dielectric layer and the second current transfer layer, and a drain region is deposited at the bottom of the wafer to perform ohmic contact and Schottky contact to complete the production of the MOSFET structure, including: depositing an isolation dielectric layer on the gate oxide layer and the gate region to form an oxide dielectric layer and wrapping the gate region in the oxide dielectric layer. A ninth barrier layer is grown on the oxide dielectric layer, the ninth barrier layer is etched by photoresist and the oxide dielectric layer is etched through the ninth barrier layer to form a source metal deposition region and a Schottky contact electrode region, and the ninth barrier layer is removed. After depositing source metal in the source metal deposition region to form a source region, drain metal is deposited at the bottom of the wafer to form a drain region to complete ohmic contact. While depositing source metal in the source metal deposition region to form a source region, a Schottky contact electrode is deposited on the Schottky contact electrode region to form a Schottky contact region to complete Schottky contact. Specifically, as Fig.21 As shown, an isolation dielectric layer is deposited on the gate oxide layer and the gate region to form an oxide dielectric layer, and the gate region is wrapped in the oxide dielectric layer. Fig. 22 As shown, a ninth barrier layer is grown on the oxidized dielectric layer, and the ninth barrier layer is etched by photoresist to form an oxidized dielectric layer etching region. While forming the oxidized dielectric layer etching region, the gate region and the gate oxide layer below the gate region and the isolation dielectric layer above the gate region are protected (that is, when etching the ninth barrier layer, the region of the ninth barrier layer corresponding to the gate region is not etched). Fig.23 As shown, the etched area of ​​the oxide dielectric layer is further etched downward by photoresist to form a source metal deposition area and a Schottky contact electrode area. Then, the ninth barrier layer forming the source metal deposition area and the Schottky contact electrode area is removed. Fig.24 As shown, drain metal is deposited at the bottom of the wafer to form a drain region, source metal is deposited in the source metal deposition region to form a source region, and at the same time, a Schottky contact electrode is deposited on the Schottky contact electrode region to form a Schottky contact region, ohmic contact is completed through the drain region and the source region, and Schottky contact is completed through the Schottky contact region to form a MOSFET structure.

[0089] Fig.25 This is a comparison diagram of the output characteristic curves of a conventional planar MOSFET structure with an integrated Schottky structure and the MOSFET structure of the present invention under normal conduction conditions. Figure 1 It can be seen that under normal conduction and the same driving voltage, the saturation current of the MOSFET structure of the present invention is much smaller than that of the conventional planar MOSFET structure with integrated Schottky structure. Fig.26 This is a comparison diagram of gate oxide strength between a conventional planar MOSFET structure with integrated Schottky structure and the MOSFET structure of the present invention within a certain process window. Figure 2It can be seen that under the reverse bias state, within a certain process window, the gate oxide strength of the MOSFET structure of the present invention remains unchanged, while the gate oxide electric field strength of the conventional integrated Schottky structure planar MOSFET structure fluctuates greatly with the influence of the change of doping concentration. Therefore, the MOSFET structure of the present invention has good short-circuit performance and good reliability, can make the device work stably and for a long time without failure, and has good market appeal.

[0090] Embodiment 2:

[0091] like Figure 2-Figure 24 As shown, a MOSFET structure includes: a wafer 1, a doped region 2, a p-type shielding region 3, a groove 4, two gate regions 5, an oxidized dielectric layer 6, a source region 7, a Schottky contact region 8 and a drain region 9. The wafer 1 includes a first current transmission layer 13 and a second current transmission layer 14, and the first current transmission layer 13 wraps the side of the second current transmission layer 14. The groove 4 is arranged on both sides of the second current transmission layer 14, and the doped region 2 and the gate region 5 are arranged on both sides of the second current transmission layer 14. The p-type shielding region 3 is arranged on both sides of the wafer 1, and the p-type shielding region 3 is located below the groove 4. The source region 7, the oxidized dielectric layer 6 and the Schottky contact region 8 are arranged on both sides above the doped region 2 and the second current transmission layer 14 from the outside to the inside, and the oxidized dielectric layer 6 wraps the gate region 5, and the drain region 9 is arranged at the bottom of the wafer 1.

[0092] Specifically, the MOSFET structure of this embodiment is obtained by adopting the manufacturing method in the first embodiment of the present invention. In the manufacturing process, it is necessary to grow the first barrier layer 101 on the first current transmission layer 13 according to the method steps of the first embodiment and etch it, so as to make a wafer 1 having the first current transmission layer 13 and the second current transmission layer 14. The two current transmission layers can improve the effect of increasing the current path and reducing the on-resistance. In the process of manufacturing the MOSFET structure, it is necessary to grow the second barrier layer 102 on the wafer 1 according to the method steps of the first embodiment and etch it, so as to inject the p-type shielding region 3 into the two current transmission layers of the wafer 1. The p-type shielding region 3 is used for the gate region 5 and the Schottky contact region 8 of the MOSFET structure. By growing the third barrier layer 103 on the wafer 1 according to the method steps of the first embodiment and etching it, the groove 4 is etched on both sides of the wafer 1. By growing the fourth barrier layer 104, the fifth barrier layer 105, the sixth barrier layer 106 and the seventh barrier layer 107 on the wafer 1 according to the method steps of the first embodiment and etching them, the doping region 2 is set on both sides of the second current transmission layer 14. By growing a gate oxide layer 61 and an eighth barrier layer 108 on the doped region 2 and the wafer 1 according to the method steps of the first embodiment and etching the eighth barrier layer 108 , both gate regions 5 are disposed in the trench 4 and on the doped region 2 .

[0093] The oxidized dielectric layer 6 is arranged on the doped region 2 to wrap the gate region 5, and the oxidized dielectric layer 6 is composed of a gate oxide layer 61 and an isolation dielectric layer 62. The ninth barrier layer 109 is grown on the oxidized dielectric layer 6 and etched according to the method steps of the first embodiment, so that the source region 7 and the Schottky contact region 8 are deposited in the corresponding etched area, so that the P+plus region 23, the N+ region 22, the Pwell region 21 and the upper sides of the second current transmission layer 14 are respectively provided with the source region 7, the oxidized dielectric layer 6 and the Schottky contact region 8 from the outside to the inside, and the gate region 5 is arranged in the middle of the oxidized dielectric layer 6. The Schottky contact region 8 is arranged between the two P+ regions 24 arranged above the second current transmission layer 14.

[0094] The MOSFET structure of the present invention can reduce the saturation current, improve the short-circuit capability, and provide good protection for the gate oxide, thereby improving the reliability and durability of the MOSFET structure, while maintaining its flow capacity without loss, constant on-resistance, and maintaining a certain breakdown voltage. Within a certain process range, the gate oxide layer of the MOSFET structure of the present invention can only withstand a relatively low electric field strength under a reverse bias state, and the electric field strength hardly changes. In addition, under the linkage of the p-type shielding region 3 and the P+ region 24, the device gate-drain capacitance is relatively small, the switching speed is relatively fast, and a shielding effect is effectively produced on large currents, and the short-circuit tolerance time is increased.

[0095] As an optional implementation, the width range of the groove 4 is 1um-1.4um, and the depth range of the groove 4 is 0.1um-0.5um; the depth range of the p-type shielding region 3 is 1um-1.5um, and the width range of the p-type shielding region 3 is 1.4um-2um. Specifically, the width range and depth range of the groove 4 and the width range and depth range of the p-type shielding region 3 can be adaptively set according to time requirements.

[0096] As an optional embodiment, the wafer 1 includes an N+ substrate layer 11, an N-epitaxial layer 12, a first current transmission layer 13 and a second current transmission layer 14. The N+ substrate layer 11, the N-epitaxial layer 12, the first current transmission layer 13 and the second current transmission layer 14 are stacked in sequence from bottom to top, and the first current transmission layer 13 wraps the side of the second current transmission layer 14. The thickness of the first current transmission layer 13 is in the range of 1.5um-3um; the width of the second current transmission layer 14 is in the range of 0.4um-1um, and the depth of the second current transmission layer 14 is in the range of 0um-2um. Specifically, the N-epitaxial layer 12 is arranged above the N+ substrate layer 11, the first current transmission layer 13 is arranged on the N-epitaxial layer 12, and the second current transmission layer 14 is arranged in the middle above the first current transmission layer 13, and the bottom and side of the second current transmission layer 14 are wrapped by the first current transmission layer 13, thereby forming the wafer 1. The first current transmission layer 13 is used to increase the current path and reduce the on-resistance, and the second current transmission layer 14 is used to further increase the current path and reduce the on-resistance.

[0097] As an optional embodiment, the doping region 2 includes a first doping region and a second doping region, the first doping region includes a Pwell region 21, an N+ region 22 and a P+plus region 23, the second doping region includes a P+ region 24, the P+ region 24 is arranged at the upper and lower ends of the second current transmission layer 14 opposite to the p-type shielding region 3, the P+ region 24 is arranged on both sides above the second current transmission layer 14, and the P+ region 24 is in contact with the oxide dielectric layer 6, and the p-type shielding region 3 is arranged on both sides below the second current transmission layer 14. The Pwell region 21 is arranged above the p-type shielding region 3, and the P+plus region 23 and the N+ region 22 are arranged on both sides above the Pwell region 21 from the outside to the inside, and the P+ region 24 is arranged on both sides above the second current transmission layer 14. The depth of the Pwell region 21 is in the range of 0.9um-1.2um, the depth of the N+ region 22 is in the range of 0.1um-0.4um, the depth of the P+plus region 23 is in the range of 0.2um-1um, the depth of the P+ region 24 is in the range of 0.1um-0.3um, and the width of the P+ region 24 is in the range of 0.1um-0.5um. Specifically, the Pwell region 21 and the second current transmission layer 14 are arranged on both sides above the p-type shielding region 3 from the outside to the inside. The P+ region 24 is used to further protect the gate region 5 and the Schottky contact region 8.

[0098] The above description is only the preferred embodiment of the present invention. It is known to those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application belong to the protection scope of the present invention.

Claims

1. A method for manufacturing a MOSFET structure, characterized in that: include: Manufacturing a wafer, performing ion implantation on the wafer to form a p-type shielding region, and etching a groove on the wafer, wherein the wafer comprises a first current transport layer and a second current transport layer, wherein the first current transport layer wraps a side surface of the second current transport layer; The grooves are distributed on both sides of the second current transport layer, and the p-type shielding region is located below the grooves; forming doped regions on both sides of the second current transport layer, wherein the doped regions include a first doped region and a second doped region, the first doped region is located below the trench, and the second doped region is located on both sides above the second current transport layer; Growing a gate oxide layer and an eighth barrier layer on the doped region and the wafer, etching the eighth barrier layer by photoresist and depositing polysilicon to form two gate regions; Forming an oxide dielectric layer to wrap the gate region, depositing a source region and a Schottky contact region on the doped region, the oxide dielectric layer and the second current transmission layer, depositing a drain region at the bottom of the wafer, making ohmic contacts and Schottky contacts, and completing the manufacture of a MOSFET structure; Among them, the first doped region includes a Pwell region, an N+ region and a P+plus region, the second doped region includes a P+ region, the P+ region and the p-type shielding region are arranged at the upper and lower ends of the second current transmission layer opposite to each other, the P+ region is arranged on both sides above the second current transmission layer, and the P+ region is in contact with the oxide medium layer, and the p-type shielding region is arranged on both sides below the second current transmission layer; the Pwell region is arranged above the p-type shielding region, and the P+plus region and the N+ region are arranged on both sides above the Pwell region in sequence from the outside to the inside; the gate region isolates the P+ region from the Pwell region, the N+ region and the P+plus region.

2. The method for manufacturing a MOSFET structure according to claim 1, characterized in that: The wafer manufacturing method comprises: After growing an N-epitaxial layer on the N+ substrate layer, growing a first current transport layer on the N-epitaxial layer; After growing a first blocking layer on the first current transport layer, etching and N ion implantation are performed on the middle of the first blocking layer using photoresist to form a second current transport layer and removing the first blocking layer, thereby completing the manufacture of the wafer.

3. The method for manufacturing a MOSFET structure according to claim 2, characterized in that: The step of performing ion implantation on the wafer to form a p-type shielding region and etching a groove on the wafer comprises: After growing a second blocking layer on the first current transport layer and the second current transport layer, etching both sides of the second blocking layer and implanting Al+ ions through photoresist to form a p-type shielding region and removing the second blocking layer; Growing a third blocking layer on the second current transport layer of the wafer, and etching two sides of the third blocking layer by photoresist to form a groove area; Then, etching is performed along the groove region into the wafer to form grooves on both sides of the wafer and remove the third barrier layer.

4. The method for manufacturing a MOSFET structure according to claim 3, characterized in that: The forming of doped regions on both sides of the second current transport layer comprises: Growing a fourth blocking layer on the groove and the second current transport layer, etching both sides of the fourth blocking layer by photoresist and implanting Al+ ions to form a Pwell region and removing the fourth blocking layer; Growing a fifth blocking layer on the Pwell region, the trench and the second current transport layer, etching and N ion implanting on both sides of the fifth blocking layer by photoresist to form an N+ region and removing the fifth blocking layer; Growing a sixth blocking layer on the N+ region, the Pwell region, the trench and the second current transport layer, etching both sides of the sixth blocking layer and implanting Al+ ions through photoresist to form a P+plus region and removing the sixth blocking layer; A seventh blocking layer is grown on the P+plus region, the N+ region, the Pwell region, the trench and the second current transport layer, and the seventh blocking layer is etched and Al+ ion implanted by photoresist to form a P+ region and remove the seventh blocking layer.

5. The method for manufacturing a MOSFET structure according to claim 4, characterized in that: The method of growing a gate oxide layer and an eighth barrier layer on the doped region and the wafer, etching the eighth barrier layer by photoresist and depositing polysilicon to form gate regions on both sides includes: growing a gate oxide layer on the P+plus region, the N+ region, the Pwell region, the trench, the P+ region and the second current transport layer; The eighth barrier layer is grown on the gate oxide layer, the eighth barrier layer is etched by photoresist and polysilicon is deposited, two gate regions are formed on the trench and the eighth barrier layer is removed.

6. The method for manufacturing a MOSFET structure according to claim 5, characterized in that: The step of forming an oxide dielectric layer to wrap the gate region, depositing a source region and a Schottky contact region on the doped region, the oxide dielectric layer and the second current transmission layer, depositing a drain region at the bottom of the wafer, and making ohmic contacts and Schottky contacts to complete the manufacture of a MOSFET structure includes: Depositing an isolation dielectric layer on the gate oxide layer and the gate region to form an oxide dielectric layer and wrapping the gate region in the oxide dielectric layer; Growing a ninth barrier layer on the oxidized dielectric layer, etching the ninth barrier layer by photoresist and etching the oxidized dielectric layer through the ninth barrier layer to form a source metal deposition region and a Schottky contact electrode region, and removing the ninth barrier layer; After depositing source metal in the source metal deposition area to form a source region, a drain metal is deposited at the bottom of the wafer to form a drain region to complete ohmic contact; While depositing source metal in the source metal deposition area to form a source region, a Schottky contact electrode is deposited on the Schottky contact electrode area to form a Schottky contact area, completing the Schottky contact, thereby completing the manufacture of the MOSFET structure.

7. A MOSFET structure, characterized in that: include: A wafer, a doped region, a p-type shielding region, a trench, two gate regions, an oxide dielectric layer, a source region, a Schottky contact region and a drain region; the wafer comprises a first current transmission layer and a second current transmission layer, the first current transmission layer wraps the side of the second current transmission layer; the trench is arranged on both sides of the second current transmission layer, the doped region and the gate region are arranged on both sides of the second current transmission layer, the p-type shielding region is arranged on both sides of the wafer, and the p-type shielding region is located below the trench; The source region, the oxidized dielectric layer and the Schottky contact region are respectively disposed on both sides above the doped region and the second current transmission layer from outside to inside, and the oxidized dielectric layer wraps the gate region; the drain region is disposed at the bottom of the wafer; The doping region includes a first doping region and a second doping region, the first doping region includes a Pwell region, an N+ region and a P+plus region, the second doping region includes a P+ region, the P+ region and the p-type shielding region are arranged at the upper and lower ends of the second current transmission layer opposite to each other, the P+ region is arranged on both sides above the second current transmission layer, and the P+ region is in contact with the oxide medium layer, and the p-type shielding region is arranged on both sides below the second current transmission layer; the Pwell region is arranged above the p-type shielding region, and the P+plus region and the N+ region are arranged on both sides above the Pwell region in sequence from the outside to the inside; the gate region isolates the P+ region from the Pwell region, the N+ region and the P+plus region.

8. The MOSFET structure according to claim 7, characterized in that: The width of the groove is in the range of 1um-1.4um, and the depth of the groove is in the range of 0.1um-0.5um; the depth of the p-type shielding region is in the range of 1um-1.5um, and the width of the p-type shielding region is in the range of 1.4um-2um.

9. The MOSFET structure according to claim 7, characterized in that: The wafer also includes an N+ substrate layer and an N-epitaxial layer. The N+ substrate layer, the N-epitaxial layer, the first current transmission layer and the second current transmission layer are stacked in sequence from bottom to top, and the first current transmission layer wraps the side of the second current transmission layer; the thickness range of the first current transmission layer is 1.5um-3um; the width range of the second current transmission layer is 0.4um-1um, and the depth range of the second current transmission layer is 0um-2um.

10. The MOSFET structure according to claim 9, characterized in that: The depth range of the Pwell region is 0.9um-1.2um, the depth range of the N+ region is 0.1um-0.4um, the depth range of the P+plus region is 0.2um-1um, the depth range of the P+ region is 0.1um-0.3um, and the width range of the P+ region is 0.1um-0.5um.

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