Chip stacking packaging structure and packaging method

Abstract

The invention relates to a chip stacking packaging structure and a packaging method, and relates to the technical field of microelectronic packaging. The device comprises a packaging shell, a first chip, a second chip, an adhesive layer, a bonding wire, a packaging substrate and substrate outer pins, the first shell and the second shell are located in the packaging shell, and the packaging substrate is coated with the packaging shell; the packaging substrate is provided with substrate outer pins; the front surface of the first chip is fixedly connected with the front surface of the packaging substrate through the salient points; the back surface of the second chip is connected with the back surface of the first chip through an adhesive; and the front surface of the second chip is connected with the packaging substrate through a bonding wire. According to the invention, the two chips are packaged in a stacked manner in a manner of combining back-off welding and bonding, so that the number of packaging external leading-out ends is effectively increased, and the efficiency of the chip preparation process is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of microelectronic packaging, and in particular to a chip stacking packaging structure and a packaging method. Background Art

[0002] Packaging refers to the process of bonding the bare chip of integrated circuits to the packaging substrate that plays a supporting role, leading out the pins, and then fixing the package to form a whole. The purpose of packaging is to protect the bare chip, enhance its mechanical strength and facilitate subsequent mounting processing, so as to better realize the function of the chip. With the rapid development of the field of microelectronics, people's demand for high-density and high-integration packaging is increasing. Single chip packaging can no longer meet people's needs, so research on multi-chip packaging is becoming increasingly urgent.

[0003] At present, the packaging of multiple chips is mainly carried out by staggered chip stacking, but this method has high requirements on chip stacking accuracy and bonding technology, and it is easy to cause scratches on the chip surface during stacking, causing the wiring area on the chip surface to be damaged, and then causing the chip to fail such as malfunction during use.

[0004] That is, the stacked chip manufacturing yield in the related art is low, and the manufacturing process results in a small number of lead terminals. Summary of the invention

[0005] The present invention relates to a chip stacking packaging structure and a packaging method, which can increase the number of external lead terminals of the package after the chips are stacked and enhance the stability of the chip stacking packaging. The technical solution is as follows: On the one hand, a chip stacking packaging structure is provided, which includes a packaging shell, a first chip, a second chip, an adhesive layer, a bonding wire, a packaging substrate, and substrate external pins; The packaging substrate has substrate external pins; The front side of the first chip is fixedly connected to the front side of the packaging substrate via bumps; the back side of the first chip faces upwards; The back side of the second chip is connected to the back side of the first chip by the adhesive; The bonding fingers of the second chip are connected to the bonding fingers on the front side of the substrate through bonding wires, and the front side of the packaging substrate is covered with a packaging shell.

[0006] In an optional embodiment, the bumps on the front side of the first chip are implemented as ball implants.

[0007] In an optional embodiment, the material of the bump is tin-lead alloy, tin-silver-copper alloy, copper or gold.

[0008] In an optional embodiment, the packaging substrate is a ceramic substrate, a copper-clad substrate or a plastic-encapsulated substrate.

[0009] In an optional embodiment, the bonding wire is a gold wire, a silicon aluminum wire or a copper wire.

[0010] In an optional embodiment, the material of the external pins of the substrate is tin, lead, tin-lead alloy or tin-silver-copper alloy.

[0011] In an optional embodiment, the packaging shell is made of ceramic, metal or plastic resin.

[0012] In an optional embodiment, the adhesive is a conductive, insulating, thermally conductive or corrosion-resistant adhesive.

[0013] On the other hand, a packaging method of a chip stacking packaging structure is provided, the method is used to prepare any of the above chip stacking packaging structures, the method comprising: Step S1: obtaining a packaging substrate; Step S2: printing solder on the front pad of the package substrate, aligning the front of the first chip with the front pad of the package substrate using a fixture; placing the first chip in a high-temperature furnace or a reflow furnace for heating and welding, so that the first chip and the package substrate are fixedly interconnected; the reflow peak temperature of the heating and welding is 220°C-255°C; the reflow time is: 115-125s; so that the first chip and the package substrate are fixedly interconnected; Step S3: after the welding is completed, an adhesive is applied on the back of the first chip to form an adhesive layer, and the first chip and the second chip are bonded together through the adhesive layer; and then heated and cured; the heating and curing temperature is 175° C.-200° C.; and the curing time is 28 min-35 min; Step S4: connecting the bonding fingers of the second chip to the bonding fingers of the package substrate through bonding wires; Step S5: The packaging shell is fixed on the front side of the packaging substrate to cover the first chip, the second chip and the bonding wires, thereby completing the chip stacking packaging.

[0014] In an optional embodiment, the packaging shell is fixed to the front side of the packaging substrate by means of plastic molding, bonding, gold-tin solder welding or parallel sealing.

[0015] The beneficial effects brought about by the technical solution provided by the present invention include at least: In the chip stacking packaging structure, the lower chip is packaged in the form of flip-flop welding, and the electrical structure is interconnected by bonding with the packaging substrate using metal bumps. The upper chip is fixed to the back of the lower chip with adhesive, and the bonding fingers of the upper chip are connected to the substrate keys and fingers through bonding wires. The upper chip and the lower chip are covered with an encapsulation structure. The combination of flip-flop welding and bonding enables the two chips to be stacked and packaged, effectively increasing the number of external lead terminals of the package and improving the efficiency of the chip preparation process. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 A structural front view of a chip stacking package structure provided by an exemplary embodiment of the present invention is shown.

[0018] Figure 2 A top view of a chip stacking package structure provided by an exemplary embodiment of the present invention is shown.

[0019] Figure 3 A schematic flow chart of a packaging method for a chip stacking packaging structure provided by an exemplary embodiment of the present invention is shown. DETAILED DESCRIPTION

[0020] In order to make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0021] Example 1 Figure 1 FIG. 4 shows a front view of a chip stacking package structure provided by an exemplary embodiment of the present invention. Figure 2 The corresponding top view of the structure is shown, please refer to Figure 1 as well as Figure 2 The chip stacking package structure includes a package shell 1, a first chip 2, a second chip 3, an adhesive 4, a bonding wire 5, a bump 6, a package substrate 7 and a substrate external pin 8; The first shell and the second shell are located inside the packaging shell, and the front side of the packaging substrate 7 is covered by the packaging shell 1; The packaging substrate 7 has substrate external pins 8; The front side of the first chip 2 is fixedly connected to the front side of the packaging substrate 7 via the bumps 6; The back side of the second chip 3 is connected to the back side of the first chip 2 by means of adhesive 4; The front surface of the second chip 3 is connected to the packaging substrate 7 via bonding wires 5 .

[0022] Next, the specific materials of each part in the chip stacking package structure are described: In an optional embodiment, the adhesive may be a conductive adhesive, or an insulating adhesive, or a thermally conductive adhesive, or a corrosion-resistant adhesive. The present invention does not limit the actual material of the adhesive.

[0023] In an optional embodiment, the bumps are implemented as ball implants.

[0024] In an optional embodiment, the material of the bump is tin-lead alloy, tin-silver-copper alloy, copper or gold. Optionally, the bonding wire is gold wire, silicon-aluminum wire or copper wire.

[0025] In an optional embodiment, the material of the packaging substrate is a copper clad substrate.

[0026] In an optional embodiment, the material of the external pins of the substrate is tin, lead, tin-lead alloy or tin-silver-copper alloy.

[0027] In an optional embodiment, the second chip has bonding fingers, and the bonding fingers are used to connect bonding wires.

[0028] In an optional embodiment, the bumps on the front side of the first chip are implemented as ball implants.

[0029] In an optional embodiment, the bump material is tin-lead alloy, tin-silver-copper alloy, copper or gold.

[0030] In an optional embodiment, the packaging substrate is a ceramic substrate, a copper-clad substrate or a plastic-encapsulated substrate.

[0031] In an optional embodiment, the bonding wire is a gold wire, a silicon aluminum wire or a copper wire.

[0032] In an optional embodiment, the material of the external pins of the substrate is tin, lead, tin-lead alloy or tin-silver-copper alloy.

[0033] In an optional embodiment, the packaging shell is made of ceramic, metal or plastic resin.

[0034] In an optional embodiment, the adhesive is an electrically conductive, insulating, thermally conductive or corrosion-resistant adhesive.

[0035] Figure 3 A schematic diagram of a packaging method for a chip stacking packaging structure provided by an exemplary embodiment of the present invention is shown, and the method is applied to preparing Figure 1 to Figure 2Taking the chip stacking package structure shown in FIG. 1 as an example, the method includes: Step S1, obtaining a packaging substrate.

[0036] The packaging substrate is the initial material for preparing the packaging structure shown in the embodiment of the present invention.

[0037] Step S2, printing a layer of solder on the front pad of the package substrate.

[0038] In the embodiment of the present invention, the material type selected for the printed solder is Pb90Sn10.

[0039] Step S3, aligning the package substrate after printing the solder with the first chip.

[0040] Optionally, the first chip is moved by a fixture to align the first chip with the packaging substrate after the solder is printed.

[0041] Step S4, when the alignment is completed, the packaging substrate and the first chip are placed in a reflow furnace for heating and welding.

[0042] In the embodiment of the present invention, the heating welding temperature and curve are determined according to the material of the bumps of the corresponding first chip.

[0043] In the embodiment of the present invention, the peak temperature is 245° C. and the reflow time is 120 seconds, so that the first chip and the packaging substrate are fixedly interconnected.

[0044] Step S5, when the welding is completed, apply adhesive on the back side of the first chip to form an adhesive layer.

[0045] In the embodiment of the present invention, the model of the adhesive is sy-73 conductive adhesive, and the thickness of the adhesive layer is determined according to the thickness of the first chip, which is not limited in the embodiment of the present invention.

[0046] Step S6, bonding the first chip to the back side of the second chip through the bonding layer, and heating and curing the bonding.

[0047] In the embodiment of the present invention, the heating curing temperature is 175° C. and the curing time is 30 minutes.

[0048] Step S7, connecting the bonding fingers of the second chip and the bonding fingers of the package substrate through bonding wires.

[0049] The bonding wire is made of 20um gold wire.

[0050] Step S8, fixing the packaging shell on the front side of the packaging substrate, and encapsulating the first chip, the second chip and the bonding wires through the packaging shell.

[0051] The encapsulation shell is encapsulated by plastic resin molding to complete the entire encapsulation method.

[0052] After the bonding wires are assembled, the second chip is connected to the electrical structure by bonding.

[0053] Example 2 like Figure 1 and Figure 2 According to the technical solution provided by the present invention, the chip stacking packaging structure includes a packaging shell 1, a first chip 2, a second chip 3, an adhesive 4, a bonding wire 5, a bump 6, a packaging substrate 7 and a substrate external pin 8; Step S1, print a layer of solder paste on the front pad of the packaging substrate, use a fixture to align the front of the first chip with the front pad of the packaging substrate, put it into a reflow oven for heating and welding, with a peak temperature of 220°C and a reflow time of 120s, so that the first chip and the packaging substrate are fixedly interconnected.

[0054] Step S2, bonding glue on the back of the first chip, using insulating glue produced by Henkel Loctite, bonding the first chip to the back of the second chip, and then heating and curing, the heating temperature is 175° C., and the heating time is 30 minutes.

[0055] Step S3: Connect the bonding fingers of the second chip and the bonding fingers of the package substrate through bonding wires, wherein the bonding wires are made of 31.75 um silicon aluminum wires.

[0056] Step S4, fixing the packaging shell on the front side of the packaging substrate, covering the first chip, the third chip and the bonding wires, and molding the packaging shell with a plastic resin to complete the entire packaging method.

[0057] In summary, the device and method provided by the embodiment of the present invention, in the chip stacking packaging structure, the lower chip is packaged in the form of flip-flop welding, and the electrical structure is interconnected by bonding with the packaging substrate using metal bumps, the upper chip is fixed to the back of the lower chip using adhesive, the bonding fingers of the upper chip are connected to the substrate keys and fingers through bonding wires, and the upper chip and the lower chip are coated with an encapsulation structure. By combining flip-flop welding and bonding, two chips are stacked and packaged, which effectively increases the number of external lead terminals of the package and improves the efficiency of the chip preparation process.

[0058] The above are only optional embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A chip stacking packaging structure, It is characterized in that The chip stacking packaging structure comprises a packaging shell, a first chip, a second chip, an adhesive layer, bonding wires, a packaging substrate and substrate external pins; The packaging substrate has substrate external pins; The front side of the first chip is fixedly connected to the front side of the packaging substrate via bumps; the back side of the first chip faces upwards; The back side of the second chip is connected to the back side of the first chip by the adhesive; The bonding fingers of the second chip are connected to the bonding fingers on the front side of the substrate through bonding wires, and the front side of the packaging substrate is covered with a packaging shell.

2. The chip stacking package structure according to claim 1, It is characterized in that The bumps on the front side of the first chip are implemented as ball implants.

3. The chip stacking package structure according to claim 2, It is characterized in that The material of the bumps is tin-lead alloy, tin-silver-copper alloy, copper or gold.

4. The chip stacking package structure according to claim 1, It is characterized in that The packaging substrate is a ceramic substrate, a copper-clad substrate or a plastic-encapsulated substrate.

5. The chip stacking package structure according to claim 1, It is characterized in that The bonding wire is a gold wire, a silicon aluminum wire or a copper wire.

6. The chip stacking package structure according to claim 1, It is characterized in that The material of the outer pins of the substrate is tin, lead, tin-lead alloy or tin-silver-copper alloy.

7. The chip stacking package structure according to claim 1, It is characterized in that The packaging shell is made of ceramic, metal or plastic resin.

8. The chip stacking package structure according to claim 1, It is characterized in that The adhesive is conductive, insulating, thermally conductive or corrosion-resistant.

9. A packaging method for a chip stacking packaging structure, It is characterized in that The method is applied to prepare a chip stacking package structure as claimed in any one of claims 1 to 6, and the method comprises: Step S1: obtaining a packaging substrate; Step S2: printing solder on the front pad of the package substrate, aligning the front of the first chip with the front pad of the package substrate using a fixture; placing the first chip in a high-temperature furnace or a reflow furnace for heating and welding, so that the first chip and the package substrate are fixedly interconnected; the reflow peak temperature of the heating and welding is 220°C-255°C; the reflow time is: 115-125s; so that the first chip and the package substrate are fixedly interconnected; Step S3: after the welding is completed, an adhesive is applied on the back of the first chip to form an adhesive layer, and the first chip and the second chip are bonded together through the adhesive layer; and then heated and cured; the heating and curing temperature is 175° C.-200° C.; and the curing time is 28 min-35 min; Step S4: connecting the bonding fingers of the second chip to the bonding fingers of the package substrate through bonding wires; Step S5: The packaging shell is fixed on the front side of the packaging substrate to cover the first chip, the second chip and the bonding wires, thereby completing the chip stacking packaging.

10. The packaging method of a chip stacking packaging structure according to claim 9, It is characterized in that The packaging shell is fixed on the front side of the packaging substrate by means of plastic molding, bonding, gold-tin solder welding or parallel sealing.

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