Semiconductor device

Abstract

Provided is a semiconductor device capable of improving element performance and reliability. The semiconductor device may include: an active pattern including a lower pattern extending in a first direction on a substrate and a sheet pattern on the lower pattern; a field insulating layer, the field insulating layer defining the active pattern on the substrate; a gate structure on the lower pattern and including a gate insulating layer and a gate electrode, the gate electrode extending in a second direction perpendicular to the first direction; a gate spacer at least partially surrounding the gate structure, and including a first portion on a sidewall of the gate structure and a second portion on a bottom surface of the gate structure; and a source / drain pattern on the lower pattern and in contact with the sheet pattern.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices, and more particularly to a multi-bridge channel field effect transistor (MBCFET) comprising TM ) semiconductor devices. Background Art

[0002] As one of scaling technologies for increasing the density of semiconductor devices, a multi-gate transistor has been proposed, in which a multi-channel active pattern (or silicon body) in a fin or nanowire shape is formed on a substrate and a gate is formed on a surface of the multi-channel active pattern.

[0003] Since the multi-gate transistor uses a three-dimensional (3D) channel, it is easy to achieve scaling of the multi-gate transistor. In addition, the current control capability can be improved without increasing the gate length of the multi-gate transistor. In addition, the short channel effect (SCE) in which the potential of the channel region is affected by the drain voltage can be effectively suppressed. Summary of the invention

[0004] Aspects of the present disclosure provide a semiconductor device capable of improving element performance and reliability.

[0005] However, aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0006] According to some embodiments of the present disclosure, a semiconductor device is provided, comprising: an active pattern, the active pattern comprising a lower pattern extending in a first direction on a substrate and a sheet pattern located on the lower pattern, the first direction being parallel to a top surface of the substrate; a field insulation layer, the field insulation layer defining the active pattern on the substrate; a gate structure, the gate structure being located on the lower pattern and comprising a gate insulation layer and a gate electrode, the gate electrode extending in a second direction perpendicular to the first direction and parallel to the top surface of the substrate; a gate spacer, the gate spacer at least partially surrounding the gate structure and comprising a first portion located on a sidewall of the gate structure and a second portion located on a bottom surface of the gate structure; and a source / drain pattern, the source / drain pattern being located on the lower pattern and in contact with the sheet pattern.

[0007] According to some embodiments of the present disclosure, a semiconductor device is provided, the semiconductor device comprising: a plurality of active patterns, each of the active patterns comprising a lower pattern extending in a first direction on a substrate and a sheet pattern located on the lower pattern, the first direction being parallel to a top surface of the substrate; a field trench, the field trench being defined by the top surface of the substrate and the sidewall of the lower pattern; a field insulating layer, the field insulating layer being located in the field trench; a gate structure, the gate structure being located on the lower pattern and comprising a gate insulating layer and a gate electrode, the gate electrode extending in a second direction perpendicular to the first direction and parallel to the top surface of the substrate; a gate spacer, the gate spacer comprising a first portion extending in a third direction perpendicular to the top surface of the substrate along the sidewall of the gate structure and a second portion extending in the first direction along the top surface of the field insulating layer; a source / drain pattern, the source / drain pattern being located on the lower pattern and in contact with the sheet pattern; and a first interlayer insulating layer, the first interlayer insulating layer being located on the field insulating layer and the source / drain pattern and on one side of the gate structure.

[0008] According to some embodiments of the present disclosure, a semiconductor device is provided, the semiconductor device comprising: an active pattern, the active pattern comprising a lower pattern extending in a first direction on a substrate and a sheet pattern located on the lower pattern, the first direction being parallel to the top surface of the substrate; a field insulating layer, the field insulating layer defining the active pattern on the substrate; a gate structure, the gate structure being located on the lower pattern and comprising a gate insulating layer and a gate electrode, the gate electrode extending in a second direction perpendicular to the first direction and parallel to the top surface of the substrate; a gate spacer, the gate spacer at least partially surrounding the gate structure and comprising a first portion located on a sidewall of the gate structure and a second portion located on a bottom surface of the gate structure; a source / drain pattern, the source / drain pattern being located on the lower pattern and in contact with the sheet pattern; and a first interlayer insulating layer, the first interlayer insulating layer being located on the field insulating layer and the source / drain pattern and extending in the second direction. The second portion of the gate spacer may be located between the field insulating layer and the gate structure, but may not be located between the field insulating layer and the first interlayer insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects and features of the present disclosure will become more apparent by describing in detail example embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0010] Figure 1 is an example top view illustrating a semiconductor device according to some embodiments.

[0011] Figure 2 It is along Figure 1 Example cross-sectional view taken along line AA.

[0012] Figure 3 It is along Figure 1 An example cross-sectional view taken along line BB.

[0013] Figure 4 It is along Figure 1 Example cross-sectional view taken along line CC.

[0014] Figure 5 It is along Figure 1 An example cross-sectional view taken along line DD.

[0015] Figures 6 to 8 is a diagram illustrating a semiconductor device according to some embodiments.

[0016] Fig. 9 is a diagram illustrating a semiconductor device according to some embodiments.

[0017] Fig.10 is a diagram illustrating a semiconductor device according to some embodiments.

[0018] Fig.11 is a diagram illustrating a semiconductor device according to some embodiments.

[0019] Fig.12 is a diagram illustrating a semiconductor device according to some embodiments.

[0020] Figures 13 to 32 are diagrams illustrating intermediate steps of a method for fabricating a semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0021] The semiconductor device according to some embodiments may include a tunnel field effect transistor (FET), a three-dimensional (3D) FET, or a FET based on a two-dimensional (2D) material and a heterostructure thereof. In addition, the semiconductor device according to some embodiments may include a bipolar junction transistor (BJT), a lateral double diffused MOS (LDMOS) transistor, etc.

[0022] Will refer to Figures 1 to 5 A semiconductor device according to some embodiments is described.

[0023] Figure 1 is an example top view illustrating a semiconductor device according to some embodiments. Figure 2 It is along Figure 1 Example cross-sectional view taken along line AA. Figure 3 It is along Figure 1 An example cross-sectional view taken along line BB. Figure 4It is along Figure 1 Example cross-sectional view taken along line CC. Figure 5 It is along Figure 1 An example cross-sectional view taken along line DD.

[0024] Figure 1 It is a simplified view excluding the gate capping pattern 145 , the gate spacer 140 , the source / drain contacts 170 , the etch stop layer 185 , the first interlayer insulating layer 190 , and the like.

[0025] refer to Figures 1 to 5 , a semiconductor device according to some embodiments may include a substrate 100 , an active pattern AP1 , a plurality of gate structures GS1 , a gate spacer 140 , and a source / drain pattern 150 .

[0026] The substrate 100 may be a bulk silicon or silicon-on-insulator (SOI) substrate. Alternatively, the substrate 100 may be a silicon substrate, or may include other materials such as silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but is not limited thereto.

[0027] The active pattern AP1 may be disposed on the substrate 100. The active pattern AP1 may be elongated in a first direction D1 parallel to the top surface of the substrate 100. The active patterns AP1 may be spaced apart from each other in a second direction D2 parallel to the top surface of the substrate 100. The active patterns AP1 may be arranged in the second direction D2. For example, the first direction D1 may be a direction intersecting the second direction D2. In another example, the first direction D1 may be a direction perpendicular to the second direction D2.

[0028] For example, the active pattern AP1 may be disposed in a region where a PMOS is formed. For another example, the active pattern AP1 may be disposed in a region where an NMOS is formed.

[0029] The active pattern AP1 may be a multi-channel active pattern. The active pattern AP1 may include a lower pattern BP1 and a plurality of sheet patterns NS1. The lower pattern BP1 may protrude from the substrate 100. The lower pattern BP1 may be elongated in the first direction D1. For example, the lower pattern BP1 may extend longitudinally in the first direction D1.

[0030] The lower patterns BP1 may be spaced apart from each other in the second direction D2. The lower patterns BP1 may be separated from each other by field trenches FT extending in the first direction D1. The field trenches FT may be defined by sidewalls BP1_SW of the lower patterns BP1 and the top surface 100_US of the substrate 100.

[0031] A plurality of sheet patterns NS1 may be disposed above the lower pattern BP1. The plurality of sheet patterns NS1 may be spaced apart from the lower pattern BP1 in the third direction D3. For example, the third direction D3 may be a direction perpendicular to the top surface 100_US of the substrate 100. The plurality of sheet patterns NS1 spaced apart from each other may be arranged along the top surface of the lower pattern BP1 in the first direction D1.

[0032] The sheet pattern NS1 may include a plurality of nanosheets sequentially arranged in the third direction D3. Each sheet pattern NS1 may include a top surface NS1_US and a bottom surface NS1_BS (eg, see Figure 2 ). The top surface NS1_US of the first sheet pattern is opposite to the bottom surface NS1_BS of the first sheet pattern in the third direction D3. The top surface NS1_US of the sheet pattern NS1 may be connected to the bottom surface NS1_BS of the sheet pattern NS1 via the connection surface of the sheet pattern NS1. The connection surface of the sheet pattern NS1 may be connected to and in contact with the source / drain pattern 150 to be described later. The connection surface of the sheet pattern NS1 may be a boundary surface between the sheet pattern NS1 and the source / drain pattern 150.

[0033] The third direction D3 may intersect the first direction D1 and the second direction D2. For example, the third direction D3 may be a thickness direction of the substrate 100. The first direction D1 may be a direction intersecting the second direction D2. The third direction D3 may be perpendicular to the first direction D1 and the second direction D2. For example, the third direction D3 may be perpendicular to the top surface 100_US of the substrate 100.

[0034] The sheet pattern NS1 may include a plurality of sheet patterns NS1 (also referred to as sub-sheet patterns). For example, the plurality of sheet patterns NS1 may include a plurality of nanosheets, respectively. Although three sheet patterns NS1 are shown to be arranged in the third direction D3, this is only for simplicity of description, and the present disclosure is not limited thereto. For example, the number of sheet patterns NS1 may be four.

[0035] Each lower pattern BP1 may be formed by etching a portion of the substrate 100, or may include an epitaxial layer grown from the substrate 100. Each lower pattern BP1 may include silicon or germanium, both of which are elemental semiconductor materials. In addition, each lower pattern BP1 may include a compound semiconductor, such as a group IV-IV compound semiconductor or a group III-V compound semiconductor.

[0036] The IV-IV compound semiconductor may be a binary or ternary compound including at least two elements selected from the group consisting of carbon (C), silicon (Si), germanium (Ge) and tin (Sn), or the above compounds doped with a IV group element.

[0037] The III-V compound semiconductor may be, for example, a binary compound, a ternary compound, or a quaternary compound formed by combining at least one of the III-group elements aluminum (Al), gallium (Ga), or indium (In) with one of the V-group elements phosphorus (P), arsenic (As), or antimony (Sb).

[0038] The sheet pattern NS1 may include one of silicon or germanium as an elemental semiconductor material, a group IV-IV compound semiconductor, or a group III-V compound semiconductor. The sheet pattern NS1 may include the same material as the lower pattern BP1 or may include a material different from that of the lower pattern BP1.

[0039] In the semiconductor device according to some embodiments, the lower pattern BP1 may be a silicon lower pattern including silicon, and the sheet pattern NS1 may be a silicon sheet pattern including silicon.

[0040] Taking the active pattern AP1 as an example, the width of the first sheet pattern NS1 in the second direction D2 may be increased or decreased in proportion to the width of the lower pattern BP1 in the second direction D2. In one example, although the sheet patterns NS1 stacked in the third direction D3 are shown to have the same width in the second direction D2 (see, for example, FIG. Figure 4 ), but this is only for simplicity of description, and the present disclosure is not limited thereto. Unlike the illustrated example, the width of the sheet pattern NS1 stacked in the third direction D3 in the second direction D2 may decrease as the distance from the lower pattern BP1 increases.

[0041] The field insulating layer 105 may fill a portion (i.e., a part) of the field trench FT. For example, the field insulating layer 105 may be located in the field trench FT. The field insulating layer 105 may be disposed between adjacent lower patterns BP1. The field insulating layer 105 may extend in the first direction D1. The field insulating layer 105 may be formed on the top surface 100_US of the substrate 100. The field insulating layer 105 may cover a portion of the side wall BP1_SW of the lower pattern BP1. The field insulating layer 105 is not disposed on the top surface BP1_US of the lower pattern BP1. The top surface BP1_US of the lower pattern BP1 may protrude from the top surface of the field insulating layer 105 in the third direction D3. The field insulating layer 105 may define the active pattern AP1 on the substrate 100.

[0042] Each sheet pattern NS1 is disposed higher than the top surface of the field insulating layer 105. The field insulating layer 105 may include, for example, an oxide layer, a nitride layer, an oxynitride layer, or a combination thereof. Although the field insulating layer 105 is shown as a single layer, this is only for simplicity of description and the present disclosure is not limited thereto.

[0043] A plurality of gate structures GS1 may be disposed on the substrate 100. Each gate structure GS1 may extend in the second direction D2. The gate structures GS1 may be spaced apart from each other in the first direction D1. The gate structures GS1 may be adjacent to each other in the first direction D1.

[0044] The gate structure GS1 may be disposed on the active pattern AP1. The gate structure GS1 may cross the active pattern AP1.

[0045] The gate structure GS1 may cross the lower pattern BP1. The gate structure GS1 may surround each sheet pattern NS1. The gate structure GS1 may include, for example, a gate electrode 120 and a gate insulating layer 130.

[0046] Although the gate structure GS1 is shown to be disposed above the active pattern AP1, this is only for simplicity of description and the present disclosure is not limited thereto. That is, the gate structure GS1 may be divided into two parts so that the gate structure GS1 intersecting one active pattern AP1 may be spaced apart from the gate structure GS1 intersecting another active pattern AP1 in the second direction D2.

[0047] The gate structure GS1 may include a plurality of first inner gate structures INT_GS1 disposed between adjacent sheet patterns NS1 in the third direction D3 and between the lower pattern BP1 and the sheet pattern NS1. The first inner gate structure INT_GS1 may be disposed between a top surface of the lower pattern BP1 and a bottom surface of the sheet pattern NS1, and between a top surface of the sheet pattern NS1 and a bottom surface of the sheet pattern NS1 facing each other in the third direction D3.

[0048] The number of the inner gate structures INT_GS1 may be the same as the number of the sheet patterns NS1 The inner gate structures INT_GS1 contact a top surface of the lower pattern BP1 , a top surface of the sheet pattern NS1 , and a bottom surface of the sheet pattern NS1 .

[0049] The inner gate structure INT_GS1 includes a first gate electrode 120 and a first gate insulating layer 130 disposed between adjacent sheet patterns NS1 and between the lower pattern BP1 and the sheet pattern NS1.

[0050] In the semiconductor device according to some embodiments, the inner gate structure INT_GS1 may be in contact with the source / drain pattern 150 to be described later. For example, the inner gate structure INT_GS1 may be in direct contact with the source / drain pattern 150. The inner gate structure INT_GS1 is in contact with the top surface BP1_US of the lower pattern BP1, the top surface NS1_US of the sheet pattern NS1, and the bottom surface NS1_BS of the sheet pattern NS1.

[0051] In the semiconductor device according to some embodiments, each inner gate structure INT_GS1 may have the same width in the first direction D1. The width of each inner gate structure INT_GS1 in the first direction D1 may be the same as the width of the sheet pattern NS1 in the first direction D1. However, the present disclosure is not limited thereto.

[0052] Different from the illustration, in the semiconductor device according to some embodiments, the width of some inner gate structures INT_GS1 in the first direction D1 may be greater than the width of adjacent inner gate structures INT_GS1 in the first direction D1.

[0053] The gate electrode 120 may be formed on the lower pattern BP1. The gate electrode 120 may intersect the lower pattern BP1. The gate electrode 120 may extend in the second direction D2. The gate electrode 120 may cover the sheet pattern NS1.

[0054] Taking the active pattern AP1 as an example, a portion of the gate electrode 120 may be disposed between adjacent sheet patterns NS1, and between the lower pattern BP1 and the sheet pattern NS1. When the sheet pattern NS1 includes a first sub-sheet pattern and a second sub-sheet pattern adjacent to each other in the third direction D3, a portion of the gate electrode 120 may be disposed between a top surface NS1_US of the first sub-sheet pattern and a bottom surface NS1_BS of the second sub-sheet pattern facing each other. In addition, a portion of the gate electrode 120 may be disposed between a top surface BS1_US of the lower pattern BP1 and a bottom surface NS1_BS of the lowermost sheet pattern NS1. The first sub-sheet pattern may be the lowermost sheet pattern NS1, or may not be the lowermost sheet pattern NS1.

[0055] The gate electrode 120 may include at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, or a conductive metal oxynitride. The gate electrode 120 may include, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten ( At least one selected from the group consisting of W, aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V) or a combination thereof. The conductive metal oxide and the conductive metal oxynitride may include oxidized forms of the above materials, but are not limited thereto.

[0056] The gate electrode 120 may be disposed at both sides of a source / drain pattern 150 to be described later. The gate structure GS1 may be disposed at both sides of the source / drain pattern 150 in the first direction D1.

[0057] For example, the gate electrodes 120 disposed on both sides of the source / drain pattern 150 may be ordinary gate electrodes used as a transistor gate. As another example, the gate electrode 120 disposed on one side of the source / drain pattern 150 may be used as a transistor gate, and the gate electrode 120 disposed on the other side of the source / drain pattern 150 may be a dummy gate electrode.

[0058] The gate insulating layer 130 may extend along the top surface of the gate spacer 140 and the top surface BP1_US of the lower pattern BP1. The gate insulating layer 130 may cover the sheet pattern NS1. The gate insulating layer 130 may be disposed along the periphery of the sheet pattern NS1. The gate electrode 120 is disposed on the gate insulating layer 130.

[0059] A portion of the gate insulating layer 130 may be disposed between the sheet patterns NS1 adjacent to each other in the third direction D3, and between the lower pattern BP1 and the sheet pattern NS1. When the sheet pattern NS1 includes a first sub-sheet pattern and a second sub-sheet pattern adjacent to each other, a portion of the gate insulating layer 130 may extend along a top surface NS1_US of the first sub-sheet pattern and a bottom surface NS1_BS of the second sub-sheet pattern facing each other.

[0060] Although the gate insulating layer 130 is illustrated as a single layer, the present disclosure is not limited thereto. The gate insulating layer 130 may include an interface insulating layer and a high-k insulating layer. The interface insulating layer may be disposed between the high-k insulating layer and the sheet pattern NS1.

[0061] The gate insulating layer 130 may include silicon oxide, silicon oxynitride, silicon nitride, or a high-k material having a higher dielectric constant than silicon oxide. The high-k material may include, for example, at least one selected from the group consisting of boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0062] The semiconductor device according to some embodiments may include a negative capacitor (NC) FET (ie, NC-FET) using a negative capacitor (NC). For example, the gate insulating layer 130 may include a ferroelectric material layer having a ferroelectric property and a paraelectric material layer having a paraelectric property.

[0063] The ferroelectric material layer may have a negative capacitance, while the paraelectric material layer may have a positive capacitance. For example, when two or more capacitors are connected in series and the capacitance of each capacitor is positive, the total capacitance becomes smaller than the capacitance of each capacitor. On the other hand, when at least one of the capacitances of the two or more capacitors connected in series is negative, the total capacitance may be positive and may be greater than the absolute value of each capacitor.

[0064] When a ferroelectric material layer with negative capacitance and a paraelectric material layer with positive capacitance are connected in series, the total capacitance value of the ferroelectric material layer and the paraelectric material layer connected in series can be increased. By utilizing the principle of increasing the total capacitance value, the subthreshold swing (SS) of a transistor including a ferroelectric material layer at room temperature can be lower than or equal to a threshold voltage of 60mV / decade.

[0065] The ferroelectric material layer may have ferroelectric properties. The ferroelectric material layer may include, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, or zirconium titanium lead oxide. In this case, as an example, the hafnium zirconium oxide may be a material containing hafnium oxide doped with zirconium (Zr). As another example, the hafnium zirconium oxide may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0066] The ferroelectric material layer may further include a dopant doped therein. For example, the dopant may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr) or tin (Sn). The type of dopant included in the ferroelectric material layer may vary depending on the ferroelectric material included in the ferroelectric material layer.

[0067] When the ferroelectric material layer includes hafnium oxide, the dopant included in the ferroelectric material layer may include, for example, at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), or yttrium (Y).

[0068] When the dopant is aluminum (Al), the ferroelectric material layer may include 3 to 8 atomic percent (at%) of aluminum. In this case, the ratio of the dopant may be a ratio of aluminum to the sum of hafnium and aluminum.

[0069] When the dopant is silicon (Si), the ferroelectric material layer may contain 2 to 10 at% silicon. When the dopant is yttrium (Y), the ferroelectric material layer may contain 2 to 10 at% yttrium. When the dopant is gadolinium (Gd), the ferroelectric material layer may contain 1 to 7 at% gadolinium. When the dopant is zirconium (Zr), the ferroelectric material layer may contain 50 to 80 at% zirconium.

[0070] The paraelectric material layer may have paraelectric properties. The paraelectric material layer may include, for example, at least one of silicon oxide or metal oxide having a high dielectric constant. The metal oxide included in the paraelectric material layer may include, for example, at least one of hafnium oxide, zirconium oxide, or aluminum oxide, but is not limited thereto.

[0071] The ferroelectric material layer and the paraelectric material layer may include the same material. The ferroelectric material layer may have ferroelectric properties, but the paraelectric material layer may not have ferroelectric properties. For example, when the ferroelectric material layer and the paraelectric material layer include hafnium oxide, the crystal structure of the hafnium oxide included in the ferroelectric material layer is different from the crystal structure of the hafnium oxide included in the paraelectric material layer.

[0072] The ferroelectric material layer may have a thickness that exhibits ferroelectric properties. The thickness of the ferroelectric material layer may be, for example, in the range of 0.5 nanometers (nm) to 10 nm, but is not limited thereto. Since the critical thickness at which each ferroelectric material exhibits ferroelectric properties may be different, the thickness of the ferroelectric material layer may vary depending on the ferroelectric material.

[0073] In one example, the gate insulating layer 130 may include one ferroelectric material layer. In another example, the gate insulating layer 130 may include a plurality of ferroelectric material layers spaced apart from each other. The gate insulating layer 130 may have a laminated layer structure in which a plurality of ferroelectric material layers and a plurality of paraelectric material layers are alternately laminated.

[0074] In the semiconductor device according to some embodiments, the gate structure GS1 may further include a gate capping pattern 145. The gate capping pattern 145 may be disposed on the gate electrode 120, the gate insulating layer 130, and the gate spacer 140. For example, the gate capping pattern 145 may be located on the top surface of the gate electrode 120. The top surface of the gate capping pattern 145 may be located on the same plane as the top surface of the first interlayer insulating layer 190 (e.g., may be coplanar therewith). Unlike the illustrated example, the gate capping pattern 145 may be disposed between the gate spacers 140.

[0075] The gate capping pattern 145 may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), or a combination thereof. The gate capping pattern 145 may include, for example, a material having an etching selectivity with respect to the first interlayer insulating layer 190 .

[0076] The gate spacer 140 may be disposed on the field insulating layer 105 and the active pattern AP1. The gate spacer 140 may surround the gate structure GS1. For example, the gate spacer 140 may surround a portion of the gate structure GS1. The gate spacer 140 may extend in the second direction D2 along the sidewall GS1_SW of the gate structure GS1 (for example, see Figure 3 ). The gate spacer 140 may be disposed on the bottom surface GS1_BS of the gate structure GS1. It will be understood that "element A surrounds element B" (or similar language) used herein means that element A at least partially surrounds element B, but does not necessarily mean that element A completely surrounds element B.

[0077] The gate spacer 140 may include a first portion 141 and a second portion 142. The first portion 141 of the gate spacer 140 may be defined as a portion disposed on the sidewall GS1_SW of the gate structure GS1. The second portion 142 of the gate spacer 140 may be defined as a portion disposed on the bottom surface GS1_BS of the gate structure GS1. The first portion 141 and the second portion 142 of the gate spacer 140 may be connected to each other to surround the gate structure GS1.

[0078] The first portion 141 of the gate spacer 140 may extend in the second direction D2 and the third direction D3 along the sidewall GS1_SW of the gate structure GS1. The gate capping pattern 145 may be disposed on the first portion 141 of the gate spacer 140. The first portion 141 of the gate spacer 140 may be disposed on the gate insulating layer 130 and the etch stop layer 185. The first portion 141 of the gate spacer 140 may be disposed between the gate structure GS1 and the first interlayer insulating layer 190.

[0079] The second portion 142 of the gate spacer 140 may be disposed on the bottom surface GS1_BS of the gate structure GS1. The second portion 142 of the gate spacer 140 may be disposed on the field insulation layer 105. The second portion 142 of the gate spacer 140 may extend in the first direction D1 along the top surface 105_US of the field insulation layer 105 (eg, see Figure 3 ).

[0080] The second portion 142 of the gate spacer 140 may be disposed adjacent to the first interlayer insulating layer 190. That is, the second portion 142 of the gate spacer 140 may overlap the first interlayer insulating layer 190 in the first direction D1. For example, a lower portion of the first interlayer insulating layer 190 may overlap the second portion 142 of the gate spacer 140 in the first direction D1. The second portion 142 of the gate spacer 140 may not be disposed between the first interlayer insulating layer 190 and the field insulating layer 105. The second portion 142 of the gate spacer 140 may not overlap the first interlayer insulating layer 190 in the third direction D3. That is, the second portion 142 of the gate spacer 140 may not overlap the first interlayer insulating layer 190 in the third direction D3. For example, the first interlayer insulating layer 190 may not overlap the gate spacer 140 in the third direction D3.

[0081] The second portion 142 of the gate spacer 140 may be disposed between the field insulating layer 105 and the gate structure GS1. The second portion 142 of the gate spacer 140 may not cover the top surface BP1_US of the lower pattern BP1. For example, the second portion 142 of the gate spacer 140 may not be present on the top surface BP1_US of the lower pattern BP1. The second portion 142 of the gate spacer 140 does not overlap with the sheet pattern NS1 in the third direction D3. That is, the second portion 142 of the gate spacer 140 may not overlap with the sheet pattern NS1 in the third direction D3. The second portion 142 of the gate spacer 140 is not disposed between the gate electrode 120 and the top surface NS1_US of the sheet pattern NS1. The second portion 142 of the gate spacer 140 is not disposed between the gate electrode 120 and the bottom surface NS1_BS of the sheet pattern NS1.

[0082] The second portion 142 of the gate spacer 140 may be disposed on a portion of the sidewall BP1_SW of the lower pattern BP1 (eg, see Figure 4 ). The sidewall BP1_SW of the lower pattern BP1 may be completely covered by the field insulating layer 105 and the second portion 142 of the gate spacer 140. For example, the field insulating layer 105 may be located on the first portion of the sidewall BP1_SW of the lower pattern BP1, and the second portion 142 of the gate spacer 140 may be located on the second portion of the sidewall BP1_SW of the lower pattern BP1. The first portion and the second portion of the sidewall BP1_SW of the lower pattern BP1 may be connected to each other. The sidewall BP1_SW of the lower pattern BP1 may be continuous. Figure 4 The top of the second portion 142 of the gate spacer 140 is shown to be lower than the top surface BP1_US of the lower pattern BP1, but the disclosure is not limited thereto. For example, the top of the second portion 142 of the gate spacer 140 may be located on the same plane as the top surface BP1_US of the lower pattern BP1.

[0083] The gate spacer 140 may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon oxycarbon nitride (SiOCN), silicon boron nitride (SiBN), silicon boron nitride oxide (SiOBN), silicon oxycarbide (SiOC), or a combination thereof. Although the gate spacer 140 is shown as a single layer, this is only for simplicity of description, and the present disclosure is not limited thereto.

[0084] The field insulating layer 105 may include a first region overlapping the gate structure GS1 in the third direction D3. The field insulating layer 105 may include a second region overlapping the first interlayer insulating layer 190 in the third direction D3. The second portion 142 of the gate spacer 140 may be disposed in the first region of the field insulating layer 105 and may not be disposed in the second region therein. The first region may be different from the second region. The height H1 of the first region of the field insulating layer 105 may be greater than the height H2 of the second region of the field insulating layer 105 (e.g., see Figure 4 and Figure 5 ). For example, the height H1 may be the thickness of the first region of the field insulation layer 105 in the third direction D3, and the height H2 may be the thickness of the second region of the field insulation layer 105 in the third direction D3. In other words, the thickness H1 of the first region of the field insulation layer 105 in the third direction D3 may be greater than the thickness H2 of the second region of the field insulation layer 105 in the third direction D3. The second region of the field insulation layer 105 may not overlap with the gate structure GS1 in the third direction D3.

[0085] The source / drain pattern 150 may be disposed on the active pattern AP1. The source / drain pattern 150 may be disposed on the lower pattern BP1. The source / drain pattern 150 is connected (eg, electrically connected) to the sheet pattern NS1. The source / drain pattern 150 may be in contact with the sheet pattern NS1. The source / drain pattern 150 may be connected to the sheet patterns NS1 spaced apart in the first direction D1.

[0086] The source / drain pattern 150 may be disposed on at least one side of the gate structure GS1. The source / drain pattern 150 may be disposed between adjacent gate structures GS1 in the first direction D1. For example, the source / drain pattern 150 may be disposed on both sides (e.g., opposite sides) of the gate structure GS1. Different from the illustration, the source / drain pattern 150 may be disposed on one side of the gate structure GS1 and may not be disposed on the other side of the gate structure GS1.

[0087] The source / drain pattern 150 may be included in a source / drain of a transistor using the sheet pattern NS1 as a channel region.

[0088] The source / drain pattern 150 may be disposed in the source / drain recess. The source / drain recess 150R extends in the third direction D3 (eg, see Fig.24 ). Source / drain recesses may be defined between gate structures GS1 adjacent to each other in the first direction D1.

[0089] For example, the bottom surface of the source / drain recess may be defined by the lower pattern BP1. The sidewall of the source / drain recess may be defined by the sheet pattern NS1 and the inner gate structure INT_GS1. A portion of the sidewall of the source / drain recess may be defined by the gate structure GS1 between the uppermost sheet patterns NS1. In the semiconductor device according to some embodiments, the sidewall of the inner gate structure INT_GS1 may be defined by the gate insulating layer 130 of the inner gate structure INT_GS1.

[0090] Between the lowermost sheet pattern NS1 and the lower pattern BP1, a boundary between the gate insulating layer 130 and the lower pattern BP1 may be a top surface BP1_US of the lower pattern BP1 (eg, see Figure 4 ). A bottom surface of the source / drain recess is lower than a top surface BP1_US of the lower pattern BP1.

[0091] The source / drain pattern 150 may be disposed in the source / drain recess. The source / drain pattern 150 may fill the source / drain recess.

[0092] The source / drain pattern 150 may be in contact with the sheet pattern NS1 and the lower pattern BP1. The inner gate structure INT_GS1 may be in contact with the source / drain pattern 150. Although the top surface of the source / drain pattern 150 is shown as being higher than the uppermost sheet pattern NS1, the present disclosure is not limited thereto. In some embodiments, unlike the illustration, the top surface of the source / drain pattern 150 may be disposed on the same plane as the top surface of the uppermost sheet pattern NS1, or may be disposed lower than its top surface.

[0093] The source / drain pattern 150 may include an epitaxial pattern. The source / drain pattern 150 includes a semiconductor material.

[0094] The source / drain pattern 150 may include, for example, silicon or germanium, which is an elemental semiconductor material. In addition, the source / drain pattern 150 may be a binary compound or a ternary compound including at least two elements selected from the group consisting of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or the above compound doped with a group IV element. For example, the source / drain pattern 150 may include silicon, silicon germanium, germanium, silicon carbide, etc., but the present disclosure is not limited thereto.

[0095] The source / drain pattern 150 may include impurities doped into the semiconductor material. The doped impurities may include, but are not limited to, at least one of boron (B), phosphorus (P), carbon (C), arsenic (As), antimony (Sb), bismuth (Bi), or oxygen (O).

[0096] Although the source / drain pattern 150 is illustrated as a single layer, this is only for simplicity of description and the present disclosure is not limited thereto.

[0097] Although the source / drain patterns 150 contacting the inner gate structure INT_GS1 are illustrated as having the same width in the first direction D1 , the present disclosure is not limited thereto.

[0098] Unlike the illustration, in the semiconductor device according to some embodiments, the width of the source / drain pattern 150 in the first direction D1 may increase and then decrease as it moves away from the lower pattern BP1 in the third direction D3 .

[0099] Unlike the illustration, in the semiconductor device according to some embodiments, the width of the source / drain pattern 150 in the first direction D1 may be greater than the width of the etch stop layer 185 in the first direction D1. In this case, the width of the source / drain pattern 150 in the first direction D1 may be the distance between adjacent sheet patterns NS1 in the first direction D1.

[0100] The etch stop layer 185 may extend along sidewalls of the gate capping pattern 145 , a top surface of the field insulation layer 105 , and outlines of the source / drain pattern 150 .

[0101] The etch stop layer 185 may include a material having an etch selectivity with respect to the first interlayer insulating layer 190, which will be described later. The etch stop layer 185 may include, for example, at least one of silicon nitride (SiN), silicon oxide (SiO2), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron nitride (SiOBN), silicon oxycarbide (SiOC), or a combination thereof.

[0102] The first interlayer insulating layer 190 may be disposed on the etch stop layer 185. The first interlayer insulating layer 190 may be disposed on the source / drain pattern 150. The first interlayer insulating layer 190 may be disposed on one side of the gate structure GS1. The first interlayer insulating layer 190 may be disposed between the gate structures GS1. The first interlayer insulating layer 190 may be disposed on the field insulating layer 105. The first interlayer insulating layer 190 may extend in the second direction D2.

[0103] The first interlayer insulating layer 190 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, or a low-k material. The low-k material may include, for example, fluorinated tetraethyl orthosilicate (FTEOS), hydrogen silsesquioxane (HSQ), bisbenzocyclobutene (BCB), tetramethyl orthosilicate (TMOS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilyl borate (TMSB), diacyloxydi-tert-butylsilane (DADBS), trimethyl phosphate (TMSP), polytetrafluoroethylene (PTFE), toner silazane (TOSZ), fluorosilicate glass (FSG), polyimide nanofoam such as polypropylene oxide, carbon-doped silicon oxide (CDO), organosilicate glass (OSG), SiLK, amorphous fluorinated carbon, silica aerogel, silica xerogel, mesoporous silica, or a combination thereof, but is not limited thereto.

[0104] The source / drain contact 170 may be disposed on the source / drain pattern 150 (eg, see Figure 2 The source / drain contact 170 may penetrate (ie, extend into) the first interlayer insulating layer 190 and the etch stop layer 185. The source / drain contact 170 may be connected (eg, electrically connected) to the source / drain pattern 150.

[0105] A contact silicide layer 175 may be disposed between the source / drain contacts 170 and the source / drain patterns 150 .

[0106] The source / drain contacts 170 may include a conductive material such as at least one of a metal, a metal nitride, a metal carbonitride, a two-dimensional (2D) material, or a conductive semiconductor material. The contact silicide layer 175 may include a metal silicide material.

[0107] Although the source / drain contact 170 is illustrated as a single layer, the present disclosure is not limited thereto. For example, the source / drain contact 170 may include a contact barrier layer and a contact filling layer filling a space defined by the contact barrier layer.

[0108] Figures 6 to 8 1 is a diagram showing a semiconductor device according to some embodiments. For simplicity of description, the following description will focus on the above reference Figures 1 to 5 For reference, Figure 6 It is along Figure 1 A cross-sectional view taken along line AA. Figure 7 It is along Figure 1 A cross-sectional view taken along line BB. Figure 8 It is along Figure 1 Cross-sectional view taken along line CC.

[0109] refer to Figures 6 to 8 In the semiconductor device according to some embodiments, the gate spacer 140 may include a first insulating layer 111, a second insulating layer 112, and a third insulating layer 113. The description of the first portion 141 and the second portion 142 of the gate spacer 140 is the same as described above.

[0110] The first insulating layer 111 may surround the gate structure GS1. The first insulating layer 111 may be disposed on the sidewall GS1_SW and the bottom surface GS1_BS of the gate structure GS1 (eg, see Figure 7 ). The first insulating layer 111 may be disposed on the gate insulating layer 130 . For example, the first insulating layer 111 may be in contact with the gate structure GS1 . The first insulating layer 111 may be disposed in the first portion 141 and the second portion 142 of the gate spacer 140 .

[0111] The first insulating layer 111 may include, for example, at least one of silicon (Si), silicon nitride (SiN), silicon oxide (SiO 2 ), or silicon oxynitride (SiON).

[0112] The second insulating layer 112 may be disposed on the first insulating layer 111. The second insulating layer 112 may surround the gate structure GS1. The second insulating layer 112 may be disposed above the sidewall GS1_SW and the bottom surface GS1_BS of the gate structure GS1. The second insulating layer 112 may be disposed along the sidewall GS1_SW and the bottom surface GS1_BS of the gate structure GS1. The second insulating layer 112 may be disposed on the etch stop layer 185. The second insulating layer 112 may be disposed between the first insulating layer 111 and the third insulating layer 113. The second insulating layer 112 may be disposed in the first portion 141 and the second portion 142 of the gate spacer 140.

[0113] The second insulating layer 112 may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron nitride oxide (SiOBN), silicon oxycarbide (SiOC), or a combination thereof. In some embodiments, the first insulating layer 111 and the second insulating layer 112 may include different materials.

[0114] The third insulating layer 113 may be disposed on the second insulating layer 112. The third insulating layer 113 may be disposed along the top surface 105_US of the field insulating layer 105 (eg, see Figure 7 ). For example, the third insulating layer 113 may be located between the first insulating layer 112 and the field insulating layer 105. The third insulating layer 113 may include the same material as the first insulating layer 111. The first insulating layer 111 may be connected to the third insulating layer 113 on the sidewall BP1_SW of the lower pattern BP1 (eg, see Figure 8 ).

[0115] The third insulating layer 113 may include, for example, at least one of silicon (Si), silicon nitride (SiN), silicon oxide (SiO 2 ), or silicon oxynitride (SiON).

[0116] Fig. 9 1 is a diagram showing a semiconductor device according to some embodiments. For simplicity of description, the following description will focus on the above reference Figures 1 to 8 The difference in description.

[0117] refer to Fig. 9, a semiconductor device according to some embodiments may include a liner layer 103 disposed along the sidewall and bottom surface of the field trench FT. The liner layer 103 may be disposed along the top surface 100_US of the substrate 100 and the sidewall BP1_SW of the lower pattern BP1. The liner layer 103 may completely cover the sidewall BP1_SW of the lower pattern BP1. However, the present disclosure is not limited thereto. Unlike the illustration, the liner layer 103 may cover a portion of the sidewall BP1_SW of the lower pattern BP1. The gate spacer 140 may cover the remaining portion of the sidewall BP1_SW of the lower pattern BP1.

[0118] The liner layer 103 may include, for example, at least one of silicon (Si), silicon nitride (SiN), silicon oxide (SiO 2 ), or silicon oxynitride (SiON).

[0119] The field insulating layer 105 may be disposed on the liner layer 103. The first insulating layer 111 and the third insulating layer 113 may be disposed on the liner layer 103. In some embodiments, a boundary between the first insulating layer 111 and the third insulating layer 113 and the liner layer 103 may not be distinguished.

[0120] Fig.10 1 is a diagram showing a semiconductor device according to some embodiments. For simplicity of description, the following description will focus on the above reference Figures 1 to 5 The difference in description.

[0121] refer to Fig.10 , the sidewall of the first source / drain pattern 150 may have a wavy shape. The source / drain pattern 150 may include a plurality of width extended regions 150_ER. The width extended region 150_ER of each source / drain pattern 150 may be defined above the top surface BP1_US of the lower pattern BP1.

[0122] The width extended region 150_ER of the source / drain pattern 150 may be defined between the sheet patterns NS1 adjacent in the third direction D3. The width extended region 150_ER of the source / drain pattern 150 may be defined between the lower pattern BP1 and the sheet pattern NS1. The width extended region 150_ER of the source / drain pattern 150 may be defined between the inner gate structures INT1_GS1 adjacent in the first direction D1.

[0123] As moving away from the top surface BP1_US of the lower pattern BP1 (e.g., moving away in the third direction D3), the width extended region 150_ER of each source / drain pattern 150 may include a portion where its width in the first direction D1 increases and a portion where its width in the first direction D1 decreases. For example, the width of the width extended region 150_ER of the source / drain pattern 150 in the first direction D1 may first increase and then decrease as moving away from the top surface BP1_US of the lower pattern BP1.

[0124] The widths of the width extended regions 150_ER of the respective source / drain patterns 150 in the first direction D1 are illustrated to be the same, but the present disclosure is not limited thereto.

[0125] Fig.11 1 is a diagram showing a semiconductor device according to some embodiments. For simplicity of description, the following description will focus on the above reference Figures 1 to 5 The difference in description.

[0126] refer to Fig.11 The semiconductor device according to some embodiments may further include an inner spacer 143 disposed between the gate structure GS1 and the source / drain pattern 150 .

[0127] The inner spacer 143 may be disposed between the inner gate structure INT_GS1 and the source / drain pattern 150. Bottom sidewalls of the source / drain recesses may be defined by the inner spacer 143.

[0128] The inner spacer 143 may be in contact with the inner gate structure INT_GS1 . The inner spacer 143 may be in contact with the source / drain pattern 150 .

[0129] The inner spacer 143 may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron nitride (SiOBN), silicon oxycarbide (SiOC), or a combination thereof.

[0130] Fig.12 1 is a diagram showing a semiconductor device according to some embodiments. For simplicity of description, the following description will focus on the above reference Figures 1 to 5 The difference in description.

[0131] refer to Fig.12 , the semiconductor device according to some embodiments may not include the gate capping pattern 145. The gate structure GS1 may include a gate electrode 120 and a gate insulating layer 130. Figure 2 Differently, the gate capping pattern 145 may not be disposed on the top of the gate structure GS1.

[0132] A top surface of the gate electrode 120 may be disposed on the same plane as a top surface of the gate spacer 140. A top surface of the gate electrode 120 may be disposed on the same plane as a top surface of the first interlayer insulating layer 190.

[0133] Figures 13 to 32 are diagrams illustrating intermediate steps of a method for fabricating a semiconductor device according to some embodiments. Fig.13 is an example top view illustrating a method for manufacturing a semiconductor device according to some embodiments. Fig.16 , Fig.21 , Fig.24 , Fig. 27 and Fig.30 It is along Fig.13 A cross-sectional view taken along line AA. Fig.17 , Fig.19 , Fig. 22 , Fig.25 , Fig.28 and Fig.31 It is along Fig.13 A cross-sectional view taken along line BB. Fig.14 , Fig.15 , Fig.18 , Fig. 20 , Fig.23 , Fig.26 , Fig.29 and Fig.32 It is along Fig.13 Cross-sectional view taken along line CC.

[0134] refer to Fig.13 and Fig.14 , a lower pattern BP1 , a pattern structure U_AP, and a field insulation layer 105 may be formed on the substrate 100 .

[0135] Specifically, a lower pattern BP1 may be formed on the substrate 100, and a pattern structure U_AP may be formed on the lower pattern BP1. The pattern structure U_AP may extend in the first direction D1. The pattern structures U_AP may be spaced apart from each other in the second direction D2. The pattern structure U_AP may include sacrificial patterns SC_P and active patterns ACT_P that are alternately stacked.

[0136] The pattern structure U_AP may be formed on the stacked pattern using the first hard mask pattern HM1 as an etching mask. While the pattern structure U_AP is formed, the substrate 100 is partially etched so that the lower pattern BP1 may be formed. The pattern structure U_AP is formed on the lower pattern BP1.

[0137] Subsequently, a field insulating layer 105 may be formed in the field trench FT. The field insulating layer 105 may be formed by forming a first insulating material in the field trench FT and removing an upper portion of the first insulating material. The field insulating layer 105 may cover a portion of the sidewall BP1_SW of the lower pattern BP1.

[0138] refer to Fig.15 , a sacrificial liner layer 107 may be formed on the field insulating layer 105 .

[0139] Specifically, the sacrificial liner layer 107 may be formed by depositing a second insulating material on the field insulating layer 105 and removing an upper portion of the second insulating material. The second insulating material may be a material having an etching selectivity with respect to the field insulating layer 105.

[0140] A sacrificial liner layer 107 may be disposed on the top surface 105_US of the field insulating layer 105 and the sidewall BP1_SW of the lower pattern BP1. The sacrificial liner layer 107 and the field insulating layer 105 may completely cover the sidewall BP1_SW of the lower pattern BP1.

[0141] Subsequently, the first hard mask pattern HM1 may be removed to expose a top surface of the pattern structure U_AP.

[0142] refer to Figures 16 to 18 , a first insulating liner layer 109 , a dummy gate electrode 120P, and a second hard mask pattern HM2 may be formed on the pattern structure U_AP.

[0143] The first insulating liner layer 109 may cover a top surface of the sacrificial liner layer 107 and a portion of the pattern structure U_AP. The first insulating liner layer 109 may expose a portion of the pattern structure U_AP.

[0144] A dummy gate electrode 120P may be disposed on the first insulating liner layer 109. The dummy gate electrode 120P may be elongated in the second direction D2. A second hard mask pattern HM2 may be disposed on the dummy gate electrode 120P.

[0145] The dummy gate electrode 120p may include, for example, polysilicon, but the present disclosure is not limited thereto. The second hard mask pattern HM2 may include, for example, silicon nitride, but is not limited thereto.

[0146] The dummy gate electrode 120P may be formed by using the second hard mask pattern HM2 as an etching mask. For example, polysilicon may be deposited on the pattern structure U_AP and patterned using the second hard mask pattern HM2 as an etching mask. The patterned polysilicon may be the dummy gate electrode 120P.

[0147] refer to Fig.19 and Fig. 20, the sacrificial liner layer 107 may be removed to expose the field insulating layer 105 .

[0148] Specifically, the sacrificial liner layer 107 may be removed and the top surface 105_US of the field insulating layer 105 may be exposed. The sacrificial liner layer 107 may be removed to form a first space 107S between the field insulating layer 105 and the first insulating liner layer 109. The sidewall BP1_SW of the lower pattern BP1 may be partially exposed by the first space 107S.

[0149] refer to Figure 21 to Figure 23 , a first pre-gate spacer 140P1 may be formed on the pattern structure U_AP and the field insulation layer 105 .

[0150] Specifically, the first pre-gate spacer 140P1 may be disposed along the contours of the second hard mask pattern HM2 and the dummy gate electrode 120P. The first pre-gate spacer 140P1 may cover the exposed top surface of the pattern structure U_AP and the exposed top surface 105_US of the field insulation layer 105. The first pre-gate spacer 140P1 may fill the first space 107S.

[0151] refer to Figure 24 to Figure 26 , the second pre-gate spacer 140P2 and the source / drain recesses 150R may be formed using the second hard mask pattern HM2 as a mask.

[0152] A portion of the source / drain recess 150R may be formed in the lower pattern BP1. The source / drain recess 150R may be formed at least one side of the dummy gate electrode 120P. The source / drain recess 150R may expose the active pattern ACT_P and the sacrificial pattern SC_P. In this case, the thickness of the second hard mask pattern HM2 may be reduced.

[0153] The upper surface 105_US of the field insulation layer 105 may be partially exposed by forming the second pre-gate spacer 140P2 . The second pre-gate spacer 140P2 may be disposed between the dummy gate electrode 120P and the field insulation layer 105 .

[0154] refer to Figure 27 to Figure 29 , a source / drain pattern 150 , an etch stop layer 185 , and a first interlayer insulating layer 190 may be formed.

[0155] Specifically, the source / drain pattern 150 may fill the source / drain recess 150R. The source / drain pattern 150 may be formed at least one side of the dummy gate electrode 120P. The source / drain pattern 150 may contact the active pattern ACT_P and the sacrificial pattern SC_P.

[0156] Then, an etch stop layer 185 and a first interlayer insulating layer 190 may be sequentially formed on the source / drain pattern 150 .

[0157] The second pre-gate spacer 140P2 (eg, see Fig. 27 ) and the top surface 105_US of the field insulation layer 105 form an etch stop layer 185. A first interlayer insulation layer 190 may be formed on the etch stop layer 185.

[0158] While forming the etch stop layer 185 and the first interlayer insulating layer 190, the second hard mask pattern HM2 may be removed to expose the top surface of the dummy gate electrode 120P. In addition, the upper portion of the second pre-gate spacer 140P2 may be removed to form the gate spacer 140. The gate spacer 140 may include a first portion 141 and a second portion 142.

[0159] refer to Figure 30 to Figure 32 , the dummy gate electrode 120P, the first insulating liner layer 109 and the sacrificial pattern SC_P may be removed.

[0160] Specifically, the exposed dummy gate electrode 120P may be removed. In this case, the first insulating liner layer 109 may not be removed. When the dummy gate electrode 120P is removed, the first insulating liner layer 109 may protect the active pattern ACT_P and the sacrificial pattern SC_P.

[0161] Subsequently, the first insulating liner layer 109 and the sacrificial pattern SC_P may be removed. The first insulating liner layer 109 and the sacrificial pattern SC_P may be removed sequentially. The sacrificial pattern SC_P may be removed to form a sheet pattern NS1 and a gate trench 120t.

[0162] Then, refer to Figures 2 to 5 , a gate electrode 120 may be formed on the gate trench 120 t and the sheet pattern NS1. A gate capping pattern 145 may be formed on the gate electrode 120. A contact silicide layer 175 and a source / drain contact 170 may be formed on the source / drain pattern 150.

[0163] As used herein, the terms "comprising," "including," "comprising," "having," "containing," "having" and any other variations thereof indicate the presence of stated features, steps, operations, elements, components and / or groups, and do not exclude the presence or addition of one or more other features, steps, operations, elements, components and / or groups thereof.

[0164] In summarizing the detailed description, those skilled in the art will appreciate that many variations and modifications may be made to the exemplary embodiments without departing substantially from the principles of the inventive concept. Therefore, the disclosed exemplary embodiments are only used in a general and descriptive sense and not for limiting purposes.

Claims

1. A semiconductor device, the semiconductor device include: an active pattern, the active pattern comprising a lower pattern extending in a first direction on a substrate and a sheet pattern located on the lower pattern, the first direction being parallel to a top surface of the substrate; a field insulating layer defining the active pattern on the substrate; a gate structure located on the lower pattern and comprising a gate insulating layer and a gate electrode extending in a second direction perpendicular to the first direction and parallel to the top surface of the substrate; a gate spacer at least partially surrounding the gate structure and comprising a first portion located on a sidewall of the gate structure and a second portion located on a bottom surface of the gate structure; and A source / drain pattern is located on the lower pattern and in contact with the sheet pattern.

2. The semiconductor device according to claim 1, in, The gate spacer includes a first insulating layer contacting the gate structure and a second insulating layer at least partially surrounding the first insulating layer.

3. The semiconductor device according to claim 2, in, The gate spacer further includes a third insulating layer between the second insulating layer and the field insulating layer, and The first insulating layer and the third insulating layer include the same material.

4. The semiconductor device according to claim 1, in, The second portion of the gate spacer is located between the field insulation layer and the gate structure.

5. The semiconductor device according to claim 1, in, The second portion of the gate spacer is located on a sidewall of the lower pattern.

6. The semiconductor device according to claim 1, in, The second portion of the gate spacer has no overlap with the flake pattern in a third direction perpendicular to the top surface of the substrate.

7. The semiconductor device according to claim 1, further comprising a first interlayer insulating layer located on the field insulating layer and the source / drain pattern, in, A lower portion of the first interlayer insulating layer overlaps the second portion of the gate spacer in the first direction.

8. The semiconductor device according to claim 7, in, The second portion of the gate spacer is not located between the first interlayer insulating layer and the field insulating layer.

9. The semiconductor device according to claim 1, in, The field insulating layer is located on a first portion of a sidewall of the lower pattern, and the second portion of the gate spacer is located on a second portion of the sidewall of the lower pattern, and Wherein, the first portion and the second portion of the sidewall of the lower pattern are connected to each other.

10. The semiconductor device according to claim 1, further comprising a liner layer on a top surface of the substrate and a sidewall of the lower pattern, in, The field insulating layer is located on the liner layer.

11. The semiconductor device according to claim 1, in, The gate structure includes a gate capping pattern on a top surface of the gate electrode.

12. The semiconductor device according to claim 1, in, The flake pattern includes a plurality of flake patterns spaced apart from each other, The gate structure includes an inner gate structure located between the lower pattern and the sheet pattern and between sheet patterns adjacent to each other among the plurality of sheet patterns. Wherein, the inner gate structure comprises the gate electrode and the gate insulating layer, and Wherein, the semiconductor device further includes an inner spacer located between the inner gate structure and the source / drain pattern.

13. A semiconductor device, the semiconductor device include: a plurality of active patterns, each of the active patterns comprising a lower pattern extending in a first direction on a substrate and a sheet pattern located on the lower pattern, the first direction being parallel to a top surface of the substrate; a field trench defined by a top surface of the substrate and a sidewall of the lower pattern; a field insulating layer, wherein the field insulating layer is located in the field trench; a gate structure located on the lower pattern and comprising a gate insulating layer and a gate electrode extending in a second direction perpendicular to the first direction and parallel to the top surface of the substrate; a gate spacer comprising a first portion extending along a sidewall of the gate structure in a third direction perpendicular to the top surface of the substrate and a second portion extending along a top surface of the field insulation layer in the first direction; a source / drain pattern, the source / drain pattern being located on the lower pattern and contacting the sheet pattern; as well as A first interlayer insulating layer is located on the field insulating layer and the source / drain pattern and on one side of the gate structure.

14. The semiconductor device according to claim 13, in, The first interlayer insulating layer has no overlap with the gate spacer in the third direction.

15. The semiconductor device according to claim 13, in, The second portion of the gate spacer is located between the gate structure and the field insulation layer.

16. The semiconductor device according to claim 13, in, The gate spacer includes a first insulating layer in contact with the gate structure and a second insulating layer at least partially surrounding the first insulating layer, and The first insulating layer and the second insulating layer include different materials.

17. The semiconductor device according to claim 16, in, The gate spacer further includes a third insulating layer between the second insulating layer and the field insulating layer, and The first insulating layer and the third insulating layer include the same material.

18. The semiconductor device according to claim 13, in, The field insulating layer includes a first region overlapping with the gate structure in the third direction and a second region not overlapping with the gate structure in the third direction, and The thickness of the first region of the field insulation layer in the third direction is greater than the thickness of the second region of the field insulation layer in the third direction.

19. The semiconductor device according to claim 13, further comprising a liner layer on a top surface of the substrate and a sidewall of the lower pattern, in, The field insulating layer is located on the liner layer.

20. A semiconductor device, the semiconductor device include: an active pattern, the active pattern comprising a lower pattern extending in a first direction on a substrate and a sheet pattern located on the lower pattern, the first direction being parallel to a top surface of the substrate; a field insulating layer defining the active pattern on the substrate; a gate structure located on the lower pattern and comprising a gate insulating layer and a gate electrode extending in a second direction perpendicular to the first direction and parallel to the top surface of the substrate; a gate spacer at least partially surrounding the gate structure and comprising a first portion located on a sidewall of the gate structure and a second portion located on a bottom surface of the gate structure; a source / drain pattern, the source / drain pattern being located on the lower pattern and contacting the sheet pattern; as well as a first interlayer insulating layer, the first interlayer insulating layer being located on the field insulating layer and the source / drain pattern and extending in the second direction, The second portion of the gate spacer is located between the field insulation layer and the gate structure, but not between the field insulation layer and the first interlayer insulation layer.

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