Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the method comprises the steps: providing a substrate, forming a channel structure protruding from the substrate on the substrate, forming a gate structure crossing the channel structure on the substrate, and enabling the gate structure to cover the top and side walls of the channel structure; removing part of the channel structure on the two sides of the gate structure to form a groove; and forming a source-drain doping layer in the groove, wherein the source-drain doping layer is in contact with the end part of the channel structure, and a gap is formed between the source-drain doping layer and the channel structure at the bottom of the source-drain doping layer. The working performance of the semiconductor structure can be improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] In order to better adapt to the reduction of feature size, semiconductor processes have gradually begun to transition from planar MOSFET to three-dimensional transistors with higher power efficiency, such as fin field effect transistors (FinFET). In FinFET, the gate structure can control the ultra-thin body (fin) from at least two sides. Compared with planar MOSFET, the gate structure has stronger control over the channel and can effectively suppress the short channel effect. In addition, FinFET has better compatibility with existing integrated circuit manufacturing than other devices.

[0003] In semiconductor manufacturing, with the development trend of very large-scale integrated circuits, the feature size of integrated circuits continues to decrease. Due to the increasing complexity of processes and equipment, the expansion rate of CMOS has slowed down, and it is becoming increasingly important to develop new features to continue the expansion of CMOS. Summary of the invention

[0004] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure to improve the working performance of the semiconductor structure.

[0005] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate; a channel structure protruding from the substrate; a gate structure spanning the channel structure, the gate structure covering the top and side walls of the channel structure; a source-drain doped layer located in the channel structure on both sides of the gate structure and in contact with the end of the channel structure, and a gap is provided between the source-drain doped layer and the channel structure at its bottom.

[0006] Optionally, the semiconductor structure further includes: a growth inhibition layer located at the top of the channel structure at the bottom of the source and drain doping layer, and the growth inhibition layer and the bottom of the source and drain doping layer form a gap.

[0007] Optionally, the channel structure at the bottom of the source-drain doping layer has a concave morphology, and the growth inhibition layer is located at the concave morphology.

[0008] Optionally, the concave shape is an arc shape.

[0009] Optionally, the growth inhibition layer has a thickness of 5 angstroms to 20 angstroms.

[0010] Optionally, the growth inhibition layer is an ion-doped layer, and the ion-doped layer is provided by a channel structure doped with ions.

[0011] Optionally, the doping ions of the ion-doped layer include carbon ions, hydrogen ions, boron ions or fluorine ions.

[0012] Optionally, a distance between a top and a bottom of the gap is 1 nanometer to 10 nanometers.

[0013] Optionally, the semiconductor structure further includes: an isolation layer, which is located on the substrate and covers a portion of the thickness of the sidewall of the channel structure; and a top surface of the channel structure at the bottom of the source and drain doping layer is lower than a top surface of the isolation layer.

[0014] Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate, a channel structure protruding from the substrate is formed on the substrate, and a gate structure spanning the channel structure is also formed on the substrate, the gate structure covers the top and side walls of the channel structure; removing part of the channel structure on both sides of the gate structure to form a groove; forming a source-drain doping layer in the groove, the source-drain doping layer is in contact with the end of the channel structure and has a gap between it and the channel structure at the bottom.

[0015] Optionally, after forming the trench and before forming the source-drain doping layer, the forming method further includes: forming a growth inhibition layer at the bottom of the trench; in the step of forming the source-drain doping layer, the growth inhibition layer and the bottom of the source-drain doping layer form a gap.

[0016] Optionally, in the step of removing part of the channel structure on both sides of the gate structure, in which the channel structure at the bottom of the trench has a concave morphology; in the step of forming the source and drain doping layer, the concave morphology and the bottom of the source and drain doping layer form a gap.

[0017] Optionally, the step of forming a growth inhibition layer at the bottom of the trench includes: performing ion implantation on the channel structure at the bottom of the trench to form an ion doped layer, wherein the ion doped layer is used as the growth inhibition layer.

[0018] Optionally, in the step of performing ion implantation on the channel structure at the bottom of the trench, the ions implanted by the ion implantation include carbon ions, hydrogen ions, boron ions or fluorine ions.

[0019] Optionally, in the step of performing ion implantation on the trench structure at the bottom of the trench, the implantation dose of the ion implantation is 1e12 atoms / cm 2 To 1e20 atoms / cm 2 , the injection energy is 1keV-10keV.

[0020] Optionally, in the step of performing ion implantation on the channel structure at the bottom of the trench, the implantation depth of the ion implantation is 5 angstroms to 20 angstroms.

[0021] Optionally, in the step of performing ion implantation on the channel structure at the bottom of the trench, the angle between the implantation angle of the ion implantation and the direction perpendicular to the substrate surface is 0° to 5°.

[0022] Optionally, in the step of forming a source-drain doping layer in the trench, a distance between a top and a bottom of the gap is 1 nanometer to 10 nanometers.

[0023] Optionally, in the step of providing a substrate, an isolation layer is also formed on the substrate, and the isolation layer covers a portion of the thickness of the sidewalls of the channel structure; in the step of removing part of the channel structure on both sides of the gate structure to form a groove, the bottom of the groove is lower than the top surface of the isolation layer.

[0024] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0025] In the semiconductor structure provided by the embodiment of the present invention, the source-drain doped layer is located in the channel structure on both sides of the gate structure and is in contact with the end of the channel structure, and there is a gap between the source-drain doped layer and the channel structure at the bottom thereof; the dielectric constant of air is small, so there is a gap between the source-drain doped layer and the channel structure at the bottom thereof, which is beneficial to reducing the capacitance between the source-drain doped layer and the channel structure at the bottom, thereby facilitating improving the working performance of the semiconductor structure.

[0026] In the formation method provided by the embodiment of the present invention, a source-drain doping layer is formed in the groove, the source-drain doping layer is in contact with the end of the channel structure, and has a gap with the channel structure at the bottom; the dielectric constant of air is small, so there is a gap between the source-drain doping layer and the channel structure at the bottom, which is beneficial to reducing the capacitance between the source-drain doping layer and the channel structure at the bottom, thereby helping to improve the working performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figures 1 to 9 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0028] Figures 10 to 12 is a structural schematic diagram corresponding to an embodiment of a semiconductor structure of the present invention;

[0029] Figures 13 to 24 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0030] At present, the working performance of semiconductor structures needs to be improved. The reasons why the performance needs to be improved are analyzed in combination with a method for forming a semiconductor structure.

[0031] Figures 1 to 9 The present invention is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure.

[0032] Combined with reference Figures 1 to 3 , Figure 2 for Figure 1 Cross-sectional view along AA direction, Figure 3 for Figure 1 In the cross-sectional view along the BB direction, a substrate 10 is provided, on which a channel structure 20 protruding from the substrate 10 is formed, and on which a gate structure 30 spanning the channel structure 20 is also formed, and the gate structure 30 covers the top and sidewalls of the channel structure 20 .

[0033] Combined with reference Figures 4 to 6 , Figure 5 for Figure 4 Cross-sectional view along AA direction, Figure 6 for Figure 4 In the cross-sectional view along the BB direction, a portion of the channel structure 20 on both sides of the gate structure 30 is removed to form a trench 21 .

[0034] Combined with reference Figures 7 to 9 , Figure 8 for Figure 7 Cross-sectional view along AA direction, Fig. 9 for Figure 7 In the cross-sectional view along the BB direction, a source-drain doping layer 40 is formed in the trench 21 , and the source-drain doping layer 40 is in contact with the end and the bottom of the channel structure 20 .

[0035] If the source-drain doped layer 40 contacts the end and bottom of the channel structure 20 , it is difficult to reduce the capacitance between the source-drain doped layer 40 and the bottom of the channel structure 20 , thereby making it difficult to improve the working performance of the semiconductor structure.

[0036] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, a channel structure protruding from the substrate is formed on the substrate, and a gate structure spanning the channel structure is also formed on the substrate, and the gate structure covers the top and side walls of the channel structure; removing part of the channel structure on both sides of the gate structure to form a groove; forming a source-drain doping layer in the groove, the source-drain doping layer is in contact with the end of the channel structure, and has a gap between it and the channel structure at the bottom.

[0037] In the formation method provided by the embodiment of the present invention, a source-drain doping layer is formed in the groove, the source-drain doping layer is in contact with the end of the channel structure, and has a gap with the channel structure at the bottom; the dielectric constant of air is small, so there is a gap between the source-drain doping layer and the channel structure at the bottom, which is beneficial to reducing the capacitance between the source-drain doping layer and the channel structure at the bottom, thereby helping to improve the working performance of the semiconductor structure.

[0038] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0039] Figures 10 to 12 It is a structural schematic diagram corresponding to an embodiment of a semiconductor structure of the present invention.

[0040] Combined with reference Figures 10 to 12 , Fig.11 for Fig.10 Cross-sectional view along AA direction, Fig.12 for Fig.10 In the cross-sectional view along the BB direction, the semiconductor structure includes: a substrate 100; a channel structure 200 protruding from the substrate 100; a gate structure 400 spanning the channel structure 200, and the gate structure 300 covers the top and sidewalls of the channel structure 200; a source-drain doped layer 400, located in the channel structure 200 on both sides of the gate structure 300, and in contact with the end of the channel structure 200, and there is a gap between the source-drain doped layer 400 and the channel structure 200 at its bottom.

[0041] The substrate 100 provides a process operation basis for the formation process of the semiconductor structure.

[0042] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon substrate on an insulator or a germanium substrate on an insulator. The material of the substrate may be a material suitable for process requirements or easy to integrate.

[0043] The channel structure 200 is used to provide a channel for a semiconductor structure.

[0044] In this embodiment, the channel structure 200 is a fin. In other embodiments, the channel structure may also be a channel stack.

[0045] In this embodiment, the material of the channel structure 200 includes silicon, germanium, silicon germanium or III-V semiconductor materials. As an example, the material of the channel structure 200 is silicon. In other embodiments, the material of the channel structure is determined according to the type and performance of the transistor.

[0046] It should be noted that, in this embodiment, the channel structure 200 and the substrate 100 are made of the same material. In other embodiments, the channel structure and the substrate may be made of different materials.

[0047] The gate structure 300 is used to control the opening and closing of the channel of the transistor.

[0048] In this embodiment, the gate structure 300 includes a gate dielectric layer covering the channel structure 200 and a gate electrode layer located on the gate dielectric layer.

[0049] The gate dielectric layer is used to isolate the gate structure 300 from the channel structure 200 .

[0050] The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3. In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. Among them, the high-k dielectric material refers to a dielectric material whose relative dielectric constant is greater than the relative dielectric constant of silicon oxide. Specifically, the material of the high-k gate dielectric layer includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3, etc.

[0051] It should be noted that the gate dielectric layer may further include a gate oxide layer, and the gate oxide layer is located between the high-k gate dielectric layer and the channel structure 200. Specifically, the material of the gate oxide layer may be silicon oxide.

[0052] In this embodiment, the material of the gate electrode layer is one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

[0053] In this embodiment, the gate structure 300 is a metal gate structure.

[0054] Therefore, the gate electrode layer includes a work function layer (not labeled) and an electrode layer (not labeled) located on the work function layer. The work function layer is used to adjust the threshold voltage of the transistor, and the electrode layer is used to lead out the electrical properties of the metal gate structure.

[0055] In other embodiments, according to process requirements, the gate structure may also be a polysilicon gate structure.

[0056] In some other embodiments, the gate structure may also be a dummy gate structure.

[0057] The source-drain doped layer 400 is used as a source region or a drain region of a semiconductor structure. Specifically, the doping type of the source-drain doped layer 400 is the same as the channel conductivity type of the corresponding transistor.

[0058] In this embodiment, there is a gap between the source-drain doped layer 400 and the channel structure 200 at the bottom. The dielectric constant of air is small, so there is a gap between the source-drain doped layer 400 and the channel structure 200 at the bottom, which is beneficial to reducing the capacitance between the source-drain doped layer 400 and the channel structure 200 at the bottom, thereby helping to improve the working performance of the semiconductor structure.

[0059] It should be noted that, in this embodiment, the distance d between the top and bottom of the gap should not be too large or too small. If the distance d between the top and bottom of the gap is too large, it is easy to cause the gap to occupy too much space, resulting in unnecessary waste of space; if the distance d between the top and bottom of the gap is too small, it is difficult to effectively reduce the capacitance between the source-drain doped layer 400 and the bottom channel structure 200, thereby making it difficult to effectively improve the working performance of the semiconductor structure. For this reason, in this embodiment, the distance d between the top and bottom of the gap is 1 nanometer to 10 nanometers.

[0060] In this embodiment, the semiconductor structure further includes: a growth inhibition layer 220 located at the top of the channel structure 200 at the bottom of the source-drain doping layer 400 , and the growth inhibition layer 220 and the bottom of the source-drain doping layer 400 form a gap.

[0061] The growth inhibition layer 220 is used to inhibit the source / drain doping layer 400 from growing on the channel structure 200 at the bottom thereof during the process of forming the source / drain doping layer 400 , thereby facilitating the source / drain doping layer 400 and the channel structure 200 at the bottom thereof to form a gap.

[0062] In this embodiment, the channel structure 200 at the bottom of the source-drain doping layer 400 has a concave morphology, and the growth inhibition layer 220 is located at the concave morphology.

[0063] The channel structure 200 at the bottom of the source-drain doping layer 400 has a concave morphology, and the growth inhibition layer 220 is located at the concave morphology, that is, the growth inhibition layer 220 has a concave morphology. In the process of forming the source-drain doping layer 400, the source-drain doping layer 400 is grown at the ends of the channel structure 200 on both sides of the gate structure 300, and does not grow on the growth inhibition layer 220. The growth inhibition layer 220 is concave, which makes it easy for the source-drain doping layer 400 and the growth inhibition layer 220 to form a gap, and it is beneficial to make the space of the gap surrounded by the source-drain doping layer 400 and the growth inhibition layer 220 more sufficient, which can better reduce the capacitance between the source-drain doping layer 400 and the channel structure 200 at the bottom.

[0064] In this embodiment, the concave shape is an arc shape.

[0065] The concave shape is an arc shape, which is relatively smooth and uniform, which is conducive to forming a better film quality of the growth inhibition layer 220, and is conducive to reducing the difficulty of forming the growth inhibition layer 220 in the concave part. At the same time, the concave part of the arc shape can form a larger space, which is conducive to making the space between the source and drain doping layer 400 and the growth inhibition layer 220 more sufficient, and can better reduce the capacitance between the source and drain doping layer 400 and the bottom channel structure 200.

[0066] It should be noted that, in this embodiment, the thickness of the growth inhibition layer 220 should not be too large or too small. If the thickness of the growth inhibition layer 220 is too large, it is easy to cause the space occupied at the bottom of the source-drain doping layer 400 to be too large, resulting in unnecessary waste and easily affecting the working performance of the channel structure 200; if the thickness of the growth inhibition layer 220 is too small, it is easy to cause the growth inhibition layer 220 to have a good growth inhibition effect on the source-drain doping layer 400, thereby affecting the formation of the gap between the source-drain doping layer 400 and the bottom channel structure 200. For this reason, in this embodiment, the thickness of the growth inhibition layer 220 is 5 angstroms to 20 angstroms.

[0067] In this embodiment, ion implantation is performed on the channel structure 200 at the bottom of the source / drain doping layer 400 to destroy the material structure on the surface of the channel structure 200, thereby achieving the effect of inhibiting the growth of the source / drain doping layer 400. To this end, in this embodiment, the growth inhibition layer 220 is an ion doping layer, and the ion doping layer is provided by the channel structure 200 doped with ions.

[0068] In this embodiment, the doping ions of the ion-doped layer include carbon ions, hydrogen ions, boron ions or fluorine ions.

[0069] During the ion implantation process of the channel structure 200 at the bottom of the source-drain doped layer 400 , carbon ions or hydrogen ions are implanted, which can destroy the material structure on the surface of the channel structure 200 and inhibit the growth of the source-drain doped layer 400 .

[0070] In this embodiment, the semiconductor structure further includes: an isolation layer 110 , which is located on the substrate 100 and covers a portion of the thickness of the sidewall of the channel structure 200 .

[0071] The isolation layer 100 is used to achieve insulation between different devices. For example, in a CMOS manufacturing process, the isolation layer 100 is usually formed between an NMOS transistor and a PMOS transistor.

[0072] In this embodiment, the isolation layer 110 is a shallow trench isolation (STI) structure.

[0073] In this embodiment, the material of the isolation layer 110 is an insulating material. As an example, the material of the isolation layer 110 is silicon oxide.

[0074] In this embodiment, the top surface of the channel structure 200 at the bottom of the source-drain doping layer 400 is lower than the top surface of the isolation layer 110 .

[0075] The top surface of the channel structure 200 at the bottom of the source-drain doped layer 400 is lower than the top surface of the isolation layer 110, which is beneficial to provide a space for the source-drain doped layer 400 and the bottom channel structure 200 to form a gap, so that the formation of the gap has little impact on the formation of normal devices and has better process compatibility.

[0076] Figures 13 to 24 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0077] Combined with reference Figures 13 to 15 , Fig.14 for Fig.13 Cross-sectional view along AA direction, Fig.15 for Fig.13 In the cross-sectional view along the BB direction, a substrate 100 is provided, on which a channel structure 200 protruding from the substrate 100 is formed, and on which a gate structure 300 spanning the channel structure 200 is also formed, and the gate structure 300 covers the top and sidewalls of the channel structure 200 .

[0078] The substrate 100 provides a process operation basis for the formation process of the semiconductor structure.

[0079] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon substrate on an insulator or a germanium substrate on an insulator. The material of the substrate may be a material suitable for process requirements or easy to integrate.

[0080] The channel structure 200 is used to provide a channel for a semiconductor structure.

[0081] In this embodiment, the channel structure 200 is a fin. In other embodiments, the channel structure may also be a channel stack.

[0082] In this embodiment, the material of the channel structure 200 includes silicon, germanium, silicon germanium or III-V semiconductor materials. As an example, the material of the channel structure 200 is silicon. In other embodiments, the material of the channel structure is determined according to the type and performance of the transistor.

[0083] It should be noted that, in this embodiment, the channel structure 200 and the substrate 100 are made of the same material. In other embodiments, the channel structure and the substrate may be made of different materials.

[0084] In this embodiment, the gate structure 300 is a dummy gate structure, which is used to occupy a space position for subsequently forming a device gate structure.

[0085] In this embodiment, the dummy gate structure may be a single-layer structure or a stacked-layer structure, and the material of the dummy gate structure includes one or both of amorphous silicon and polycrystalline silicon.

[0086] In this embodiment, in the step of providing the substrate 100 , an isolation layer 110 is further formed on the substrate 100 , and the isolation layer 110 covers a portion of the thickness of the sidewall of the channel structure 200 .

[0087] The isolation layer 100 is used to achieve insulation between different devices. For example, in a CMOS manufacturing process, the isolation layer 100 is usually formed between an NMOS transistor and a PMOS transistor.

[0088] In this embodiment, the isolation layer 110 is a shallow trench isolation (STI) structure.

[0089] In this embodiment, the material of the isolation layer 110 is an insulating material. As an example, the material of the isolation layer 110 is silicon oxide.

[0090] Combined with reference Figures 16 to 18 , Fig.17 for Fig.16 Cross-sectional view along AA direction, Fig.18 for Fig.16 In the cross-sectional view along the BB direction, a portion of the channel structure 200 on both sides of the gate structure 300 is removed to form a trench 210 .

[0091] The trench 210 is used to provide a spatial location for the subsequent formation of source and drain doping layers.

[0092] In the present embodiment, in the step of removing a portion of the channel structure 200 on both sides of the gate structure 300 to form the trench 210 , the bottom of the trench 210 is lower than the top surface of the isolation layer 110 .

[0093] The bottom of the trench 210 is lower than the top surface of the isolation layer 110 , which is conducive to providing a space for the source and drain doping layer subsequently formed in the trench 210 to enclose a gap with the bottom channel structure 200 , so that the formation of the gap has little impact on the formation of normal devices and has better process compatibility.

[0094] In this embodiment, in the step of removing a portion of the channel structure 200 on both sides of the gate structure 300 to form the trench 210 , the channel structure 200 at the bottom of the trench 210 has a concave morphology.

[0095] The channel structure 200 at the bottom of the groove 210 has a concave morphology, which is conducive to the subsequent formation of a gap between the source-drain doping layer formed in the groove 210 and the bottom of the groove 210, and is conducive to making the space between the source-drain doping layer and the bottom of the groove 210 relatively sufficient, which can better reduce the capacitance between the source-drain doping layer and the bottom of the channel structure 200.

[0096] In this embodiment, the concave shape is an arc shape.

[0097] The concave morphology is an arc-shaped morphology, which is relatively smooth and uniform, which is conducive to better quality of the film layer formed in the subsequent growth inhibition layer in the concave part, and is conducive to reducing the difficulty of forming the growth inhibition layer in the concave part. At the same time, the concave part of the arc-shaped morphology can form a larger space, which is conducive to making the space between the source and drain doping layers and the growth inhibition layer more sufficient, and can better reduce the capacitance between the source and drain doping layers and the channel structure 200 at the bottom.

[0098] Combined with reference Figures 19 to 24 , a source-drain doping layer 400 is formed in the trench 210 , the source-drain doping layer 400 is in contact with the end of the channel structure 200 , and there is a gap between the source-drain doping layer 400 and the channel structure 200 at the bottom thereof.

[0099] The source-drain doped layer 400 is used as a source region or a drain region of a semiconductor structure. Specifically, the doping type of the source-drain doped layer 400 is the same as the channel conductivity type of the corresponding transistor.

[0100] In this embodiment, there is a gap between the source-drain doped layer 400 and the channel structure 200 at the bottom. The dielectric constant of air is small, so there is a gap between the source-drain doped layer 400 and the channel structure 200 at the bottom, which is beneficial to reducing the capacitance between the source-drain doped layer 400 and the channel structure 200 at the bottom, thereby helping to improve the working performance of the semiconductor structure.

[0101] It should be noted that, in the present embodiment, in the step of forming the source-drain doped layer 400 in the groove 210, the distance d between the top and the bottom of the gap should not be too large or too small. If the distance d between the top and the bottom of the gap is too large, it is easy to cause the gap to occupy too much space, resulting in unnecessary waste of space; if the distance d between the top and the bottom of the gap is too small, it is difficult to effectively reduce the capacitance between the source-drain doped layer 400 and the channel structure 200 at the bottom, thereby making it difficult to effectively improve the working performance of the semiconductor structure. For this reason, in the present embodiment, in the step of forming the source-drain doped layer 400 in the groove 210, the distance d between the top and the bottom of the gap is 1 nanometer to 10 nanometers.

[0102] Combined with reference Figures 19 to 21 , Fig. 20 for Fig.19 Cross-sectional view along AA direction, Fig.21 for Fig.19 In the cross-sectional view along the BB direction, after forming the trench 210 and before forming the source-drain doping layer 400 , the forming method further includes: forming a growth inhibition layer 220 at the bottom of the trench 210 .

[0103] The growth inhibition layer 220 is used to inhibit the source / drain doping layer 400 from growing on the channel structure 200 at the bottom thereof during the process of forming the source / drain doping layer 400 , thereby facilitating the source / drain doping layer 400 and the channel structure 200 at the bottom thereof to form a gap.

[0104] In this embodiment, the growth inhibition layer 220 is located at the concave morphology.

[0105] The channel structure 200 at the bottom of the source-drain doping layer 400 has a concave morphology, and the growth inhibition layer 220 is located at the concave morphology, that is, the growth inhibition layer 220 has a concave morphology. In the process of forming the source-drain doping layer 400, the source-drain doping layer 400 is grown at the ends of the channel structure 200 on both sides of the gate structure 300, and does not grow on the growth inhibition layer 220. The growth inhibition layer 220 is concave, which makes it easy for the source-drain doping layer 400 and the growth inhibition layer 220 to form a gap, and it is beneficial to make the space of the gap surrounded by the source-drain doping layer 400 and the growth inhibition layer 220 more sufficient, which can better reduce the capacitance between the source-drain doping layer 400 and the channel structure 200 at the bottom.

[0106] In this embodiment, the step of forming the growth inhibition layer 220 at the bottom of the trench 210 includes: performing ion implantation on the channel structure 200 at the bottom of the trench 210 to form an ion doped layer, and the ion doped layer is used as the growth inhibition layer 220 .

[0107] By performing ion implantation on the channel structure 200 at the bottom of the source-drain doped layer 400, the material structure on the surface of the channel structure 200 is destroyed, thereby achieving the effect of inhibiting the growth of the source-drain doped layer 400. Moreover, the growth inhibition layer 220 is obtained by the ion implantation process, and the growth inhibition layer 220 can be directly obtained without depositing additional film layers, which is beneficial to reducing the impact on other film layers.

[0108] It should be noted that, in the present embodiment, in the step of performing ion implantation on the channel structure 200 at the bottom of the groove 210, the angle between the implantation angle of the ion implantation and the direction perpendicular to the surface of the substrate 100 should not be too large. If the angle between the implantation angle of the ion implantation and the direction perpendicular to the surface of the substrate 100 should not be too large, it is easy to cause the channel structure 200 on the side wall of the groove 210 to also be implanted with ions, and a growth inhibition layer 220 is also formed in the channel structure 200 on the side wall of the groove 210. Therefore, in the process of forming the source-drain doped layer 400, it is also difficult for the channel structure 200 on the side wall of the groove 210 to grow the source-drain doped layer 400, thereby affecting the formation of the source-drain doped layer 400 and affecting the performance of the semiconductor structure. For this reason, in the present embodiment, in the step of performing ion implantation on the channel structure 200 at the bottom of the groove 210, the angle between the implantation angle of the ion implantation and the direction perpendicular to the surface of the substrate 100 is 0° to 5°.

[0109] In the present embodiment, in the step of performing ion implantation on the channel structure 200 at the bottom of the trench 210 , the ions implanted include carbon ions, hydrogen ions, boron ions or fluorine ions.

[0110] In the process of performing ion implantation on the channel structure 200 at the bottom of the trench 210 , carbon ions or hydrogen ions are implanted, which can destroy the material structure on the surface of the channel structure 200 and inhibit the growth of the source-drain doped layer 400 .

[0111] It should be noted that, in the present embodiment, during the process of ion implantation of the channel structure 200 at the bottom of the groove 210, the implantation dose of the ion implantation should not be too large or too small. If the implantation dose of the ion implantation is too large, it is easy to cause the ion implantation range to be too large, and the process technology is difficult to control. Correspondingly, the depth of the growth inhibition layer 220 is too large; if the implantation dose of the ion implantation is too small, the reaction time of the ion implantation is too long, the efficiency of the process technology is reduced, the depth of the growth inhibition layer 220 is affected, and the process effect cannot be achieved. It is easy to cause the growth inhibition layer 220 to have a good growth inhibition effect on the source-drain doping layer 400, thereby affecting the formation of the gap between the source-drain doping layer 400 and the channel structure 200 at its bottom. For this reason, in the present embodiment, during the process of ion implantation of the channel structure 200 at the bottom of the groove 210, the implantation dose of the ion implantation is 1e12 atoms / cm 2 To 1e20atoms / cm 2 .

[0112] It should also be noted that, in the present embodiment, during the process of performing ion implantation on the channel structure 200 at the bottom of the groove 210, the implantation energy of the ion implantation should not be too large or too small. If the implantation energy of the ion implantation is too large, it is easy to cause the ion implantation range to be too large, and the process technology is difficult to control, and accordingly, the depth of the growth inhibition layer 220 is too large; if the implantation energy of the ion implantation is too small, it is easy to cause the reaction time of the ion implantation to be too long, and the efficiency of the process technology is reduced. For this reason, in the present embodiment, during the process of performing ion implantation on the channel structure 200 at the bottom of the groove 210, the implantation energy of the ion implantation is 1keV-10keV.

[0113] It should also be noted that, in the present embodiment, during the process of ion implantation of the channel structure 200 at the bottom of the groove 210, the implantation depth of the ion implantation should not be too large or too small. If the implantation depth of the ion implantation is too large, it is easy to cause the thickness of the growth inhibition layer 220 to be too large, and it is easy to cause the space occupied at the bottom of the source-drain doping layer 400 to be too large, resulting in unnecessary waste and affecting the working performance of the channel structure 200; if the implantation depth of the ion implantation is too small, it is easy to cause the thickness of the growth inhibition layer 220 to be too small, and it is easy to cause the growth inhibition layer 220 to have a good growth inhibition effect on the source-drain doping layer 400, thereby affecting the formation of the gap between the source-drain doping layer 400 and the channel structure 200 at its bottom. For this reason, in the present embodiment, during the process of ion implantation of the channel structure 200 at the bottom of the groove 210, the implantation depth of the ion implantation is 5 angstroms to 20 angstroms.

[0114] Combined with reference Figure 22 to Figure 24 , Fig.23 for Fig.12 Cross-sectional view along AA direction, Fig.24 for Fig. 22 In the cross-sectional view along the BB direction, in the step of forming the source-drain doped layer 400 , the growth inhibition layer 220 and the bottom of the source-drain doped layer 400 form a gap.

[0115] Specifically, in the present embodiment, in the step of forming the source-drain doped layer 400 in the trench 210 , the concave morphology and the bottom of the source-drain doped layer 400 form a gap.

[0116] The concave part of the concave shape can form a larger space, which is beneficial to make the gap between the concave shape and the bottom of the source-drain doping layer 400 more sufficient, and can better reduce the capacitance between the source-drain doping layer and the bottom channel structure 200.

[0117] In this embodiment, after the source-drain doping layer 400 is formed, the forming method further includes: removing the gate structure 300 to form a gate opening; and forming a device gate structure in the gate opening.

[0118] The device gate structure is used to control the opening and closing of the channel of the transistor.

[0119] In this embodiment, the device gate structure includes a gate dielectric layer covering the channel structure 200 and a gate electrode layer located on the gate dielectric layer.

[0120] The gate dielectric layer is used to isolate the device gate structure from the channel structure 200 .

[0121] The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3. In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. Among them, the high-k dielectric material refers to a dielectric material whose relative dielectric constant is greater than the relative dielectric constant of silicon oxide. Specifically, the material of the high-k gate dielectric layer includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3, etc.

[0122] It should be noted that the gate dielectric layer may further include a gate oxide layer, and the gate oxide layer is located between the high-k gate dielectric layer and the channel structure 200. Specifically, the material of the gate oxide layer may be silicon oxide.

[0123] In this embodiment, the material of the gate electrode layer is one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

[0124] In this embodiment, the device gate structure is a metal gate structure.

[0125] Therefore, the gate electrode layer includes a work function layer (not labeled) and an electrode layer (not labeled) located on the work function layer. The work function layer is used to adjust the threshold voltage of the transistor, and the electrode layer is used to lead out the electrical properties of the metal gate structure.

[0126] In other embodiments, according to process requirements, the gate structure may also be a polysilicon gate structure.

[0127] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A channel structure protrudes from the substrate; A gate structure, spanning the channel structure, the gate structure covering the top and sidewalls of the channel structure; The source-drain doped layer is located in the channel structure at both sides of the gate structure and is in contact with the end of the channel structure. There is a gap between the source-drain doped layer and the channel structure at the bottom thereof.

2. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes: a growth inhibition layer located at the top of the channel structure at the bottom of the source-drain doping layer, and the growth inhibition layer and the bottom of the source-drain doping layer form the gap.

3. The semiconductor structure according to claim 2, wherein: The channel structure at the bottom of the source-drain doping layer is in a concave shape, and the growth inhibition layer is located at the concave shape.

4. The semiconductor structure according to claim 3, characterized in that The concave shape is an arc shape.

5. The semiconductor structure according to claim 2, wherein: The growth inhibition layer has a thickness of 5 angstroms to 20 angstroms.

6. The semiconductor structure according to claim 2, wherein: The growth inhibition layer is an ion doped layer, and the ion doped layer is provided by a channel structure doped with ions.

7. The semiconductor structure according to claim 6, wherein: The doping ions of the ion-doping layer include carbon ions, hydrogen ions, boron ions or fluorine ions.

8. The semiconductor structure according to claim 1, wherein: The distance between the top and the bottom of the gap is 1 nanometer to 10 nanometers.

9. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes: an isolation layer, located on the substrate and covering a portion of the thickness of the sidewall of the channel structure; A top surface of the channel structure at the bottom of the source-drain doping layer is lower than a top surface of the isolation layer.

10. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, on which a channel structure protruding from the substrate is formed, and on which a gate structure spanning the channel structure is also formed, wherein the gate structure covers the top and sidewalls of the channel structure; Removing part of the channel structure on both sides of the gate structure to form a trench; A source-drain doping layer is formed in the trench, wherein the source-drain doping layer is in contact with the end of the channel structure and has a gap with the channel structure at the bottom.

11. The method for forming a semiconductor structure according to claim 10, wherein: After forming the trench and before forming the source-drain doping layer, the forming method further comprises: forming a growth inhibition layer at the bottom of the trench; In the step of forming the source-drain doped layer, the growth inhibition layer and the bottom of the source-drain doped layer form the gap.

12. The method for forming a semiconductor structure according to claim 11, wherein: In the step of removing part of the channel structure on both sides of the gate structure to form a trench, the channel structure at the bottom of the trench has a concave morphology; In the step of forming the source-drain doped layer, the concave morphology and the bottom of the source-drain doped layer form the gap.

13. The method for forming a semiconductor structure according to claim 11, wherein: The step of forming a growth inhibition layer at the bottom of the trench includes: performing ion implantation on the channel structure at the bottom of the trench to form an ion doped layer, wherein the ion doped layer is used as the growth inhibition layer.

14. The method for forming a semiconductor structure according to claim 13, wherein: In the step of performing ion implantation on the channel structure at the bottom of the trench, the ions implanted by the ion implantation include carbon ions, hydrogen ions, boron ions or fluorine ions.

15. The method for forming a semiconductor structure according to claim 13, wherein:In the step of performing ion implantation on the channel structure at the bottom of the trench, the implantation dose of the ion implantation is 1e12 atoms / cm 2 To 1e20atoms / cm 2 , the injection energy is 1keV-10keV.

16. The method for forming a semiconductor structure according to claim 13, wherein: In the step of performing ion implantation on the channel structure at the bottom of the trench, the implantation depth of the ion implantation is 5 angstroms to 20 angstroms.

17. The method for forming a semiconductor structure according to claim 13, wherein: In the step of performing ion implantation on the channel structure at the bottom of the trench, the angle between the implantation angle of the ion implantation and the direction perpendicular to the substrate surface is 0° to 5°.

18. The method for forming a semiconductor structure according to claim 10, wherein: In the step of forming a source-drain doping layer in the trench, the distance between the top and the bottom of the gap is 1 nanometer to 10 nanometers.

19. The method for forming a semiconductor structure according to claim 10, wherein: In the step of providing a substrate, an isolation layer is also formed on the substrate, and the isolation layer covers a portion of the thickness of the sidewall of the channel structure; In the step of removing part of the channel structure on both sides of the gate structure to form a trench, the bottom of the trench is lower than the top surface of the isolation layer.

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