Novel nano wall (NWaFET) IC basic structure with ferroelectric material

Abstract

The invention discloses a novel nano wall (NWaFET) IC basic structure with a ferroelectric material, and relates to the field of microelectronic technology and integrated circuits (IC). According to the nanowall structure, the SiO2 structure is embedded among the N-drain region, the P-type channel semiconductor region and the N + source region, and the ferroelectric layer structure is attached outside the gate oxide layer, so that the leakage current can be effectively reduced, and the SS is less than 60mV / decade.

Description

Technical Field

[0001] The present invention relates to the fields of microelectronics and integrated circuits. Background Art

[0002] The integrated circuit industry has developed rapidly since the 1950s. [1] The number of components on a chip doubles every six months (every 18 months after 1975), and the performance and capacity of semiconductors will grow exponentially. [2] The basis of Moore's Law is the scaling down of integrated circuits. However, according to the IEEE International Roadmap for Devices and Systems (IRDS), the channel length Lch of integrated circuits cannot exceed (be less than) 12nm. [3] , Moore's Law will face the dilemma of being unable to move forward.

[0003] HVTFET (heterojunction vertical channel field effect transistor) and new nano-wall NWaFET structure before this invention [4-7] , adopting a vertical design scheme, greatly improving the integration of the device, and suppressing the DIBL effect through a combined structure of heavily doped channel region and lightly doped drift region. HVT and NWaFET structures achieve a further reduction in Lch by adopting heavily doped channel. It is better than the existing FINFET [8] , GAA [9] Etc. have a shorter channel length Lch and a higher degree of integration. In the above-mentioned new devices with SS less than 60mV / decade, although the tunneling transistor has a very small off-state current due to the band-to-band tunneling mechanism, its disadvantages of low driving capability and small on-state current are more obvious. Compared with other transistors, the manufacturing process of nanoelectromechanical transistors is complex and the switching speed is extremely slow. Since the research team of Purdue University in the United States proposed the concept of using the negative capacitance effect to manufacture new low-power transistors in 2008, NCFET has been attracting much attention. First, it is because of its excellent switching performance such as low off-state current and high on-state current, and second, it is compatible with the manufacturing process of current mainstream CMOS devices, and only needs to add a layer of ferroelectric material with negative capacitance effect in the dielectric layer of the gate. Therefore, NCFET is considered to be a favorable competitor for low-power devices in the era of transistor super-scaling.

[0004] This paper proposes a new type of nano-wall IC basic structure with ferroelectric materials. On the basis of the nano-wall device, SiO2 is embedded between the channel, source region and lightly doped drain region, so that the off-state current is reduced and the on-state current is increased. A ferroelectric layer is inserted between the gate oxide layer and the polysilicon gate to further reduce the off-state current, increase the on-state current, and make SS less than 60mV / decade. The present invention also combines NMOS and PMOS into a CMOS structure and connects them into an inverter structure through interconnects. Compared with planar processes and FINFET and GAA processes, this structure can significantly improve the integration. The structure also adopts a gate alignment method. The gate region of the structure of the present invention only wraps the channel region or the channel region and the lightly doped drift region adjacent to it, which can greatly reduce the parasitic capacitance between the gate and the heavily doped source and drain region, so that the device frequency characteristics are improved. In principle, the present invention still uses the HVTFET and NWaFET structures to achieve a shorter channel length Lch, and suppresses the DIBL effect through the combined structure of heavily doped channel region and lightly doped drift region.

[0005] References

[0006] [1].MOORE GECramming More Components Onto Integrated Circuits[J].Proceedings of the IEEE,1998,86(1):82–85.

[0007] [2]. Thompson S, Packan P, Bohr M. MOS scaling: transistor challenges for the 21st century. Intel Technology Journal, 1998; pp 1-18.

[0008] [3].https: / / semiwiki.com / events / 306532-ibm-at-iedm /

[0009] [4].https: / / en.wikipedia.beta.wmflabs.org / wiki / Static_random-access_memory

[0010] [5].Liu C,Ma W,Chen M,et al.A vertical silicon-graphene-germaniumtransistor[J].Nature communications,2019,10(1):4873.

[0011] [6].Moore G E.Cramming more components onto integrated circuits[J].Proceedings of the IEEE,1998,86(1):82-85.

[0012] [7]. Liao Yongbo, Liu Jinming, Li Ping et al. A high-integration nano-wall integrated circuit structure [P]. China, invention patent, application number: CN202210413345.4.2022.

[0013] [8].Chenming Hu,Lee WC,Kedzierski J,et al.FinFET-a self-aligneddouble-gateMOSFET scalable to 20nm[J].IEEE Transactions on Electron Devices,2000,47(12):2320-2325.

[0014] [9].JPColinge,MHGao,A.Romano,H.Maes,C.Claeys.Silicon-on-insulator "gate-all-around" MOS device[C].1990IEEE SOS / SOI Technology Conference.Proceedings.Key West, FL, USA: IEEE, 1990:137-138. Summary of the invention

[0015] Technical solution 1 of the present invention is a basic structure of a new nano-wall IC with ferroelectric materials, such as Figure 1 and Figure 2 As shown, Figure 1 The NC-NWaFET structure shown is NMOS, with a P-Substrate silicon single crystal semiconductor region 105 at the bottom of a single vertical channel MOS tube, and upwards are the N+ drain region 104, N- drain region 103, P-type channel semiconductor region 102, N+ source region 101 of the NMOS, and a SiO2 structure 106 is embedded in the middle of the N- drain region, the P-type channel semiconductor region, and the N+ source region. The outside of the active region is a SiO2 gate oxide layer structure 106, followed by an Insuator ferroelectric structure 107 outside the SiO2 structure, and the outermost gray area is a Poly-Si gate 108; Figure 2The NC-NWaFET structure shown is a PMOS, with an N-well silicon single crystal semiconductor region 205 at the bottom of a single vertical channel MOS tube, and upwards are the NMOS P+ drain region 204, P-drain region 203, N-type channel semiconductor region 202, P+ source region 201, and a SiO2 structure 106 embedded in the middle of the P-drain region, N-type channel semiconductor region, and P+ source region. The outside of the active region is a SiO2 gate oxide layer structure 106, followed by an Insuator ferroelectric structure 107 outside the SiO2 gate oxide layer structure, and the outermost gray area is a Poly-Si gate 108. Figure 4 The figure shows a cross-sectional view of the NMOS structure, wherein the bottom is a P-Substrate silicon single crystal semiconductor region 105, and upwards are the NMOS N+ drain region 104, N-drain region 103, P-type channel semiconductor region 102, N+ source region 101, and a SiO2 structure 106 is embedded in the middle of the N-drain region, the P-type channel semiconductor region, and the N+ source region. The outside of the active region is a SiO2 gate oxide layer structure 106, and the outside of the SiO2 gate oxide layer structure is an Insuator ferroelectric structure 107. The outermost gray area is a Poly-Si gate 108; Figure 5 FIG. 1 is a side view of the NMOS structure, wherein the bottom is a P-Substrate silicon single crystal semiconductor region 105, and upwards are the N+ drain region 104 of the NMOS, the SiO2 gate oxide layer structure 106, and the Poly-Si gate 108; Figure 6 The top view of the structure is shown. The structure of the present invention can adopt four gate structures, which can be four-sided ring gate (a), three-sided ring gate (b), two-sided ring gate (a), and single-sided ring gate (d). The innermost side is the SiO2 structure 106, followed by the N+ source region 101, the SiO2 gate oxide layer structure 106, the Insuator ferroelectric structure 107, and the Poly-Si gate 108 from the inside to the outside.

[0016] Technical solution 2 of the present invention is a CMOS integrated circuit structure composed of a new type of nano-wall IC basic structure with ferroelectric materials, such as Figure 7 As shown in FIG. 1 , the CMOS is composed of two nano-wall basic units with embedded SiO2 with ferroelectric material, one NMOS and one PMOS, respectively. Figure 1 and Figure 2As shown, at the bottom of a single vertical channel NMOS tube is a P-Substrate silicon single crystal semiconductor region 105, and upwards are the NMOS N+ drain region 104, N-drain region 103, P-type channel semiconductor region 102, N+ source region 101, and SiO2 structure 106 is embedded in the middle of the N-drain region, P-type channel semiconductor region, and N+ source region. The outside of the active area is the SiO2 gate oxide layer structure 106, and the outside of the SiO2 structure is the Insuator ferroelectric structure 107. The outermost gray area is the Poly-Si gate 108. At the bottom of a single vertical channel PMOS tube is an N-well silicon single crystal semiconductor region 205, and upwards are the NMOS P+ drain region 204, P-drain region 203, N-channel The semiconductor region 202, the P+ source region 201, the SiO2 structure 106 is embedded in the middle of the P-drain region, the N-channel semiconductor region, and the P+ source region. The SiO2 gate oxide layer structure 106 is outside the active region, and the Insuator ferroelectric structure 107 is outside the SiO2 gate oxide layer structure. The outermost gray area is the Poly-Si gate 108; a groove is arranged in the Poly gate on its side, and the groove is filled with a gate electrode; the PMOS drain electrode and the NMOS drain electrode are arranged on the sides of the NMOS and PMOS; the NMOS drain electrode is in contact with its N+ drain region; the PMOS drain electrode is in contact with its P+ drain region; the NMOS source electrode is directly led out and in contact with its N+ source region; the insulating material isolates the PMOS drain electrode and the NMOS drain electrode from other regions. The drain of NMOS is connected to the drain of PMOS through a wire; the gate of NMOS is connected to the gate of PMOS through a wire, the source of NMOS is connected to VDD, and the source of PMOS is connected to GND to form an inverter. The circuit formed is as follows: Figure 8 shown.

[0017] Furthermore, the thickness of the P-type channel semiconductor region is less than 12 nm.

[0018] Furthermore, the doping concentration of the P-type channel semiconductor region is more than 2 orders of magnitude higher than that of the N-drain region.

[0019] Furthermore, the thickness of the N-type channel semiconductor region is less than 12 nm.

[0020] Furthermore, the doping concentration of the N-type channel semiconductor region is more than 2 orders of magnitude higher than that of the N-drain region.

[0021] Furthermore, the gate electrode is disposed on the entire area of ​​four side surfaces of the semiconductor region, or the entire area of ​​three side surfaces of the semiconductor region and a partial area of ​​the last side surface, such as Figure 6 (a) shown.

[0022] Furthermore, the gate electrode is disposed on the entire area of ​​three sides of the semiconductor region, or the entire area of ​​two sides of the semiconductor region and a partial area of ​​the other side, such as Figure 6 (b) as shown.

[0023] Furthermore, the gate electrode is disposed on the entire area of ​​both side surfaces of the semiconductor region, or the entire area of ​​one side surface of the semiconductor region and a partial area of ​​the other side surface, such as Figure 6 (c) as shown.

[0024] Furthermore, the gate electrode is disposed on the entire area of ​​one side of the semiconductor region, or on a local area of ​​one side of the semiconductor region, such as Figure 6 (d) as shown.

[0025] Furthermore, the thickness of all layers ranges from 1 nm to 100 nm, and the doping concentration ranges from 1e14 cm-3 to 1e20 cm-3.

[0026] Further, when the channel semiconductor region, heavily doped drain region, semiconductor substrate or well is single crystal silicon, the lightly doped drain region is a narrow bandgap pseudocrystalline semiconductor material (such as SiGe pseudocrystalline); when the channel semiconductor region, heavily doped drain region, semiconductor substrate or well is a wide bandgap single crystal semiconductor material (such as SiC single crystal or GaN single crystal), the lightly doped drain region is a pseudocrystalline Si semiconductor material. Using pseudocrystalline in the lightly doped drain region can introduce stress in the channel semiconductor and increase the mobility of carriers.

[0027] Further, when the channel semiconductor region, heavily doped drain region, semiconductor substrate or well is single crystal silicon, the heavily doped source region is single crystal Si or narrow bandgap single crystal semiconductor material, and the heavily doped source region is polycrystalline Ge, polycrystalline SiGe, polycrystalline TWS (mercury cadmium telluride), polycrystalline InP, polycrystalline InSb or other narrow bandgap semiconductor polycrystalline materials, or a combination of the above materials; when the channel semiconductor region, heavily doped drain region, semiconductor substrate or well is wide bandgap single crystal semiconductor material (such as SiC single crystal or GaN single crystal), the heavily doped source region is single crystal Si semiconductor material, and the heavily doped source region is polycrystalline Si semiconductor material. If the heavily doped source region uses narrow bandgap pseudocrystalline semiconductor material, due to the stress generated by lattice mismatch, its thickness must be very thin, and the source region metal alloy may penetrate the pseudocrystalline source region, causing device failure. The heavily doped source region uses polycrystalline material, there is no lattice mismatch problem, so its thickness can be thicker, thereby avoiding the problems caused by pseudocrystals.

[0028] This paper proposes a new type of nano-wall IC basic structure with ferroelectric materials. Based on the nano-wall device, SiO2 is embedded between the channel, source region and lightly doped drain region.

[0029] It is combined with PMOS to form a CMOS structure, and connected to an inverter structure through interconnection lines. In addition, the structure also adopts a gate alignment method. The gate area of ​​the structure of the present invention only wraps the channel area or the channel area and the lightly doped drift area adjacent to it, which can greatly reduce the parasitic capacitance between the gate and the heavily doped source and drain area, thereby improving the device frequency characteristics. Compared with planar processes and FINFET and GAA processes, this structure can significantly improve integration and save chip area. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 This is an oblique cross-sectional view of a basic unit NMOS of a new type of nano-wall IC basic structure with ferroelectric material according to the present invention.

[0031] Figure 2 This is an oblique cross-sectional view of a basic unit PMOS of a new type of nano-wall IC basic structure with ferroelectric material according to the present invention.

[0032] Figure 3 This is a diagram of NMOS and PMOS electronic components composed of a basic structure of a new type of nano-wall IC with ferroelectric material according to the present invention.

[0033] Figure 4 It is a front plan view of a basic unit NMOS of a new type of nano-wall IC basic structure with ferroelectric material according to the present invention.

[0034] Figure 5 It is a side plan view of a basic unit NMOS of a new type of nano-wall IC basic structure with ferroelectric material according to the present invention.

[0035] Figure 6 The top plan view of the basic unit NMOS of the basic structure of a novel nano-wall IC with ferroelectric material of the present invention, wherein 6(a) is a four-sided ring gate, 6(b) is a three-sided ring gate, 6(c) is a two-sided ring gate, and 6(d) is a one-sided ring gate.

[0036] Figure 7 This is a side cross-sectional view of a basic unit CMOS of a new type of nano-wall IC basic structure with ferroelectric material of the present invention. The left side is an NMOS basic unit and the right side is a PMOS basic unit.

[0037] Figure 8 In order to invent an inverter composed of a basic unit of a new type of nano-wall IC basic structure with ferroelectric material of the present invention, a three-dimensional schematic diagram of an actual connection method of the structure described in Technical Solution 2 is provided.

[0038] Fig. 9 A circuit diagram of an inverter composed of a basic structural unit of a novel nano-wall IC with ferroelectric material according to the present invention.

[0039] Fig.10 This is a simulation comparison diagram of the basic structure of the new nanowall IC with ferroelectric materials and the nanowall structure without ferroelectric materials, where the upper figure is the output characteristic curve and the lower figure is the transfer characteristic curve (the vertical axis is logarithmic). DETAILED DESCRIPTION

[0040] Example 1: A new nano-wall IC basic structure with ferroelectric materials

[0041] A new type of nano-wall IC basic structure with ferroelectric material, characterized in that the device structure is based on the nano-wall basic structure, with a silicon dioxide insulating part embedded in the middle and a ferroelectric layer attached to the gate oxide layer. Figure 1 The three-dimensional diagram and the cross-sectional diagram are shown in FIG4 : the region 104 is the heavily doped source region N+, the region 103 is the lightly doped drain region N-, the region 102 is the heavily doped channel region P, the region 101 is the heavily doped drain region N+, and the region 106 is the silicon dioxide insulating part embedded therein, from the surface of the source to the lightly doped drain, and the specific depth of embedding in the lightly doped drain is adjustable. The side is the gate oxide layer region 106 close to the silicon region, the outer layer is the ferroelectric material 107, and the outermost layer is the polysilicon gate 108. The output characteristic curve of this structure when the channel length is 5nm is shown in FIG4 . Figure 7 Compared with the traditional NWaFET structure when the channel length is 5nm, the simulation results are shown in Fig.10 .

Claims

1. A new nano-wall FET (NWaFET) IC basic structure with ferroelectric materials, characterized in that: The device structure is based on the basic structure of nanowalls, with a silicon dioxide insulating part embedded in the middle and a ferroelectric layer attached to the outside of the gate oxide layer. As shown in Figure 1, the 3D view and Figure 4, the cross-sectional view: region 104 is the heavily doped drain region N+, region 103 is the lightly doped drain region N-, region 102 is the heavily doped channel region P, region 101 is the heavily doped source region N+, and region 106 is the silicon dioxide insulating portion embedded therein, from the source surface to the lightly doped drain, and the specific depth of embedding in the lightly doped drain is adjustable. The side is the gate oxide layer region 106 close to the silicon region, the outer layer is the ferroelectric material 107, and the outermost layer is the polysilicon gate layer 108.

2. A novel nano-wall IC basic structure with ferroelectric material as claimed in claim 1, characterized in that: The thickness of the P-type channel semiconductor region 102 of the NMOS is less than 12 nm.

3. According to the basic structure of a novel nano-wall IC with ferroelectric material as claimed in claim 1, the doping concentration of the P-type channel semiconductor region 102 of the NMOS is more than one order of magnitude higher than that of the N-drain region 103.

4. A novel nano-wall IC basic structure with ferroelectric material as claimed in claim 1, characterized in that: The thickness of all layers ranges from 1nm to 100nm, and the doping concentration ranges from 1e14cm-3 to 1e20cm-3.

5. A basic structure of a novel nano-wall IC with ferroelectric material as claimed in claim 1, when the channel semiconductor region 102, the heavily doped drain region 104, the semiconductor substrate 105 or the well 205 are single crystal silicon, the lightly doped drain region 103 is a narrow bandgap pseudocrystalline semiconductor material (such as SiGe pseudocrystalline), the heavily doped source region 101 is single crystal Si or a narrow bandgap single crystal semiconductor material, and the gate 108 is polycrystalline Ge, polycrystalline SiGe, polycrystalline TWS (mercury cadmium telluride), polycrystalline InP , polycrystalline InSb and other narrow bandgap semiconductor polycrystalline materials, or a combination of the above materials; when the channel semiconductor region 102, the heavily doped drain region 104, the semiconductor substrate 105 or the well 205 are wide bandgap single crystal semiconductor materials (such as SiC single crystal or GaN single crystal), the lightly doped drain region 103 is a pseudomorphous Si semiconductor material, the heavily doped source region 101 is a single crystal Si semiconductor material, and the gate 108 is composed of heavily doped polycrystalline or refractory metal silicide or refractory metal or a combination thereof.

6. A novel nano-wall IC basic structure with ferroelectric material as claimed in claim 1, characterized in that: The gate 108 is arranged in the entire area of ​​one side surface of the semiconductor region, or in a local area of ​​one side surface of the semiconductor region; further, the gate electrode is arranged in the entire area of ​​two side surfaces of the semiconductor region, or in the entire area of ​​one side surface of the semiconductor region and in a local area of ​​the other side surface; further, the gate electrode is arranged in the entire area of ​​three side surfaces of the semiconductor region, or in the entire area of ​​two side surfaces of the semiconductor region and in a local area of ​​the other side surface; further, the gate is arranged in the entire area of ​​four side surfaces of the semiconductor region, or in the entire area of ​​three side surfaces of the semiconductor region and in a local area of ​​the last side surface.

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