Planar gate SiC MOSFET device with cell expansion region and preparation method thereof

Abstract

The embodiment of the invention provides a planar gate SiC MOSFET device with a cell expansion region and a preparation method of the planar gate SiC MOSFET device. The planar gate SiC MOSFET device comprises a doped semiconductor substrate, a drift region, the cell expansion region and a gate bonding pad from bottom to top. Wherein the cell expansion area is located below the grid electrode bonding pad, a grid electrode structure comprising a polycrystalline silicon grid electrode, a dielectric layer, a source electrode metal layer and a cell area are integrated in the cell expansion area, and the source electrode metal layer constructs an efficient source electrode signal channel in the cell expansion area. In a grid interconnection structure defined by the dielectric layer, the source metal layer, the grid structure and the grid bonding pad, the grid bonding pad and the polycrystalline silicon grid form a grid signal conductive path through the grid interconnection structure, and grid source signal insulation is formed through the dielectric layer and the source metal layer. According to the embodiment of the invention, the gate bonding pad is suspended above the cell expansion region, so that the number of cells in a unit area is effectively increased, the specific on-resistance can be effectively reduced, and the power density of the device is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to, but are not limited to, the field of power electronics technology, and in particular to a planar gate SiC MOSFET device with a cell expansion region and a method for preparing the same. Background Art

[0002] Vertical double-diffused metal oxide field effect transistor (MOSFET), with its high withstand voltage, low on-resistance and fast switching characteristics, has become a core power device in high-end applications such as industrial control, consumer electronics, and especially new energy vehicles. Among them, semiconductor MOSFET (such as SiC MOSFET) has become a strong competitor and substitute for silicon-based insulated gate bipolar transistor (IGBT) with its significant material advantages, such as three times the bandgap width of silicon, ten times the critical breakdown field strength of silicon, and excellent thermal conductivity. In the design of SiC MOSFET, planar gate SiC MOSFET has certain limitations in on-resistance and current density, especially its higher specific on-resistance (Specific On-Resistance, Ron,sp) limits the further improvement of power density. Summary of the invention

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] The embodiment of the present application provides a planar gate SiC MOSFET device with a cell expansion region, which can effectively increase the number of cells per unit area, thereby effectively reducing the specific on-resistance and further improving the power density of the device.

[0005] In the first aspect, an embodiment of the present application provides a planar gate SiC MOSFET device with a cell expansion region, comprising: a doped semiconductor substrate, a doped semiconductor drift region, a cell expansion region and a gate pad from bottom to top; the cell expansion region is located below the gate pad, the cell expansion region includes a cell region, a gate structure, a dielectric layer, and a source metal layer, the gate structure includes a polysilicon gate, and the cell expansion region forms a source signal path through the source metal layer; the gate structure, the dielectric layer, the source metal layer and the gate pad form a gate interconnection structure, the gate pad forms a gate signal conductive path with the polysilicon gate through the gate interconnection structure, and forms gate-source signal insulation with the source metal layer through the dielectric layer.

[0006] In combination with the first aspect, in a possible implementation of the first aspect, the source metal layer includes a source metal contact layer and a source first metal layer from bottom to top, and the dielectric layer includes a first interlayer dielectric layer; the source metal contact layer and the source first metal layer are located at the lower end of the first interlayer dielectric layer; and the gate pad is located at the upper end of the first interlayer dielectric layer.

[0007] In combination with the first aspect, in a possible implementation of the first aspect, the source metal layer includes a source second metal layer, the source second metal layer is located on the upper end of the source first metal layer, and the first interlayer dielectric layer is located between the source second metal layer and the source first metal layer.

[0008] In combination with the first aspect, in a possible implementation of the first aspect, the gate structure includes a gate oxide layer, and the polysilicon gate is located at the upper end of the gate oxide layer; the dielectric layer includes a second interlayer dielectric layer, and the polysilicon gate is located at the lower end of the second interlayer dielectric layer; the combined structure formed by the source metal contact layer and the source first metal layer forms an insulating circuit with the polysilicon gate through the second interlayer dielectric layer.

[0009] In combination with the first aspect, in a possible implementation of the first aspect, the source metal layer includes the source metal contact layer, the source first metal layer and the source second metal layer; the cell expansion area forms a source signal path through the source metal layer, including: the cell expansion area forms a source signal path with the source metal contact layer through the source first metal layer and the source second metal layer.

[0010] In combination with the first aspect, in a possible implementation of the first aspect, the gate pad forms a gate signal conductive path with the polysilicon gate through the gate interconnection structure, including: the gate pad is interconnected with the gate polysilicon layer through the source metal contact layer and the source first metal layer to form a gate signal conductive path.

[0011] In combination with the first aspect, in a possible implementation of the first aspect, the doped semiconductor substrate is a P-type substrate or an N-type substrate; when the doped semiconductor substrate is a P-type substrate, the doped semiconductor drift region is a P-type semiconductor drift region; when the doped semiconductor substrate is an N-type substrate, the doped semiconductor drift region is an N-type semiconductor drift region.

[0012] In combination with the first aspect, in a possible implementation of the first aspect, the preparation material of the source first metal layer and the source second metal layer includes at least one of gold, silver, aluminum and aluminum alloy; the preparation material of the dielectric layer includes at least one of silicon dioxide, silicon nitride and high-K dielectric.

[0013] In a second aspect, an embodiment of the present application provides a method for preparing a planar gate SiC MOSFET device with a cell expansion region, which is applied to the planar gate SiC MOSFET device with a cell expansion region as described above, comprising: obtaining a semiconductor material, and processing the semiconductor material according to a first preset doping concentration to obtain a doped semiconductor substrate; performing an epitaxial growth process on the doped semiconductor substrate according to a second preset doping concentration to form a doped semiconductor drift region on the doped semiconductor substrate; performing doping and high-temperature annealing on the doped semiconductor drift region to form a cell region, and forming a cell expansion region in the cell region, and at the same time forming a gate pad suspended above the cell expansion region; based on the doped semiconductor substrate, the doped semiconductor drift region, the cell expansion region and the gate pad, a planar gate SiC MOSFET device with a cell expansion region is obtained.

[0014] In combination with the second aspect, in a possible implementation of the second aspect, forming a cell expansion region in the cell region includes: performing doping and thermal annealing on the cell region to form a gate oxide layer on the cell region; performing epitaxial growth and etching on the gate oxide layer according to a third preset doping concentration to obtain a polysilicon gate; and depositing a first dielectric layer, a source metal contact layer, a source first metal layer, a second interlayer dielectric layer and a source second metal layer on the polysilicon gate to form a cell expansion region.

[0015] The embodiment of the present application integrates the doped semiconductor substrate, drift region, cell expansion region and gate pad from bottom to top. Among them, the cell expansion region is located below the gate pad. This area not only integrates the gate structure including the polysilicon gate, but also integrates the dielectric layer, the source metal layer and the key cell region. The source metal layer constructs an efficient source signal path in the cell expansion region to ensure smooth and unobstructed signal. In addition, the gate interconnection structure defined by the dielectric layer, the source metal layer, the gate structure and the gate pad realizes an efficient conduction path for the gate signal. In particular, the gate pad is closely connected to the polysilicon gate through the gate interconnection structure to form a gate signal conductive path, ensuring the accurate transmission of the gate signal; at the same time, the gate pad and the source metal layer are isolated by the dielectric layer, ensuring the insulation safety of the gate source signal. The embodiment of the present application introduces the cell expansion region and suspends the gate pad above the cell expansion region, effectively increasing the number of cells per unit area, thereby effectively reducing the specific on-resistance and thus improving the power density of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic diagram of the cell expansion region structure of a planar gate SiC MOSFET device with a cell expansion region provided in an embodiment of the present application;

[0017] Figure 2 It is a schematic diagram of the gate interconnection structure of another planar gate SiC MOSFET device with a cell expansion region provided in an embodiment of the present application;

[0018] Figure 3 It is a flow chart of a method for preparing a planar gate SiC MOSFET device with a cell expansion region provided in an embodiment of the present application;

[0019] Figure 4 It is a schematic diagram of a process for preparing a planar gate SiC MOSFET device with a cell expansion region provided by a specific example of the present application;

[0020] Figure numerals: doped semiconductor substrate 100; doped semiconductor drift region 101; cell region 102; gate oxide layer 201; polysilicon gate 202; first interlayer dielectric layer 204; second interlayer dielectric layer 203; source metal contact layer 301; source first metal layer 302; source second metal layer 303; gate pad 304; cell expansion region 401; gate interconnect structure 402. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0022] It should be noted that, although the logical order is shown in the flowchart, in some cases, the steps shown or described can be performed in a different order from that in the flowchart. The terms "first", "second", etc. in the specification, claims and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions that the present invention can be implemented, so they have no technical substantive significance. Any modification of the structure, change of the proportional relationship or adjustment of the size, without affecting the effects that the present invention can produce and the purposes that can be achieved, should still fall within the scope of the technical content disclosed by the present invention. At the same time, the terms such as "upper", "lower", "left", "right", "middle" and "one" quoted in this specification are only for the convenience of narration, and are not used to limit the scope of the implementation of the present invention. The change or adjustment of the relative relationship should also be regarded as the scope of the implementation of the present invention without substantially changing the technical content.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0024] Vertical double diffused metal oxide field effect transistor (VDMOSFET), with its high withstand voltage, low on-resistance and fast switching characteristics, has become a core power device in high-end applications such as industrial control, consumer electronics, and especially new energy vehicles. With the update and iteration of semiconductor technology, the introduction of third-generation wide bandgap semiconductor materials such as silicon carbide (SiC), the electrothermal performance of power MOSFET has been significantly improved. With its significant material advantages, such as a bandgap width three times that of silicon, a critical breakdown field strength ten times that of silicon, and excellent thermal conductivity, SiC MOSFET has become a strong competitor and substitute for silicon-based insulated gate bipolar transistors (IGBT). These characteristics enable SiC MOSFET to achieve a breakdown voltage comparable to that of silicon-based devices on a thinner drift layer, while significantly reducing the on-voltage drop, increasing the switching frequency, and being able to operate stably at higher temperatures, greatly broadening its application range. In the design of SiC MOSFET, planar gate MOSFET has certain limitations in terms of on-resistance and current density, especially its high on-resistance (Ron,sp) limits the further improvement of power density. To overcome this problem, common methods include reducing the effective cell size to increase the number of cells per unit area, shortening the channel length to reduce the channel resistance, and introducing an N-type buffer layer to compress the chip thickness. However, these methods are often constrained by the complexity of the manufacturing process and design limitations in practical applications, making it difficult to achieve significant performance breakthroughs.

[0025] In view of this, an embodiment of the present application provides a planar gate SiC MOSFET device with a cell expansion region and a preparation method thereof, wherein the SiC MOSFET device integrates a doped semiconductor substrate, a drift region, a cell expansion region and a gate pad in sequence from bottom to top. Among them, the cell expansion region is located below the gate pad. This region not only integrates a gate structure including a polysilicon gate, but also integrates a dielectric layer, a source metal layer and a key cell region, and the source metal layer constructs an efficient source signal path in the cell expansion region to ensure smooth and unobstructed signal flow. In addition, the gate interconnection structure defined by the dielectric layer, the source metal layer, the gate structure and the gate pad realizes an efficient conduction path for the gate signal. In particular, the gate pad is closely connected to the polysilicon gate through the gate interconnection structure to form a gate signal conductive path, ensuring the accurate and correct transmission of the gate signal; at the same time, the gate pad and the source metal layer are isolated by a dielectric layer to ensure the insulation safety of the gate-source signal. The embodiment of the present application introduces a cell expansion area and suspends the gate pad above the cell expansion area, thereby effectively increasing the number of cells per unit area, thereby effectively reducing the specific on-resistance and further improving the power density of the device.

[0026] The embodiments of the present application are further described below in conjunction with the accompanying drawings.

[0027] See also Figure 1 , Figure 1It is a schematic diagram of the cell expansion region structure of the planar gate SiC MOSFET device with a cell expansion region provided in an embodiment of the present application. The planar gate SiC MOSFET device with a cell expansion region adopts a layered structure, and integrates the doped semiconductor substrate 100, the doped semiconductor drift region 101, the cell expansion region 401 and the gate pad 304 from bottom to top. Among them, the cell expansion region 401 integrates the cell region 102, the gate structure, the dielectric layer and the source metal layer. This area is placed under the gate pad 304, and a smooth source signal path is constructed through the source metal layer, which not only enhances the efficiency of signal transmission, but also optimizes the overall layout and performance of the device. Specifically, the gate structure integrates the gate oxide layer 201 and the polysilicon gate 202, the dielectric layer integrates the first interlayer dielectric layer 204 and the second interlayer dielectric layer 203, and the source metal layer integrates the source metal contact layer 301, the source first metal layer 302 and the source second metal layer 303 from bottom to top. In the cell expansion area 401, the construction of the source signal path depends on the precise connection between the source second metal layer 303, the source first metal layer 302, the source metal contact layer 301 and the cell area 102. As a key link in signal transmission, the source second metal layer 303 is closely connected to the underlying source first metal layer 302, and then forms a direct and efficient electrical connection with the source region in the cell area 102 through the source metal contact layer 301. The construction of this path ensures that the source signal can be quickly and stably transmitted to the entire cell expansion area 401, providing a solid guarantee for the efficient operation of SiC MOSFET devices.

[0028] See also Figure 2 , Figure 2It is a schematic diagram of the gate interconnection structure of a planar gate SiC MOSFET device with a cell expansion region provided in an embodiment of the present application. On the basis of the planar gate SiC MOSFET device with a cell expansion region, further, the dielectric layer, the source metal layer, the gate structure and the gate pad 304 work together to form a gate interconnection structure 402. Among them, the gate pad 304 is closely connected to the polysilicon gate 202 through the gate interconnection structure 402, constructing an efficient gate signal conductive path, ensuring the rapid transmission and precise control of the signal. At the same time, the gate pad 304 and the source metal layer are electrically isolated from the gate source signal through the dielectric layer, effectively blocking the potential signal interference path, and significantly improving the overall safety of the device. Specifically, the gate pad 304 is located at the top of the first interlayer dielectric layer 204, while the source metal contact layer 301 and the source first metal layer 302 are located below the first interlayer dielectric layer 204. This layout ensures effective isolation between the combined structure of the source metal contact layer 301 and the source first metal layer 302 and the gate pad 304. The first interlayer dielectric layer 204 and the second interlayer dielectric layer 203 jointly assume the electrical isolation between the gate signal and the source signal. At the same time, the gate pad 304 and the source second metal layer 303 are electrically isolated in the horizontal direction through the metal etching process, further improving the safety of the device. The gate structure formed by the close combination of the polysilicon gate 202 and the gate oxide layer 201, as a key part of the control signal, the polysilicon gate 202 is placed below the second interlayer dielectric layer 203. In order to ensure the smooth transmission of the gate signal, the gate pad 304 can penetrate through the second interlayer dielectric layer 203, the source metal contact layer 301, and the source first metal layer 302 through an appropriate through-hole or contact hole structure, and finally form an efficient and stable gate signal conductive path with the polysilicon gate 202. At the same time, it is worth noting that the combined structure formed by the source metal contact layer 301 and the source first metal layer 302 forms a reliable insulation circuit with the polysilicon gate 202 under the isolation of the second interlayer dielectric layer 203. This insulation design effectively prevents current leakage between the gate and the source, ensuring the stability and safety of the SiC MOSFET device.

[0029] This embodiment innovates on the basis of the traditional gate pad layout, and realizes the suspended design of the gate pad by introducing the cell expansion area. This innovative design suspends the gate pad directly above the cell area, rather than directly occupying the area of ​​the chip active area (including the gate structure, channel injection area, source and drain electrodes, and the cell structure area). Not only does it significantly optimize the space utilization of the chip, but it also enables the area that may have been occupied by the gate pad to be converted into an effective cell area, thereby greatly increasing the number of cells on the entire chip. As the number of cells increases, the number of parallel paths of the chip during the conduction process also increases, which directly leads to a significant reduction in the chip's specific on-resistance (Ron,sp). It can be understood that Ron,SP is one of the key parameters for measuring the performance of power semiconductor devices such as SiC MOSFET devices. Its reduction means that under the same operating conditions, the device can conduct current more effectively, reduce energy loss, and improve overall efficiency.

[0030] In a feasible embodiment, the semiconductor substrate is an important basic material for the manufacture of power semiconductor devices, and the purity and quality of the substrate are directly related to the performance and reliability of power semiconductor devices. The doped semiconductor substrate 100 is introduced with specific impurity elements through a doping process to change its electrical properties. For example, the doped semiconductor substrate 100 can be made of semiconductor materials such as silicon carbide (SiC), and an N-type or P-type substrate is formed by doping. The doped SiC substrate serves as the base layer of the power SiCMOSFET device, which provides a stable structural support for the entire device and serves as a connection basis for the electrical, thermal and mechanical properties of the device.

[0031] In a feasible embodiment, the doped semiconductor substrate 100 is the underlying structure of the SiC MOSFET device, and the doped semiconductor drift region 101 is located (grown on) the doped semiconductor substrate 100, forming a part of the device. In terms of function, the doped semiconductor substrate 100 provides a stable mechanical support and electrical foundation for the doped semiconductor drift region 101. The doped semiconductor drift region 101 utilizes its own doping characteristics and structural advantages to withstand high voltage while achieving effective current transmission. The two work together to ensure that the device can work stably in harsh environments such as high voltage and high current. It is understandable that in the manufacturing process of semiconductor devices, the formation of the doped semiconductor substrate 100 and the drift region is usually achieved through a series of complex process steps. These process steps include wafer cleaning, doping, heat treatment, thin film deposition, etc., which are intended to ensure that the quality and performance of the substrate and drift region meet the design requirements.

[0032] In a feasible embodiment, the doped semiconductor substrate 100 can be precisely controlled to be an N-type or P-type semiconductor substrate according to requirements. This choice will directly affect the characteristics of the doped semiconductor drift region 101, and the two present a close coupling relationship. Specifically, if the doped semiconductor substrate 100 is set as a P-type substrate, the drift region will also be doped into a P-type semiconductor drift region accordingly, and such a configuration promotes the formation of a P-type channel SiC MOSFET device. On the contrary, when the doped semiconductor substrate 100 is selected as an N-type substrate, the drift region will be adjusted to an N-type semiconductor drift region, which is conducive to the construction of an N-type channel SiC MOSFET device. This flexible doping control strategy provides a broad space for the design and application of SiC MOSFET devices. It should be noted that doping can be achieved in a variety of ways, such as ion implantation, thermal diffusion, etc. These methods can accurately introduce impurity atoms into the substrate and control their distribution and concentration.

[0033] In a feasible embodiment, the doping concentrations of the doped semiconductor substrate 100 and the doped semiconductor drift region 101 are different. The doping concentration of the doped semiconductor substrate 100 may be in the range of 1×10 20 cm -3 ~1×10 21 cm -3 The thickness range can be 80 μm to 180 μm. The doping concentration range of the doped semiconductor drift region 101 can be 1×10 16 cm -3 ~1×10 17 cm -3 , the thickness range can be 10 microns to 20 microns. It should be noted that the impurity concentration in the substrate has an important influence on the performance of the device. Too high an impurity concentration may lead to increased carrier scattering, thereby reducing mobility and conductivity; while too low an impurity concentration may not provide enough carriers, affecting the conduction ability of the device. The embodiments of the present application do not limit the selected doping concentration range and thickness range, and the specific doping concentration and thickness can be selected according to actual needs.

[0034] In a feasible embodiment, the preparation materials of the source first metal layer 302 and the source second metal layer 303 can be selected from metals with good conductivity and stability such as gold (Au), silver (Ag), aluminum (Al) or their alloys. These metal layers can be accurately formed by advanced thin film deposition techniques, such as the sputtering deposition method in physical vapor deposition (PVD), or chemical vapor deposition (CVD) technology. In the PVD sputtering deposition process, high-energy particles bombard the metal target material, causing metal atoms or molecules to be sputtered out and deposited on the substrate to form a dense metal film. CVD chemical deposition generates the desired metal film on the surface of the substrate through chemical reactions. This method can accurately control the composition, structure and thickness of the film.

[0035] In a feasible embodiment, the main function of the dielectric layer (i.e., the first interlayer dielectric layer 204 and the second interlayer dielectric layer 203) is to provide electrical isolation between different metal layers or semiconductor regions to ensure the normal operation of the device. In terms of material selection, the dielectric layer can adopt a variety of dielectric materials with high insulation performance, such as silicon dioxide, silicon nitride or high-K dielectric. Specifically, silicon dioxide has excellent insulation properties, good stability and compatibility with semiconductor processes; silicon nitride not only has excellent insulation properties, but also has high hardness and wear resistance, which can protect the underlying semiconductor structure from physical damage to a certain extent. At the same time, silicon nitride can also act as a barrier layer under specific process conditions to prevent impurity diffusion and adverse reactions during metal interconnection; high-K dielectric materials have relatively high dielectric constants, which can maintain or even improve the performance of the device while reducing the power consumption of the device.

[0036] In addition, the embodiment of the present application provides a method for preparing a planar gate SiC MOSFET device with a cell expansion region, which can be applied to the planar gate SiC MOSFET device with a cell expansion region as described above. Figure 3 As shown, the preparation method includes but is not limited to steps 310 to 340.

[0037] Step 310: obtaining a semiconductor material, and performing a doping process on the semiconductor material according to a first preset doping concentration to obtain a doped semiconductor substrate;

[0038] Step 320: performing an epitaxial growth process on the doped semiconductor substrate according to a second preset doping concentration to form a doped semiconductor drift region on the doped semiconductor substrate;

[0039] Step 330: performing doping and high-temperature annealing on the doped semiconductor drift region to form a cell region, and forming a cell extension region in the cell region, and forming a gate pad suspended above the cell extension region;

[0040] Step 340: Based on the doped semiconductor substrate, the doped semiconductor drift region, the cell extension region and the gate pad, a planar gate SiC MOSFET device with a cell extension region is obtained.

[0041] In a feasible embodiment, the semiconductor material includes a variety of compound semiconductors, such as gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), etc. For different compound semiconductors, the execution method of step 310 is also different. As a compound semiconductor, SiC has many superior physical properties, such as high band gap, high conductivity, high thermal conductivity, etc. Exemplarily, when the semiconductor material is SiC, when the SiC (semiconductor material) is doped according to the first preset doping concentration, the dopant ions can be implanted into the substrate by ion implantation technology. In addition, the dopant can be directly introduced during the growth of SiC, and the doping can be achieved by growth techniques such as physical vapor transport (PVT) method or chemical vapor deposition (CVD) method. In this process, the desired doping concentration (i.e., the first preset doping concentration) can be achieved by controlling the concentration and distribution of the dopant.

[0042] In a feasible embodiment, when the semiconductor material is doped, a specific type of impurity (such as boron B for p-type doping and phosphorus P for n-type doping) can be injected into the semiconductor material at a certain concentration according to the needs of device design. This process can be achieved through ion implantation, diffusion and other processes, and the purpose is to change the conductivity type (p-type or n-type) and conductivity of the semiconductor material.

[0043] In a feasible embodiment, the first preset doping concentration may be 1×10 20 cm -3 ~1×10 21 cm -3 That is, the concentration of the doped semiconductor substrate prepared according to the first preset doping concentration is 1×10 20 cm -3 ~1×10 21 cm -3 In addition, the thickness of the doped semiconductor substrate can be 80 microns to 180 microns to meet the requirements of substrate performance and structural strength in different application scenarios.

[0044] In a feasible embodiment, in step 320, a new layer of semiconductor material may be grown on the doped semiconductor substrate in an epitaxial furnace using methods such as chemical vapor deposition (CVD) or molecular beam epitaxy (MBE). This layer of material has the same crystal structure and lattice constant as the substrate, but the doping concentration (i.e., the second preset doping concentration) may be different to form the desired drift region. The drift region is the main area in the MOSFET that withstands high voltage.

[0045] In a feasible embodiment, the second preset doping concentration may be 1×10 16 cm -3 ~1×10 17 cm -3 The thickness of the doped semiconductor drift region may range from 10 microns to 20 microns.

[0046] In a feasible embodiment, in step 330, in the process of doping and high-temperature annealing the doped semiconductor drift region to form the cell region, specific elements can be implanted into the doped semiconductor drift region, including multiple P-type and N-type ion implantations, followed by high-temperature annealing. This treatment method not only ensures the effective diffusion and activation of elements in semiconductor materials, but also achieves fine control of the distribution of conductivity types inside the device. Ultimately, through this series of process steps, a cell region with a clear channel structure is constructed, laying a solid foundation for performance optimization and function realization of semiconductor devices.

[0047] In a feasible embodiment, for P-type ion implantation, a trivalent element such as boron (B) or aluminum (Al) can be selected as a P-type dopant, and then an ion implanter is used to accelerate the P-type ions at high energy and implant them into a specified depth of the semiconductor drift region. For N-type ion implantation, a pentavalent element such as phosphorus (P) or arsenic (As) can be selected as an N-type dopant. Similar to P-type ion implantation, N-type ions are also implanted into different locations of the drift region or different depths of the same location to form a desired doping distribution. After ion implantation and annealing, the P-type ions and N-type ions in the semiconductor drift region will form a specific doping distribution, such as an effective cell region with a channel structure.

[0048] In a feasible embodiment, annealing is performed after ion implantation to make the implanted ions become effective doping atoms, repair lattice damage that may be caused during the ion implantation process, and promote diffusion of doping atoms in the semiconductor to form a desired doping distribution.

[0049] In a feasible embodiment, the specific process of forming the cell expansion area within the cell area in step 330 may include but is not limited to steps 410 to 430.

[0050] Step 410: performing doping and thermal annealing on the cell region to form a gate oxide layer on the cell region;

[0051] Step 420: performing epitaxial growth and etching on the gate oxide layer according to a third preset doping concentration to obtain a polysilicon gate;

[0052] Step 430: depositing a first dielectric layer, a source metal contact layer, a source first metal layer, a second interlayer dielectric layer and a source second metal layer on the polysilicon gate to form a cell expansion region.

[0053] In a feasible embodiment, step 410 is intended to form a high-quality silicon dioxide film, namely, a gate oxide layer, on the cell region of the doped semiconductor substrate. The oxide layer can be used as an insulating layer between the gate and the substrate to be formed subsequently.

[0054] In a feasible embodiment, before the cell region is subjected to thermal oxidation treatment, the cell region may be thoroughly cleaned and pretreated to remove surface pollutants and impurities to ensure that the oxidation reaction can be carried out on a clean silicon surface; the pretreated cell region is then placed in an oxidation furnace and exposed to an oxidizing environment (such as oxygen or water vapor) at a high temperature (usually between hundreds of degrees Celsius and thousands of degrees Celsius). The oxidant reacts chemically with the silicon surface to form a dense silicon dioxide film.

[0055] In a feasible embodiment, by accurately controlling process parameters such as oxidation temperature, oxidation time, and gas composition in the oxidation environment, the thickness of the gate oxide layer can be accurately controlled. According to design requirements, the thickness of the gate oxide layer is generally from a few nanometers to tens of nanometers. Exemplarily, the thickness of the gate oxide layer can be 30 nanometers to 50 nanometers.

[0056] In a feasible embodiment, step 420 is intended to form a layer of polysilicon (poly-Si) on the gate oxide layer as a gate material to form a gate structure of a planar gate SiC MOSFET device.

[0057] In a feasible embodiment, the gate oxide layer may be processed by deposition, photolithography and dry etching processes to form a polysilicon gate on the upper surface of the gate oxide layer.

[0058] In a feasible embodiment, the thickness of the formed polysilicon gate may be 0.1 micrometer to 0.5 micrometer, which can ensure that the gate electrode has sufficient conductivity and avoid excessive parasitic capacitance and power consumption.

[0059] In a feasible embodiment, the third preset doping concentration may be 1×10 19 cm -3 ~1×10 20 cm -3 The doping elements may be boron (B), phosphorus (P), etc., wherein boron is used to form a P-type gate electrode and phosphorus is used to form an N-type gate electrode.

[0060] In a feasible embodiment, the polysilicon film is doped according to the third preset doping concentration, which can be achieved through ion implantation, diffusion and other processes to ensure that the polysilicon gate has the required doping concentration and conductive properties.

[0061] In a feasible embodiment, the process of constructing the cell expansion area and suspending the gate pad above it starts from depositing the second dielectric layer, the source metal contact layer, the source first metal layer, the first interlayer dielectric layer layer by layer on the polysilicon gate through a series of steps, and finally covering it with the source second metal layer. In particular, during the formation of the source second metal layer, the gate pad suspended above the cell expansion area is also constructed synchronously. Specifically, first, the second dielectric layer is uniformly deposited on the surface of the polysilicon gate; then, the source first metal layer is deposited in sequence to enhance the conductivity, and the source second metal layer is continuously deposited to expand the connection area; then, the first interlayer dielectric layer is covered to provide the necessary insulation and support for the entire structure; finally, by using high-precision deposition, photolithography and etching technology, the formation of the source second metal is completed in the same metal layer, and the gate pad is accurately shaped, achieving dual optimization of structure and function.

[0062] It is worth noting that although the gate pad and the source second metal layer share the same layer of metal material during the deposition stage, the subsequent metal etching process can separate them from each other with extremely high precision to achieve electrical isolation, ensuring that their independent functional areas do not interfere with each other.

[0063] The following is a specific example to illustrate the process of constructing the cell expansion area and the gate pad.

[0064] First, through the deposition process, using materials such as tetraethoxysilane (TEOS) or boron phospho-silicate glass (BPSG), a second interlayer dielectric layer is formed in the designated area, and its thickness is precisely controlled between 1 micron and 2 microns to ensure good insulation and compatibility between subsequent layers. Subsequently, dry etching and sputtering techniques are used to accurately make source metal contact layers on the second interlayer dielectric layer. These contact layers serve as bridges to closely connect the cell area with the polysilicon gate. The openings of the contact layer are finely designed, with a size between 0.5 microns and 1 micron, and are filled with an optimized combination of materials such as nickel (Ni), titanium (Ti), tungsten (W) or titanium nitride (TIN). These materials not only show excellent filling performance, but also ensure the formation of ohmic contact, thereby effectively reducing contact resistance and improving device performance. Next, a layer of metal Al with a thickness of 2 to 3 microns is deposited as the first metal layer of the source, providing a solid foundation for subsequent electrical connections. Afterwards, through fine photolithography and dry etching steps, the connection between the source metal and the gate metal is precisely disconnected, achieving the first electrical isolation and ensuring the independence and stability of each part of the circuit. When constructing the first interlayer dielectric layer, the same method of combining deposition, photolithography and etching processes is used. TEOS or BPSG can continue to be used in material selection, and the thickness is controlled at 2 to 3 microns to provide sufficient support and insulation effects, laying a solid foundation for the subsequent installation of the floating gate pad. Through a series of high-precision deposition, photolithography and etching processes, the gate pad and the second metal layer of the source are successfully formed, and the photolithography and dry etching technology are used to disconnect the connection between the source metal and the gate metal for the second time, completely achieving electrical isolation, and laying a perfect structural foundation for the final completion and performance testing of the planar gate SiCMOSFET device with a cell expansion area.

[0065] See also Figure 4 , Figure 4 This is a schematic diagram of a process for preparing a planar gate SiC MOSFET device with a cell extension region provided by a specific example of the present application. The process includes steps S1 to S10, and these steps are described in detail below.

[0066] Step S1: According to 1×10 20 cm -3 ~1×10 21 cm -3 The SiC is doped with a doping concentration of 100 μm to obtain a doped SiC substrate with a thickness of 80 μm to 180 μm;

[0067] Step S2: After an epitaxial process, a doping concentration of 1×10 16 cm -3 ~1×10 17 cm -3, a low doping concentration drift region having a thickness of 10 microns to 20 microns;

[0068] Step S3: forming a cell region with a channel structure through multiple P-type and N-ion implantation and a high-temperature annealing activation process;

[0069] Step S4: forming a gate oxide layer with a thickness of 30 nanometers to 50 nanometers on the upper surface of the cell region through a thermal oxidation process;

[0070] Step S5: After deposition, photolithography and dry etching processes, a doping concentration of 1×10 19 cm -3 ~1×10 20 cm -3 , a polysilicon gate having a thickness of 0.1 micron to 0.5 micron;

[0071] Step S6: forming a second interlayer dielectric layer with a thickness of 1 μm to 2 μm through a deposition process;

[0072] Step S7: dry etching and sputtering are performed to form a source metal contact layer connecting the polysilicon gate and the cell region, wherein the size of the contact layer opening is between 0.5 microns and 1 micron, and the filling material can be a combination of Ni, Ti, W or TIN and other materials.

[0073] Step S8: Select aluminum material, and form a source first metal layer with a thickness of 2 to 3 microns through deposition, and then use one-time photolithography and dry etching to disconnect the connection between the source metal and the gate metal to achieve the first electrical isolation:

[0074] Step S9: forming a first interlayer dielectric layer with a thickness of 2 microns to 3 microns through deposition, photolithography and etching processes;

[0075] Step S10: Form a gate pad and a second source metal layer through deposition, photolithography and etching processes, and use one photolithography and dry etching to disconnect the source metal from the gate metal to achieve a second electrical isolation.

[0076] The entire process of this specific example covers the process from the preparation of the SiC substrate to the formation of the final structure of the planar gate SiCMOSFET device with a cell extension region. Each step precisely controls the composition, thickness and position of the material to ensure the performance and reliability of the SiCMOSFET device.

[0077] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A planar gate SiC MOSFET device with a cell extension region, characterized in that: include: From bottom to top, there are a doped semiconductor substrate, a doped semiconductor drift region, a cell expansion region and a gate pad; the cell expansion region is located below the gate pad, the cell expansion region includes a cell region, a gate structure, a dielectric layer, and a source metal layer, the gate structure includes a polysilicon gate, and the cell expansion region forms a source signal path through the source metal layer; the gate structure, the dielectric layer, the source metal layer and the gate pad form a gate interconnection structure, the gate pad forms a gate signal conductive path with the polysilicon gate through the gate interconnection structure, and forms a gate-source signal insulation with the source metal layer through the dielectric layer.

2. A planar gate SiC MOSFET device with a cell extension region according to claim 1, characterized in that: The source metal layer includes a source metal contact layer and a source first metal layer from bottom to top, and the dielectric layer includes a first interlayer dielectric layer; the source metal contact layer and the source first metal layer are located at the lower end of the first interlayer dielectric layer; the gate pad is located at the upper end of the first interlayer dielectric layer.

3. A planar gate SiC MOSFET device with a cell extension region according to claim 2, characterized in that: The source metal layer includes a source second metal layer, the source second metal layer is located on the upper end of the source first metal layer, and the first interlayer dielectric layer is located between the source second metal layer and the source first metal layer.

4. A planar gate SiC MOSFET device with a cell extension region according to claim 2, characterized in that: The gate structure includes a gate oxide layer, and the polysilicon gate is located at the upper end of the gate oxide layer; the dielectric layer includes a second interlayer dielectric layer, and the polysilicon gate is located at the lower end of the second interlayer dielectric layer; the combined structure composed of the source metal contact layer and the source first metal layer forms an insulating circuit with the polysilicon gate through the second interlayer dielectric layer.

5. A planar gate SiC MOSFET device with a cell extension region according to claim 3, characterized in that: The source metal layer includes the source metal contact layer, the source first metal layer and the source second metal layer; The cell expansion region forms a source signal path through the source metal layer, including: the cell expansion region forms a source signal path through the source first metal layer and the source second metal layer and the source metal contact layer.

6. A planar gate SiC MOSFET device with a cell extension region according to claim 5, characterized in that: The gate pad forms a gate signal conductive path with the polysilicon gate through the gate interconnection structure, including: the gate pad is interconnected with the gate polysilicon layer through the source metal contact layer and the source first metal layer to form a gate signal conductive path.

7. A planar gate SiC MOSFET device with a cell extension region according to claim 1, characterized in that: The doped semiconductor substrate is a P-type substrate or an N-type substrate; when the doped semiconductor substrate is a P-type substrate, the doped semiconductor drift region is a P-type semiconductor drift region; when the doped semiconductor substrate is an N-type substrate, the doped semiconductor drift region is an N-type semiconductor drift region.

8. A planar gate SiC MOSFET device with a cell extension region according to claim 3, characterized in that: The material for preparing the source first metal layer and the source second metal layer includes at least one of gold, silver, aluminum and aluminum alloy; the material for preparing the dielectric layer includes at least one of silicon dioxide, silicon nitride and high-K dielectric.

9. A method for preparing a planar gate SiC MOSFET device with a cell expansion region, characterized in that: The planar gate SiC MOSFET device with a cell extension region as claimed in any one of claims 1 to 8 comprises: Obtaining a semiconductor material, and processing the semiconductor material according to a first preset doping concentration to obtain a doped semiconductor substrate; Performing an epitaxial growth process on the doped semiconductor substrate according to a second preset doping concentration to form a doped semiconductor drift region on the doped semiconductor substrate; Performing doping and high-temperature annealing on the doped semiconductor drift region to form a cell region, forming a cell extension region in the cell region, and forming a gate pad suspended above the cell extension region; Based on the doped semiconductor substrate, the doped semiconductor drift region, the cell extension region and the gate pad, a planar gate SiC MOSFET device with a cell extension region is obtained.

10. The method for preparing a planar gate SiC MOSFET device with a cell extension region according to claim 9, characterized in that: The forming of a cell expansion region within the cell region includes: performing doping and thermal annealing treatment on the cell region to form a gate oxide layer on the cell region; performing epitaxial growth and etching treatment on the gate oxide layer according to a third preset doping concentration to obtain a polysilicon gate; and depositing a first dielectric layer, a source metal contact layer, a source first metal layer, a second interlayer dielectric layer and a source second metal layer on the polysilicon gate to form a cell expansion region.

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