Power device and forming method thereof
By designing the surrounding structure of the well region and the trench region in the SiC-based power device, the reliability problem at the bottom corner of the gate oxide layer is solved, the voltage withstandness and reliability of the device are improved, and the on-resistance is reduced.
Patent Information
- Application Number
- CN202411201114.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-29
- Publication Date
- 2024-12-13
AI Technical Summary
The reliability of the gate oxide layer of SiC-based power devices is poor, and breakdown is prone to problems, mainly due to premature breakdown and long-term reliability problems caused by high electric field stress.
Design a power device that includes a gate region, a gate oxide layer and a trench region, the well region surrounds the bottom angle of the trench region, forms a surround structure to shield the high electric field, and reduces conduction by adjusting the doping concentration of the well region resistance.
The surrounding structures of the well region and the trench region are depleted from each other during the reverse withstand voltage, forming a space charge region, shielding the influence of the high electric field on the gate oxide layer, improving the reliability of the device, and reducing the on-resistance.
Smart Images
Figure CN119133241A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a power device and a method for forming the same. Background Art
[0002] As a new type of power switching device, SiC-based power devices can achieve faster switching speeds, higher device efficiency and lower on-resistance in more harsh environments such as high temperature and high pressure compared to traditional Si-based power devices. They are showing great potential in the power market, especially in the fields of photovoltaic power generation, new energy vehicles, and high-end power supplies, and their market share is increasing. A key factor affecting the performance of SiC power devices is the specific on-resistance (on-resistance per unit chip area), which includes multiple distributed resistances in series, of which the channel resistance accounts for a large proportion, especially in low-voltage devices. Since the gate oxide layer quality of SiC-based devices is slightly worse than that of Si-based devices, and the electron mobility of the inversion layer is not high, the planar MOSFET of the prior art generally uses a short channel to reduce the channel resistance. However, this method has certain limitations and risks, and since the planar MOSFET has a typical JFET region, its resistance accounts for a high proportion, making the final specific on-resistance also high.
[0003] Since SiC materials have the characteristics of crystal polymorphism and anisotropy, the electron mobility between crystal forms is in the {0001} plane (μ⊥) and the c-axis direction. <0001> The μ∥ and μ⊥ of 4H-SiC are about 1200 and 1000 cm-1, respectively. 2 / V·s, so the trench structure can alleviate the problem of low inversion electron mobility of the MOS structure to a certain extent. By placing the channel in the c-axis direction, on the one hand, the cell size can be reduced and the channel density can be increased. On the other hand, since the JFET area is eliminated, the overall on-resistance can be further reduced. However, according to Gauss's theorem, the electric field strength on the surface of the gate oxide layer in the SiC-based MOSFET power device is about 2.5 times the electric field strength on the corresponding SiC surface. Since the bottom corner electric field of the trench region is relatively more concentrated when reverse biased, the gate oxide layer of the trench-type power device will be subjected to extremely large electric field stress at the bottom corner, causing premature breakdown and long-term reliability problems. Summary of the invention
[0004] Therefore, the present invention provides a power device to solve the problem that the bottom corner of the gate oxide layer of the trench-type SiC-based power device has poor reliability and is prone to breakdown.
[0005] The present invention provides a power device, comprising: a gate region; the gate region is located in a well region; a gate oxide layer; the gate oxide layer completely surrounds the gate region; a groove region; the groove region surrounds at least part of the bottom and part of the side of the gate oxide layer; the top and side of the groove region are surrounded by the well region, and the well region extends from the side bottom corner edge of the groove region to the center of the bottom surface of the groove region to form a surrounding structure for the bottom corner of the groove region; the well region; the well region surrounds the side and part of the bottom of the groove region, and together with the groove region forms a surrounding structure for the bottom corner of the gate oxide layer; the gate oxide layer separates the gate region from the groove region and the well region.
[0006] Optionally, the power device of the present invention further comprises: a substrate layer; the substrate layer is a first conductivity type highly doped region; an epitaxial layer; the epitaxial layer is located on the surface of the substrate layer and is a first conductivity type low doped region; the well region is partially located in the epitaxial layer and partially located on the surface of the epitaxial layer; the well region is a second conductivity type low doped region; the well region surrounds the bottom of the portion of the trench region that is higher than the epitaxial layer; a source region; the source region is located on the surface of the well region and on the side of the gate oxide layer; the source region is a first conductivity type heavily doped region; The gate oxide layer also separates the gate region from the source region; an ohmic contact region; the ohmic contact region is located on the surface of the well region and on the side of the source region; the ohmic contact region is a heavily doped region of the second conductivity type; a first electrode is located on the surface of the substrate layer facing away from the epitaxial layer; a second electrode is located on the surface of the gate oxide layer facing away from the substrate layer and extends laterally to cover the surface of the source region facing away from the substrate layer and the surface of the ohmic contact region facing away from the substrate layer; the trench region is a first conductivity type region.
[0007] Optionally, the power device of the present invention further includes: a substrate layer; the substrate layer is a highly doped region of the first conductivity type; an epitaxial layer; the epitaxial layer is located on the surface of the substrate layer and is a low doped region of the first conductivity type; the well region is located on the surface of the epitaxial layer; the well region is a low doped region of the second conductivity type; a source region; the source region is located on the surface of the well region and on the side of the gate oxide layer; the source region is a heavily doped region of the first conductivity type; the gate oxide layer also separates the gate region from the source region; an ohmic contact region; the ohmic contact region is located on the surface of the well region and on the side of the source region; the ohmic contact region is a heavily doped region of the second conductivity type; a first electrode is located on the side surface of the substrate layer facing away from the epitaxial layer; a second electrode is located on the side surface of the gate oxide layer facing away from the substrate layer and extends laterally to cover the side surface of the source region facing away from the substrate layer and the side surface of the ohmic contact region facing away from the substrate layer; the trench region is a region of the first conductivity type.
[0008] Optionally, the side end of the well region extending toward the center of the bottom surface of the trench region extends from the vertical plane where the gate oxide layer on the same side is located to the center of the bottom surface of the trench region by ±0.8 μm.
[0009] Optionally, the trench region completely covers the bottom surface of the gate oxide layer; or, the trench region extends from a side bottom corner edge of one side of the gate oxide layer to the opposite side.
[0010] Optionally, the power device of the present invention further comprises: a spacer region, located at the bottom surface of the gate oxide layer, spacing the bottom surface of the gate oxide layer from the trench region; the spacer region and the trench region are regions of different conductivity types.
[0011] Optionally, the ohmic contact region further extends to cover a side portion of the well region; and the second electrode further extends to cover a side portion of the ohmic contact region on a side portion of the well region.
[0012] The present invention also provides a method for forming a power device provided by the present invention, comprising the following steps: forming a well region; forming a groove region in the well region; forming a gate region and a gate oxide layer in the groove region; the gate oxide layer completely surrounds the gate region, separating the gate region from the well region; the groove region surrounds at least part of the bottom and part of the side of the gate oxide layer; the top and side of the groove region are surrounded by the well region, and the well region extends from the side bottom corner edge of the groove region to the center of the bottom surface of the groove region, forming a surrounding structure for the bottom corner of the groove region.
[0013] Optionally, the method for forming a power device of the present invention comprises the following steps: providing a semiconductor substrate as a substrate layer; forming an epitaxial layer on a surface of one side of the semiconductor substrate; forming a first initial well region on a side of the epitaxial layer facing away from the substrate layer; forming an initial source region on a side of the first initial well region facing away from the substrate layer; forming an ohmic contact region on a side of the initial source region; forming a first hard mask layer, wherein the first hard mask layer covers a surface of the ohmic contact region and a portion of a surface of the initial source region; performing ion implantation on the epitaxial layer using the first hard mask layer as a mask, and implanting ions on the epitaxial layer; forming an ohmic contact region on a side of ... The second initial well region is formed in the first well region; the upper surface of the second initial well region is connected to the lower surface of the first initial well region to form an initial well region together; the first sidewall is formed by depositing and etching on the inner side of the first hard mask layer; the first initial well region is ion-implanted with the first hard mask layer and the first sidewall as a mask to form a first initial trench region in the second initial well region; the second sidewall is formed by depositing and etching on the inner side of the first sidewall; the first initial trench region is exposed by ion-implanting with the first hard mask layer, the first sidewall and the second sidewall as a mask, A second initial trench region is formed at the bottom of an initial trench region; the bottom of the second initial trench region contacts the epitaxial layer; the bottom of the first initial trench region contacts the second initial well region remaining at the side of the second initial trench region; using the first hard mask layer, the first sidewall and the second sidewall as masks, a groove is etched, the groove passes through the initial source region, the first initial well region, and goes deep into the first initial trench region; the remaining initial source region constitutes a source region; the remaining first initial trench region and the second initial trench region constitute the trench region; the remaining first initial well region and the remaining The remaining second initial well region constitutes the well region; the well region forms a surrounding structure for the bottom corner of the trench region; the gate region and the gate oxide layer are formed in the notch; the gate oxide layer completely surrounds the gate region, and completely isolates the gate region from the trench region, the source region, and the well region; a first electrode is formed on the surface of the substrate layer facing away from the epitaxial layer; a second electrode is formed on the surface of the gate oxide layer facing away from the substrate layer, and the second electrode extends laterally to cover the surface of the source region facing away from the substrate layer and the surface of the ohmic contact region facing away from the substrate layer.
[0014] Optionally, the method for forming a power device of the present invention comprises the following steps: providing a semiconductor substrate as a substrate layer; forming an epitaxial layer on a surface of one side of the semiconductor substrate; forming a first initial well region on a side of the epitaxial layer facing away from the substrate layer; forming an initial source region on a side of the first initial well region facing away from the substrate layer; forming an ohmic contact region on a side of the initial source region; forming a first hard mask layer, the first hard mask layer covering the surface of the ohmic contact region and the surface of the initial source region; etching a groove, the groove penetrating the first hard mask layer, the initial source region, and the first hard mask layer. The first hard mask layer is used as a mask to implant ions into the bottom and sidewalls of the notch of the epitaxial layer, and form an initial trench region in the epitaxial layer; the first hard mask layer is removed; a second hard mask layer is formed, and the second hard mask layer covers the surface of the ohmic contact region, the surface of the source region, and the bottom of the notch; the second hard mask layer is etched to form a third hard mask layer located on the surface of the ohmic contact region and the surface of the source region, and a third hard mask layer located on the surface of the notch a fourth hard mask layer in the middle; a gap exists between the third hard mask layer and the opening edge of the notch; a gap exists between the fourth hard mask layer and the sidewall of the notch; using the third hard mask layer and the fourth hard mask layer as masks, ions are implanted into the epitaxial layer and the initial trench region to form a second well region surrounding the side of the initial trench region and at least part of the bottom of the initial trench region; the remaining initial trench region constitutes the trench region; the remaining first initial well region constitutes the first well region, and the second well region together constitutes the well region, and the well region is for the trench region The bottom corner of the substrate layer forms an enclosing structure; the third mask layer and the fourth mask layer are removed; the gate region and the gate oxide layer are formed in the notch; the gate oxide layer completely surrounds the gate region, and the gate region is completely isolated from the trench region, the source region, and the well region; a first electrode is formed on the surface of the substrate layer facing away from the epitaxial layer; a second electrode is formed on the surface of the gate oxide layer facing away from the substrate layer, and the second electrode extends laterally to cover the surface of the source region facing away from the substrate layer and the surface of the ohmic contact region facing away from the substrate layer.
[0015] The technical solution of the present invention has the following advantages:
[0016] The power device provided by the present invention forms a surrounding structure for the bottom corner of the gate oxide layer by the well region and the trench region, which can deplete each other during reverse withstand voltage to form a space charge region, thereby shielding the influence of the high electric field on the gate oxide layer and improving the reliability of the device. In addition, the on-resistance of the current path in the surrounding area can be reduced by adjusting the doping concentration of the well region surrounding the trench region, thereby obtaining a lower on-resistance of the device.
[0017] The method for forming the power device provided by the present invention can form the power device provided by the present invention. By forming a surrounding structure for the bottom corner of the gate oxide layer by the well region and the trench region, they can be mutually depleted during reverse withstand voltage to form a space charge region, thereby shielding the influence of the high electric field on the gate oxide layer and improving the reliability of the device. In addition, by adjusting the doping concentration of the well region surrounding the trench region, the on-resistance of the current path in the surrounding area can be reduced, thereby obtaining a lower on-resistance of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0019] Figure 1-Figure 4 A schematic diagram of the structure of a power device according to an embodiment of the present invention;
[0020] Figure 5a-5j A schematic diagram of the states of various steps in a process of forming a power device according to an embodiment of the present invention;
[0021] Figure 6a-6h The figure is a schematic diagram of the states of various steps in the process of forming a power device according to another embodiment of the present invention.
[0022] Description of reference numerals:
[0023] 1-substrate layer; 2-epitaxial layer; 3-well region; 31-first well region; 31'-first initial well region; 32-second well region; 32'-second initial well region; 4-trench region; 4'-initial trench region; 41-first trench region; 41'-first initial trench region; 42-second trench region; 42'-second initial trench region; 5-gate region; 6-gate oxide layer; 7-source region; 7'-initial source region; 8-ohmic contact region; 9-first electrode; 10-second electrode. DETAILED DESCRIPTION
[0024] In order to solve the problem that the bottom corner of the gate oxide layer of a trench-type SiC-based power device has poor reliability and is prone to breakdown, the present invention provides a power device and a method for forming the same.
[0025] The present invention provides a power device, comprising: a gate region; the gate region is located in a well region; a gate oxide layer; the gate oxide layer completely surrounds the gate region; a groove region; the groove region surrounds at least part of the bottom and part of the side of the gate oxide layer; the top and side of the groove region are surrounded by the well region, and the well region extends from the side bottom corner edge of the groove region to the center of the bottom surface of the groove region to form a surrounding structure for the bottom corner of the groove region; the well region; the well region surrounds the side of the groove region and the groove region is higher than the bottom of the epitaxial layer, and together with the groove region, forms a surrounding structure for the bottom corner of the gate oxide layer; the gate oxide layer separates the gate region from the groove region and the well region.
[0026] The present invention also provides a method for forming a power device provided by the present invention, comprising the following steps: forming a well region; forming a groove region in the well region; forming a gate region and a gate oxide layer in the groove region; the gate oxide layer completely surrounds the gate region; the groove region surrounds at least part of the bottom and part of the side of the gate oxide layer; the top and side of the groove region are surrounded by the well region, and the well region extends from the side bottom corner edge of the groove region to the center of the bottom surface of the groove region to form a surrounding structure for the bottom corner of the groove region; the well region and the groove region jointly form a surrounding structure for the bottom corner of the gate oxide layer; the gate oxide layer separates the gate region from the groove region and the well region.
[0027] The technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. In the description of the present invention, it should be noted that the terms "first", "second" and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.
[0028] Example 1
[0029] refer to Figure 1-Figure 4 , this embodiment provides a power device, including:
[0030] The gate region 5 is located in the well region 3 (the well region 3 in the figure includes two parts; due to process reasons, the two parts are formed successively, and there is actually no obvious interlayer spacing, and it is an integral area); in this embodiment, the gate region is a polysilicon layer.
[0031] Gate oxide layer 6; the gate oxide layer 6 completely surrounds the gate region 5; the gate oxide layer is a SiO2 layer.
[0032] A trench region 4; the trench region 4 surrounds at least part of the bottom and part of the side of the gate oxide layer 6; the top and side of the trench region 4 are surrounded by the well region 3, and the well region 3 extends from the side bottom corner edge of the trench region 4 to the center of the bottom surface of the trench region 4, forming a surrounding structure for the bottom corner of the trench region 4.
[0033] Well region 3; the well region 3 surrounds the side and part of the bottom of the trench region 4, and together with the trench region 4 forms a surrounding structure for the gate oxide layer 6.
[0034] The gate oxide layer 6 separates the gate region 5 from the trench region 4 and the well region 3 .
[0035] The power device provided in this embodiment forms a surrounding structure for the bottom corner of the gate oxide layer 6 by the well region 3 and the trench region 4, which can deplete each other during reverse withstand voltage to form a space charge region, thereby shielding the influence of the high electric field on the gate oxide layer 6 and improving the reliability of the device. In addition, by adjusting the doping concentration of the well region 3 surrounding the trench region 4, the on-resistance of the current path in the surrounding area can be reduced, and a lower device on-resistance can be obtained. In addition, by fully wrapping the trench structure with the well region 3, a part of the gate area overlapping with the drain is blocked, the overlapping area of the gate and the drain can be reduced, the gate-drain capacitance is further reduced, and the switching loss can be reduced.
[0036] Furthermore, the side end of the well region 3 extending toward the center of the bottom surface of the trench region 4 extends from the vertical plane where the gate oxide layer on the same side is located to the center of the bottom surface of the trench region by ±0.8 μm, that is, from the plane where the well region 3 is flush with the gate oxide layer 6, to the center of the bottom surface of the trench region by ±0.8 μm. By fully wrapping the trench structure with the well region 3 and extending toward the center, a part of the drain electrode can be shielded, that is, Figure 1 9, the area of the overlapping gate region 5 reduces the overlapping area of the gate and the drain, further reduces the gate-drain capacitance, and can reduce switching losses. More importantly, the two well regions are close to each other, and when reverse depletion occurs, the well region can pinch off the trench region earlier, reduce the electric field at the bottom of the gate oxide, and improve device reliability. However, if the extension distance is too large, it will affect the conduction path in the forward direction, and if it is too small, it will not be able to pinch off quickly during reverse withstand voltage, and the bottom corner protection capability of the gate oxide layer 6 will be weakened.
[0037] Specifically, refer to Figure 1-Figure 3 In this embodiment, the power device further includes:
[0038] Substrate layer 1; the substrate layer 1 is a first conductivity type highly doped region;
[0039] Epitaxial layer 2; the epitaxial layer 2 is located on the surface of the substrate layer 1 and is a low-doped region of the first conductivity type;
[0040] The well region 3 is partially located in the epitaxial layer 2 and partially located on the surface of the epitaxial layer 2; the well region 3 is a low-doped region of the second conductivity type; the well region 3 surrounds the bottom of the trench region 4 that is higher than the epitaxial layer 2;
[0041] A source region 7; the source region 7 is located on the surface of the well region 3 and on the side of the gate oxide layer 6; the source region 7 is a heavily doped region of the first conductivity type; the gate oxide layer 6 also separates the gate region 5 from the source region 7;
[0042] An ohmic contact region 8; the ohmic contact region 8 is located on the surface of the well region 3 and on the side of the source region 7; the ohmic contact region is a heavily doped region of the second conductivity type;
[0043] A first electrode 9, located on a surface of the substrate layer 1 facing away from the epitaxial layer 2, serving as a drain;
[0044] A second electrode 10 is located on a surface of the gate oxide layer 6 facing away from the substrate layer 1 and extends laterally to cover a surface of the source region 7 facing away from the substrate layer 1 and a surface of the ohmic contact region 8 facing away from the substrate layer 1;
[0045] The trench region 4 is a first conductivity type region.
[0046] The first conductivity type and the second conductivity type are opposite carrier conductivity types. In this embodiment, the first conductivity type is N-type carrier conductivity, and the second conductivity type is P-type carrier conductivity.
[0047] In some other embodiments, reference Figure 4 , power devices also include:
[0048] Substrate layer 1; the substrate layer 1 is a first conductivity type highly doped region;
[0049] Epitaxial layer 2; the epitaxial layer 2 is located on the surface of the substrate layer 1 and is a low-doped region of the first conductivity type; the well region 3 is located on the surface of the epitaxial layer 2; the well region 3 is a low-doped region of the second conductivity type;
[0050] A source region 7; the source region 7 is located on the surface of the well region 3 and on the side of the gate oxide layer 6; the source region 7 is a heavily doped region of the first conductivity type; the gate oxide layer 6 also separates the gate region 5 from the source region 7;
[0051] An ohmic contact region 8; the ohmic contact region 8 is located on the surface of the well region 3 and on the side of the source region 7; the ohmic contact region 8 is a heavily doped region of the second conductivity type;
[0052] A first electrode 9, located on a surface of the substrate layer 1 facing away from the epitaxial layer 2, serving as a drain;
[0053] A second electrode 10 is located on a surface of the gate oxide layer 6 facing away from the substrate layer 1, and extends laterally to cover a surface of the source region 7 facing away from the substrate layer 1 and a surface of the ohmic contact region 8 facing away from the substrate layer;
[0054] The trench region 4 is a first conductivity type region.
[0055] With the aforementioned Figure 1-Figure 3 The difference is that the well region 3 is entirely located on the surface of the epitaxial layer 2 rather than being partially located in the epitaxial layer 2 and partially located on the surface of the epitaxial layer 2 .
[0056] In some embodiments, the trench region 4 completely covers the bottom surface of the gate oxide layer 6 (eg Figure 1 Alternatively, the trench region 4 extends from the bottom corner of the side of the gate oxide layer 6 to the opposite side (as shown in Figure 3 shown). Figure 3 The structure shown can provide better protection for the corresponding bottom corners. Specifically, the corner of the gate oxide layer 6 on one side is in the P-type well region 3, which better reduces the electric field at the reverse withstand voltage and improves the reliability of the device.
[0057] refer to Figure 2 In some embodiments, the power device further includes: a spacer region 33, located on the bottom surface of the gate oxide layer 6, forming a spacer between the bottom surface of the gate oxide layer 6 and the trench region 4; the spacer region 33 and the trench region 4 are different conductivity type regions. Figure 2 The structure can better alleviate the electric field concentration at the bottom corner of the gate oxide layer 6.
[0058] refer to Figure 4 In some embodiments, the ohmic contact region 8 also extends to cover the side of the well region 3 ; the second electrode 10 also extends to cover the side of the ohmic contact region 8 on the side of the well region 3 .
[0059] Example 2
[0060] refer to Figure 5a-5j This embodiment provides a method for forming the power device of the above-mentioned embodiment 1, comprising the following steps:
[0061] forming a well region; forming a trench region in the well region;
[0062] A gate region and a gate oxide layer are formed in the trench region; the gate oxide layer completely surrounds the gate region; the trench region surrounds at least part of the bottom and part of the side of the gate oxide layer; the top and side of the trench region are surrounded by the well region, and the well region extends from the side bottom corner edge of the trench region to the center of the bottom surface of the trench region to form a surrounding structure for the bottom corner of the trench region; the well region and the trench region jointly form a surrounding structure for the bottom corner of the gate oxide layer; the gate oxide layer separates the gate region from the trench region and the well region.
[0063] The method for forming the power device provided by the present invention provided in this embodiment can form the power device provided by the present invention. By forming a surrounding structure for the bottom corner of the gate oxide layer by the well region and the trench region, they can be mutually depleted during reverse withstand voltage to form a space charge region, thereby shielding the influence of the high electric field on the gate oxide layer and improving the reliability of the device. In addition, by adjusting the doping concentration of the well region surrounding the trench region, the on-resistance of the current path in the surrounding area can be reduced, thereby obtaining a lower on-resistance of the device.
[0064] refer to Figure 5a-5j In a specific embodiment, the method for forming a power device of this embodiment includes the following steps:
[0065] refer to Figure 5a A semiconductor substrate is provided as a substrate layer 1; an epitaxial layer 2 is formed on one surface of the semiconductor substrate; in this embodiment, the semiconductor substrate is an N-type doped SiC substrate. The epitaxial layer 2 is formed by epitaxial growth and is an N-type doped layer.
[0066] refer to Figure 5b A first initial well region 31' is formed on the side of the epitaxial layer 2 facing away from the substrate layer 1. The first initial well region 31' is formed by ion implantation into the epitaxial layer 2. In this embodiment, P-type ions are implanted.
[0067] refer to Figure 5c , an initial source region 7' is formed on the side of the first initial well region 31' facing away from the substrate layer 1. The initial source region 7' is formed by ion implantation. In this embodiment, N-type ions are implanted.
[0068] refer to Figure 5d An ohmic contact region 8 is formed on the side of the initial source region 7'; the ohmic contact region 8 is formed by ion implantation. In this embodiment, P-type ions are implanted.
[0069] refer to Figure 5e, forming a first hard mask layer HM1, the first hard mask layer HM1 covers the surface of the ohmic contact area 8 and part of the surface of the initial source area 7'; using the first hard mask layer HM1 as a mask, ion implantation is performed on the epitaxial layer 2 to form a second initial well area 32' in the epitaxial layer; the upper surface of the second initial well area 32' is connected to the lower surface of the first initial well area 31', together forming an initial well area; the first hard mask layer HM1 is formed by the steps of deposition and etching. P-type ions are implanted during the formation of the second initial well area 32'.
[0070] refer to Figure 5f , depositing and etching on the inner side of the first hard mask layer HM1 to form a first sidewall spacer SW1;
[0071] refer to Figure 5g , using the first hard mask layer HM1 and the first sidewall SW1 as masks, ion implantation is performed on the initial well region to form a first initial trench region 41 ′ in the second initial well region 32 ′. In this embodiment, P-type ions are implanted.
[0072] refer to Figure 5h , deposit and etch the inner side of the first sidewall SW1 to form the second sidewall SW2; use the first hard mask layer HM1, the first sidewall SW1 and the second sidewall SW2 as masks to continue ion implantation into the exposed first initial trench region 41', and form the second initial trench region 42' at the bottom of the first initial trench region 41'; the bottom of the second initial trench region 42' contacts the epitaxial layer 2; the bottom of the first initial trench region 41' contacts the remaining second initial well region 32' at the side of the second initial trench region 42'. In this embodiment, P-type ions are continuously implanted.
[0073] refer to Figure 5i , using the first hard mask layer HM1, the first sidewall SW1 and the second sidewall SW2 as masks, etching a notch, the notch passing through the initial source region 7', the first initial well region 31', and going deep into the first initial trench region 41'; the remaining initial source region 7' constitutes the source region 7; the remaining first initial trench region 41' and the second initial trench region 42' constitute the trench region 4; the remaining first initial well region 31' and the remaining second initial well region 32' constitute the well region 3; the well region 3 forms a surrounding structure for the bottom corner of the trench region 4;
[0074] refer to Figure 5j, the gate region 5 and the gate oxide layer 6 are formed in the notch; the gate oxide layer 6 completely surrounds the gate region 5, and completely isolates the gate region 5 from the trench region 4, the source region 7, and the well region 3; a first electrode 9 is formed on the surface of the substrate layer 1 on the side facing away from the epitaxial layer 2; a second electrode 10 is formed on the surface of the gate oxide layer 6 on the side facing away from the substrate layer 1, and the second electrode 10 extends laterally to cover the surface of the source region 7 on the side facing away from the substrate layer 1 and the surface of the ohmic contact region 8 on the side facing away from the substrate layer.
[0075] The gate region 5 and the gate oxide layer 6 can be formed by conventional technical means in the art. For example, a first initial gate oxide layer is first deposited on the bottom and sidewalls of the notch, and then a gate region 5 of polysilicon is deposited in the opening of the first initial gate oxide layer, and then a second initial gate oxide layer is deposited to cover the gate region 5 and the exposed first initial gate oxide layer, and together form a complete gate oxide layer 6. Those skilled in the art may also select other appropriate methods to form, which will not be described in detail here.
[0076] Above Figure 5a-5j The process can obtain power devices with high symmetry.
[0077] refer to Figure 6a-6h In another specific embodiment, the method for forming a power device of this embodiment comprises the following steps:
[0078] refer to Figure 6a A semiconductor substrate is provided as a substrate layer 1; an epitaxial layer 2 is formed on one surface of the semiconductor substrate; in this embodiment, the semiconductor substrate is an N-type doped SiC substrate. The epitaxial layer 2 is formed by epitaxial growth and is an N-type doped layer.
[0079] refer to Figure 6b A first initial well region 31' is formed on the side of the epitaxial layer 2 facing away from the substrate layer 1. The first initial well region 31' is formed by ion implantation into the epitaxial layer 2. In this embodiment, P-type ions are implanted.
[0080] refer to Figure 6c The initial source region 7' is formed on the side of the first initial well region 31' facing away from the substrate layer. The initial source region 7' is formed by ion implantation. In this embodiment, N-type ions are implanted.
[0081] refer to Figure 6d An ohmic contact region 8 is formed on the side of the initial source region 7'; the ohmic contact region 8 is formed by ion implantation. In this embodiment, P-type ions are implanted.
[0082] refer to Figure 6e, forming a first hard mask layer HM1, wherein the first hard mask layer HM1 covers the surface of the ohmic contact region 8 and the surface of the initial source region 7'; etching a groove, wherein the groove penetrates the first hard mask layer HM1, the initial source region 7' and the first initial well region 31', and penetrates into the epitaxial layer 2; the remaining initial source region 7' constitutes the source region 7.
[0083] refer to Figure 6f , using the first hard mask layer HM1 as a mask, ion implantation is performed into the bottom and sidewalls of the notch of the epitaxial layer 2 to form an initial trench region 4' in the epitaxial layer;
[0084] refer to Figure 6g , remove the first hard mask layer HM1; then form a second hard mask layer (the second hard mask layer is not shown in the figure), the second hard mask layer covers the surface of the ohmic contact area 8 and the surface of the source area 7 and the bottom of the groove; etch the second hard mask layer to form a third hard mask layer HM3 located on the surface of the ohmic contact area 8 and the surface of the source area 7 and a fourth hard mask layer HM4 located in the groove; there is a gap between the third hard mask layer HM3 and the opening edge of the groove; the fourth hard mask layer HM4 is located at the bottom of the groove; There is a gap between the side walls of the groove; using the third hard mask layer HM3 and the fourth hard mask layer HM4 as masks, ions are implanted into the epitaxial layer 2 and the initial trench area 4' to form a second well area 32 surrounding the side of the initial trench area 4' and at least part of the bottom of the initial trench area 4'; the remaining initial trench area 4' constitutes the trench area 4; the remaining first initial well area 31' constitutes the first well area 31, and together with the second well area 32 constitute the well area 3, and the well area 3 forms a surrounding structure for the bottom corner of the trench area 4.
[0085] refer to Figure 6h , remove the third hard mask layer HM3 and the fourth hard mask layer HM4; form the gate region 5 and the gate oxide layer 6 in the notch; the gate oxide layer 6 completely surrounds the gate region 5, and completely isolates the gate region 5 from the trench region 4, the source region 7, and the well region 3; form a first electrode 9 on the surface of the substrate layer 1 facing away from the epitaxial layer 2; form a second electrode 10 on the surface of the gate oxide layer 6 facing away from the substrate layer 1, and the second electrode 10 extends laterally to cover the surface of the source region 7 facing away from the substrate layer 1 and the surface of the ohmic contact region 8 facing away from the substrate layer 1.
[0086] The formation of the gate region 5 and the gate oxide layer 6 may refer to the previous example process, or may be formed by other conventional technical means in the art, which will not be described in detail here.
[0087] Above Figure 6a-6h The process is simpler and easier to implement.
[0088] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the invention.
Claims
1. A power device, It is characterized in that include: gate region; The gate region is located in the well region; A gate oxide layer; the gate oxide layer completely surrounds the gate region; Groove area; The trench region surrounds at least part of the bottom and part of the side of the gate oxide layer; the top and side of the trench region are surrounded by the well region, and the well region extends from the side bottom corner edge of the trench region to the center of the bottom surface of the trench region to form a surrounding structure for the bottom corner of the trench region; The well region surrounds the side and part of the bottom of the trench region, and together with the trench region forms a surrounding structure for the bottom corner of the gate oxide layer; The gate oxide layer separates the gate region from the trench region and the well region.
2. The power device according to claim 1, It is characterized in that Also includes: Substrate layer; the substrate layer is a first conductivity type highly doped region; Epitaxial layer; The epitaxial layer is located on the surface of the substrate layer and is a low-doped region of the first conductivity type; The well region is partially located in the epitaxial layer and partially located on the surface of the epitaxial layer; the well region is a low-doped region of the second conductivity type; The well region surrounds the bottom of the portion of the trench region that is higher than the epitaxial layer; A source region; the source region is located on the surface of the well region and on the side of the gate oxide layer; the source region is a heavily doped region of the first conductivity type; the gate oxide layer also separates the gate region from the source region; An ohmic contact region; the ohmic contact region is located on the surface of the well region and on the side of the source region; the ohmic contact region is a heavily doped region of the second conductivity type; A first electrode is located on a surface of the substrate layer facing away from the epitaxial layer; A second electrode is located on a surface of the gate oxide layer facing away from the substrate layer, and extends laterally to cover a surface of the source region facing away from the substrate layer and a surface of the ohmic contact region facing away from the substrate layer; The trench region is a first conductivity type region.
3. The power device according to claim 1, It is characterized in that Also includes: Substrate layer; the substrate layer is a first conductivity type highly doped region; Epitaxial layer; The epitaxial layer is located on the surface of the substrate layer and is a low-doped region of the first conductivity type; The well region is located on the surface of the epitaxial layer; the well region is a low-doped region of the second conductivity type; source region; The source region is located on the surface of the well region and on the side of the gate oxide layer; the source region is a heavily doped region of the first conductivity type; the gate oxide layer also separates the gate region from the source region; An ohmic contact region; the ohmic contact region is located on the surface of the well region and on the side of the source region; the ohmic contact region is a heavily doped region of the second conductivity type; A first electrode is located on a surface of the substrate layer facing away from the epitaxial layer; A second electrode is located on a surface of the gate oxide layer facing away from the substrate layer, and extends laterally to cover a surface of the source region facing away from the substrate layer and a surface of the ohmic contact region facing away from the substrate layer; The trench region is a first conductivity type region.
4. The power device according to claim 2 or 3, It is characterized in that The side end of the well region extending toward the center of the bottom surface of the trench region extends from the vertical plane where the gate oxide layer on the same side is located to the center of the bottom surface of the trench region by ±0.8 μm.
5. The power device according to claim 2 or 3, It is characterized in that The trench region completely covers the bottom surface of the gate oxide layer; Alternatively, the trench region extends from a bottom corner edge of a side portion of one side of the gate oxide layer to an opposite side.
6. The power device according to claim 2 or 3, It is characterized in that Also includes: A spacer region, located at the bottom surface of the gate oxide layer, forming a spacer between the bottom surface of the gate oxide layer and the trench region; The spacer region and the trench region are regions of different conductivity types.
7. The power device according to claim 2 or 3, It is characterized in that The ohmic contact region also extends to cover the side of the well region; The second electrode also extends to cover the side of the ohmic contact region at the side of the well region.
8. A method for forming a power device according to any one of claims 1 to 7, It is characterized in that The following steps are involved: forming a well region; forming a trench region in the well region; forming a gate region and a gate oxide layer in the trench region; The gate oxide layer completely surrounds the gate region; The trench region surrounds at least part of the bottom and part of the side of the gate oxide layer; the top and side of the trench region are surrounded by the well region, and the well region extends from the bottom corner edge of the side of the trench region to the center of the bottom surface of the trench region to form a surrounding structure for the bottom corner of the trench region; the well region and the trench region together form a surrounding structure for the bottom corner of the gate oxide layer; The gate oxide layer separates the gate region from the trench region and the well region.
9. The method for forming a power device according to claim 8, It is characterized in that The following steps are involved: Providing a semiconductor substrate as a substrate layer; forming an epitaxial layer on one side surface of the semiconductor substrate; forming a first initial well region on a side of the epitaxial layer facing away from the substrate layer; forming an initial source region on a side of the first initial well region facing away from the substrate layer; forming an ohmic contact region on a side of the initial source region; forming a first hard mask layer, wherein the first hard mask layer covers a surface of the ohmic contact region and a portion of a surface of the initial source region; Using the first hard mask layer as a mask, ion implantation is performed on the epitaxial layer to form a second initial well region in the epitaxial layer; The upper surface of the second initial well region is connected to the lower surface of the first initial well region to form an initial well region; Depositing and etching the inner side of the first hard mask layer to form a first sidewall; using the first hard mask layer and the first sidewall as masks, ion implanting the initial well region to form a first initial trench region in the second initial well region; Depositing and etching the inner side of the first sidewall to form a second sidewall; using the first hard mask layer, the first sidewall and the second sidewall as masks, continuing to implant ions into the exposed first initial trench region to form a second initial trench region at the bottom of the first initial trench region; the bottom of the second initial trench region contacts the epitaxial layer; The bottom of the first initial trench region contacts the second initial well region remaining on the side of the second initial trench region; Using the first hard mask layer, the first sidewall and the second sidewall as masks, etching a notch, wherein the notch penetrates the initial source region, the first initial well region and goes deep into the first initial trench region; the remaining initial source region constitutes the source region; the remaining first initial trench region and the second initial trench region constitute the trench region; the remaining first initial well region and the remaining second initial well region constitute the well region; the well region forms a surrounding structure for the bottom corner of the trench region; The gate region and the gate oxide layer are formed in the notch; the gate oxide layer completely surrounds the gate region, and completely isolates the gate region from the trench region, the source region, and the well region; forming a first electrode on a surface of the substrate layer facing away from the epitaxial layer; A second electrode is formed on a surface of the gate oxide layer facing away from the substrate layer, and the second electrode extends laterally to cover a surface of the source region facing away from the substrate layer and a surface of the ohmic contact region facing away from the substrate layer.
10. The method for forming a power device according to claim 8, It is characterized in that The following steps are involved: Providing a semiconductor substrate as a substrate layer; forming an epitaxial layer on one side surface of the semiconductor substrate; forming a first initial well region on a side of the epitaxial layer facing away from the substrate layer; forming an initial source region on a side of the first initial well region facing away from the substrate layer; forming an ohmic contact region on a side of the initial source region; forming a first hard mask layer, wherein the first hard mask layer covers a surface of the ohmic contact region and a surface of the initial source region; Etching a notch, wherein the notch penetrates the first hard mask layer, the initial source region and the first initial well region, and penetrates into the epitaxial layer; the remaining initial source region constitutes a source region; Using the first hard mask layer as a mask, ion implantation is performed into the bottom and sidewalls of the notch of the epitaxial layer to form an initial trench region in the epitaxial layer; removing the first hard mask layer; Then forming a second hard mask layer, wherein the second hard mask layer covers the surface of the ohmic contact region, the surface of the source region and the bottom of the notch; Etching the second hard mask layer to form a third hard mask layer located on the surface of the ohmic contact region and the surface of the source region and a fourth hard mask layer located in the groove; There is a gap between the third hard mask layer and the opening edge of the notch; There is a gap between the fourth hard mask layer and the sidewall of the notch; using the third hard mask layer and the fourth hard mask layer as masks, ion implantation is performed into the epitaxial layer and the initial trench region to form a second well region surrounding the side of the initial trench region and at least a portion of the bottom of the initial trench region; The remaining initial trench region constitutes the trench region; the remaining first initial well region and the second well region constitute the well region, and the well region forms a surrounding structure for the bottom corner of the trench region; removing the third mask layer and the fourth mask layer; The gate region and the gate oxide layer are formed in the notch; the gate oxide layer completely surrounds the gate region, and completely isolates the gate region from the trench region, the source region, and the well region; forming a first electrode on a surface of the substrate layer facing away from the epitaxial layer; A second electrode is formed on a surface of the gate oxide layer facing away from the substrate layer, and the second electrode extends laterally to cover a surface of the source region facing away from the substrate layer and a surface of the ohmic contact region facing away from the substrate layer.