Wide-forbidden-band groove type MOSFET device and manufacturing method thereof

Abstract

The invention discloses a wide bandgap trench type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device and a manufacturing method thereof, which can be used in the field of semiconductor devices, in the device, an N-type epitaxial layer, a P-base region and a source region are sequentially arranged on one side of an N-type substrate; the drain electrode is arranged on the other side of the N-type substrate; the N accumulation type channel is arranged on the inner surface of the trench of the P-base region and is respectively contacted with the gate region, the P-base region and the N channel; the depth of the groove is smaller than the thickness of the P-base region; the N channel is arranged on the lower surface of the groove, penetrates through the P-base region and is in contact with the N-type epitaxial layer, the gate region and the N accumulation channel respectively; the gate region is disposed inside the trench, and is in contact with the N channel, the N accumulation channel, and the source region. Therefore, by constructing the P-base region deeper than the trench, and the conductive channel formed by the N accumulation channel and the N channel at the bottom, the conduction characteristic of the device is improved, and meanwhile, the gate region is well protected.

Description

Technical Field

[0001] The present application relates to the field of semiconductor devices, and in particular to a wide bandgap trench MOSFET device and a manufacturing method thereof. Background Art

[0002] Silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), diamond (C) and aluminum nitride (AlN) are new ultra-wide bandgap semiconductor materials with advantages such as ultra-wide bandgap, ultra-high breakdown field strength, and electron saturation drift velocity better than silicon (Si). They are widely used in the field of new energy.

[0003] Existing wide bandgap trench MOSFET designs have poor tolerance to electrostatic effects in harsh environments and high voltage spikes in circuits, and the electron mobility in the channel is very low, which degrades the conduction characteristics of the device.

[0004] Therefore, how to improve the conduction characteristics of the device while providing good protection for the gate region is an issue that those skilled in the art need to solve urgently. Summary of the invention

[0005] Based on the above problems, the present application provides a wide bandgap trench MOSFET device and a manufacturing method thereof, which improves the conduction characteristics of the device and provides good protection for the gate area by constructing a P-base region deeper than the trench and a conductive channel formed by an N accumulation channel and an N channel at the bottom.

[0006] In a first aspect, an embodiment of the present application provides a wide bandgap trench MOSFET device, the device comprising: an N-type substrate, an N-type epitaxial layer, an N-channel, an N-accumulation channel, a P-base region, a source region, a drain electrode, and a gate region;

[0007] The N-type epitaxial layer, the P-base region and the source region are sequentially arranged on one side of the N-type substrate; the drain electrode is arranged on the other side of the N-type substrate;

[0008] The N accumulation channel is arranged on the inner surface of the trench of the P-base region and is in contact with the gate region, the P-base region and the N channel respectively; the depth of the trench is less than the thickness of the P-base region;

[0009] The N channel is disposed on the lower surface of the trench, penetrates the P-base region, and contacts the N-type epitaxial layer, the gate region, and the N accumulation-type channel respectively;

[0010] The gate region is arranged inside the trench and is in contact with the N channel, the N accumulation-type channel and the source region respectively.

[0011] Optionally, the gate region includes: an interlayer dielectric layer, a gate dielectric layer and a gate;

[0012] The gate dielectric layer, the gate and the interlayer dielectric layer are sequentially arranged inside the trench from bottom to top;

[0013] The gate is wrapped by the gate dielectric layer and the interlayer dielectric layer.

[0014] Optionally, the width of the gate is wider than the width of the N channel.

[0015] Optionally, the source region includes: an N-type source and a P-type source;

[0016] The N-type source is close to the trench and in contact with the interlayer dielectric layer; the P-type source is far away from the trench and in contact with the N-type source.

[0017] Optionally, the N-type doping concentration of the N-type source is higher than the N-type doping concentration of the N channel;

[0018] The P-type doping concentration of the P-type source is higher than the P-type doping concentration of the P-base region.

[0019] Optionally, the P-base region includes: a P-base1 region arranged at an upper layer and a P-base2 region arranged at a lower layer;

[0020] The P-type doping concentration of the P-base2 region is higher than the P-type doping concentration of the P-base1 region.

[0021] Optionally, the N-type doping concentration of the N channel is higher than the N-type doping concentration of the N accumulation channel.

[0022] Optionally, the device further comprises: a source electrode;

[0023] The source electrode is arranged at the other side of the source region and is in contact with the source region and the interlayer dielectric layer respectively.

[0024] In a second aspect, an embodiment of the present application provides a method for manufacturing a wide bandgap trench MOSFET device, which is used to manufacture the wide bandgap trench MOSFET device as described above, and the method comprises:

[0025] Providing an N-type substrate;

[0026] Growing an N-type epitaxial layer on the N-type substrate;

[0027] Sequentially forming a P-base region and the source region on the N-type epitaxial layer;

[0028] Performing pattern etching on the source region until a portion of the P-base region is etched away and a groove is formed; the depth of the groove is less than the thickness of the P-base region;

[0029] Based on the ion implantation process, an N accumulation type channel is formed on the inner surface of the trench, and an N channel is formed at the bottom of the trench; the N type doping concentration of the N channel is higher than the N type doping concentration of the N accumulation type channel;

[0030] growing a gate region in the groove;

[0031] Based on a deposition process, a source electrode is formed on the gate region, and a drain electrode is formed under the N-type substrate.

[0032] Optionally, growing a gate region in the groove includes:

[0033] forming a layer of gate dielectric on the inner surface of the groove;

[0034] Growing polysilicon on the gate dielectric and performing pattern etching to form a gate;

[0035] An insulating dielectric is grown on the gate and pattern-etched to form an interlayer dielectric; the width of the gate dielectric is greater than the width of the gate, and the width of the interlayer dielectric is greater than the width of the gate.

[0036] It can be seen from the above technical solutions that compared with the prior art, the present application has the following advantages:

[0037] The wide bandgap trench MOSFET device provided in the embodiment of the present application includes: an N-type substrate, an N-type epitaxial layer, an N channel, an N accumulation-type channel, a P-base region, a source region, a drain electrode and a gate region; the N-type epitaxial layer, the P-base region and the source region are sequentially arranged on one side of the N-type substrate; the drain electrode is arranged on the other side of the N-type substrate; the N accumulation-type channel is arranged on the inner surface of the trench in the P-base region, and is in contact with the gate region, the P-base region and the N channel respectively; the depth of the trench is less than the thickness of the P-base region; the N channel is arranged on the lower surface of the trench, passes through the P-base region, and is in contact with the N-type epitaxial layer, the gate region and the N accumulation-type channel respectively; the gate region is arranged inside the trench, and is in contact with the N channel, the N accumulation-type channel and the source region respectively. In this way, by constructing a P-base region deeper than the trench, and a conductive channel formed by the N accumulation-type channel and the N channel at the bottom, the conduction characteristics of the device are improved while providing good protection for the gate region. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0039] Figure 1 A schematic diagram of the structure of a wide bandgap trench MOSFET device provided in an embodiment of the present application;

[0040] Figure 2 A schematic diagram of the structure of a gate region provided in an embodiment of the present application;

[0041] Figure 3 A schematic diagram of the structure of a source region provided in an embodiment of the present application;

[0042] Figure 4 A schematic diagram of the structure of a P-base region provided in an embodiment of the present application;

[0043] Figure 5 A schematic diagram of the structure of a source electrode provided in an embodiment of the present application;

[0044] Figure 6 A schematic diagram of a device blocking characteristic provided in an embodiment of the present application;

[0045] Figure 7 A schematic diagram of a device conduction characteristic provided in an embodiment of the present application;

[0046] Figure 8 A schematic diagram of the structure of an N-channel design provided in an embodiment of the present application;

[0047] Fig. 9 A schematic diagram of another N-channel design provided in an embodiment of the present application;

[0048] Fig.10 A flow chart of a method for manufacturing a wide bandgap trench MOSFET device provided in an embodiment of the present application;

[0049] Fig.11 A flowchart of another N-channel construction method provided in an embodiment of the present application;

[0050] Fig.12 A schematic diagram of the structure of another N-channel design provided in an embodiment of the present application. DETAILED DESCRIPTION

[0051] As mentioned above, the existing wide bandgap trench MOSFET design has the problem of poor high-voltage spike tolerance and low electron mobility in the channel. Specifically, the high electric field in the drift region of the wide bandgap semiconductor material in the existing design leads to a high electric field on the gate dielectric layer. This problem is exacerbated at the groove corner, causing the gate dielectric layer to break down rapidly under high drain electrode voltage, that is, there is a problem of poor high-voltage spike tolerance. In addition, the interface state density at the interface between the wide bandgap semiconductor material and silicon dioxide (SiO2) in the existing design is too high, resulting in very low electron mobility in the channel, thereby degrading the conduction characteristics of the device.

[0052] To solve the above problems, an embodiment of the present application provides a wide bandgap trench MOSFET device and a manufacturing method thereof, wherein the device includes: an N-type substrate, an N-type epitaxial layer, an N-channel, an N-accumulation-type channel, a P-base region, a source region, a drain electrode and a gate region; the N-type epitaxial layer, the P-base region and the source region are sequentially arranged on one side of the N-type substrate; the drain electrode is arranged on the other side of the N-type substrate; the N-accumulation-type channel is arranged on the inner surface of the trench in the P-base region, and is in contact with the gate region, the P-base region and the N-channel respectively; the depth of the trench is less than the thickness of the P-base region; the N-channel is arranged on the lower surface of the trench, passes through the P-base region, and is in contact with the N-type epitaxial layer, the gate region and the N-accumulation-type channel respectively; the gate region is arranged inside the trench, and is in contact with the N-channel, the N-accumulation-type channel and the source region respectively.

[0053] In this way, by constructing a P-base region deeper than the trench and a conductive channel formed by the N accumulation channel and the N channel at the bottom, the conduction characteristics of the device are improved while providing good protection for the gate region.

[0054] It should be noted that the wide bandgap trench MOSFET device and the manufacturing method thereof provided by the present application can be applied to the field of semiconductor devices. The above is only an example and does not limit the application field of the wide bandgap trench MOSFET device and the manufacturing method thereof provided by the present application.

[0055] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0056] Figure 1 A schematic diagram of the structure of a wide bandgap trench MOSFET device provided in an embodiment of the present application. Figure 1As shown, the device includes: an N-type substrate 100, an N-type epitaxial layer 200, an N channel 300, an N accumulation channel 400, a P-base region 500, a source region 600, a drain electrode 700 and a gate region 800;

[0057] The N-type epitaxial layer 200, the P-base region 500 and the source region 600 are sequentially arranged on one side of the N-type substrate 100; the drain electrode 700 is arranged on the other side of the N-type substrate 100;

[0058] The N accumulation channel 400 is disposed on the inner surface of the trench of the P-base region 500 and is in contact with the gate region 800, the P-base region 500 and the N channel 300 respectively; the depth of the trench is less than the thickness of the P-base region 500;

[0059] The N channel 300 is disposed on the lower surface of the trench, penetrates the P-base region 500, and contacts the N-type epitaxial layer 200, the gate region 800, and the N accumulation channel 400 respectively;

[0060] The gate region 800 is disposed inside the trench and is in contact with the N channel 300 , the N accumulation channel 400 , and the source region 600 , respectively.

[0061] Specifically, the problem of a high electric field on the gate dielectric layer caused by the high electric field in the drift region of the wide bandgap semiconductor material is more obvious at the groove corners. Therefore, the present application constructs a P-base region 500 that is deeper than the groove, so that the P-base region 500 wraps around the groove corners, and forms a conductive channel through the N accumulation channel 400 and the N channel 300, thereby improving the device's conduction characteristics while providing good protection for the gate region 800.

[0062] Figure 2 A schematic diagram of the structure of a gate region provided in an embodiment of the present application. Figure 2 As shown, the gate region 800 includes: an interlayer dielectric layer 801, a gate dielectric layer 802 and a gate 803;

[0063] The gate dielectric layer 802, the gate 803 and the interlayer dielectric layer 801 are sequentially arranged inside the trench from bottom to top;

[0064] The gate 803 is wrapped by the gate dielectric layer 802 and the interlayer dielectric layer 801 .

[0065] Specifically, the gate dielectric layer 802, the gate 803 and the interlayer dielectric layer 801 are sequentially arranged from bottom to top, and the gate 803 is wrapped between the gate dielectric layer 802 and the interlayer dielectric layer 801. The gate dielectric layer 802 is formed based on the deposition or thermal oxidation of the insulating dielectric layer, the interlayer dielectric layer 801 is formed based on the deposition of the insulating dielectric layer, and the gate 803 is formed based on the deposition of polysilicon.

[0066] In addition, regarding how to design the gate 803 , the width of the gate 803 is correspondingly wider than the width of the N channel 300 .

[0067] Specifically, the gate dielectric layer 802 and the gate 803 are sequentially arranged in the trench from bottom to top, and the interlayer dielectric layer 801 is arranged above the gate 803. The widths of the gate dielectric layer 802, the gate 803 and the interlayer dielectric layer 801 are all wider than the width of the N channel 300.

[0068] Figure 3 A schematic diagram of the structure of a source region provided in an embodiment of the present application. Figure 3 As shown, the source region 600 includes: an N-type source 601 and a P-type source 602;

[0069] The N-type source 601 is close to the trench and in contact with the interlayer dielectric layer 801 ; the P-type source 602 is away from the trench and in contact with the N-type source 601 .

[0070] Specifically, the N-type source 601 and the P-type source 602 are formed by ion implantation or secondary epitaxy. The lower surface of the P-type source 602 contacts the P-base region 500, and one side of the surface contacts the one side of the N-type source 601. The lower surface of the N-type source 601 contacts the P-base region 500 and the N accumulation channel 400, respectively, and the other side contacts the gate dielectric layer 802.

[0071] In addition, regarding how to design the P-type source 602 and the N-type source 601, the N-type doping concentration of the N-type source 601 is correspondingly higher than the N-type doping concentration of the N channel 300;

[0072] The P-type doping concentration of the P-type source 602 is higher than the P-type doping concentration of the P-base region 500 .

[0073] Specifically, the P-type source 602 and the N-type source 601 with high doping concentration can increase the carrier concentration of the source region 600, thereby reducing the contact resistance between the source metal and the semiconductor material and improving the conductivity of the material.

[0074] Figure 4 A schematic diagram of the structure of a P-base region provided in an embodiment of the present application. Figure 4As shown, the P-base region 500 includes: a P-base1 region 501 arranged at an upper layer and a P-base2 region 502 arranged at a lower layer;

[0075] The P-type doping concentration of the P-base2 region 502 is higher than the P-type doping concentration of the P-base1 region 501 .

[0076] Specifically, the trench is set in the P-base1 region 501, and the trench depth is less than the thickness of the P-base1 region 501. In the differently set doping concentrations, the P-base1 region 501 with a lower doping concentration is more likely to invert and form an N accumulation channel 400, thereby improving the conduction characteristics of the device, and the P-base2 region 502 with a higher doping concentration can play a good protective role on the gate oxide layer (gate dielectric layer 802) in the device trench.

[0077] In addition, regarding how to design the N channel 300 and the N accumulation channel 400 , the N-type doping concentration of the N channel 300 is correspondingly higher than the N-type doping concentration of the N accumulation channel 400 .

[0078] Specifically, the doping concentrations that are differently set between the N channel 300 and the N accumulation channel 400 can make it easier for the current channel to be pinched off when the device withstands reverse voltage.

[0079] Figure 5 A schematic diagram of the structure of a source electrode provided in an embodiment of the present application. Figure 5 As shown, the device further includes: a source electrode 900;

[0080] The source electrode 900 is disposed on the other side of the source region 600 , and is in contact with the source region 600 and the interlayer dielectric layer 801 , respectively.

[0081] Specifically, a relatively thick metal film may be deposited and patterned on the N-type source 601 and the P-type source 602 to serve as a thickened electrode of the source.

[0082] Figure 6 A schematic diagram of a device blocking characteristic provided in an embodiment of the present application. Figure 6 As shown, taking SiC material as an example, the wide bandgap trench MOSFET device provided by the present application has a breakdown voltage of 1747V. The embedded figure is the electric field distribution diagram of the device at 1200V, from which it can be seen that the position of the peak electric field is transferred from the corner of the trench to the bottom of the trench, avoiding the high peak electric field caused by the electric field concentration at the corner. The electric field between the P-base region 500 and the N-type epitaxial layer 200 is 2.87MV / cm. The peak electric field of the gate dielectric layer 802 at the bottom of the trench is 1.19MV / cm, which is much lower than the 2.5MV / cm that the industry believes will affect the reliability of the gate dielectric layer 802.

[0083] Figure 7 A schematic diagram of a device conduction characteristic provided in an embodiment of the present application. Figure 7 As shown, taking SiC material as an example, the wide bandgap trench MOSFET device provided by the present application can be obtained by calculation that the specific on-resistance of the device is 1.58 mΩ·cm 2 , lower than the 2.2mΩ·cm achieved by common brands 2 and 2.6 mΩ·cm 2 , so it has better conduction characteristics.

[0084] Figure 8 A schematic diagram of the structure of an N-channel design provided in an embodiment of the present application. Figure 8 As shown, a is a top view of a wide bandgap trench MOSFET device, and b and c are cross-sectional views of the device at two different positions. A shielding layer (P+Shield layer) can be introduced at the bottom of the trench and inside the N accumulation channel by ion implantation, thereby further increasing the concentration of the N channel 300 of the device while keeping the peak electric field of the gate 803 unchanged or even reducing it.

[0085] Fig. 9 A schematic diagram of another N-channel design provided in an embodiment of the present application. Fig. 9 As shown, by adjusting the width of the hard mask on the trench sidewall during ion implantation, the width of the N channel 300 under the trench can be adjusted. When there is no hard mask on the trench sidewall, the left and right sides of the N channel 300 will be flush with the two sides of the trench.

[0086] In summary, the wide bandgap trench MOSFET device provided in the embodiment of the present application includes: an N-type substrate, an N-type epitaxial layer, an N channel, an N accumulation-type channel, a P-base region, a source region, a drain electrode and a gate region; the N-type epitaxial layer, the P-base region and the source region are sequentially arranged on one side of the N-type substrate; the drain electrode is arranged on the other side of the N-type substrate; the N accumulation-type channel is arranged on the inner surface of the trench in the P-base region, and is respectively in contact with the gate region, the P-base region and the N channel; the depth of the trench is less than the thickness of the P-base region; the N channel is arranged on the lower surface of the trench, passes through the P-base region, and is respectively in contact with the N-type epitaxial layer, the gate region and the N accumulation-type channel; the gate region is arranged inside the trench, and is respectively in contact with the N channel, the N accumulation-type channel and the source region. In this way, by constructing a P-base region deeper than the trench, and a conductive channel formed by the N accumulation-type channel and the N channel at the bottom, the conduction characteristics of the device are improved while providing good protection for the gate region.

[0087] Fig.10A flowchart of a method for manufacturing a wide bandgap trench MOSFET device provided in an embodiment of the present application. Fig.10 As shown, the method may include:

[0088] S1: Provide an N-type substrate.

[0089] In practical applications, the N-type substrate can be N-type doped SiC, GaN, Ga2O3, C, AlN, etc.

[0090] S2: growing an N-type epitaxial layer on the N-type substrate.

[0091] In practical applications, an N-type epitaxial layer is grown on an N-type substrate layer, wherein the doping concentration in the N-type epitaxial layer is lower than the doping concentration in the N-type substrate.

[0092] S3: forming a P-base region and the source region in sequence on the N-type epitaxial layer.

[0093] In practical applications, a P-base region can be formed on the N-type epitaxial layer by ion implantation, secondary epitaxy, etc. The P-base region includes the upper P-base1 region and the lower P-base2 region, and the P-type doping concentration of the P-base2 region is higher than the P-type doping concentration of the P-base1 region. Afterwards, a source region is formed above the P-base1 region by ion implantation, secondary epitaxy, etc. The source region includes an N-type source close to the trench and a P-type source far from the trench, and the N-type doping concentration of the N-type source is higher than the N-type doping concentration of the N channel, and the P-type doping concentration of the P-type source is higher than the P-type doping concentration of the P-base region.

[0094] S4: performing pattern etching on the source region until a portion of the P-base region is etched away and a trench is formed; the depth of the trench is less than the thickness of the P-base region.

[0095] In actual applications, a photolithography process is performed above the source region to open an etching area and protect the non-etching area. Then, dry etching is performed to etch away the source at the center of the device and part of the P-base1 region, forming a gate trench in the P-base1 region.

[0096] S5: Based on an ion implantation process, an N accumulation type channel is formed on the inner surface of the trench, and an N channel is formed at the bottom of the trench; the N type doping concentration of the N channel is higher than the N type doping concentration of the N accumulation type channel.

[0097] In practical applications, an N accumulation channel and an N channel are formed by an ion implantation process, wherein the N accumulation channel has a lower N-type doping concentration, which can avoid excessive leakage current of the device; and the N channel has a higher N-type doping concentration, which is beneficial to improving the conduction characteristics of the device.

[0098] S6: growing a gate region in the groove.

[0099] In practical applications, a gate region is formed in the trench by combining deposition, growth, and etching processes.

[0100] S7: Based on a deposition process, a source electrode is formed on the gate region, and a drain electrode is formed under the N-type substrate.

[0101] Finally, a drain electrode is formed below the N-type substrate by a metal film deposition process, and a source electrode is formed above the source region by a metal film deposition and etching process.

[0102] In addition, since the design methods of the gate region are not the same, the embodiment of the present application can be described with respect to a possible design method.

[0103] In one embodiment, the step of growing a gate region in the groove comprises:

[0104] forming a layer of gate dielectric on the inner surface of the groove;

[0105] Growing polysilicon on the gate dielectric and performing pattern etching to form a gate;

[0106] An insulating dielectric is grown on the gate and pattern-etched to form an interlayer dielectric; the width of the gate dielectric is greater than the width of the gate, and the width of the interlayer dielectric is greater than the width of the gate.

[0107] In practical applications, it is necessary to first grow a layer of insulating dielectric on the inner surface of the trench, that is, grow the gate dielectric, then grow and etch the gate polysilicon on the gate dielectric in the trench to form a gate, and finally deposit and etch the interlayer dielectric above the gate to obtain a complete gate area.

[0108] Fig.11 A flowchart of another N-channel construction method provided in an embodiment of the present application. Fig.11 As shown, the N channel can be formed in two stages. In the first stage (a), a hard mask is grown on the upper surface of the device and inside the trench, and a T-type N channel is formed by etching, and then ion implantation is performed to form a partial N channel. In the second stage (b), the thickness of the sidewall hard mask is increased by growing a sidewall on the basis of the first stage, thereby forming a narrower T-type N channel, which will not increase the length of the low-concentration N accumulation channel while strengthening the protection of the gate oxide, thereby avoiding significant degradation of the conduction characteristics. Then, as shown in c, the hard mask is removed, and then other layers are constructed, as shown in d, to obtain a complete wide bandgap trench MOSFET device.

[0109] Fig.12A schematic diagram of another N-channel design provided in an embodiment of the present application. Fig.12 As shown, a is a top view of the wide bandgap trench MOSFET device, and b and c are cross-sectional views of the device at two different positions. Fig.11 Based on the wide bandgap trench MOSFET device shown in (d), a P+Shield of the same T-type design is added to the bottom of the trench through ion implantation to enhance the electric field shielding effect and achieve grounding in three-dimensional directions.

[0110] In summary, the present application provides a method for manufacturing a wide bandgap trench MOSFET device, including: providing an N-type substrate; growing an N-type epitaxial layer on the N-type substrate; forming a P-base region and a source region on the N-type epitaxial layer in sequence based on processes such as ion implantation and secondary epitaxy; etching the source region until a portion of the P-base region is etched away and a trench is formed; the depth of the trench is less than the thickness of the P-base region; based on the ion implantation process, forming an N accumulation-type channel on the inner surface of the trench, and forming an N channel at the bottom of the trench; the N-type oxide doping concentration of the N channel is higher than the N-type oxide doping concentration of the N accumulation-type channel; growing a gate region in the groove; based on a deposition process, forming a source electrode on the gate region, and forming a drain electrode under the N-type substrate. In this way, by constructing a P-base region deeper than the trench, and a conductive channel formed by the N accumulation-type channel and the N channel at the bottom, the conduction characteristics of the device are improved while providing good protection for the gate region.

[0111] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A wide bandgap trench MOSFET device, characterized in that: The device comprises: an N-type substrate, an N-type epitaxial layer, an N-channel, an N-accumulation-type channel, a P-base region, a source region, a drain electrode and a gate region; The N-type epitaxial layer, the P-base region and the source region are sequentially arranged on one side of the N-type substrate; the drain electrode is arranged on the other side of the N-type substrate; The N accumulation channel is arranged on the inner surface of the trench of the P-base region and is in contact with the gate region, the P-base region and the N channel respectively; the depth of the trench is less than the thickness of the P-base region; The N channel is disposed on the lower surface of the trench, penetrates the P-base region, and contacts the N-type epitaxial layer, the gate region, and the N accumulation-type channel respectively; The gate region is arranged inside the trench and is in contact with the N channel, the N accumulation-type channel and the source region respectively.

2. The device according to claim 1, characterized in that The gate region includes: an interlayer dielectric layer, a gate dielectric layer and a gate; The gate dielectric layer, the gate and the interlayer dielectric layer are sequentially arranged inside the trench from bottom to top; The gate is wrapped by the gate dielectric layer and the interlayer dielectric layer.

3. The device according to claim 2, characterized in that The width of the gate is wider than the width of the N channel.

4. The device according to claim 2, characterized in that The source region includes: an N-type source and a P-type source; The N-type source is close to the trench and in contact with the interlayer dielectric layer; the P-type source is far away from the trench and in contact with the N-type source.

5. The device according to claim 4, characterized in that The N-type doping concentration of the N-type source is higher than the N-type doping concentration of the N-channel; The P-type doping concentration of the P-type source is higher than the P-type doping concentration of the P-base region.

6. The device according to claim 1, characterized in that The P-base region includes: a P-base1 region arranged in an upper layer and a P-base2 region arranged in a lower layer; The P-type doping concentration of the P-base2 region is higher than the P-type doping concentration of the P-base1 region.

7. The device according to claim 1, characterized in that The N-type doping concentration of the N channel is higher than the N-type doping concentration of the N accumulation channel.

8. The device according to claim 1, characterized in that The device further comprises: a source electrode; The source electrode is arranged at the other side of the source region and is in contact with the source region and the interlayer dielectric layer respectively.

9. A method for manufacturing a wide bandgap trench MOSFET device, characterized in that: For manufacturing a wide bandgap trench MOSFET device as claimed in claims 1 to 8, the method comprises: Providing an N-type substrate; Growing an N-type epitaxial layer on the N-type substrate; Sequentially forming a P-base region and the source region on the N-type epitaxial layer; Performing pattern etching on the source region until a portion of the P-base region is etched away and a groove is formed; the depth of the groove is less than the thickness of the P-base region; Based on the ion implantation process, an N accumulation type channel is formed on the inner surface of the trench, and an N channel is formed at the bottom of the trench; the N type doping concentration of the N channel is higher than the N type doping concentration of the N accumulation type channel; growing a gate region in the groove; Based on a deposition process, a source electrode is formed on the gate region, and a drain electrode is formed under the N-type substrate.

10. The method according to claim 9, characterized in that The step of growing a gate region in the groove comprises: forming a layer of gate dielectric on the inner surface of the groove; Growing polysilicon on the gate dielectric and performing pattern etching to form a gate; An insulating dielectric is grown on the gate and pattern-etched to form an interlayer dielectric; the width of the gate dielectric is greater than the width of the gate, and the width of the interlayer dielectric is greater than the width of the gate.

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