A MOSFET structure with multi-layer gate control region and preparation method thereof

Abstract

The present invention provides a MOSFET structure with a multi-layer gate control region and a preparation method, comprising: a substrate, the substrate comprising a first surface and a second surface arranged oppositely, the first surface covered with a doped drift layer, the surface of the doped drift layer is provided with a gate region and two source regions, the gate region is placed between the source regions; the gate region comprises a gate control region, the gate control region comprises a first gate control layer, a second gate control layer, a third gate control layer, a fourth gate control layer and a fifth gate control layer stacked in sequence and having different concentrations, the first gate control layer covers the doped drift layer. By setting the gate control region, the P-shield layer can be in a floating state when the device is turned on, which helps to improve the injection and distribution of carriers, reduce the lateral JFET resistance to a certain extent, reduce the amount of stored charge, and thereby reduce the on-resistance of the device, improve the reliability of the gate oxide layer, and improve the breakdown resistance of the device.

Description

Technical Field

[0001] The invention relates to a power semiconductor device, and in particular to a MOSFET structure with a multi-layer gate control region and a preparation method thereof. Background Art

[0002] In the field of modern power electronics, silicon carbide (SiC) MOSFET has attracted widespread attention due to its excellent high temperature stability, high voltage tolerance and fast switching characteristics. The wide bandgap characteristics of SiC material enable it to perform well in high frequency, high efficiency and high temperature working environments, especially in high-performance applications such as electric vehicles, renewable energy systems, and industrial motor control. However, traditional SiC MOSFET designs often require a trade-off between on-resistance and breakdown voltage, which limits further improvements in device performance.

[0003] In existing SiC MOSFET structures, smaller cell sizes are usually used to reduce on-resistance, but this may lead to lower breakdown voltage. In addition, the uneven distribution of the gate oxide electric field may cause reliability issues for the device under high voltage. Summary of the invention

[0004] In view of the above problems, the present invention provides a trench SiC MOSFET structure with a multi-layer gate control region, which achieves dual optimization of on-resistance and breakdown voltage through an innovative multi-layer gate control region control mechanism.

[0005] In a first aspect, the present invention provides a MOSFET structure with a multi-layer gate control region, comprising: a substrate, the substrate comprising a first surface and a second surface arranged opposite to each other, the first surface being covered with a doped drift layer, the surface of the doped drift layer being provided with a gate region and two source regions, the gate region being arranged between the source regions;

[0006] The gate region includes a gate control region, the gate control region includes a first gate control layer, a second gate control layer, a third gate control layer, a fourth gate control layer and a fifth gate control layer which are sequentially stacked and have different concentrations, and the first gate control layer covers the doped drift layer;

[0007] The fifth gate control layer is heavily P-type doped silicon carbide, the third gate control layer is lightly P-type doped silicon carbide, and the P-type silicon carbide doping concentration of the first gate control layer, the second gate control layer and the fourth gate control layer is between the third gate control layer and the fifth gate control layer;

[0008] The gate region further includes an oxide layer, a polysilicon region and a P-type shielding layer, wherein the oxide layer, the polysilicon region and the gate control region cover the P-type shielding layer, and the P-type shielding layer is disposed between the gate control region and the doped drift layer;

[0009] The polysilicon regions are provided with two, which are respectively placed on both sides of the gate control region, and the oxide layer surrounds the polysilicon region and the gate control region;

[0010] A source metal layer is disposed on the first surface, and the source metal layer is in contact with the fifth gate control layer.

[0011] Furthermore, the first gate control layer has a thickness of 0.2 μm-1 μm, a width of 0.2 μm-1 μm, and a doping concentration of 10 17 -10 18 cm -3 ;

[0012] The second gate control layer has a thickness of 0.2 μm-1 μm, a width of 0.2 μm-1 μm, and a doping concentration of 10 16 -10 18 cm -3 ;

[0013] The third gate control layer has a thickness of 0.1 μm-0.5 μm, a width of 0.2 μm-1 μm, and a doping concentration of 10 16 -10 17 cm -3 ;

[0014] The fourth gate control layer has a thickness of 0.2 μm-1 μm, a width of 0.2 μm-1 μm, and a doping concentration of 10 16 -10 18 cm -3 ;

[0015] The fifth gate control layer has a thickness of 0.2 μm-1 μm, a width of 0.2 μm-1 μm, and a doping concentration of 10 17 -10 18 cm -3 .

[0016] Furthermore, the source region includes a current spreading layer and a P-type well layer stacked in sequence in a direction away from the substrate, the P-type well layer is covered with an N-type heavily doped layer and a P-type heavily doped layer, and the N-type heavily doped layer is close to the gate region.

[0017] Furthermore, the source metal layer covers the source region and the gate region, and the second surface is covered with a drain metal layer.

[0018] Furthermore, the gate region has a thickness of 1 μm-3 μm and a width of 0.7 μm-5 μm.

[0019] In a second aspect, the present invention further provides a method for preparing a MOSFET structure having a multi-layer gate control region, comprising the following steps:

[0020] S1, growing a doped drift layer on a first surface of a substrate in a direction away from the substrate;

[0021] S2, sequentially growing a current spreading layer, a P-type well layer and an N-type heavily doped layer on the doped drift layer;

[0022] S3, etching the N-type heavily doped layer and the P-type well layer to form a gate region;

[0023] S4, performing ion implantation in the gate region in sequence to form a P-type shielding layer and a gate control region in sequence, wherein a first gate control layer, a second gate control layer, a third gate control layer, a fourth gate control layer and a fifth gate control layer with different concentrations are stacked in sequence in the gate control region; performing ion implantation in the P-type well layer to form a P-type heavily doped layer;

[0024] The fifth gate control layer is heavily doped P-type silicon carbide, the third gate control layer is lightly doped P-type silicon carbide, and the doping concentration of P-type silicon carbide of the first gate control layer, the second gate control layer and the fourth gate control layer is between the third gate control layer and the fifth gate control layer;

[0025] S5, etching the P-type shielding layer, the first gate control layer, the second gate control layer, the third gate control layer, the fourth gate control layer and the fifth gate control layer to form two gate trenches;

[0026] S6, performing thermal oxidation growth in the gate trench to form an oxide layer, and depositing polysilicon on the surface of the oxide layer to form two polysilicon regions respectively disposed on both sides of the gate control region, wherein the oxide layer surrounds the polysilicon region and the gate control region;

[0027] The oxide layer, the polysilicon region and the gate control region cover the P-type shielding layer, and the P-type shielding layer is placed between the gate control region and the doped drift layer;

[0028] S7. Depositing a source metal layer on the first surface, wherein the source metal layer is in contact with the fifth gate control layer.

[0029] Furthermore, when performing step S3, the P-type well layer is exposed by etching.

[0030] Furthermore, after step S6, the method further includes etching the polysilicon, and cleaning and plasma treating the surface of the fifth gate control layer;

[0031] and depositing a gate metal layer.

[0032] Compared with the prior art, the present invention at least includes the following beneficial effects: by setting the gate control layer, the P-type shielding layer can be in a floating state when the device is turned on, which helps to improve the injection and distribution of carriers, reduce the lateral JFET resistance to a certain extent, reduce the amount of stored charge, and thus reduce the on-resistance of the device. When the device breaks down, the gate control layer and the P-type shielding layer are grounded, which helps to balance the electric field, reduce the electric field concentration phenomenon, and improve the reliability of the gate oxide layer, and the device's breakdown resistance is improved. Multiple gate control layers are composed of multiple layers of P-type SiC with different concentrations. The multi-layer design of this structure creates a highly doped charge balance layer, reduces the on-resistance of the device, and evens out the electric field distribution of the device, thereby increasing the breakdown voltage of the device, while alleviating the electric field spike near the channel, which plays a positive role in the long-term reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0034] Figure 1 is a schematic diagram of the overall structure of a MOSFET structure with a multi-layer gate control region in one embodiment of the present invention;

[0035] Figure 2 is a flow chart of a method for preparing a MOSFET structure with a multi-layer gate control region in one embodiment of the present invention;

[0036] Figure 3 is a schematic diagram of the device structure in the preparation method S1 of the present invention;

[0037] Figure 4 is a schematic diagram of the device structure in the preparation method S2 of the present invention;

[0038] Figure 5 is a schematic diagram of the device structure in the preparation method S3 of the present invention;

[0039] Figure 6 is a schematic diagram of the device structure in the preparation method S4 of the present invention;

[0040] Figure 7 is a schematic diagram of the device structure in the preparation method S5 of the present invention;

[0041] Figure 8 is a schematic diagram of an embodiment of the present invention after the oxide layer and polysilicon are prepared;

[0042] Fig. 9 It is a schematic diagram of the structure of preparing the source metal layer and the drain metal layer according to the present invention;

[0043] Fig.10 This is a comparison diagram of the drain-source current of three structures, namely, a trench SiC MOSFET (PGS_MOS) with a multi-layer gate control region in an example of the present invention, an adjustable P-region potential SiC MOSFET (AP_MOS), a traditional P-shield floating SiC MOSFET (fp_MOS), and a traditional P-shield grounded SiC MOSFET (P-shield_MOS), at breakdown.

[0044] Among them, 1-substrate; 2-doped drift layer; 3-current spreading layer; 4-P-type well layer; 5-N-type heavily doped layer; 6-P-type shielding layer; 7-first gate control layer; 8-second gate control layer; 9-third gate control layer; 10-fourth gate control layer; 11-fifth gate control layer; 12-P-type heavily doped layer; 13-oxide layer; 14-polysilicon region; 15-source metal layer; 16-drain metal layer; D1-source region; D2-gate region. DETAILED DESCRIPTION

[0045] A MOSFET structure with a multi-layer gate control region and a preparation method of the present invention will be described in more detail below in conjunction with a schematic diagram, wherein a preferred embodiment of the present invention is shown, and it should be understood that those skilled in the art can modify the present invention described herein and still achieve the advantageous effects of the present invention. Therefore, the following description should be understood as being widely known to those skilled in the art and not as a limitation of the present invention.

[0046] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0047] The present invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in very simplified form and are not in exact proportions, and are only used to facilitate and clearly assist in illustrating the purpose of the embodiments of the present invention.

[0048] In a first aspect, the present invention provides a MOSFET structure with a multi-layer gate control region, comprising: a substrate 1, wherein the substrate 1 comprises a first surface and a second surface arranged opposite to each other, wherein the first surface is covered with a doped drift layer 2, wherein a gate region D2 and two source regions D1 are arranged on the surface of the doped drift layer 2, wherein the gate region is arranged between the source regions;

[0049] The gate region D2 includes a gate control region, which includes a first gate control layer 7 , a second gate control layer 8 , a third gate control layer 9 , a fourth gate control layer 10 and a fifth gate control layer 11 which are stacked in sequence and have different concentrations. The first gate control layer 7 covers the doped drift layer 2 .

[0050] Specifically, the substrate 1 of the MOSFET structure has two first surfaces and a second surface arranged opposite to each other. A doped drift layer 2 is covered on the first surface of the substrate 1, and the layer is used to provide an electric field to support the blocking voltage of the device. A gate region D2 and two source regions D1 are provided on the surface of the doped drift layer 2, and the gate region D2 is located between the two source regions D1. The gate region D2 includes a gate control region, which is composed of a plurality of gate control regions of different concentrations stacked in sequence. These stacked structures help to accurately control the gate voltage, thereby optimizing the switching characteristics of the device. The first gate control layer 7 is closest to the doped drift layer 2, which directly covers the doped drift layer 2.

[0051] Through the structural design of the multi-layer gate control region, the MOSFET in this embodiment can achieve faster switching speed and lower on-resistance while maintaining a high blocking voltage, thereby improving the overall device performance. In addition, the design of the multi-layer gate control region also helps to improve the long-term stability of the device, reduce the accumulation of gate charge, and extend the service life of the device.

[0052] Furthermore, the gate region D2 further includes an oxide layer 13, a polysilicon region 14 and a P-type shielding layer 6, wherein the oxide layer 13, the polysilicon region 14 and the gate control region cover the P-type shielding layer 6, and the P-type shielding layer 6 is disposed between the gate control region and the doped drift layer 2;

[0053] The polysilicon regions 14 are provided with two, which are respectively disposed at two sides of the gate control region, and the oxide layer 13 surrounds the polysilicon regions 14 and the gate control region.

[0054] Specifically, an oxide layer 13 is provided in the gate region D2, and the oxide layer 13 is used to isolate the polysilicon region 14 from the gate control region and provide an insulating surface for the gate. Two polysilicon regions 14 are provided in the gate region, and the two polysilicon regions 14 are respectively located on both sides of the gate control region. The polysilicon region 14 serves as a conductive part of the gate and is used to apply a gate voltage to control the conduction and cutoff of the transistor. A P-type shielding layer 6 is provided between the gate control region and the doped drift layer 2. The purpose of the P-type shielding layer 6 is to reduce the electric field concentration between the gate and the doped drift layer 2, thereby reducing the gate leakage current of the device and improving the reliability of the device.

[0055] The oxide layer 13, the polysilicon region 14 and the gate control region cover the P-type shielding layer 6 to form a composite gate structure. The oxide layer 13 not only surrounds the polysilicon region 14, but also surrounds the gate control region, ensuring the correct distribution of the electric field and the effectiveness of the gate control.

[0056] By introducing an oxide layer 13, a polysilicon region 14 and a P-type shielding layer 6 in the gate region D2, the gate's ability to control the electric field of the doped drift layer 2 is improved, thereby improving the switching characteristics of the device. The P-type shielding layer 6 helps to reduce the direct contact between the gate and the drift layer, reduce the gate leakage current, and increase the blocking voltage of the device. The setting of the polysilicon region 14 helps to improve the conductivity of the gate, so that the gate voltage can more effectively control the conduction and cutoff of the device. The presence of the oxide layer 13 ensures good insulation between the gate and the polysilicon region 14, reduces parasitic capacitance, and improves the operating frequency of the device.

[0057] Furthermore, the fifth gate control layer 11 is heavily P-type doped silicon carbide, the third gate control layer 9 is lightly P-type doped silicon carbide, and the P-type silicon carbide doping concentration of the first gate control layer 7, the second gate control layer 8 and the fourth gate control layer 10 is between the third gate control layer 9 and the fifth gate control layer 11.

[0058] Specifically, the fifth gate control layer 11 is a P-type heavily doped silicon carbide (SiC) layer with a high doping concentration, which can effectively improve the control ability of the gate, reduce the on-resistance of the device, and help to improve the switching speed of the device. The third gate control layer 9 is a P-type lightly doped silicon carbide layer with a low doping concentration, which helps to form a better electric field distribution between the gate and the doped drift layer 2, reduce the gate leakage current, and improve the blocking voltage of the device.

[0059] The P-type silicon carbide doping concentration of the first gate control layer 7, the second gate control layer 8 and the fourth gate control layer 10 is between the third gate control layer 9 and the fifth gate control layer 11. The first gate control layer 7 is adjacent to the doped drift layer 2, and its doping concentration is between heavy doping and light doping, which can effectively control the electric field distribution and reduce the interface defects between the gate and the drift layer. The second gate control layer 8 is located on the first gate control layer 7, and its doping concentration helps to further optimize the electric field distribution and reduce the gate leakage current. The fourth gate control layer 10 is located on the third gate control layer 9, and its doping concentration helps to smoothly transition to the heavily doped fifth gate control layer 11, thereby achieving better electric field control.

[0060] Through this multi-layer and doping concentration gradient design, the electric field distribution of the gate is optimized, and the switching performance and reliability of the device are improved. The gate leakage current is reduced, and the blocking voltage and power handling capacity of the device are improved. Through the gradient doping concentration, the interface defects between the gate and the drift layer are reduced, and the long-term stability of the device is improved. The heavily doped fifth gate control layer 11 helps to improve the conductivity of the gate, while the lightly doped third gate control layer 9 helps to improve the blocking ability of the device. This combined design enables the device to exhibit excellent performance in both the on and off states.

[0061] Furthermore, the first gate control layer 7 has a thickness of 0.2 μm-1 μm, a width of 0.2 μm-1 μm, and a doping concentration of 10 17 -10 18 cm -3 ;

[0062] The second gate control layer 8 has a thickness of 0.2 μm-1 μm, a width of 0.2 μm-1 μm, and a doping concentration of 10 16 -10 18 cm -3 ;

[0063] The thickness of the third gate control layer 9 is 0.1 μm-0.5 μm, the width is 0.2 μm-1 μm, and the doping concentration is 10 16 -10 17 cm -3 ;

[0064] The fourth gate control layer 10 has a thickness of 0.2 μm-1 μm, a width of 0.2 μm-1 μm, and a doping concentration of 10 16 -10 18 cm -3 ;

[0065] The fifth gate control layer 11 has a thickness of 0.2 μm-1 μm, a width of 0.2 μm-1 μm, and a doping concentration of 10 17-10 18 cm -3 .

[0066] In this embodiment, the width of the gate control layer is preferably 0.6 μm, the thickness of the first gate control layer 7 is 0.3 μm, and the doping concentration is 10 18 cm -3 The thickness of the second gate control layer 8 is 0.3 μm and the doping concentration is 5×10 17 cm -3 The thickness of the third gate control layer 9 is 0.2 μm, and the doping concentration is 4×10 16 cm -3 The thickness of the fourth gate control layer 10 is 0.3 μm and the doping concentration is 10 17 cm -3 The thickness of the fifth gate control layer 11 is 0.3 μm, and the doping concentration is 6×10 17 cm -3 .

[0067] Furthermore, the source region D1 includes a current spreading layer 3 and a P-type well layer 4 stacked in sequence in a direction away from the substrate 1, the P-type well layer 4 is covered with an N-type heavily doped layer 5 and a P-type heavily doped layer 12, and the N-type heavily doped layer 5 is close to the gate region.

[0068] Specifically, the current expansion layer 3 is located in the source region D1, close to the substrate 1, and its function is to expand the current channel, reduce the contact resistance of the device, and improve the current injection efficiency. The current expansion layer 3 usually uses lightly doped or medium-doped N-type silicon carbide. The P-type well layer 4 is located above the current expansion layer 3, and its main function is to form electrical isolation between the source region and the gate region, prevent current leakage, and help improve the breakdown voltage of the device. The N-type heavily doped layer 5 covers the P-type well layer 4, close to the gate region. The function of the N-type heavily doped layer 5 is to provide a low-resistance contact surface to facilitate the injection and extraction of electrons, thereby improving the switching speed and overall performance of the device.

[0069] The P-type heavily doped layer 12 serves as a contact layer of the source electrode, provides good ohmic contact, reduces contact resistance, and improves the conduction efficiency of the device.

[0070] The combination of the current spreading layer 3 and the P-type well layer 4 improves the breakdown voltage and power handling capability of the device. The configuration of the N-type heavily doped layer 5 and the P-type heavily doped layer 12 optimizes the contact characteristics of the source region, reduces the contact resistance, and improves the conduction performance of the device. The N-type heavily doped layer 5 near the gate region D2 helps to reduce the parasitic capacitance between the gate and the source and improve the switching speed of the device.

[0071] Furthermore, the first surface is provided with a source metal layer 15, and the second surface is covered with a drain metal layer 16;

[0072] The source metal layer 15 covers the source region D1 and the gate region D2 , and the source metal layer 15 is in contact with the fifth gate control layer 11 .

[0073] Specifically, the source metal layer 15 is located on the first surface of the MOSFET, that is, the front side of the device. The main function of the source metal layer 15 is to provide electrical connection so that the source region is connected to the external circuit. The source metal layer 15 covers the N-type heavily doped layer 5 and the P-type heavily doped layer 12 in the source region, ensuring good electrical contact between the source region and the metal layer. The source metal layer 15 is in contact with the fifth gate control layer 11. This contact method helps to reduce the resistance between the source and the gate and improve the conduction performance of the device. The drain metal layer 16 is located on the second surface, that is, the back side of the device. The function of the drain metal layer 16 is to provide electrical connection to the drain so that the drain region is connected to the external circuit. The drain metal layer 16 is usually matched with the doping type of the substrate 1 to achieve low-resistance ohmic contact.

[0074] The source metal layer 15 is located on the first surface of the device, covers the N-type heavily doped layer 5 and the P-type heavily doped layer 12 of the source region D1, and directly contacts the fifth gate control layer 11 to form an effective electrical connection. The drain metal layer 16 is located on the second surface of the device, covers the entire drain region, and contacts the N-type doped layer of the substrate 1 to ensure that the drain current can efficiently flow out of the device.

[0075] Through the direct contact between the source metal layer 15 and the fifth gate control layer 11, the contact resistance between the source and the gate is reduced, and the conduction efficiency of the device is improved. The setting of the drain metal layer 16 ensures good contact between the drain and the substrate 1, reduces the contact resistance of the drain, and improves the overall performance of the device. The optimized design of the metal layer helps to improve the heat dissipation performance of the device, because the metal has good thermal conductivity, which helps to quickly conduct away the heat generated when the device is running.

[0076] Furthermore, the gate region D2 has a thickness of 1 μm-3 μm and a width of 0.7 μm-5 μm.

[0077] The gate polysilicon of the gate region D2, the first gate control layer 7, the second gate control layer 8, the third gate control layer 9, the fourth gate control layer 10, the fifth gate control layer 11 and the P-type shielding layer 6 work together to enable the device to achieve the following effects. When a positive bias is applied to the gate, under the action of a positive electric field, holes in the gate voltage control region will be repelled, especially in the low-doped third gate voltage control region. When the gate voltage is higher than its critical voltage, the region will be pinched off, so that the first gate control layer 7, the second gate control layer 8 and the connected P-type shielding layer 6 below the third gate voltage control region are not connected to the fourth gate control layer 10, the fifth gate control layer 11 and the source metal above the third gate control layer 9, that is, the source and the P-type shielding layer 6 do not share a common ground. At this time, the P-type shielding layer 6 is in a floating state. This state helps to improve the injection and distribution of carriers, and provides a path with lower resistance in the on state. At the same time, it can disperse the electric field, reduce the lateral JFET region resistance between devices, and play a role in reducing the on-resistance; under the breakdown condition, the control region does not pinch off, and connects the source and the P-type shielding layer 6. At this time, the source and the P-type shielding layer 6 share a common ground, and the entire gate region bears the voltage drop together. In this state, the P-type shielding layer 6 can reduce the injection of charges into the gate oxide and disperse the electric field near the gate oxide, thereby improving the breakdown voltage and reliability of the device.

[0078] Since the low-doped third gate control layer 9 is sensitive to the gate voltage, in order to accurately control this area and avoid unnecessary losses, multiple small-dose ion implantations are performed during the process to form a multi-layer gate control area. The bottom first gate control layer 7 is heavily doped to ensure good contact with the P-type shielding layer 6. The concentration of the second gate control layer 8 is lower than that of the first gate control layer 7 to form a transition to ensure accurate control of the thickness and doping concentration of the third gate control layer 9. The third gate control layer 9 is low-doped, and the thickness and doping concentration are optimal values ​​based on comprehensive consideration of device parameters to ensure that it is pinched off under positive gate bias. The fourth gate control layer 10 is also a transition layer, and the fifth gate control layer 11 is heavily doped to ensure good ohmic contact with the source metal. This structure can balance the electric field when the device breaks down, especially to reduce the peak value of the oxide electric field near the channel, and also balances the thermal distribution and charge balance of the device, thereby improving the long-term reliability of the device.

[0079] In a second aspect, the present invention also provides a method for preparing a MOSFET structure having a multi-layer gate control region, see Figure 2 , including the following steps:

[0080] S1, growing a doped drift region on a first surface of a substrate 1 in a direction away from the substrate 1;

[0081] S2, sequentially growing a current spreading layer 3, a P-type well layer 4 and an N-type heavily doped layer 5 on the doped drift region;

[0082] S3, etching the N-type heavily doped layer 5 and the P-type well layer 4 to form a gate region D2;

[0083] S4, performing ion implantation in the gate region in sequence to form a P-type shielding layer 6, a first gate control layer 7, a second gate control layer 8, a third gate control layer 9, a fourth gate control layer 10 and a fifth gate control layer 11; performing ion implantation in the P-type well layer 4 to form a P-type heavily doped layer 12;

[0084] S5, etching the P-type shielding layer 6, the first gate control layer 7, the second gate control layer 8, the third gate control layer 9, the fourth gate control layer 10 and the fifth gate control layer 11 to form two gate trenches;

[0085] S6. Perform thermal oxidation growth in the gate trench to form an oxide layer, and deposit polysilicon on the surface of the oxide layer.

[0086] Furthermore, when performing step S3, the P-type well layer 4 is exposed by etching.

[0087] For details, please refer to Figure 3-Figure 9 On the first surface of the silicon carbide substrate 1, a layer of N-type doped drift layer is grown by chemical vapor deposition (CVD) or other suitable growth technology. This layer will serve as the main conductive channel of the device. On the surface of the doped drift layer, a current expansion layer 3, a P-type well layer 4 and an N-type heavily doped layer 5 are grown in sequence. These layers can be grown by CVD or other epitaxial technology. Using photolithography and etching technology, the N-type heavily doped layer 5 and the P-type well layer 4 are selectively etched to form a gate region D2, in preparation for the subsequent formation of a gate control layer.

[0088] A P-type shielding layer 6 and a multi-level gate control region are formed in the gate region D2 by ion implantation technology, and the doping concentration and thickness of each layer are controlled according to the design requirements. At the same time, ion implantation is performed on the P-type well layer 4 to form a P-type heavily doped layer 12. The formed gate control region is etched using photolithography and etching techniques to form two gate trenches in preparation for the subsequent deposition of an oxide layer 13 and polysilicon. An oxide layer is grown in the gate trench by a thermal oxidation process, and then polysilicon is deposited on the surface of the oxide layer by chemical vapor deposition (CVD) or other techniques to form the conductive portion of the gate.

[0089] In this embodiment, 2-5 times of etching are performed downward from the bottom of the etched gate region D2 with an energy of 500-800 KeV and a dose of 1×10 13 -1×10 14 ions / cm 2The boron ion implantation is performed to form a P-type shielding layer 6; the implantation is continued downward for 1-3 times with an energy of 300-500 KeV and a dose of 1×10 13 -1×10 14 ions / cm 2 The boron ion implantation is performed to form the first gate control layer 7; then 1-3 times of implantation is performed with an energy of 300-400 KeV and a dose of 5×10 13 -5×10 14 ions / cm 2 The boron ion implantation is performed 1-2 times with an energy of 300-400 KeV and a dose of 5×10 12 -1×10 13 ions / cm 2 The boron ion implantation is performed 1-3 times with an energy of 100-300 KeV and a dose of 1×10 13 -1×10 14 ions / cm 2 The boron ion implantation is performed 1-3 times with an energy of 20-100 KeV and a dose of 1×10 14 -5×10 14 ions / cm 2 The fifth gate control layer 11 is formed by implanting boron ions.

[0090] In step S3, the N-type heavily doped layer and the P-type well layer 4 are etched to form a gate region. In this process, part of the N-type heavily doped layer is etched away, thereby exposing the P-type well layer 4 underneath. Part of the P-type well layer 4 is also etched, but it is not completely etched away to retain it as part of the gate region. In this way, a clearly defined gate region can be obtained after etching, in which the P-type well layer 4 is partially exposed, providing a basis for forming a multi-layer gate control structure in subsequent steps. Such a structure helps to achieve better electric field control, thereby improving the switching performance and reliability of the MOSFET.

[0091] Furthermore, after step S6, the method further includes etching the polysilicon, and cleaning and plasma treating the surface of the fifth gate control layer 11;

[0092] And deposit a source metal layer 15 and a gate metal layer.

[0093] Specifically, after the deposition of polysilicon is completed, the polysilicon is etched into a desired shape by photolithography and etching processes to form the top structure of the gate. This step requires precise control to ensure that the geometry and size of the gate meet the design requirements. After the polysilicon etching is completed, the surface of the fifth gate control layer 11 is cleaned to remove any possible contaminants and residues. The plasma treatment step is used to improve the chemical activity of the surface of the fifth gate control layer 11, thereby improving the adhesion and contact quality during the subsequent metal deposition process.

[0094] After surface cleaning and plasma treatment, a metal layer is deposited in the source region and the gate region by physical vapor deposition (PVD), chemical vapor deposition (CVD), electroplating or other suitable metal deposition techniques. The deposition of the source metal layer 15 usually covers the N-type heavily doped layer 5 and the P-type heavily doped layer 12 in the source region, and contacts the fifth gate control layer 11 to form a good electrical connection. The deposition of the gate metal layer covers the polysilicon gate to provide an electrical connection to the gate.

[0095] In another embodiment of the present invention, the device is simulated according to a specific example, such as Fig. 9 The IV conditions of four devices under breakdown conditions are: trench SiC MOSFET with multi-layer gate control region (MGC_MOS), an adjustable P-region potential SiC MOSFET (AP_MOS), traditional P-shield floating SiC MOSFET (fp_MOS), and traditional P-shield grounded SiC MOSFET (P-shield_MOS). Fig. 9 Analysis shows that the multi-layer gate control region trench SiC MOSFET (MGC_MOS) proposed in the present invention has the highest breakdown voltage value, which is much better than the traditional P-shield floating SiC MOSFET (fp_MOS), indicating that the high voltage resistance capability of the proposed structure is greatly improved.

[0096] The above specific examples are used to illustrate the present invention, which is only used to help understand the present invention and is not intended to limit the present invention. For those skilled in the art, according to the concept of the present invention, some simple deductions, modifications or substitutions can be made.

Claims

1. A MOSFET structure with a multi-layer gate control region, characterized in that: The invention comprises: a substrate, wherein the substrate comprises a first surface and a second surface arranged opposite to each other, the first surface is covered with a doped drift layer, a gate region and two source regions are arranged on the surface of the doped drift layer, and the gate region is arranged between the source regions; The gate region includes a gate control region, the gate control region includes a first gate control layer, a second gate control layer, a third gate control layer, a fourth gate control layer and a fifth gate control layer which are sequentially stacked and have different concentrations, and the first gate control layer covers the doped drift layer; The fifth gate control layer is heavily P-type doped silicon carbide, the third gate control layer is lightly P-type doped silicon carbide, and the P-type silicon carbide doping concentration of the first gate control layer, the second gate control layer and the fourth gate control layer is between the third gate control layer and the fifth gate control layer; The gate region further includes an oxide layer, a polysilicon region and a P-type shielding layer, wherein the oxide layer, the polysilicon region and the gate control region cover the P-type shielding layer, and the P-type shielding layer is disposed between the gate control region and the doped drift layer; The polysilicon regions are provided with two, which are respectively placed on both sides of the gate control region, and the oxide layer surrounds the polysilicon region and the gate control region; A source metal layer is disposed on the first surface, and the source metal layer is in contact with the fifth gate control layer.

2. The MOSFET structure with multi-layer gate control region according to claim 1, characterized in that: The first gate control layer has a thickness of 0.2 μm-1 μm, a width of 0.2 μm-1 μm, and a doping concentration of 10 17 -10 18 cm -3 ; The second gate control layer has a thickness of 0.2 μm-1 μm, a width of 0.2 μm-1 μm, and a doping concentration of 10 16 -10 18 cm -3 ; The third gate control layer has a thickness of 0.1 μm-0.5 μm, a width of 0.2 μm-1 μm, and a doping concentration of 10 16 -10 17 cm -3 ; The fourth gate control layer has a thickness of 0.2 μm-1 μm, a width of 0.2 μm-1 μm, and a doping concentration of 10 16 -10 18 cm -3 ; The fifth gate control layer has a thickness of 0.2 μm-1 μm, a width of 0.2 μm-1 μm, and a doping concentration of 10 17 -10 18 cm -3 .

3. The MOSFET structure with multi-layer gate control region according to claim 1, characterized in that: The source region includes a current spreading layer and a P-type well layer stacked in sequence in a direction away from the substrate, the P-type well layer is covered with an N-type heavily doped layer and a P-type heavily doped layer, and the N-type heavily doped layer is close to the gate region.

4. The MOSFET structure with multi-layer gate control region according to claim 1, characterized in that: The source metal layer also covers the source region and the gate region, and the second surface is covered with a drain metal layer.

5. The MOSFET structure with multi-layer gate control region according to claim 1, characterized in that: The gate region has a thickness of 1 μm-3 μm and a width of 0.7 μm-5 μm.

6. A method for preparing a MOSFET structure having a multi-layer gate control region, characterized in that: The steps include: S1, growing a doped drift layer on a first surface of a substrate in a direction away from the substrate; S2, sequentially growing a current spreading layer, a P-type well layer and an N-type heavily doped layer on the doped drift layer; S3, etching the N-type heavily doped layer and the P-type well layer to form a gate region; S4, performing ion implantation in the gate region in sequence to form a P-type shielding layer and a gate control region in sequence, wherein a first gate control layer, a second gate control layer, a third gate control layer, a fourth gate control layer and a fifth gate control layer with different concentrations are stacked in sequence in the gate control region; performing ion implantation in the P-type well layer to form a P-type heavily doped layer; The fifth gate control layer is heavily doped P-type silicon carbide, the third gate control layer is lightly doped P-type silicon carbide, and the doping concentration of P-type silicon carbide of the first gate control layer, the second gate control layer and the fourth gate control layer is between the third gate control layer and the fifth gate control layer; S5, etching the P-type shielding layer, the first gate control layer, the second gate control layer, the third gate control layer, the fourth gate control layer and the fifth gate control layer to form two gate trenches; S6, performing thermal oxidation growth in the gate trench to form an oxide layer, and depositing polysilicon on the surface of the oxide layer to form two polysilicon regions respectively disposed on both sides of the gate control region, wherein the oxide layer surrounds the polysilicon region and the gate control region; The oxide layer, the polysilicon region and the gate control region cover the P-type shielding layer, and the P-type shielding layer is placed between the gate control region and the doped drift layer; S7. Depositing a source metal layer on the first surface, wherein the source metal layer is in contact with the fifth gate control layer.

7. The method for preparing a MOSFET structure with a multi-layer gate control region according to claim 6, characterized in that: When performing step S3, the P-type well layer is exposed by etching.

8. The method for preparing a MOSFET structure with a multi-layer gate control region according to claim 7, characterized in that: After step S6, the method further includes etching the polysilicon, and cleaning and plasma treating the surface of the fifth gate control layer; and depositing a gate metal layer.

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