Solar cell and photovoltaic module

Abstract

The embodiment of the invention relates to the photovoltaic field, provides a solar cell and a photovoltaic module, and at least can improve the photoelectric conversion efficiency of the cell. The solar cell comprises a substrate, wherein the surface of the substrate is provided with metal regions and non-metal regions which are alternately arranged; the first tunneling dielectric layer is located on the surface of the substrate; the first polycrystalline silicon layer is positioned on the surface of the first tunneling dielectric layer, and an aluminum element is doped in the first polycrystalline silicon layer; the doped semiconductor structure is located in the first polycrystalline silicon layer corresponding to the metal region and extends towards the substrate from the surface, away from the substrate, of the first polycrystalline silicon layer, and P-type doping elements are arranged in the doped semiconductor structure; the first passivation layer is located on the surface of the first polycrystalline silicon layer and the surface of the doped semiconductor structure; and the first electrode is located on the surface of the first passivation layer corresponding to the metal region, and the first electrode is electrically connected with the doped semiconductor structure.

Description

Technical Field

[0001] The embodiments of the present application relate to the photovoltaic field, and in particular to a solar cell and a photovoltaic module. Background Art

[0002] At present, with the gradual depletion of fossil energy, solar cells are becoming more and more widely used as a new energy alternative. Solar cells are devices that convert sunlight into electrical energy. Solar cells use the photovoltaic principle to generate carriers, and then use electrodes to lead the carriers out, thereby facilitating the effective use of electrical energy.

[0003] The current solar cells mainly include IBC cells (Interdigitated Back Contact), TOPCON (Tunnel Oxide Passivated Contact), PERC cells (Passivated emitter and real cell) and heterojunction cells, etc. The photoelectric conversion efficiency of solar cells is improved by reducing optical losses and reducing the recombination of photogenerated carriers on the surface and in the body of the silicon substrate through different film layer settings and functional limitations.

[0004] However, the photoelectric conversion efficiency of current solar cells is still poor. Summary of the invention

[0005] The embodiments of the present application provide a solar cell and a photovoltaic module, which are at least beneficial to improving the photoelectric conversion efficiency of the solar cell.

[0006] According to some embodiments of the present application, on the one hand, an embodiment of the present application provides a solar cell, comprising: a substrate, a surface of the substrate having metal areas and non-metal areas arranged alternately; a first tunneling dielectric layer, the first tunneling dielectric layer being located on the surface of the substrate; a first polycrystalline silicon layer, the first polycrystalline silicon layer being located on the surface of the first tunneling dielectric layer, the first polycrystalline silicon layer being doped with aluminum elements; at least one doped semiconductor structure, the doped semiconductor structure being located in the first polycrystalline silicon layer corresponding to the metal area, and extending from the surface of the first polycrystalline silicon layer away from the substrate toward the substrate, the doped semiconductor structure having a P-type doping element; a first passivation layer, the first passivation layer being located on the surface of the first polycrystalline silicon layer and the surface of the doped semiconductor structure; a first electrode, the first electrode being located on the surface of the first passivation layer corresponding to the metal area, and the first electrode being electrically connected to the doped semiconductor structure.

[0007] In some embodiments, the doped semiconductor structure includes: a second polysilicon layer, the second polysilicon layer is located in the first polysilicon layer corresponding to the metal area, the first electrode is electrically connected to the second polysilicon layer, the second polysilicon layer is doped with the P-type doping element, and the doping concentration of the P-type doping element is greater than the doping concentration of the aluminum element.

[0008] In some embodiments, the doped semiconductor structure penetrates the thickness of the first polysilicon layer, and the doped semiconductor structure also includes: a second tunneling dielectric layer, the second tunneling dielectric layer is located in the first tunneling dielectric layer, the second polysilicon layer is located on the second tunneling dielectric layer, and the second tunneling dielectric layer is doped with the P-type doping element.

[0009] In some embodiments, the doped semiconductor structure penetrates the thickness of the first tunneling dielectric layer, and the doped semiconductor structure further includes: a diffusion layer, the diffusion layer is located in the substrate, and the diffusion layer is doped with the P-type doping element.

[0010] In some embodiments, the doping depth of the diffusion layer is 10 nm to 100 nm.

[0011] In some embodiments, the second polysilicon layer, the second tunnel dielectric layer, and the diffusion layer are all doped with the aluminum element.

[0012] In some embodiments, the second polysilicon layer includes: a first polysilicon portion, the first polysilicon portion is doped with the P-type doping element; a second polysilicon portion, the second polysilicon portion is doped with the P-type doping element and the aluminum element.

[0013] In some embodiments, a ratio R of an orthographic projection area of ​​the doped semiconductor structure on the substrate to an area of ​​the metal region satisfies: 0%<R<100%.

[0014] In some embodiments, the first electrode extends along a first direction and further includes: a main gate line, the main gate line is located on the surface of the first passivation layer, the main gate line extends along a second direction, and the main gate line contacts the first electrode; the doped semiconductor structure is also located in part of the non-metallic area, and the orthographic projection of the doped semiconductor structure on the substrate surface is located within the orthographic projection of the main gate line on the substrate surface.

[0015] According to some embodiments of the present application, on the other hand, the embodiments of the present application further provide a photovoltaic assembly, including: a battery string, wherein the battery string is composed of a plurality of solar cells as described in any one of the above embodiments; a packaging film for covering the surface of the battery string; and a cover plate for covering the surface of the packaging film facing away from the battery string.

[0016] The technical solution provided by the embodiments of the present application has at least the following advantages:

[0017] In the solar cell provided in the embodiment of the present application, the solar cell has a metal area and a non-metal area respectively, and the entire surface has a first tunnel dielectric layer and a first polysilicon layer. The double passivation effect of the first tunnel dielectric layer and the first polysilicon layer can effectively reduce the carrier recombination rate of the substrate, thereby improving the battery conversion efficiency. In addition, the first polysilicon layer is doped with aluminum, and the solid solubility of aluminum in polysilicon is low, so that it is relatively easy to obtain a polysilicon layer with a low doping concentration of aluminum, and the non-metallic area can avoid the recombination loss caused by the high doping concentration. Moreover, the polysilicon layer containing aluminum elements has a good degree of impurity absorption (high minority carrier lifetime), so that the substrate can be better passivated, thereby improving the conversion efficiency of the battery; the substrate surface corresponding to the metal area also has a doped semiconductor structure, and the P-type doping element in the doped semiconductor structure can provide more P-type ions, so that it can exist as a PN junction, effectively generate and separate photogenerated carriers, and the first electrode is electrically connected to the doped semiconductor structure, so as to have a lower contact resistance and reduce electrical losses. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] One or more embodiments are exemplarily illustrated by the figures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise specified, the figures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present application or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 A cross-sectional view of a solar cell provided in one embodiment of the present application;

[0020] Figure 2 Another cross-sectional view of a solar cell provided in one embodiment of the present application;

[0021] Figure 3 Another cross-sectional view of a solar cell provided in one embodiment of the present application;

[0022] Figure 4 A top view of a first surface of a solar cell provided in an embodiment of the present application;

[0023] Figure 5 Another top view of the first surface of a solar cell provided in an embodiment of the present application;

[0024] Figures 6 to 9 A cross-sectional view of a solar cell corresponding to each step in a method for preparing a solar cell provided in another embodiment of the present application;

[0025] Fig.10 A cross-sectional view of a laminated battery provided in yet another embodiment of the present application;

[0026] Fig.11 A schematic diagram of the structure of a photovoltaic module provided in yet another embodiment of the present application;

[0027] Fig.12 for Fig.11 A cross-section along the M1-M2 section. DETAILED DESCRIPTION

[0028] As can be seen from the background art, the photoelectric conversion efficiency of current solar cells is poor.

[0029] The embodiments of the present application provide a solar cell and a photovoltaic module, wherein the surface of the solar cell is a first polysilicon layer doped with aluminum to reduce the recombination rate and improve the photoelectric conversion efficiency; a doped semiconductor structure is formed in the metal region and is in electrical contact with the first electrode, thereby reducing the contact resistance and improving the photoelectric conversion efficiency.

[0030] In the description of the embodiments of the present application, the technical terms "first", "second", etc. are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features. In the description of the embodiments of the present application, the meaning of "multiple" is more than two, unless otherwise clearly and specifically defined.

[0031] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0032] In the description of the embodiments of the present application, the term "and / or" is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists, A and B exist at the same time, and B exists. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0033] In the description of the embodiments of the present application, the term "multiple" refers to more than two (including two). Similarly, "multiple groups" refers to more than two groups (including two groups), and "multiple pieces" refers to more than two pieces (including two pieces).

[0034] In the description of the embodiments of the present application, the technical terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, which are only for the convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the embodiments of the present application.

[0035] In the description of the embodiments of the present application, unless otherwise clearly specified and limited, technical terms such as "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be the internal connection of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0036] In the accompanying drawings corresponding to the embodiments of the present application, the thickness and area of ​​the layer are magnified for better understanding and ease of description. When describing a component (such as a layer, film, region or substrate) on another component or on the surface of another component, the component can be "directly" located on the surface of another component, or there can be a third component between the two components. On the contrary, when describing a component on the surface of another component or when another component is formed or provided on the surface of a component, it means that there is no third component between the two components. In addition, when describing a component as "substantially" formed on another component, it means that the component is not formed on the entire surface (or front surface) of the other component, nor is it formed on a partial edge of the entire surface.

[0037] In the description of the embodiments of the present application, when a component "includes" another component, unless otherwise specified, other components are not excluded, and other components may be further included. In addition, when a component such as a layer, film, region, or plate is referred to as being "on / located on" another component, it may be "directly on" the other component (i.e., located on the surface of the other component with no other components between them), or another component may exist in between. In addition, when a component such as a layer, film, region, or plate is "directly located on" another component, or when a component such as a layer, film, region, or plate is located on the surface of another component, it means that no other components are located in between.

[0038] The terms used in the description of the various embodiments described herein are only used to describe specific embodiments and are not intended to be limiting. As used in the description of the various embodiments described and in the appended claims, "the part" is also intended to include the plural form unless the context clearly indicates otherwise. Among them, a component includes a layer, a film, a region, or a plate.

[0039] The following will describe the various embodiments of the present application in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present application, many technical details are provided in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solution claimed in the present application can be implemented.

[0040] Figure 1 A cross-sectional view of a solar cell provided in one embodiment of the present application.

[0041] According to some embodiments of the present application, the present application provides a solar cell. Figure 1 The solar cell includes a substrate 100, and the surface of the substrate 100 has metal areas 11 and non-metal areas 12 arranged alternately. The solar cell includes a first tunnel dielectric layer 121, and the first tunnel dielectric layer 121 is located on the surface of the substrate 100. The solar cell includes a first polysilicon layer 122, and the first polysilicon layer 122 is located on the surface of the first tunnel dielectric layer 121, and the first polysilicon layer 122 is doped with aluminum. The solar cell includes at least one doped semiconductor structure 130, and the doped semiconductor structure 130 is located in the first polysilicon layer 122 corresponding to the metal area 11, and extends from the surface of the first polysilicon layer 122 away from the substrate 100 toward the substrate 100, and the doped semiconductor structure 130 has a P-type doping element. The solar cell includes a first passivation layer 105, and the first passivation layer 105 is located on the surface of the first polysilicon layer 122 and the surface of the doped semiconductor structure 130. The solar cell includes a first electrode 106 . The first electrode 106 is located on a surface of the first passivation layer 105 corresponding to the metal region 11 , and the first electrode 106 is electrically connected to the doped semiconductor structure 130 .

[0042] In the solar cell provided in the embodiment of the present application, the solar cell has a metal region 11 and a non-metal region 12, respectively, and the entire surface has a first tunnel dielectric layer 121 and a first polysilicon layer 122. The double passivation effect of the first tunnel dielectric layer 121 and the first polysilicon layer 122 can effectively reduce the carrier recombination rate of the substrate 100, thereby improving the cell conversion efficiency. In addition, the first polysilicon layer 122 is doped with aluminum, and the solid solubility of aluminum in polysilicon is low, so that a polysilicon layer with a low doping concentration of aluminum can be obtained relatively easily, and the non-metallic region can avoid the recombination loss caused by the high doping concentration. Moreover, the polysilicon layer containing aluminum elements has a good degree of doping (high minority carrier lifetime), so that the substrate 100 can be better passivated, thereby improving the conversion efficiency of the battery; the surface of the substrate 100 corresponding to the metal area also has a doped semiconductor structure 130, and the P-type doping elements in the doped semiconductor structure can provide more P-type ions, so that it can exist as a PN junction, effectively generate and separate photogenerated carriers, and the first electrode 106 is electrically connected to the doped semiconductor structure 130, so as to have a lower contact resistance and reduce electrical losses.

[0043] In some embodiments, the material of the substrate 100 may be an elemental semiconductor material. Specifically, the elemental semiconductor material is composed of a single element, such as silicon or germanium. The elemental semiconductor material may be in a single crystalline state, a polycrystalline state, an amorphous state, or a microcrystalline state (a state having both a single crystalline state and an amorphous state is referred to as a microcrystalline state), for example, silicon may be at least one of single crystalline silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon.

[0044] In some embodiments, the material of the substrate 100 may also be a compound semiconductor material. Common compound semiconductor materials include but are not limited to silicon germanium, silicon carbide, gallium arsenide, indium gallium, perovskite, cadmium telluride, copper indium selenide and the like. The substrate 100 may also be a sapphire substrate, a silicon on insulator substrate or a germanium on insulator substrate.

[0045] In some embodiments, the substrate 100 may be an N-type semiconductor substrate. The N-type semiconductor substrate is doped with an N-type doping element, which may be any one of Group V elements such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As).

[0046] In some embodiments, the substrate 100 has a first surface and a second surface that are arranged opposite to each other. The solar cell is a single-sided cell, the first surface can be used as a light-receiving surface for receiving incident light, and the second surface is used as a backlight surface. Among them, the backlight surface can also receive incident light, but the efficiency of receiving the incident light is weaker than the efficiency of the light-receiving surface receiving the incident light.

[0047] In some embodiments, the metal region 11 refers to the region where the orthographic projection of the first electrode 106 on the substrate 100 is located, and the non-metal region 12 refers to the region other than the orthographic projection of the first electrode 106 on the substrate 100. In order to ensure that the film layer contacted by the first electrode 106 has a relatively high doping concentration or the region contacted by the first electrode 106 is a high-concentration doped semiconductor structure 130, the area of ​​the metal region 11 is generally set to be greater than or equal to the area of ​​the orthographic projection of the first electrode 106 on the substrate 100.

[0048] The first tunnel dielectric layer 121 and the first polysilicon layer 122 form a passivation contact structure. Due to the special energy band structure of the passivation contact structure, the first polysilicon layer 122 is in electrical contact with the substrate 100, so that the energy band of the substrate 100 is bent downward, reducing the electron transmission barrier. Therefore, the ultra-thin first tunnel dielectric layer 121 can allow majority carriers (the substrate 100 is an N-type substrate 100, the first polysilicon layer 122 is a P region, and the majority carriers here are holes) to tunnel while blocking minority carriers (the minority carriers here are electrons) from passing through, thereby separating electrons and holes, reducing recombination, and reducing the recombination rate.

[0049] Specifically, the ultra-thin first tunnel dielectric layer 121 causes an asymmetric shift in the energy band on the surface of the substrate 100, so that the barrier to the majority carriers (also known as majority carriers) among the carriers is lower than the barrier to the minority carriers (also known as minority carriers) among the carriers. Therefore, the majority carriers can easily perform quantum tunneling through the first tunnel dielectric layer 121, while the minority carriers are difficult to pass through the first tunnel dielectric layer 121 to achieve selective transmission of carriers. Secondly, the first tunnel dielectric layer 121 has a chemical passivation effect. Due to the presence of interface state defects at the interface between the substrate 100 and the first tunnel dielectric layer 121, the interface state density on the surface of the substrate 100 is relatively large. The increase in the interface state density will promote the recombination of photogenerated carriers, increase the fill factor, short-circuit current and open-circuit voltage of the solar cell, and improve the photoelectric conversion efficiency of the solar cell. In other words, the first tunnel dielectric layer 121 reduces the carrier recombination rate by saturating the dangling bonds of the substrate 100, reducing the defect state density of the substrate 100, and reducing the recombination center of the substrate 100.

[0050] In some embodiments, the thickness of the first tunnel dielectric layer 121 is 0.5 nm to 10 nm. The thickness of the first tunnel dielectric layer 121 ranges from 0.5 nm to 1.3 nm, 1.3 nm to 4.6 nm, 4.6 nm to 6.1 nm, or 6.1 nm to 10 nm. When the first tunnel dielectric layer 121 is within any of the above ranges, the thickness of the first tunnel dielectric layer 121 is thinner, and majority carriers can easily perform quantum tunneling through the first tunnel dielectric layer 121, while minority carriers have difficulty passing through the first tunnel dielectric layer 121, so as to achieve selective transmission of carriers.

[0051] In some embodiments, the material of the first tunnel dielectric layer 121 includes at least one of silicon oxide, amorphous silicon, microcrystalline silicon, nanocrystalline silicon, or silicon carbide.

[0052] The first polysilicon layer 122 has a field passivation effect. Specifically, an electrostatic field pointing to the inside of the substrate 100 is formed on the surface of the substrate 100, so that minority carriers escape from the interface, thereby reducing the minority carrier concentration, so that the carrier recombination rate at the interface of the substrate 100 is reduced, thereby increasing the open circuit voltage, short circuit current and fill factor of the solar cell, and improving the photoelectric conversion efficiency of the solar cell.

[0053] The aluminum element doped in the first polysilicon layer 122 can avoid the problem of light attenuation caused by the boron-oxygen complex formed by the combination of boron and oxygen, thereby increasing the life of the solar cell. The first polysilicon layer 122 is doped with aluminum element, and the solid solubility of aluminum element in polysilicon is low, so it is relatively easy to obtain a polysilicon layer with a low doping concentration, and the non-metallic region can avoid the composite loss caused by a high doping concentration. Moreover, the polysilicon layer containing aluminum element has a good degree of doping (high minority carrier lifetime), so that the substrate 100 can be better passivated, thereby improving the photoelectric conversion efficiency of the battery.

[0054] In some embodiments, the doping concentration of aluminum is 1×10 18 cm -3 ~1×10 21 cm -3 This doping concentration range can form a PN junction between the first polysilicon layer 122 corresponding to the non-metallic region 12 and the substrate 100, thereby generating photogenerated carriers and improving the photoelectric conversion efficiency of the battery; it also makes the doping concentration of the first polysilicon layer 122 lower, thereby having lower parasitic absorption and carrier recombination losses, thereby reducing optical losses.

[0055] In some embodiments, the doping concentration of aluminum element may be 1×10 18 cm -3 , 3×10 18 cm -3 , 6×10 18 cm -3 , 8×10 18 cm -3 , 2×10 19 cm -3 , 5×10 19 cm -3 ,9×10 19 cm -3 , 3×10 20 cm -3 , 6×10 20 cm -3or 1×10 21 cm -3 .

[0056] In some embodiments, the thickness of the first polysilicon layer 122 is 20 nm to 500 nm. The thickness range of the first polysilicon layer 122 can reduce the parasitic absorption of the first polysilicon layer 122, thereby reducing optical loss and improving photoelectric conversion efficiency.

[0057] The thickness of the first polysilicon layer 122 may be 20 nm, 110 nm, 180 nm, 210 nm, 250 nm, 280 nm, 320 nm, 380 nm, 430 nm, or 500 nm.

[0058] The doped semiconductor structure 130 has a doping element therein, and the doping element is a P-type doping element. A PN junction is formed between the doped semiconductor structure 130 and the substrate 100 , and the doped semiconductor structure 130 has an emitter therein.

[0059] The doping element may be boron, and the doped semiconductor structure 130 includes at least one of a single crystal silicon layer doped with boron, an amorphous silicon layer doped with boron, a microcrystalline silicon layer doped with boron, or a polycrystalline silicon layer doped with boron. Boron has a high solid solubility in semiconductor materials, and thus the doping concentration of the crystalline silicon layer (single crystal silicon layer, amorphous silicon layer, polycrystalline silicon layer, or microcrystalline silicon layer) doped with boron is high, that is, the doped semiconductor structure 130 is used as a local heavily doped region, which can make the contact resistance between the first electrode 106 and the doped semiconductor structure 130 low, forming a good ohmic contact.

[0060] The boron element has a relatively large segregation coefficient in silicon, so the resistivity of the crystalline silicon layer is uniform everywhere, and the resistance value of each region is the same, so that the first electrode 106 can have a higher contact performance when in contact with the doped semiconductor structure 130, thereby reducing electrical losses. Secondly, the boron element has a relatively large segregation coefficient in silicon, and in the process of preparing the doped semiconductor structure 130, it can be avoided that the concentration of the doped semiconductor structure 130 is low, and then the electric field force of the formed PN junction is weak, the carrier migration rate is low, and the final photoelectric conversion efficiency is affected.

[0061] In some embodiments, the doped semiconductor structure 130 may be doped with other P-type doping elements, such as any one of the III-group elements such as aluminum (Al), gallium (Ga), or indium (In).

[0062] The doped semiconductor structure 130 may include the following three situations.

[0063] First: In some embodiments, reference Figure 1, the doped semiconductor structure 130 includes: a second polysilicon layer 131, the second polysilicon layer 131 is located in the first polysilicon layer 122 corresponding to the metal area 11, the first electrode 106 is electrically connected to the second polysilicon layer 131, and the second polysilicon layer 131 is doped with a P-type doping element, and the doping concentration of the P-type doping element is greater than the doping concentration of the aluminum element. In other words, the second polysilicon layer 131 corresponding to the metal area 11 has a high doping concentration, and the first polysilicon layer 122 corresponding to the non-metallic area 12 has a low doping concentration. Then the first polysilicon layer 122 and the second polysilicon layer 131 not only act as a passivation layer to passivate the surface of the substrate 100, but the first polysilicon layer 122 and the second polysilicon layer 131 also act as an emitter together. Among them, the second polysilicon layer 131 serves as the heavily doped region in the emitter, namely the deep junction region, and the first polysilicon layer 122 serves as the lightly doped region in the emitter, namely the shallow junction region. The second polysilicon layer 131 and the first polysilicon layer 122 together constitute a selective emitter (SE). This structure can reduce the contact resistance of the silver-aluminum paste and the metal electrode contact area, while reducing the composite current density of the non-metallic electrode contact area, thereby increasing the open circuit voltage and fill factor of the battery, and thus improving the photoelectric conversion efficiency.

[0064] Figure 2 Another cross-sectional view of a solar cell provided in one embodiment of the present application.

[0065] Second: In some embodiments, reference Figure 2 The doped semiconductor structure 130 penetrates the thickness of the first polysilicon layer 122, and the doped semiconductor structure 130 also includes: a second tunneling dielectric layer 132, the second tunneling dielectric layer 132 is located in the first tunneling dielectric layer 121, the second polysilicon layer 131 is located on the second tunneling dielectric layer 132, and the second tunneling dielectric layer 132 is doped with P-type doping elements.

[0066] Figure 3 Another cross-sectional view of a solar cell provided in one embodiment of the present application.

[0067] Third: In some embodiments, reference Figure 3 The doped semiconductor structure 130 penetrates the thickness of the first tunnel dielectric layer 121 . The doped semiconductor structure 130 further includes: a diffusion layer 133 . The diffusion layer 133 is located in the substrate 100 . The diffusion layer 133 is doped with a P-type doping element.

[0068] In some embodiments, the doping depth of the diffusion layer 133 is 10 nm to 100 nm. The doping depth of the diffusion layer 133 may be 10 nm, 20 nm, 35 nm, 50 nm, 75 nm, 90 nm, or 100 nm.

[0069] In some embodiments, the second polysilicon layer 131 , the second tunnel dielectric layer 132 , and the diffusion layer 133 are all doped with aluminum.

[0070] It should be noted that for Figure 1 The second polysilicon layer 131 in the solar cell shown may be doped with aluminum; Figure 2 The second polysilicon layer 131 and the second tunnel dielectric layer 132 in the solar cell shown may be doped with aluminum.

[0071] In some embodiments, the second polysilicon layer includes: a first polysilicon portion, the first polysilicon portion is doped with a P-type doping element; a second polysilicon portion, the second polysilicon portion is doped with a P-type doping element and an aluminum element. Both the first polysilicon portion and the second polysilicon portion are used to increase the doping concentration of the second polysilicon layer corresponding to the metal region, thereby reducing the contact resistance.

[0072] Figure 4 A top view of a first surface of a solar cell provided in an embodiment of the present application.

[0073] In some embodiments, the shape of the doped semiconductor structure 130 may be Figure 4 The circle shown may also be a rectangle, an ellipse, a triangle, a hexagon, or any other shape, which is not limited in the present application. The present application also does not limit the size of the doped semiconductor structure 130 and the spacing between the doped semiconductor structures 130 and 130, and those skilled in the art may set them according to actual needs.

[0074] In some embodiments, the ratio R of the orthographic projection area of ​​the doped semiconductor structure 130 on the substrate 100 to the area of ​​the metal region 11 satisfies: 0%<R<100%. The ratio of the area of ​​the doped semiconductor structure 130 to the metal region 11 is within the above range, that is, most of the metal region 11 is the doped semiconductor structure 130, so as to reduce the contact resistance between the first electrode 106 and the doped semiconductor structure 130 to the greatest extent, thereby improving the photoelectric conversion efficiency of the battery.

[0075] Figure 5 Another top view of the first surface of a solar cell provided in an embodiment of the present application.

[0076] In some embodiments, in conjunction with reference Figure 1 and Figure 5, the first electrode 106 extends along the first direction Y, and also includes: a main grid line (not shown), the main grid line is located on the surface of the first passivation layer 105, the main grid line extends along the second direction X, and the main grid line contacts the first electrode 106; the doped semiconductor structure 130 is also located in part of the non-metallic area, that is, located in the main grid line area 13, and the positive projection of the doped semiconductor structure 130 on the surface of the substrate 100 is located within the positive projection of the main grid line on the surface of the substrate 100. In this way, the doped semiconductor structure 130 located in the main grid line area 13 can improve the carrier transmission capacity. In this way, the first polysilicon layer 122 corresponding to the non-metallic area 12 can generate photogenerated carriers, transport the carriers through the doped semiconductor structure 130, and then be collected by the first electrode 106, which can improve the photoelectric conversion efficiency of the battery. Moreover, the orthographic projection of the doped semiconductor structure 130 of the main grid line 13 on the surface of the substrate 100 is located within the orthographic projection of the main grid line on the surface of the substrate 100, which will not increase the shading area of ​​the solar cell, and thus will not have a large optical loss. Instead, it will accelerate the transmission rate of carriers and improve the photoelectric conversion efficiency.

[0077] In some embodiments, the ratio L of the orthographic projection area of ​​the doped semiconductor structure 130 on the substrate 100 to the area of ​​the main grid area 13 satisfies: 0%<L<100%. The ratio L of the area of ​​the doped semiconductor structure 130 to the main grid area 13 is within the above range, that is, most of the area of ​​the main grid area 13 is the doped semiconductor structure 130, so that without increasing the shielding area, a larger area in the non-metal area is used to increase the transmission rate of carriers, thereby improving the photoelectric conversion efficiency of the battery.

[0078] Continue to refer Figure 1 The first passivation layer 105 covers the surface of the first polysilicon layer 122 and the surface of the doped semiconductor structure 130 .

[0079] In some embodiments, the first passivation layer 105 may be a single-layer structure or a stacked-layer structure, and the material of the first passivation layer 105 may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride oxide, titanium oxide, hafnium oxide or aluminum oxide.

[0080] Continue to refer Figure 1 , the first electrode 106 serves as an electrode for collecting carriers. The first electrode 106 can be formed by sintering a burn-through type paste. The method for forming the first electrode 106 includes: printing a metal paste on a surface of a portion of the anti-reflection layer using a screen printing process. The metal paste may include at least one of silver, aluminum, copper, tin, gold, lead or nickel. Then, a sintering process is performed on the metal paste, and the metal paste contains a material with highly corrosive components such as glass powder. In this way, during the sintering process, the corrosive components will corrode the first passivation layer 105, so that the metal paste penetrates into the first passivation layer 105 and makes electrical contact with the doped semiconductor structure 130.

[0081] In some embodiments, the first electrode 106 may be formed by sintering LECO (Laser-enhanced contact optimization) slurry, and part of the LECO slurry corrodes and penetrates into the first passivation layer 105 and contacts the doped semiconductor structure 130 or forms an electrical connection with the doped semiconductor structure 130 through crystals.

[0082] It should be noted that the substrate 100 includes a first surface and a second surface, and the above-mentioned various film layers are located on the first surface or the second surface of the substrate 100. The embodiment of the present application takes the first surface as the front surface, the second surface as the back surface, the above-mentioned various film layers are located on the first surface, and the first electrode is a front electrode as an example. The first surface is not described as the back surface, the second surface is the front surface, the above-mentioned various film layers are located on the first surface, and the first electrode is the back electrode, which is also within the scope of the embodiment of the present application.

[0083] In some embodiments, the first surface of the substrate 100 has a velvet structure 111, and the velvet structure 111 includes a plurality of protrusion structures 101. The inclined surfaces of the protrusion structures 101 can increase the internal reflection of the incident light, thereby improving the utilization rate of the incident light and improving the photoelectric conversion efficiency.

[0084] Continue to refer Figure 1 The solar cell further includes: a third tunneling dielectric layer 141, which is located on the second surface of the substrate 100; a doped semiconductor layer 142, which is located on the surface of the third tunneling dielectric layer 141; a second passivation layer 115, which is located on the surface of the doped semiconductor layer 142; and a second electrode 116, which is located on the surface of the second passivation layer 115 and is electrically connected to the doped semiconductor layer 142.

[0085] It should be noted that the content of the third tunnel dielectric layer 141 may refer to the content of the first tunnel dielectric layer 121 , which will not be described in detail here.

[0086] The doped semiconductor layer 142 has a field passivation effect. Specifically, an electrostatic field pointing to the inside of the substrate 100 is formed on the surface of the substrate 100, so that minority carriers escape from the interface, thereby reducing the minority carrier concentration, so that the carrier recombination rate at the interface of the substrate 100 is reduced, thereby increasing the open circuit voltage, short circuit current and fill factor of the solar cell, and improving the photoelectric conversion efficiency of the solar cell.

[0087] In some embodiments, the substrate 100 is doped with N-type doping elements, and the doping elements in the doped semiconductor layer 142 have the same conductivity type as the doping elements in the substrate 100 , that is, the doped semiconductor layer 142 is doped with N-type doping elements.

[0088] The concentration of the doping elements in the doped semiconductor layer 142 is greater than the concentration of the doping elements in the substrate 100, and a high-low junction is formed between the doped semiconductor layer 142 and the substrate 100. Under the electric field formed by the high-low junction, a sufficiently high potential barrier can be formed on the surface of the substrate 100, so that the majority carriers in the substrate 100 can pass through the third tunneling dielectric layer 141 to the doped semiconductor layer 142, which is beneficial to improving the carrier mobility.

[0089] In some embodiments, the doped semiconductor layer 142 includes at least one of a doped amorphous silicon layer, a doped polycrystalline silicon layer, a doped microcrystalline silicon layer, or a doped silicon carbide layer.

[0090] In some embodiments, the second passivation layer 115 may be a single-layer structure or a stacked-layer structure, and the material of the second passivation layer 115 may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride oxide, titanium oxide, hafnium oxide or aluminum oxide.

[0091] In some embodiments, the second electrode 116 can be formed by sintering a burn-through paste. The method for forming the second electrode 116 includes: printing a metal paste on a portion of the back passivation layer surface using a screen printing process. The metal paste may include at least one of silver, aluminum, copper, tin, gold, lead or nickel. Then, the metal paste is subjected to a sintering process, and the metal paste contains a material with a highly corrosive component such as glass powder. In this way, during the sintering process, the corrosive component will corrode the second passivation layer 115, so that the metal paste penetrates into the second passivation layer 115 and is in electrical contact with the doped semiconductor layer 142.

[0092] In some embodiments, the second electrode 116 may be formed by sintering LECO slurry, and a portion of the LECO slurry corrodes the second passivation layer 115 to contact with the doped semiconductor layer 142 or to form an electrical connection with the doped semiconductor layer 142 through crystals.

[0093] In the solar cell provided in the embodiment of the present application, the solar cell has a metal region 11 and a non-metal region 12, respectively, and the entire surface has a first tunnel dielectric layer 121 and a first polysilicon layer 122. The double passivation effect of the first tunnel dielectric layer 121 and the first polysilicon layer 122 can effectively reduce the carrier recombination rate of the substrate 100, thereby improving the cell conversion efficiency. In addition, the first polysilicon layer 122 is doped with aluminum, and the solid solubility of aluminum in polysilicon is low, so that a polysilicon layer with a low doping concentration can be obtained more easily, and the non-metallic region can avoid the recombination loss caused by the high doping concentration. Moreover, the polysilicon layer containing aluminum elements has a good degree of doping (high minority carrier lifetime), so that the substrate 100 can be better passivated, thereby improving the conversion efficiency of the battery; the surface of the substrate 100 corresponding to the metal area also has a doped semiconductor structure 130, and the P-type doping elements in the doped semiconductor structure can provide more P-type ions, so that it can exist as a PN junction, effectively generate and separate photogenerated carriers, and the first electrode 106 is electrically connected to the doped semiconductor structure 130, so as to have a lower contact resistance and reduce electrical losses.

[0094] According to some embodiments of the present application, on the other hand, the embodiments of the present application further provide a method for preparing a solar cell, which is used to prepare the solar cell provided by the above embodiments. The technical features that are the same or corresponding to the above embodiments will not be described in detail here.

[0095] Figures 6 to 10 A cross-sectional view of a solar cell corresponding to each step in a method for preparing a solar cell provided in another embodiment of the present application.

[0096] refer to Figure 6 as well as Figure 7 The preparation method includes providing a substrate 100, and the surface of the substrate 100 has metal areas 11 and non-metal areas 12 arranged alternately.

[0097] refer to Figure 7 The preparation method includes performing a texturing process on one side of the substrate 100 so that one side of the substrate 100 has a suede structure 111. The suede structure 111 includes a plurality of first protrusion structures 101.

[0098] In some embodiments, the texturing treatment includes: chemical etching, for example, a mixed solution of potassium hydroxide and hydrogen peroxide solution can be used to clean the substrate 100, and the suede structure with the expected morphology can be formed by controlling the concentration ratio of potassium hydroxide and hydrogen peroxide solution. In some embodiments, the suede structure can also be formed by laser etching, mechanical method or plasma etching. In laser etching, the suede structure with the expected morphology is obtained by controlling the laser process parameters.

[0099] refer to Figure 8 and Fig. 9 The preparation method includes forming a first tunnel dielectric layer 121, and the first tunnel dielectric layer 121 is located on the surface of the substrate 100. The preparation method includes forming a first polysilicon layer 122, and the first polysilicon layer 122 is located on the surface of the first tunnel dielectric layer 121, and the first polysilicon layer 122 is doped with aluminum. The preparation method includes forming at least one doped semiconductor structure, the doped semiconductor structure is located in the first polysilicon layer 122 corresponding to the metal region, and extends from the surface of the first polysilicon layer 122 away from the substrate 100 toward the substrate 100, and the doped semiconductor structure has a P-type doping element.

[0100] refer to Figure 8 , forming an oxide layer 102 , wherein the oxide layer 102 is located on the surface of the substrate 100 .

[0101] The oxide layer 102 is formed by an oxidation process, a heat treatment process or a deposition process.

[0102] Continue to refer Figure 8 , forming a polysilicon film 103 doped with aluminum element, and the polysilicon film 103 is located on the surface of the oxide layer 102.

[0103] There are two methods for forming the polysilicon film 103, which will be described in detail below.

[0104] The first one: using diffusion process.

[0105] The preparation method includes: forming a semiconductor film, which is an intrinsic polysilicon film, and performing an ion implantation process on the semiconductor film to transform the intrinsic polysilicon film into a polysilicon film 103 doped with aluminum.

[0106] Since the aluminum element does not require a high-temperature activation process, that is, no subsequent high-temperature activation step is required, the number of high-temperature treatments of the solar cell is reduced, reducing the thermal damage to the solar cell.

[0107] In some other embodiments, the preparation method includes: forming a semiconductor film, the semiconductor film is an intrinsic polysilicon film; forming a doping source layer, the doping source layer contains aluminum; performing a laser doping process on the semiconductor film to diffuse the aluminum element in the doping source layer into the intrinsic polysilicon film, so that the intrinsic polysilicon film is converted into a polysilicon film 103 doped with aluminum element.

[0108] The second method uses the AIC (aluminum-induced crystallization) process.

[0109] The preparation method includes: forming a semiconductor film, which is an intrinsic amorphous silicon (a-Si) film. Forming a doping source layer, which is an aluminum layer; performing a low-temperature induction process on the semiconductor film, so that Al atoms diffuse into a-Si through the Al / a-Si interface, so that the Si-Si covalent bond is transformed into a Si-Al metal bond. The silicide formed near the interface further accelerates the mutual diffusion between Al atoms and Si atoms, resulting in the formation of a Si-Al mixed phase. Since the solid solubility of Si in Al is almost negligible at low temperatures, the supersaturated Si in Al will precipitate and nucleate from the Al / a-Si interface, and the crystal nucleus will gradually grow and finally form polycrystalline silicon. While the supersaturated Si precipitates from the Si-Al mixed phase in the form of nuclei, the remaining Al atoms tend to move to the surface of the sample and eventually precipitate all on the top layer. That is, the intrinsic polycrystalline silicon film is converted into a polycrystalline silicon film 103 doped with aluminum elements.

[0110] The polysilicon film prepared by the AIC process is thinner and has a lower annealing temperature. The crystallized polysilicon layer has a high degree of crystallization and good crystal orientation. In other words, the prepared polysilicon film 103 has fewer physical defects.

[0111] In some embodiments, after forming the polysilicon film 103 , the aluminum layer on the surface may be removed; or the aluminum layer on the surface may be oxidized to form an aluminum oxide layer.

[0112] refer to Fig. 9 The preparation method includes: performing an ion implantation process on the polysilicon film 103 in the metal region of a partial area to form a doped semiconductor structure 130, that is, Figure 1 In this process, the doping elements in the polysilicon film 103 may diffuse into the oxide layer and form a second tunnel dielectric layer, that is, Figure 2 The solar cell shown in FIG. 1 continues to diffuse into the substrate to form a diffusion layer, that is, Figure 3 The solar cell shown.

[0113] In some embodiments, the polysilicon film and the oxide film corresponding to the metal region may be removed to form a new film layer structure, ie, a doped semiconductor structure 130 , in which no aluminum element is contained.

[0114] It should be noted that, in the solar cell after the diffusion process, the remaining oxide layer serves as the first tunnel dielectric layer, and the remaining polysilicon film serves as the first polysilicon layer.

[0115] refer to Figure 1The preparation method includes: forming a first passivation layer 105, the first passivation layer is located on the surface of the first polysilicon layer and the surface of the doped semiconductor structure. The preparation method includes: forming a first electrode 106, the first electrode 106 is located on the surface of the first passivation layer 105 corresponding to the metal region 11, and the first electrode 106 is electrically connected to the doped semiconductor structure 130.

[0116] Continue to refer Figure 1 The preparation method includes: forming a third tunneling dielectric layer 141, the third tunneling dielectric layer 141 is located on the second surface of the substrate 100; forming a doped semiconductor layer 142, the doped semiconductor layer 142 is located on the surface of the third tunneling dielectric layer 141; forming a second passivation layer 115, the second passivation layer 115 is located on the surface of the doped semiconductor layer 142; forming a second electrode 116, the second electrode 116 is located on the surface of the second passivation layer 115, and the second electrode 116 is electrically connected to the doped semiconductor layer 142.

[0117] The method for preparing a solar cell provided in the embodiment of the present application forms the first polysilicon layer 122 through a diffusion process and an AIC process, thereby avoiding a high-temperature activation step and reducing the preparation cost.

[0118] According to some embodiments of the present application, another aspect of the embodiments of the present application further provides a stacked battery.

[0119] Fig.10 A cross-sectional view of a stacked battery provided in yet another embodiment of the present application.

[0120] refer to Fig.10 The stacked battery includes: a bottom battery 150, which is a solar cell as in any one of the above embodiments or a solar cell prepared by the preparation method as in any one of the above embodiments; a top battery 180, which is located on a side of the substrate 100 in the bottom battery 150 away from the first electrode 106.

[0121] In some embodiments, the stacked battery has a first gridline 186 of a first polarity and a second gridline of a second polarity, wherein the first gridline 186 is in electrical contact with the top battery 180 and the second gridline is in electrical contact with the bottom battery 150. The second gridline is the first electrode 106 of the bottom battery.

[0122] In some embodiments, an interface layer 181 is provided between the top cell and the bottom cell, and the interface layer 181 also covers the passivation contact structure on the back side, that is, covers the doped conductive layer 130 .

[0123] It is worth noting that the stacked cell in the embodiment of the present application only illustrates two layers of solar cells, and those skilled in the art can set three layers of solar cells or more than three layers of stacked solar cells according to actual needs.

[0124] In some embodiments, the top cell 180 may be a perovskite solar cell, which includes: a stacked first transmission layer 182, a perovskite substrate 183, a second transmission layer 184, a transparent conductive layer 185, and an anti-reflection layer (not shown), wherein the first transmission layer is opposite to the bottom cell.

[0125] In some embodiments, the first transport layer may be one of an electron transport layer and a hole transport layer, and the second transport layer may be the other of the electron transport layer and the hole transport layer.

[0126] Accordingly, according to some embodiments of the present application, the embodiments of the present application further provide a photovoltaic module, including the solar cell provided in the above embodiments, and the technical features that are the same as or corresponding to the above embodiments are not described in detail here.

[0127] Fig.11 A schematic diagram of the structure of a photovoltaic module provided in yet another embodiment of the present application; Fig.12 for Fig.11 A cross-section along the M1-M2 section.

[0128] refer to Fig.11 and Fig.12 The photovoltaic module includes: a battery string, the battery string is composed of a plurality of solar cells 20 as in any one of the above embodiments; a packaging film 21, used to cover the surface of the battery string; a cover plate 22, used to cover the surface of the packaging film 21 away from the battery string.

[0129] Specifically, in some embodiments, multiple cells can be electrically connected through a connecting member 218, and the connecting member 218 is welded to a main grid on the cell. The main grid includes a main electrode electrically connected to the first electrode 106 and a main electrode electrically connected to the second electrode 116.

[0130] In some embodiments, no intervals are set between the battery cells, that is, the battery cells overlap each other.

[0131] In some embodiments, the connection component 218 is welded to the secondary grid 208 on the solar cell, and the secondary grid 208 includes the first electrode 106 and the second electrode 116 .

[0132] In some embodiments, the encapsulation film 21 includes a first encapsulation layer and a second encapsulation layer, the first encapsulation layer covers one of the front side or the back side of the solar cell, and the second encapsulation layer covers the other of the front side or the back side of the solar cell. Specifically, at least one of the first encapsulation layer or the second encapsulation layer can be an organic encapsulation film such as a polyvinyl butyral (PVB) film, an ethylene-vinyl acetate copolymer (EVA) film, a polyethylene octene co-elastomer (POE) film or a polyethylene terephthalate (PET) film.

[0133] It is worth noting that there is a boundary line between the first encapsulation layer and the second encapsulation layer before lamination. After lamination, the photovoltaic module is no longer a first encapsulation layer and a second encapsulation layer, that is, the first encapsulation layer and the second encapsulation layer have formed an integral encapsulation film 21.

[0134] In some embodiments, the cover plate 22 may be a glass cover plate, a plastic cover plate or the like with a light-transmitting function. Specifically, the surface of the cover plate 22 facing the encapsulation film 21 may be a concave-convex surface, thereby increasing the utilization rate of the incident light. The cover plate 22 includes a first cover plate and a second cover plate, the first cover plate is opposite to the first encapsulation layer, and the second cover plate is opposite to the second encapsulation layer; or the first cover plate is opposite to one side of the solar cell, and the second cover plate is opposite to the other side of the solar cell.

[0135] Those skilled in the art will appreciate that the above-mentioned embodiments are specific examples for implementing the present application, and in practical applications, various changes may be made to the embodiments in form and detail without departing from the spirit and scope of the present application. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present application, and therefore the scope of protection of the present application shall be subject to the scope defined in the claims.

Claims

1. A solar cell, characterized in that: include: A substrate, wherein the surface of the substrate has metal areas and non-metal areas arranged alternately; A first tunneling dielectric layer, wherein the first tunneling dielectric layer is located on the surface of the substrate; a first polysilicon layer, wherein the first polysilicon layer is located on a surface of the first tunnel dielectric layer, and the first polysilicon layer is doped with aluminum; at least one doped semiconductor structure, the doped semiconductor structure being located in the first polysilicon layer corresponding to the metal region and extending from a surface of the first polysilicon layer away from the substrate toward the substrate, the doped semiconductor structure having a P-type doping element; A first passivation layer, the first passivation layer is located on a surface of the first polysilicon layer and a surface of the doped semiconductor structure; A first electrode is located on a surface of the first passivation layer corresponding to the metal region, and the first electrode is electrically connected to the doped semiconductor structure.

2. The solar cell according to claim 1, characterized in that The doped semiconductor structure includes: a second polysilicon layer, the second polysilicon layer is located in the first polysilicon layer corresponding to the metal area, the first electrode is electrically connected to the second polysilicon layer, the second polysilicon layer is doped with the P-type doping element, and the doping concentration of the P-type doping element is greater than the doping concentration of the aluminum element.

3. The solar cell according to claim 2, characterized in that: The doped semiconductor structure penetrates the thickness of the first polysilicon layer, and the doped semiconductor structure also includes: a second tunneling dielectric layer, the second tunneling dielectric layer is located in the first tunneling dielectric layer, the second polysilicon layer is located on the second tunneling dielectric layer, and the second tunneling dielectric layer is doped with the P-type doping element.

4. The solar cell according to claim 3, characterized in that: The doped semiconductor structure penetrates the thickness of the first tunnel dielectric layer. The doped semiconductor structure further includes a diffusion layer, which is located in the substrate and is doped with the P-type doping element.

5. The solar cell according to claim 4, characterized in that: The doping depth of the diffusion layer is 10nm-100nm.

6. The solar cell according to claim 4, characterized in that: The second polysilicon layer, the second tunnel dielectric layer and the diffusion layer are all doped with the aluminum element.

7. The solar cell according to claim 2, characterized in that: The second polysilicon layer includes: a first polysilicon portion, in which the P-type doping element is doped; a second polysilicon portion, in which the P-type doping element and the aluminum element are doped.

8. The solar cell according to claim 1, characterized in that The ratio R of the orthographic projection area of ​​the doped semiconductor structure on the substrate to the area of ​​the metal region satisfies: 0%<R<100%.

9. The solar cell according to claim 1 or 8, characterized in that: The first electrode extends along a first direction and also includes: a main gate line, which is located on the surface of the first passivation layer, the main gate line extends along a second direction, and the main gate line is in contact with the first electrode; the doped semiconductor structure is also located in part of the non-metallic area, and the orthographic projection of the doped semiconductor structure on the surface of the substrate is located within the orthographic projection of the main gate line on the surface of the substrate.

10. A photovoltaic module, characterized in that: include: A battery string, the battery string being composed of a plurality of solar cells as claimed in any one of claims 1 to 9; A packaging film, used to cover the surface of the battery string; The cover plate is used to cover the surface of the packaging film facing away from the battery string.

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