Programmable state slope compensation circuit applied to PWM converter

Abstract

The invention provides a programmable slope compensation circuit applied to a PWM (Pulse Width Modulation) converter. The programmable slope compensation circuit specifically comprises a PWM converter U in a current mode; the device comprises a frequency resistor R1, a frequency resistor R4, a frequency capacitor C2, a slow charging and quick discharging circuit, a compensation depth circuit, a first output signal end U1 and a second output signal end U2, and the compensation depth circuit is composed of a first-stage attenuation network and a second-stage attenuation network. According to the programmable slope compensation circuit applied to the PWM converter, the compensation function can be achieved under various working conditions, the stability of the converter during working is improved, and when the converter works at a light load or a small duty ratio, due to the fact that the amplitude of a sampled current signal is low or the width is narrow, the stability of the converter is improved. Excessive noise picked up at a current sampling or voltage feedback input port is particularly prominent, the noise easily causes irregular pulse width jitter, and the jitter also causes instability of a system. The slope compensation of one depth is used as a bias superposition signal, so that jitter can be effectively suppressed, and meanwhile, the duty ratio precision of output PWM is not influenced.

Description

Technical Field

[0001] The invention relates to a programmable slope compensation circuit applied to a PWM converter. Background Art

[0002] When the traditional PWM converter is working, if the duty cycle is greater than 50% and the inductor current is in continuous mode, subharmonic oscillation will occur, causing system instability. This instability has nothing to do with the closed-loop feedback system of the system. It is caused by the simultaneous operation of fixed frequency and peak current sampling. Figure 1 As shown in the figure, at t0, the switch starts to conduct, causing the inductor current to rise with a slope of m1, which is a function of the voltage applied across the inductor divided by the inductance. At t1, the inductor current reaches the threshold established by the control voltage, causing the switch to be disconnected, and the current decays with a slope of m2 until the next oscillation cycle. If a disturbance is added to the control voltage, generating a small △I (shown by the dotted line in the figure), this unstable situation can be found: within a fixed oscillator cycle, the current decay time decreases, the minimum current rises by a △I+△I*m2 / m1 at the switch-on time t2, and the minimum current decreases to (△I+△I*m2 / m1)*(m2 / m1) at t3 of the next cycle... In each subsequent cycle, the disturbance is multiplied by m2 and m1, and the inductor current is alternately increased and decreased (i.e., large and small waves) when the switch is turned on, and the converter will become unstable.

[0003] Different from the traditional voltage-mode PWM converter, which directly controls the output pulse width of the modulated converter by a single closed-loop feedback signal, the current-mode PWM converter needs to sample the inductor current signal cycle by cycle to compare it with the feedback loop signal. The width of the converter's output pulse width signal is determined by this comparison result. When the converter works at a light load or a small duty cycle, the excessive noise picked up at the current sampling or voltage feedback input port is particularly prominent due to the low amplitude or narrow width of the sampled current signal. These noises can easily cause irregular pulse width jitter, which can also cause system instability. A deep slope compensation as a "bias superposition" signal can effectively suppress jitter without affecting the duty cycle accuracy of the output PWM;

[0004] However, it should be noted that excessive slope compensation will weaken the rapid load response characteristics of the current mode, making the converter more similar to the response characteristics of the traditional voltage mode converter; excessive slope compensation will also lead to an extension of the pulse width cycle dead time, which will reduce the duty cycle utilization rate in some wide-range applications. Insufficient slope compensation cannot effectively suppress the system instability caused by the latter jitter.

[0005] Usually, the slope compensation method recommended in the user manual given by chip manufacturers is a fixed-depth compensation (that is, the compensation depth does not change with the duty cycle and load current). This fixed compensation is difficult to take into account the above-mentioned two system instability solutions. In order to resolve this conflict, a dynamic slope compensation circuit that can be programmed in stages is needed. Summary of the invention

[0006] In view of this, the present invention provides a programmable slope compensation circuit applied to a PWM converter, which obtains a sawtooth wave with the same width and synchronization with the output pulse width after processing the output pulse width signal (PWM) of the controller, and attenuates the sawtooth wave and superimposes it on the current sampling signal, thereby achieving compensation.

[0007] The present invention provides a programmable slope compensation circuit for PWM converter, the specific structure of which includes:

[0008] A current mode PWM converter U for controlling the compensation signal;

[0009] A frequency resistor R4 and a frequency capacitor C2, used to set the operating frequency of the PWM converter U1, are respectively connected in parallel with the PWM converter;

[0010] A slow charge and fast discharge circuit is used to obtain a sawtooth ramp signal with the same width and synchronization with PWM. After attenuation, this signal is superimposed on the pin3 port of the PWM converter U (i.e. the current sampling vcs input terminal of the controller) to complete the slope compensation;

[0011] a compensation depth circuit, consisting of a primary attenuation network and a secondary attenuation network, determines the amplitude of the ramp signal;

[0012] A first output signal terminal U1 and a second output signal terminal U2, wherein the first output signal terminal U1 is a control signal related to the load current, and the second output signal terminal U2 is a control signal U2 related to the duty cycle. The first output signal terminal U1 is connected to the PWM converter U through the first transistor Q1, and the second output signal terminal U2 is connected to the PWM converter U through the second transistor Q2.

[0013] Furthermore, the slow charge and fast discharge circuit is connected to the PWM converter, including a diode D1, a first resistor R1, a second resistor R2 and a first capacitor C1; wherein the diodes D1 and R1 are connected in parallel with each other, one side is connected in series with the second resistor R2, and the other side is connected in series with the first capacitor C1.

[0014] Furthermore, one side of the second resistor R2 is connected to the pin6 port of the PWM control U (i.e., the signal output terminal out of the controller), one end of the first capacitor C1 is grounded, and the other end is connected together with the diode D1 and the first resistor R1 to the pin3 port of the PWM converter U (i.e., the current sampling vcs input terminal of the controller).

[0015] Furthermore, the resistance of the second resistor R2 is smaller than that of the first resistor R1, so as to reduce the interference caused by the voltage spike caused by di / dt on the line parasitic inductance when the first capacitor C1 is discharged quickly.

[0016] Furthermore, the first-level attenuation network includes a first resistor R1, a third resistor R3 and a sixth resistor R6; the third resistor R3 and the sixth resistor R6 are connected in parallel to each other, one end is connected in series with the first resistor R1, and the other end is respectively connected to the second output signal terminal U2 and the first output signal terminal U1, the third resistor R3 is connected to the second transistor Q2, and the sixth resistor R6 is connected to the first transistor Q1.

[0017] Furthermore, the secondary attenuation network includes a fifth resistor R5 and a ninth resistor R9, the fifth resistor R5 and the ninth resistor R9 are connected in parallel to each other and are both connected to the pin3 port of the PWM converter U (i.e., the current sampling vcs input terminal of the controller), one end of the fifth resistor R5 is connected to the primary attenuation network, and one end is connected to the ninth resistor R9, and the other end of the ninth resistor R9 is grounded.

[0018] Beneficial Effects

[0019] According to the present invention, a programmable slope compensation circuit applied to a PWM converter can realize the compensation function under various working conditions and improve the stability of the converter during operation. When the converter works at a light load or a small duty cycle, due to the low amplitude or narrow width of the sampled current signal, the excessive noise picked up at the current sampling or voltage feedback input port is particularly prominent. These noises are likely to cause irregular pulse width jitter, which can also cause system instability. Using a deep slope compensation as a "bias superposition" signal can effectively suppress jitter without affecting the duty cycle accuracy of the output PWM. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solution of the embodiment of the present invention, the drawings of the embodiment are briefly introduced below.

[0021] The drawings described below are only related to some embodiments of the present invention, but are not intended to limit the present invention.

[0022] In the attached picture:

[0023] Figure 1 A schematic diagram of a circuit structure according to an embodiment of the present invention is shown;

[0024] Reference numerals list

[0025] U. PWM converter, R4. frequency resistor, C2. frequency capacitor, U1. first output signal terminal, U2. second output signal terminal, Q1. first transistor, Q2. second transistor, D1. diode, R1. first resistor, R2. second resistor, C1. first capacitor, R1. first resistor, R3. third resistor, R6. sixth resistor, R5. fifth resistor, R9. ninth resistor. DETAILED DESCRIPTION

[0026] In order to make the purpose, scheme and advantages of the technical solution of the present invention clearer, the technical solution of the embodiment of the present invention will be clearly and completely described in conjunction with the drawings of the specific embodiments of the present invention. Unless otherwise specified, the terms used herein have the usual meanings in the art. The same reference numerals in the drawings represent the same components.

[0027] In one embodiment, Figure 1 As shown:

[0028] The present invention proposes a programmable slope compensation circuit for PWM converter, the specific structure of which includes:

[0029] A current mode PWM converter U for controlling the compensation signal;

[0030] A frequency resistor R4 and a frequency capacitor C2, used to set the operating frequency of the PWM converter U1, are respectively connected in parallel with the PWM converter;

[0031] A slow charge and fast discharge circuit is used to obtain a sawtooth ramp signal with the same width and synchronization with PWM. After attenuation, this signal is superimposed on the pin3 port of the PWM converter U (i.e. the current sampling vcs input terminal of the controller) to complete the slope compensation;

[0032] a compensation depth circuit, consisting of a primary attenuation network and a secondary attenuation network, determines the amplitude of the ramp signal;

[0033] A first output signal terminal U1 and a second output signal terminal U2, wherein the first output signal terminal U1 is a control signal related to the load current, and the second output signal terminal U2 is a control signal U2 related to the duty cycle. The first output signal terminal U1 is connected to the PWM converter U through the first transistor Q1, and the second output signal terminal U2 is connected to the PWM converter U through the second transistor Q2.

[0034] Furthermore, the slow charge and fast discharge circuit is connected to the PWM converter, including a diode D1, a first resistor R1, a second resistor R2 and a first capacitor C1; wherein the diodes D1 and R1 are connected in parallel with each other, one side is connected in series with the second resistor R2, and the other side is connected in series with the first capacitor C1.

[0035] Furthermore, one side of the second resistor R2 is connected to the pin6 port of the PWM control U (i.e., the signal output terminal out of the controller), one end of the first capacitor C1 is grounded, and the other end is connected together with the diode D1 and the first resistor R1 to the pin3 port of the PWM converter U (i.e., the current sampling vcs input terminal of the controller).

[0036] Furthermore, the resistance of the second resistor R2 is smaller than that of the first resistor R1, so as to reduce the interference caused by the voltage spike caused by di / dt on the line parasitic inductance when the first capacitor C1 is discharged quickly.

[0037] Furthermore, the first-level attenuation network includes a first resistor R1, a third resistor R3 and a sixth resistor R6; the third resistor R3 and the sixth resistor R6 are connected in parallel to each other, one end is connected in series with the first resistor R1, and the other end is respectively connected to the second output signal terminal U2 and the first output signal terminal U1, the third resistor R3 is connected to the second transistor Q2, and the sixth resistor R6 is connected to the first transistor Q1.

[0038] Furthermore, the secondary attenuation network includes a fifth resistor R5 and a ninth resistor R9, the fifth resistor R5 and the ninth resistor R9 are connected in parallel to each other and are both connected to the pin3 port of the PWM converter U (i.e., the current sampling vcs input terminal of the controller), one end of the fifth resistor R5 is connected to the primary attenuation network, and one end is connected to the ninth resistor R9, and the other end of the ninth resistor R9 is grounded.

[0039] The working principle of this embodiment:

[0040] U (UC3842) is a standard current mode PWM controller, R4, C2 set the operating frequency of the converter. The PWM voltage signal output from pin6 passes through the "slow charge and fast discharge" circuit composed of D1, R1, R2, and C1 (R2 has a small value, which is used to reduce the interference caused by the voltage spike caused by di / dt on the line parasitic inductance during rapid discharge of C1), and then a sawtooth ramp signal with the same width and synchronization with PWM is obtained at the Us lope point. After attenuation, this signal is superimposed on the pin3 port (that is, the current sampling vcs input terminal of the converter) to complete the slope compensation. The compensation depth (amplitude of the ramp signal) is determined by the first-level attenuation network composed of R1, R3, and R6 and the second-level attenuation network composed of R5 and R9. It should be noted that the purpose of R5 and R9 is not to be designed as an attenuator, but to couple with the current sampling signal vcs and perform impedance matching of the port, but it forms an attenuation network in structure, so it also affects the compensation depth of the ramp signal. Under normal working conditions, U1 and U2 are both high level, the two switches Q1 and Q2 composed of NMOS controlled by them are closed, R3 and R6 are connected to the reference ground GND, and the Uslope amplitude is attenuated to the maximum. At this time, the slope compensation of the converter is in shallow compensation. When the output load current or duty cycle is less than the set level, U1 and U2 are low level, and Q1 and Q2 are controlled to be closed to cut off R3 or R6 to change the attenuation ratio of the Uslope amplitude to match the slope compensation depth required by the converter under this working condition.

[0041] Finally, it should be noted that when describing the position of each component and the matching relationship between them, the present invention usually takes one / a pair of components as an example. However, those skilled in the art should understand that such position, matching relationship, etc. are also applicable to other components / other pairs of components.

[0042] The above description is merely an exemplary embodiment of the present invention and is not intended to limit the protection scope of the present invention. The protection scope of the present invention is determined by the appended claims.

Claims

1. A programmable slope compensation circuit for a PWM converter, characterized in that: The specific structure includes: a current mode PWM converter (U) for controlling the compensation signal; A frequency resistor (R4) and a frequency capacitor (C2), used for setting the operating frequency of the PWM converter (U), are respectively connected in parallel with the PWM converter; A slow charge and fast discharge circuit is used to obtain a sawtooth ramp signal with the same width and synchronization with PWM. After attenuation, this signal is superimposed on the pin3 port (i.e. the current sampling vcs input terminal of the controller) of the PWM converter (U) to complete the slope compensation; a compensation depth circuit, consisting of a primary attenuation network and a secondary attenuation network, determines the amplitude of the ramp signal; A first output signal terminal (U1) and a second output signal terminal (U2), wherein the first output signal terminal (U1) is a control signal related to a load current, and the second output signal terminal (U2) is a control signal related to a duty cycle. The first output signal terminal (U1) is connected to the PWM converter (U) through a first transistor (Q1), and the second output signal terminal (U2) is connected to the PWM converter (U) through a second transistor (Q2).

2. The programmable slope compensation circuit for PWM converter according to claim 1, characterized in that: The slow charge and fast discharge circuit is connected to the PWM converter, and comprises a diode (D1), a first resistor (R1), a second resistor (R2) and a first capacitor (C1); wherein the diodes (D1) and (R1) are connected in parallel with each other, one side is connected in series with the second resistor (R2), and the other side is connected in series with the first capacitor (C1).

3. The programmable slope compensation circuit for PWM converter according to claim 1, characterized in that: One side of the second resistor (R2) is connected to the pin6 port of the PWM control (U) (i.e., the signal output terminal out of the controller), one end of the first capacitor (C1) is grounded, and the other end is connected together with the diode (D1) and the first resistor (R1) to the pin3 port of the PWM converter (U) (i.e., the current sampling vcs input terminal of the controller).

4. The programmable slope compensation circuit for PWM converter according to claim 1, characterized in that: The resistance of the second resistor (R2) is smaller than that of the first resistor (R1), and its function is to reduce the interference caused by the voltage spike caused by di / dt on the line parasitic inductance when the first capacitor (C1) is discharged quickly.

5. The programmable slope compensation circuit for PWM converter according to claim 1, characterized in that: The first-level attenuation network comprises a first resistor (R1), a third resistor (R3) and a sixth resistor (R6); the third resistor (R3) and the sixth resistor (R6) are connected in parallel with each other, one end of which is connected in series with the first resistor (R1), and one end of which is respectively connected to the second output signal terminal (U2) and the first output signal terminal (U1); the third resistor (R3) is connected to the second transistor (Q2), and the sixth resistor (R6) is connected to the first transistor (Q1).

6. The programmable slope compensation circuit for PWM converter according to claim 1, characterized in that: The secondary attenuation network comprises a fifth resistor (R5) and a ninth resistor (R9), the fifth resistor (R5) and the ninth resistor (R9) are connected in parallel to each other and are both connected to the pin3 port of the PWM converter (U) (i.e., the current sampling VCS input terminal of the controller), one end of the fifth resistor (R5) is connected to the primary attenuation network, and one end is connected to the ninth resistor (R9), and the other end of the ninth resistor (R9) is grounded.

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