Dual mode amplifier circuit

Abstract

A dual mode amplifier circuit includes a high-side transistor employing an NMOS having a first end coupled to a second voltage signal, a second end coupled to a second voltage signal, and a control end; the low-end transistor adopts an NMOS and is provided with a first end, a second end and a control end, the first end of the low-end transistor is coupled to the second end of the high-end transistor, the second end of the low-end transistor is coupled to a first voltage signal, the switch driving circuit is provided with an input end, a first output end and a second output end, the first output end is coupled to the control end of the high-end transistor, and the second output end is coupled to the control end of the high-end transistor. The second output end is coupled to the control end of the low-end transistor; the linear driving circuit is provided with a first output end and a second output end, the first output end of the linear driving circuit is coupled with the control end of the high-end transistor, and the second output end of the linear driving circuit is coupled with the control end of the low-end transistor; two driving modes, namely a linear driving mode and a switching mode, of the NMOS amplifier are realized in the same circuit, and switching use can be carried out according to different application scenes.

Description

Technical Field

[0001] The present invention relates to the technical field of amplifier circuits, and in particular to a dual-mode amplifier circuit using NMOS as an output stage. Background Art

[0002] An amplifier is a device that can amplify the voltage, current or power of an input signal. It is composed of electron tubes or transistors and other electronic components. It is widely used in various devices such as communications, broadcasting, radar, television, and automatic control.

[0003] Among them, the class AB amplifier is a combination of class A and class B amplifiers, which can make the working ranges of the two transistors working in the push-pull working mode overlap each other, making up for the shortcomings of class A and class B amplifiers. The class D amplifier is an amplifier that drives the speaker by controlling the switch (ON / OFF) of the switch unit. Whether it is a class AB amplifier or a class D amplifier, its output stage includes high-end transistors and low-end transistors, among which high-end transistors often use PMOS tubes. For example, the high-end NMOS transistor switch drive circuit and class AB amplifier disclosed in the Chinese patent with patent number CN202011451032.5, the high-end NMOS transistor switch drive circuit and class AB amplifier disclosed in the Chinese patent with patent number CN202011451032.5, and the class AB amplifier disclosed in the Chinese patent with patent number CN200510098559.3 all use PMOS transistors as high-end transistors to facilitate driving.

[0004] However, since the electron mobility is much higher than the hole mobility, the on-resistance of the PMOS transistor of the same area is much higher than that of the NMOS transistor. Therefore, the use of the PMOS transistor as a high-end transistor results in large power loss and reduced efficiency. When using the NMOS transistor as a high-end transistor, a special driving circuit is required to drive the NMOS transistor. The existing driving circuit for the NMOS transistor cannot be directly applied to the high-end transistor using NMOS, and the driving mode is single and cannot be switched as needed. Summary of the invention

[0005] The present invention aims to solve at least one of the technical problems existing in the prior art.

[0006] To this end, the present invention provides a dual-mode amplifier circuit.

[0007] The dual-mode amplifier circuit proposed in the present invention includes: a high-end transistor, which adopts NMOS and has a first end, a second end and a control end, and its first end is coupled to a second voltage signal; a low-end transistor, which adopts NMOS and has a first end, a second end and a control end, and its first end is coupled to the second end of the high-end transistor, and its second end is coupled to the first voltage signal: a switch drive circuit, which has an input end, a first output end and a second output end, and its first output end is coupled to the control end of the high-end transistor, and its second output end is coupled to the control end of the low-end transistor; a linear drive circuit, which has a first output end and a second output end, and the first output end of the linear drive circuit is coupled to the control end of the high-end transistor, and the second output end is coupled to the control end of the low-end transistor.

[0008] Among them, when the dual-mode amplifier works in the linear working mode, the first output end and the second output end of the switch driving circuit are in a high-impedance state, and the linear driving circuit controls the high-end transistor and the low-end transistor; when the dual-mode amplifier works in the switching mode, the first output end and the second output end of the linear driving circuit are in a high-impedance state, and the switch driving circuit controls the high-end transistor and the low-end transistor.

[0009] In summary, due to the adoption of the above technical features, the beneficial effects of the present invention are:

[0010] Two driving modes of the NMOS amplifier, namely the linear driving mode and the switching mode, are implemented in the same circuit, and can be switched for use according to different application scenarios, with good applicability and reliable switching mode. The present invention also effectively prevents the low-end transistor from being erroneously turned on or generating spikes due to the charging of the Miller capacitor during the high-end transistor turning on process by designing an enhanced turn-off unit.

[0011] Additional aspects and advantages of the present invention will become apparent from the following description or may be learned by practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0013] Figure 1 is a circuit diagram of an amplifier 10 according to an embodiment of the present invention;

[0014] Figure 2 is a schematic diagram of a linear drive circuit 20 according to an embodiment of the present invention;

[0015] Figure 3 is a circuit schematic diagram of a high-side switch driving circuit 30 according to an embodiment of the present invention;

[0016] Figure 41 is a schematic diagram of waveforms of a switch signal, a control signal and a current signal in a high-end switch driving circuit according to an embodiment of the present invention;

[0017] Figure 5 is a schematic diagram of the overall structure of an NMOS dual-mode amplifier circuit 50 according to an embodiment of the present invention;

[0018] Figure 6 FIG. 6 is a schematic diagram of a switch driving circuit 60 in an NMOS dual-mode amplifier circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0019] In order to more clearly understand the above-mentioned purpose, features and advantages of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the embodiments of the present application and the features in the embodiments can be combined with each other without conflict.

[0020] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention can also be implemented in other ways different from those described herein, and therefore, the scope of protection of the present invention is not limited by the specific embodiments disclosed below. References to "one embodiment" or "an embodiment" throughout the specification mean that the specific features, structures or characteristics described in conjunction with the embodiment are included in at least one embodiment of the present invention. Therefore, the phrases "in one embodiment" or "in an embodiment" that appear throughout this specification do not necessarily all refer to the same embodiment. The verbs "include" and "have" are used as open restrictions in this article, which neither exclude nor require the presence of undescribed features. Unless otherwise expressly stated, the features recorded in the dependent claims can be freely combined with each other. The elements defined by "one" or "one" (i.e., singular form) throughout the document do not exclude the possibility of multiple such elements. Further, the described features, structures or characteristics can be combined in any suitable manner in one or more embodiments. Unless otherwise specified, the terms "connect" and "couple" are used to specify electrical connections between circuit elements that can be direct or can be via one or more other elements. In contrast, when an element is referred to as being "directly connected to" or "directly coupled to" another element, there are no intervening elements present. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0021] Refer to the following Figures 1 to 6 A dual-mode amplifier circuit according to some embodiments of the present invention is described.

[0022] Using NMOS tubes as amplifiers for high-end transistors and low-end transistors, such as Figure 1As shown, the amplifier circuit includes a linear drive circuit and an output stage, wherein the linear drive circuit includes a first transistor N1, a second transistor N2, a first amplifier J1 and a second amplifier J2, and the output stage includes a high-end transistor N3 and a low-end transistor N4.

[0023] The first transistor N1 has a first terminal, a second terminal and a control terminal. The first terminal of the first transistor N1 is coupled to the high voltage signal BST through the first current source I1, and the control terminal of the first transistor N1 is connected to the first terminal of the first transistor N1. In some embodiments, the first terminal of the first transistor N1 can also be coupled to the high voltage signal BST through a passive device such as a first resistor. In some embodiments, the first transistor N1 adopts an NMOS tube, and the first terminal, the second terminal and the control terminal of the first transistor N1 correspond to the drain, the source and the gate of the NMOS tube respectively.

[0024] The second transistor N2 has a first end, a second end and a control end. The first end of the second transistor N2 is coupled to the second end of the first transistor N1, the second end of the second transistor N2 is coupled to the first voltage signal VSS, and the control end of the second transistor N2 receives the second amplified signal; in some embodiments, the second transistor N2 adopts an NMOS tube, and the first end, the second end and the control end of the second transistor N2 correspond to the drain, the source and the gate of the NMOS tube respectively. Among them, the second amplified signal is used to control the gate of the second transistor N2. In some embodiments, the first voltage signal VSS can be a reference ground, and in other embodiments, the first voltage signal VSS can also be a negative power supply or other power supply. In some embodiments, the first end of the second transistor is directly electrically connected to the second end of the first transistor, and in other embodiments, the first end of the second transistor can be coupled to the second end of the first transistor through devices such as resistors and transistors. In other embodiments, the second transistor can also adopt an NPN transistor.

[0025] In some embodiments, the second amplified signal is generated by the second amplifier J2, the second amplifier J2 has a first input terminal, a second input terminal and an output terminal, the first input terminal of the second amplifier J2 receives the analog input signal AIN, the second input terminal of the second amplifier J2 is coupled to the output terminal of the amplifier circuit 10 to receive the voltage output signal V0, and the output terminal of the second amplifier J2 provides the second amplified signal. In a specific embodiment, the second amplifier J2 has a non-inverting input terminal, an inverting input terminal and an output terminal, the non-inverting input terminal of the second amplifier receives the analog input signal AIN, and the analog input signal AIN can be an audio signal, etc.; the inverting input terminal of the second amplifier receives the voltage output signal V0, and the output terminal of the second amplifier outputs the second amplified signal according to the voltage difference between the analog input signal AIN and the voltage output signal V0, and the output terminal of the second amplifier is coupled to the gate of the second transistor N2. It can be understood that in other embodiments, the non-inverting input terminal of the second amplifier can also be connected to the voltage output signal V0, and the inverting input terminal can be connected to the analog input signal AIN, as long as it is ensured that the entire amplifier circuit 10 constitutes negative feedback so that the voltage output signal V0 changes with the analog input signal AIN.

[0026] Figure 2 FIG. 2 is a schematic diagram of a linear drive circuit 20 according to an embodiment of the present invention. Figure 2 As shown, the second amplifier J2 includes a third transistor PM15, a fourth transistor PM11, a fifth transistor PM17, a sixth transistor PM18, a seventh transistor NM26 and an eighth transistor NM0. The third transistor PM15 has a first end, a second end and a control end. The second end of the third transistor PM15 is coupled to the high voltage signal BST, and the control end is coupled to the control end of the sixtieth transistor PM8 to mirror the first input current signal IBN, providing bias current for the fifth transistor PM17 and the sixth transistor PM18; the fourth transistor PM11 has a first end, a second end and a control end, and its second end is coupled to the first end of the third transistor PM15. The control end of the fourth transistor PM11 is coupled to the control end of the sixtieth transistor PM9. The fourth transistor PM11 improves the accuracy of the current mirror of the third transistor PM15. In some embodiments, the fourth transistor PM11 can be ignored; the fifth transistor PM17 has a first end, a second end and a control end. The second end of the fifth transistor PM17 is coupled to the first end of the fourth transistor PM11. The control end of the fifth transistor PM17 is connected to the control end of the sixtieth transistor PM9. Figure 2 The INN terminal shown receives the analog input signal AIN; the sixth transistor PM18 has a first terminal, a second terminal and a control terminal, the second terminal of the sixth transistor PM18 is coupled to the first terminal of the fourth transistor PM11, and the control terminal of the sixth transistor PM18 is connected to the first terminal of the fourth transistor PM11. Figure 2The INP terminal shown receives the voltage output signal V0; the seventh transistor NM26 has a first terminal, a second terminal and a control terminal, the first terminal of the seventh transistor NM26 is coupled to the first terminal of the fifth transistor PM17, the second terminal of the seventh transistor NM26 is coupled to the first voltage signal, and the control terminal of the seventh transistor NM26 is coupled to the first terminal of the seventh transistor NM26; the eighth transistor NM0 has a first terminal, a second terminal and a control terminal, the first terminal of the eighth transistor NM0 is coupled to the first terminal of the sixth transistor PM18, and provides a second amplified signal, the second terminal of the eighth transistor NM0 is coupled to the first voltage signal VSS, and the control terminal of the eighth transistor NM0 is coupled to the control terminal of the seventh transistor NM26.

[0027] Among them, the high voltage signal BST is connected through the third transistor PM15 and the fourth transistor PM11 to provide bias current for the entire second amplifier; the fifth transistor PM17 and the sixth transistor PM18 are differential pairs, the control end of the fifth transistor PM17 is used as the in-phase input end of the second amplifier, and the analog input signal AIN is connected, and the control end of the sixth transistor PM18 is used as the inverting input end of the second amplifier, and the voltage output signal V0 is connected. The seventh transistor NM26 and the eighth transistor NM0 form an NMOS current mirror as the load of the second amplifier J2. In another specific embodiment, the second amplifier J2 also includes a diode D5 and a diode D6, which are reversely connected in series between the control end of the fifth transistor PM17 and the control end of the sixth transistor PM18, and play a protective role to prevent the voltage difference at the input end of the second amplifier J2 from being too large, causing damage to the device. In the above-mentioned second amplifier J2, the common end of the sixth transistor PM18 and the eighth transistor NM0 is used as the output end of the second amplifier J2, and is coupled to the gate of the second transistor N2.

[0028] Continue reading Figure 1 , wherein the high-end transistor N3 adopts an NMOS tube, having a first end, a second end and a control end, which correspond to the drain, source and gate of the NMOS tube respectively; the first end of the high-end transistor N3 is coupled to the second voltage signal VCC, the second end of the high-end transistor N3 is configured as the output end of the amplifier circuit 10 to provide the voltage output signal V0, and the control end of the high-end transistor N3 is coupled to the drain of the first transistor N1; the voltage of the high voltage signal BST is higher than the second voltage signal VCC. The low-end transistor N4 adopts an NMOS tube, having a first end, a second end and a control end, which correspond to the drain, source and gate of the NMOS tube respectively; the first end of the low-end transistor N4 is coupled to the second end of the high-end transistor N3, the second end of the low-end transistor N4 is coupled to the first voltage signal VSS, and the control end of the low-end transistor N4 receives the first amplified signal.

[0029] The first amplified signal is generated by the first amplifier J1. Specifically, the first amplifier J1 has a first input terminal, a second input terminal and an output terminal. The first input terminal of the first amplifier J1 is coupled to the second terminal of the first transistor N1, the second input terminal of the first amplifier J1 is coupled to the second terminal of the high-end transistor N3, and the output terminal of the first amplifier J1 outputs the first amplified signal. The first amplifier J1 and the low-end transistor N4 form a negative feedback loop, so that the voltages of the two input terminals of the first amplifier J1 are equal, that is, the voltage of the second terminal of the first transistor N1 is equal to the voltage of the second terminal of the high-end transistor N3.

[0030] In a specific embodiment, the first amplifier J1 has a non-inverting input terminal, an inverting input terminal and an output terminal. The inverting input terminal of the first amplifier is coupled to the second terminal of the first transistor N1, the non-inverting input terminal of the first amplifier is coupled to the second terminal of the high-end transistor N3, and the output terminal of the first amplifier outputs a first amplified signal. The first amplified signal controls the low-end transistor N4 so that the voltage at the second terminal of the first transistor N1 is equal to the voltage at the second terminal of the high-end transistor N3. Since the control terminal voltages of the first transistor N1 and the high-end transistor N3 are equal, the gate-source voltage difference of the first transistor N1 and the high-end transistor N3 is equal, so that the current per unit area of ​​the high-end transistor N3 is equal to the current per unit area of ​​the first transistor N1. Further, the current on the first transistor N1 is the current provided by the first current source I1. The current flowing through the high-end transistor N3 can be obtained according to the ratio of the width-to-length ratio of the high-end transistor N3 and the first transistor N1, that is, Figure 1 The quiescent current of the amplifier circuit in Figure 1 In the illustrated embodiment, the first transistor N1 and the high-side transistor N3 are both NMOS transistors. In other embodiments, the first transistor N1 and the high-side transistor N3 may also be both NPN transistors.

[0031] Through the above configuration, the first amplifier J1, the second amplifier J2 and the transistors N1-N4 together form a negative feedback loop, so that the voltages at the two input terminals of the second amplifier J2 are equal, that is, the voltage output signal V0 changes with the analog input signal AIN. In some embodiments, according to the actual needs of the circuit, the voltage output signal V0 can also be coupled to the input terminal of the second amplifier J2 after being divided by a resistor, so that the voltage output signal V0 has a multiple relationship with the analog input signal AIN. Therefore, the second amplifier J2 coupling the voltage output signal V0 does not mean that it must directly receive the voltage output signal V0, but can also receive the amplified and reduced voltage output signal V0.

[0032] Continue reading Figure 2In a specific embodiment, the first amplifier J1 includes: a ninth transistor PM2, a tenth transistor PM3, an eleventh transistor PM12, a twelfth transistor PM10, a thirteenth transistor NM3 and a fourteenth transistor NM4. Specifically, the ninth transistor PM2 has a first terminal, a second terminal and a control terminal, the second terminal of the ninth transistor PM2 is coupled to the high voltage signal BST, and the control terminal of the ninth transistor PM2 is coupled to the control terminal of the sixtieth transistor PM8 to mirror the first input current signal IBN; the tenth transistor PM3 has a first terminal, a second terminal and a control terminal, the second terminal of the tenth transistor PM3 is coupled to the first terminal of the ninth transistor PM2, and the control terminal of the tenth transistor PM3 is coupled to the control terminal of the sixtieth transistor PM9 to mirror the first input current signal IBN; the eleventh transistor PM12 has a first terminal, a second terminal and a control terminal, the second terminal of the eleventh transistor PM12 is coupled to the first terminal of the tenth transistor PM3, the control terminal of the eleventh transistor PM12 is coupled to the second terminal of the first transistor, and the first terminal of the eleventh transistor PM12 is coupled to the first voltage signal VSS; The twelfth transistor PM10 has a first end, a second end and a control end, the second end of the twelfth transistor PM10 is coupled to the first end of the tenth transistor PM3, and the control end of the twelfth transistor PM10 is coupled to the second end of the high-end transistor N3; the thirteenth transistor NM3 has a first end, a second end and a control end, the first end of the thirteenth transistor NM3 is coupled to the first end of the twelfth transistor PM10, the second end of the thirteenth transistor NM3 is coupled to the first voltage signal VSS, and the control end of the thirteenth transistor NM3 is coupled to the first end of the thirteenth transistor NM3; the fourteenth transistor NM4 has a first end, a second end and a control end, the first end of the fourteenth transistor NM4 provides a first amplified signal, the second end of the fourteenth transistor NM4 is coupled to the first voltage signal VSS, and the control end of the fourteenth transistor NM4 is coupled to the control end of the thirteenth transistor NM3.

[0033] The high voltage signal BST is connected through the ninth transistor PM2 and the tenth transistor PM3, thereby providing a positive voltage for the first amplifier J1; the eleventh transistor PM12 and the twelfth transistor PM10 are differential pairs, the control end of the eleventh transistor PM12 serves as the inverting input end of the first amplifier J1, and the twelfth transistor PM10 serves as the non-inverting input end of the first amplifier J1. Figure 2As shown, the first amplifier J1 further includes a sixty-second transistor PM6 and a sixty-third transistor PM7, the second end of the sixty-second transistor PM6 is coupled to the high voltage signal BST, the first end of the sixty-second transistor PM6 is coupled to the second end of the sixty-third transistor PM7, and the control end of the sixty-second transistor PM6 is coupled to the control end of the sixtieth transistor PM8 to mirror the first input current signal IBN; the first end of the sixty-third transistor PM7 is coupled to the second end of the fourteenth transistor NM4, and the control end of the sixty-third transistor PM7 is coupled to the control end of the sixty-first transistor PM9 to mirror the first input current signal IBN. In some embodiments, the sixty-third transistor PM7 can be omitted. The thirteenth transistor NM3 and the fourteenth transistor NM4 form an NMOS current mirror as the load of the first amplifier J1. The targeted use of such a load structure can simplify the loop compensation of the first amplifier J1 and the entire amplifier 10. In another specific embodiment, the first amplifier J1 further includes a diode D0 and a diode D3, which are reversely connected in series between the control end of the eleventh transistor PM12 and the control end of the twelfth transistor PM10 to play a protective role. In the above-mentioned first amplifier J1 , the common terminal of the fourteenth transistor NM4 and the sixty-third transistor PM7 serves as the output terminal of the first amplifier J1 and is coupled to the control terminal of the low-side transistor N4 .

[0034] exist Figure 2 In the figure, the wiring terminal of the lead wire from the first end of the first transistor N1 is indicated as the HG output terminal, and the HG output terminal is used to control the high-end transistor N3; the wiring terminal of the lead wire from the output end of the first amplifier J1 is indicated as the LG output terminal, and the LG output terminal is used to control the low-end transistor N4; the second end of the high-end transistor N3 is indicated as the OUT terminal, that is, the output terminal of the amplifier circuit 10, and the control terminal of the twelfth transistor PM10 is coupled to the OUT terminal to receive the voltage output signal V0 output by the second end of the high-end transistor N3.

[0035] In a specific embodiment, the potential of the high voltage signal BST is 5V higher than the potential of the second voltage signal VCC, that is, the high voltage signal BST is a high power supply voltage. In other embodiments, the potential of the high voltage signal BST can also be 3.3V, 1.8V or other magnitudes higher than the potential of the second voltage signal VCC.

[0036] In some embodiments, the second input terminal of the first amplifier J1 receives the voltage output signal V0 through the ESD resistor R0 .

[0037] In some embodiments, since the second transistor N2 is a low-voltage tube, a common-gate tube NM7 is also provided in the amplifier circuit 10. The common-gate tube NM7 has a first end, a second end and a control end. The first end of the common-gate tube NM7 is coupled to the second end of the first transistor N1, the second end of the common-gate tube NM7 is coupled to the first end of the second transistor N2, and the control end of the common-gate tube NM7 receives the bias voltage signal VB. At this time, the first input end of the first amplifier J1 is coupled to the second end of the common-gate tube NM7. The common-gate tube NM7 is used to exert its shielding characteristics to isolate and protect the second transistor N2.

[0038] In some embodiments, when the first current source I1 provides current to the first transistor N1, the first current source I1 is coupled between the high voltage signal BST and the first terminal of the first transistor N1. Figure 2 As shown, the common-source and common-gate current source formed by the transistor PM0 and the transistor PM1 is the first current source I1, and the first transistor N1 provides current; in some embodiments, the transistor PM1 can be omitted.

[0039] In a specific embodiment, the current of the PMOS current mirror in the above embodiments all mirrors the first input current IBN.

[0040] Specifically, see Figure 2 , the whole formed by connecting the PMOS current mirrors in the amplifier circuit is defined as a PMOS current mirror unit. Then the PMOS current mirror unit includes: transistors PM8, PM9, PM15, PM11, PM0, PM1, PM2, PM3, PM6, PM7.

[0041] In the PMOS current mirror unit, transistors PM8, PM15, PM0, PM2, and PM6 are connected in common source and gate, and transistors PM9, PM11, PM1, PM3, and PM7 are connected in common gate; wherein, the drain of transistor PM0 is coupled to the source of transistor PM1, and the drain of transistor PM1 is coupled to the drain of the first transistor N1; the sixtieth transistor PM8 and the sixty-first transistor PM9 are both diode-connected, that is, the gate and the drain are short-circuited; the source of the sixtieth transistor PM8 is coupled to the high voltage signal BST, and the drain of the sixtieth transistor PM8 is coupled to the source of the sixty-first transistor PM9.

[0042] In some embodiments, in order to realize the control of the PMOS current mirror unit, a nineteenth transistor NM12 is further provided. The nineteenth transistor NM12 has a first end, a second end and a control end, the first end of the nineteenth transistor NM12 is coupled to the gate of the sixty-first transistor PM9, the second end of the nineteenth transistor NM12 receives the first input current signal IBN, and the control end of the nineteenth transistor NM12 receives the bias voltage signal VB.

[0043] In the above embodiment, the bias voltage signal VB for controlling the common-gate transistor NM7 and the nineteenth transistor NM12 is provided by the drain of the transistor NM14.

[0044] In some embodiments, a shutdown unit for controlling the shutdown of the linear driving circuit is also designed to start and terminate the linear driving mode. The shutdown unit receives an enable signal SD, which is inverted to obtain a first enable signal SDN, which is inverted to obtain a second enable signal SDP.

[0045] See also Figure 2 Specifically, the shutdown unit includes: a fifteenth transistor NM2, a sixteenth transistor NM9, a twentieth transistor NM16 and a twenty-first transistor NM17 controlled by a first enable signal SDN, and a seventeenth transistor PM14, an eighteenth transistor PM16 and a twenty-second transistor PM19 controlled by a second enable signal SDP.

[0046] Taking the above transistors as MOS tubes as an example, the first end, the second end and the control end of the fifteenth transistor NM2, the sixteenth transistor NM9, the seventeenth transistor PM14, the eighteenth transistor PM16 and the twentieth transistor NM16 correspond to the drain, the source and the gate of the MOS tube respectively. The twentieth transistor NM16 is used to adjust the bias voltage signal VB according to the first enable signal SDN, so as to control the on and off of the nineteenth transistor NM12 and the common gate tube NM7.

[0047] Specifically, the sources of NM2 and NM16 are respectively coupled to the first voltage signal VSS, the gates are respectively coupled to the first enable signal SDN, and the drains are respectively coupled to the gates of N2 and NM14. When SDN is a high voltage, the gates of NM2 and NM16 are high voltages, NM2 and NM16 are turned on, and the gate voltages of N2 and NM14 are pulled down to VSS, thereby turning off N2 and NM7. After any one of N2 and NM7 is turned off, the discharge path of the HG port to the ground will be closed (or the HG port is in a high impedance state to the ground). The sources of PM14 and PM16 are respectively coupled to the high power supply voltage VBST, and the gates are respectively coupled to the second enable signal SDP. The drain of PM14 is coupled to the gate of transistor PM1, and the drain of PM16 is coupled to the gate of PM0. When SDP is a low voltage, the gates of PM14 and PM16 are low voltages, PM14 and PM16 are turned on, and the gate voltages of PM1 and PM0 are pulled up to VBST, so that PM1 and PM0 are turned off. After any one of PM1 and PM0 is turned off, the discharge path of the HG port to VBST will be closed (or the HG port will be in a high impedance state to the high power supply). That is, when SDN is a high level, the linear drive module will enter a low-power standby state, and the HG port will be in a high impedance state to both the high power supply and the ground. At this time, the gate of the high-end transistor N3 can be controlled by other signals (such as the switch signal provided by the switch circuit to be introduced later). Based on the same working principle, when SDN is at a high level, with the cooperation of transistors NM9, NM16, PM14 and PM16, the LG port also presents a high impedance state to both the high power supply and the ground, and the gate of the low-end transistor N4 can be controlled by other signals (such as the switch signal provided by the switch circuit to be introduced later). For this reason, high impedance does not require infinite resistance, and the equivalent resistance only needs to be large enough not to affect the control of other signals.

[0048] The shutdown logic of other transistors in the shutdown unit is as follows: the twenty-first transistor NM17 pulls down the gate voltage of the transistor NM10 to the first voltage signal VSS according to the first enable signal SDN, and the twenty-second transistor PM19 pulls up the gate voltage of the transistor PM4 to the supply voltage signal VDD according to the second enable signal SDP.

[0049] In some embodiments, the amplifier circuits proposed in the above embodiments are applied to a class AB amplifier or a class D amplifier to achieve linear driving of the amplifier.

[0050] Since the amplifier circuit in the above embodiment uses an NMOS tube as the high-end transistor N3 and implements the linear driving mode of the NMOS amplifier, in order to implement the switch driving mode, it is also necessary to design a switch driving circuit for the high-end transistor N3. Some embodiments of the present invention further propose a high-end switch driving circuit to drive the high-end transistor N3 in the amplifier circuit, such as Figure 3As shown, the high-end switch driving circuit includes: a control signal generating unit, a discharge circuit and a charging circuit. The switch driving circuit is applicable to the case where the high-end transistor in the output stage of all types of amplifiers is an NMOS tube. In the accompanying drawings corresponding to the embodiments described below, the connection position with the gate of the high-end transistor N3 is shown as port HDV.

[0051] Among them, the control signal generating unit is connected to the switch signal HS (controlling the high-end transistor to be turned on and off) and the mode selection signal ABD (selecting the high-end transistor to work in the class AB linear mode or the class D switch mode), and generates the first control signal AS, the second control signal BS and the third control signal CS according to the switch signal HS and the mode selection signal ABD, and the first control signal AS and the second control signal BS are logically complementary. Among them, the mode selection signal ABD is a mode control signal when the high-end transistor N3 is driven by a switch, and the switch signal HS is an input signal for controlling the setting of the high-end transistor N3. When the mode selection signal ABD is enabled, the switch signal HS controls the switch of the high-end transistor N3; when the mode selection signal ABD is not enabled, the high-end switch drive circuit enters the standby state, and the output terminal HDV of the high-end NMOS transistor switch drive circuit is in a high-impedance state, so that Figure 2 The linear drive circuit shown can perform linear drive on the high-end transistor. Figure 3 In the circuit shown, when the linear driving mode is not required, the ABD signal can be ignored. Accordingly, the same technical effect can be achieved by replacing the NAND gate or NOR gate in the circuit with an inverter.

[0052] When the switch signal HS has a first level (such as a high level), the charging circuit charges the control end of the high-end transistor N3, and the control end of the high-end transistor N3 is a high voltage; when the switch signal HS has a second level (such as a low level), the discharge circuit discharges the control end of the high-end transistor N3, and the control end of the high-end transistor N3 is a low voltage; when the switch signal HS changes from the second level to the first level, the third control signal CS generates a pulse voltage to increase the charging current of the charging circuit to the control end of the high-end transistor N3 within a set time.

[0053] The discharge circuit includes a discharge transistor X6, wherein the discharge transistor X6 has a first terminal, a second terminal and a control terminal, wherein the first terminal is configured as an output terminal of the discharge circuit, and the second terminal is coupled to the second terminal of the high-end transistor N3. Figure 3 In FIG. 1 , the second end of the high-end transistor N3 is shown as a SW point. When the switch signal HS changes from the second level to the first level, the third control signal CS generates a pulse voltage to increase the discharge current of the control end of the discharge transistor X6 within a set time.

[0054] In some embodiments, the control signal generating unit has a first logic judgment path A, a second logic judgment path B and a third logic judgment path C; the switch signal generates a first control signal AS through the first logic judgment path A, the switch signal generates a second control signal BS through the second logic judgment path B, and the switch signal generates a third control signal CS through the third logic judgment path C; the waveforms of the switch signal HS, the first control signal AS, the second control signal BS and the third control signal CS are as follows: Figure 4 As shown, the first control signal AS and the switch signal HS have substantially the same waveform (same here means substantially the same phase), the second control signal BS is logically complementary to the first control signal AS, and the third control signal is a sharp pulse signal. In an actual circuit, Figure 4 As shown, due to the delay in the logic judgment process, the first control signal AS will slightly lag behind the switch signal HS, and the second control signal BS will slightly lag behind the first control signal AS. In a specific embodiment, the rising edge of the third control signal CS is basically consistent with that of the first control signal AS.

[0055] In a specific embodiment, the control signal generating unit includes: a first NAND gate I17, having a first end, a second end and an output end, wherein the first end receives the switch signal, and the second end receives the mode selection signal; a first NOT gate I16, having an input end and an output end, wherein the input end is coupled to the output end of the first NAND gate I17; a second NOT gate X63, having an input end and an output end, wherein the input end is coupled to the output end of the first NOT gate I16; a third NOT gate X64, having an input end and an output end, wherein the input end is coupled to the output end of the second NOT gate X63, and the output end provides the first control signal. a control signal; a fourth NOT gate I21, having an input terminal and an output terminal, wherein the input terminal is coupled to the output terminal of the first NOT gate I16; a second NAND gate I20, having a first terminal, a second terminal and an output terminal, wherein the first terminal receives the mode selection signal, and the second terminal is coupled to the output terminal of the fourth NOT gate I21; a fifth NOT gate I19, having an input terminal and an output terminal, wherein the input terminal is coupled to the output terminal of the second NAND gate I20, and the output terminal provides a second control signal; a sixth NOT gate I3, having an input terminal and an output terminal, wherein the input terminal is coupled to the output terminal of the first NOT gate I16; a seventh NOT gate I7 , having an input terminal and an output terminal, and its input terminal is coupled to the output terminal of the sixth NOT gate I3; the eighth NOT gate I8, having an input terminal and an output terminal, and its input terminal is coupled to the output terminal of the seventh NOT gate I7; the ninth NOT gate I6, having an input terminal and an output terminal, and its input terminal is coupled to the output terminal of the eighth NOT gate I8; the tenth NOT gate I5, having an input terminal and an output terminal, and its input terminal is coupled to the output terminal of the ninth NOT gate I6; the fortieth transistor X0, having a first terminal, a second terminal and a control terminal, its first terminal is coupled to its second terminal, and its control terminal is coupled to the output terminal of the seventh NOT gate I7; the fourth The eleventh transistor X10 has a first end, a second end and a control end, wherein the first end is coupled to the second end, and the control end is coupled to the output end of the ninth NOT gate I6. The fortieth transistor X0 and the forty-first transistor X10 constitute a delay capacitor. The third NAND gate I27 has a first end, a second end and an output end, wherein the first end is coupled to the output end of the first NOT gate I16, and the second end is coupled to the output end of the tenth NOT gate I5. The eleventh NOT gate I4 has an input end and an output end, wherein the input end is coupled to the output end of the third NAND gate I27, and the output end provides a third control signal.

[0056] Among them, I17, I16, X63, and X64 form a first logic judgment path A; I17, I16, I21, I20, and I19 form a first logic judgment path B; I17, I16, I8, I7, I3, I5, I6, X0, and X10 form a third logic judgment path C, wherein the transistors X10 and X0 act as capacitors, generating delays, thereby setting the sharp pulse width of the third control signal CS. It can be understood that the specific structure of the above-mentioned control signal generating unit is only an example given in the present disclosure, and those skilled in the art can adjust the number and position of logic gates according to the above-mentioned examples according to actual needs, as long as the first control signal AS, the second control signal BS, and the third control signal CS limited by the present disclosure can be generated.

[0057] In some embodiments, Figure 3 As shown, the discharge circuit includes: a twenty-third transistor X3, a twenty-fourth transistor X7, a twenty-fifth transistor X4, a twenty-sixth transistor X54, a twenty-seventh transistor X57, a twenty-eighth transistor X55, a twenty-ninth transistor P3, a thirtieth transistor P5 and a discharge transistor X6.

[0058] Specifically, the twenty-third transistor X3 has a first terminal, a second terminal and a control terminal, the first terminal of which receives the second input current signal I2, the second terminal of which is coupled to the reference ground, and the control terminal of which is coupled to the first terminal; the twenty-fourth transistor X7 has a first terminal, a second terminal and a control terminal, the second terminal of which is coupled to the reference ground, the control terminal of which is coupled to the control terminal of the twenty-third transistor X3 to mirror the second input current I2, and the first terminal of which provides a current IX7; the twenty-fifth transistor X4 has a first terminal, a second terminal and a control terminal, the second terminal of which is coupled to the reference ground, the control terminal of which is coupled to the control terminal of the twenty-fourth transistor X7, and the first terminal of which provides a current IX4; the twenty-sixth transistor X54 has a first terminal, a second terminal and a control terminal, the first terminal of which provides a second current signal ndeo2, the second terminal of which is coupled to the first terminal of the twenty-fourth transistor X7, and the control terminal of which receives the second control signal BS; the twenty-seventh transistor X57 has a first terminal, a second terminal and a control terminal, the second terminal of which is coupled to the first terminal of the twenty-fifth transistor X4, and the control terminal of which is coupled to the control terminal of the twenty-fifth transistor X7. The 28th transistor X55 has a first terminal, a second terminal and a control terminal, the first terminal of which provides a third current signal ndeo3, the second terminal of which is respectively coupled to the first terminal of the 27th transistor X57 and the first terminal of the 24th transistor X7, and the control terminal of which receives the first control signal AS; the 29th transistor P3 has a first terminal, a second terminal and a control terminal, the first terminal of which receives the second current signal ndeo2, the second terminal of which is coupled to the driving voltage source VCP, and the control terminal of which is coupled to the first terminal; the 30th transistor P5 has a first terminal, a second terminal and a control terminal, the second terminal of which is coupled to the driving voltage source VCP, and the control terminal of which is coupled to the control terminal of the 29th transistor P3; the first terminal of the discharge transistor X6 is configured as the output terminal of the discharge circuit, the second terminal of the discharge transistor X6 is coupled to the second terminal of the high-end transistor N3, and the control terminal of the discharge transistor X6 is respectively coupled to the first terminal of the 30th transistor P5 and the first terminal of the 28th transistor X55. In one embodiment, the driving voltage source VCP can be coupled to a high power supply voltage.

[0059] Among them, the first end of the twenty-fourth transistor X7 and the first end of the twenty-fifth transistor X4 are two current output ends of the current mirror structure, in which the second input current signal I2 is mirrored and output through the corresponding output end. The twenty-ninth transistor P3 and the thirtieth transistor P5 form another current mirror structure for mirroring the second current signal nedo2. It can be understood that in the current mirror of the present disclosure, the current mirror can amplify or reduce the current signal of the input current mirror as needed during the mirroring process, and the magnification is related to the ratio of the width-to-length ratio of the tube.

[0060] In a specific embodiment, the discharge circuit further includes a pull-down resistor R4, which has a first end and a second end, wherein the first end is coupled to the control end of the discharge transistor X6, and the second end is coupled to the second end (SW point) of the high-end transistor N3. The pull-down resistor R4 is used to prevent floating, and plays a shut-off role when no current flows upstream of the pull-down resistor R4.

[0061] In some embodiments, the charging circuit includes: a thirty-first transistor X5, a thirty-second transistor X61, a thirty-third transistor X56, a thirty-fourth transistor X53, a thirty-fifth transistor P2 and a charging transistor X1.

[0062] Specifically, the thirty-first transistor X5 has a first terminal, a second terminal and a control terminal, the second terminal of which is coupled to the reference ground, the control terminal of which is coupled to the control terminal of the twenty-third transistor X3 to mirror the second input current signal I2, and the first terminal of which provides a current IX5; the thirty-second transistor X61 has a first terminal, a second terminal and a control terminal, the second terminal of which is coupled to the reference ground, the control terminal of which is coupled to the control terminal of the thirty-first transistor X5, and the first terminal of which provides a current IX61; the thirty-third transistor X56 has a first terminal, a second terminal and a control terminal, the second terminal of which is coupled to the first terminal of the thirty-first transistor X5, and the control terminal of which receives the third control signal CS; the thirty-fourth transistor X53 has a first terminal, a second terminal and a control terminal, the second terminal of which is coupled to the first terminal of the thirty-first transistor X5, and the control terminal receives the third control signal CS; The thirty-fifth transistor P2 has a first end, a second end and a control end, the first end of which provides a first current signal ndeo1, the second end of which is respectively coupled to the first end of the thirty-third transistor X56 and the first end of the thirty-second transistor X61, and the control end of which receives the first control signal AS; the thirty-fifth transistor P2 has a first end, a second end and a control end, the first end of which receives the first current signal ndeo1, the second end of which is coupled to the driving voltage source VCP, and the control end of which is coupled to its first end; the charging transistor X1 has a first end, a second end and a control end, the first end of which serves as the output end of the charging circuit, the second end of which is coupled to the driving voltage source VCP, and the control end of which is coupled to the control end of the thirty-fifth transistor P2.

[0063] The first end of the 31st transistor X5 and the first end of the 32nd transistor X61 serve as two current output ends of a current mirror structure, in which the second input current signal I2 is mirrored and outputted via corresponding output ends. The 35th transistor P2 and the charging transistor X1 form another current mirror structure for mirroring the first current signal nedo1.

[0064] In some embodiments, in order to improve the accuracy of the current in the circuit, a thirty-sixth transistor P4 and a thirty-seventh transistor P6 are provided in the discharge circuit, and a thirty-eighth transistor P0 and a thirty-ninth transistor X9 are provided in the charging circuit.

[0065] Specifically, the thirty-sixth transistor P4 has a first end, a second end and a control end, and its first end is coupled to the first end of the twenty-sixth transistor X54, its second end is coupled to the first end of the twenty-ninth transistor P3, and its control end is coupled to the first end; the thirty-seventh transistor P6 has a first end, a second end and a control end, its first end is coupled to the control end of the discharge transistor X6, its second end is coupled to the first end of the thirtieth transistor P5, and its control end is coupled to the control end of the thirty-sixth transistor P4; the thirty-eighth transistor P0 has a first end, a second end and a control end, its first end is coupled to the first end of the thirty-fourth transistor X53, its second end is coupled to the first end of the thirty-fifth transistor P2, and its control end is coupled to the first end; the thirty-ninth transistor X9 has a first end, a second end and a control end, its first end is coupled to the control end (HDV) of the high-end transistor N3, its second end is coupled to the first end of the charging transistor X1, and its control end is coupled to the control end of the thirty-eighth transistor P0.

[0066] In some embodiments, the 23rd transistor X3, the 24th transistor X7, the 25th transistor X4, the 31st transistor X5 and the 32nd transistor X61 form a first current mirror unit, and mirror the second input current signal I2 to generate multiple output currents. The control terminals of the 24th transistor X7, the 25th transistor X4, the 31st transistor X5 and the 32nd transistor X61 are all coupled to the control terminal of the 23rd transistor X3.

[0067] It should be noted that in the present disclosure, for transistors whose specific device types are not specified, MOS tubes are used as examples for explanation, and the first end, the second end and the control end of each transistor correspond to the drain, source and gate of the MOS tube respectively.

[0068] Continue reading Figure 4 The working principle of the high-end switch driving circuit disclosed in the above embodiment is as follows:

[0069] At time T1, when the switch signal HS changes from low level to high level:

[0070] The second control signal BS becomes low level, the twenty-sixth transistor X54 is turned off, the second current signal ndeo2 current becomes 0, the current on the twenty-ninth transistor P3 is 0, and the current on the thirtieth transistor P5 is 0, that is, the thirtieth transistor P5 no longer charges the gate of the discharge transistor X6.

[0071] The first control signal AS and the second control signal CS become high level, the twenty-eighth transistor X55 and the twenty-seventh transistor X57 are turned on, and the current of the third current signal nedo3 is the sum of the current of the twenty-fifth transistor X4 and the current of the twenty-fourth transistor X7, that is, the charge stored in the gate of the discharge transistor X6 is released with a large current, so that the discharge transistor X6 is turned off, and after the discharge transistor X6 is turned off, it no longer discharges to the gate of the high-end transistor N3.

[0072] The first control signal AS and the second control signal CS become high level, the current of the first current signal nedo1 is the sum of the current of the thirty-first transistor X5 and the current of the thirty-second transistor X61, and the current of the first current signal nedo1 is mirrored to the charging transistor X1 through the thirty-fifth transistor P2, that is, the charging transistor X1 charges the gate of the high-end transistor N3 with a large current, causing it to become a high level.

[0073] After the set time (between time T1 and time T2, i.e., the third control signal CS sharp pulse width), at time T2, the third control signal CS becomes low level. At this time:

[0074] The thirty-third transistor X56 and the twenty-seventh transistor X57 are turned off, that is, the current provided by the thirty-first transistor X5 and the twenty-fifth transistor X4 terminates the output, thereby saving static current.

[0075] At this time, the current of the third current signal nedo3 is the current of the twenty-fourth transistor X7, that is, a relatively small current is used to continuously discharge the gate of the discharge transistor X6 to keep it at a low level.

[0076] The current of the first current signal nedo1 is the current of the thirty-second transistor X61. The current of the first current signal nedo1 is mirrored to the charging transistor X1 through the thirty-fifth transistor P2. That is, the charging transistor X1 continuously charges the gate of the high-end transistor N3 with a smaller current to keep it at a high level.

[0077] At time T3, when the switch signal HS changes from high level to low level:

[0078] The first control signal AS becomes a low level, the twenty-eighth transistor X55 is turned off, the third current signal nedo3 becomes 0, and the gate of the discharge transistor X6 is no longer discharged; the thirty-fourth transistor X53 is turned off, and the current of the first current signal nedo1 is 0, resulting in the current of the thirty-fifth transistor P2 and the charging transistor X1 being 0, that is, the charging circuit no longer charges the gate of the high-end transistor N3.

[0079] The second control signal BS becomes a high level, the twenty-sixth transistor X54 is turned on, the second current signal ndeo2 current becomes the current on the twenty-fourth transistor X7, and passes through the mirror image of the twenty-ninth transistor P3 and the thirtieth transistor P5 to charge the gate of the discharge transistor X6. X6 is turned on to discharge the gate of the high-end transistor N3, and the gate of the high-end transistor N3 becomes a low level.

[0080] In some embodiments, in order to end the switch driving mode of the high-end switch driving circuit for the high-end transistor, a 42nd transistor NM25, a 43rd transistor P8 and a 44th transistor P9 are further provided. Among them, the 42nd transistor NM25 has a first end, a second end and a control end, and its first end is coupled to the first end of the 23rd transistor X3, its second end is coupled to the reference ground, and its control end receives the enable signal SD; the 43rd transistor P8 has a first end, a second end and a control end, its first end is coupled to the control end of the 35th transistor P2, its second end is coupled to the driving voltage source VCP, and its control end is driven at least according to the enable signal SD; the 44th transistor P9 has a first end, a second end and a control end, its first end is coupled to the control end of the 29th transistor P3, its second end is coupled to the driving voltage source VCP, and its control end is driven at least according to the enable signal SD. When ABD or SD is not enabled, the 43rd transistor P8 is turned on, and the control terminal of the 35th transistor P2 is pulled up to VCP, and the charging transistor X1 is turned off, so that the HDV port presents a high impedance state to the driving voltage source VCP; the 44th transistor P9 is turned on, and the control terminal of the 29th transistor P3 is pulled up to VCP, so that the 29th transistor is turned off; the 42nd transistor NM25 is turned on, and the control terminal of the 23rd transistor X3 is pulled down to the ground voltage, so that the 25th transistor X4 is turned off, and the resistor R4 pulls down the voltage of the control terminal of the discharge transistor X6, so that the discharge transistor X6 is turned off, that is, the HDV port presents a high impedance state to SW. That is, when ABD or SD is not enabled, Figure 3 The circuit 30 shown no longer controls the high-side switch and can be Figure 2 The circuit structure shown realizes the linear drive of the NMOS output stage. In a specific embodiment, the enable signal SD is input to one end of the NAND gate I22 after passing through the NOT gate I23, and the other end of the NAND gate I22 receives the mode selection signal ABD, and the output end of the NAND gate is respectively coupled to the control end of the 43rd transistor P8 and the 44th transistor P9 after passing through the level shift circuit.

[0081] In this disclosure, by Figure 2 The circuit structure shown can realize the linear drive mode of NMOS output stage. Figure 3The circuit structure shown can realize the switch driving mode of the NMOS output stage. However, the two modes have different characteristics and are suitable for different application scenarios. They can be used in separate chips or in the same chip. The above-mentioned linear driving mode and switch driving mode are integrated into the same chip to form a dual-mode amplifier circuit. Therefore, in some embodiments of the present invention, a dual-mode amplifier circuit 50 is proposed, such as Figure 5 As shown, it includes a high-side transistor N3, a low-side transistor N4, a linear driving circuit 20 and a switch driving circuit 60.

[0082] The switch driving circuit 60 has an input terminal, a first output terminal and a second output terminal. Figure 5 HDV) is coupled to the control terminal of the high-side transistor N3, and its second output terminal (such as Figure 5 LS) is coupled to the control terminal of the low-side transistor N4. The linear drive circuit 20 has a first output terminal and a second output terminal. The first output terminal of the linear drive circuit (such as Figure 5 HG) is coupled to the control terminal of the high-end transistor N3, and the second output terminal (such as Figure 5 The LG shown is coupled to the control terminal of the low-side transistor N4.

[0083] When the dual-mode amplifier 50 operates in the linear operating mode, the first output terminal and the second output terminal of the switch driving circuit 60 are in a high-impedance state, and the high-end transistor N3 and the low-end transistor N4 are controlled by the linear driving circuit 20; when the dual-mode amplifier operates in the switching mode, the first output terminal and the second output terminal of the linear driving circuit 20 are in a high-impedance state, and the switch driving circuit 60 controls the high-end transistor N3 and the low-end transistor N4.

[0084] In some embodiments, the mode switching of the dual-mode amplifier circuit is realized at least by the enable signal SD, and the enable signal SD is sent to the switch drive circuit 60 and the linear drive circuit 20 respectively. The enable signal SD enables the switch drive circuit 60 and the linear drive circuit 20 respectively in different logic states. Specifically, the enable signal SD can turn off the switch drive circuit 60 and the linear drive circuit 20 at the same time, or turn off one of them alone, so that the other circuit drives the high-end transistor N3 and the low-end transistor N4 alone. In order to facilitate the switching of the linear drive mode (AB) and the switch mode (D), the mode selection signal ABD is introduced below. It should be noted that in actual chip control, the mode selection signal ABD and the enable signal SD are generally a logical combination of an external enable signal, a mode selection signal and other control signals, so as to control the chip to work according to the set mode.

[0085] Furthermore, in order to facilitate the description of signal logic control in the present disclosure, the signal generated by the mode selection signal ABD through the inverter L33 is defined as the first mode selection signal ABDN, and the signal generated by the first mode selection signal ABDN through the inverter L32 is defined as the second mode selection signal ABDP. The signal generated by the enable signal SD through the inverter L36 is defined as the first enable signal SDN, and the signal generated by the first enable signal SDN through the inverter L35 is defined as the second enable signal SDP.

[0086] Figure 5 The linear drive circuit 20 shown in FIG. 1 includes a first transistor N1, a second transistor N2, a first amplifier J1, and a second amplifier J2. The linear drive circuit 20 may be configured as follows: Figure 1 and Figure 2 The circuit structure in the embodiment shown realizes the linear drive of the high-end transistor N3 and the low-end transistor N4. Figure 1 and Figure 2 The illustrated embodiment adjusts the internal structure of the linear drive circuit, or adopts other linear drive methods.

[0087] Continue reading Figure 5In some embodiments, the switch driving circuit 60 includes a dead time generating unit, a high-end switch driving unit and a low-end switch driving unit. The dead time generating unit has a first input terminal, a first output terminal and a second output terminal, wherein the first input terminal is coupled to the digital input signal DIN, and the dead time generating unit generates a first intermediate control signal ZKL1 ​​and a second intermediate control signal ZKL2 according to the digital input signal DIN; wherein the first intermediate control signal ZKL1 ​​and the second intermediate control signal ZKL2 have complementary effective time, that is, only when the first intermediate control signal ZKL1 ​​is logically invalid (for example, logical low), the second intermediate control signal ZKL2 is flipped to logically valid (for example, logical high), that is, in this mode, the low-end transistor N4 can be turned on only after the high-end transistor N3 is turned off through the dead time generating unit. It should be noted that due to the existence of the dead time, the first intermediate control signal ZKL1 ​​and the second intermediate control signal ZKL2 are not strictly logically complementary, and the first intermediate control signal ZKL1 ​​and the second intermediate control signal ZKL2 are both in a logical invalid state during the dead time. And the first intermediate control signal ZKL1 ​​participates in the generation of the second intermediate control signal ZKL2, and the second intermediate control signal ZKL2 participates in the generation of the first intermediate control signal ZKL1 ​​to generate the dead time. The high-end switch driving unit receives the first intermediate control signal ZKL1, generates the switch signal HS, and its output end serves as the first output end of the switch driving circuit 60, and charges or discharges the control end of the high-end transistor N3 according to the switch signal HS. The low-end switch driving unit receives the second intermediate control signal ZKL2, and its output end serves as the second output end of the switch driving circuit 60, and charges or discharges the control end of the low-end transistor N4 according to the second intermediate control signal ZKL2. Due to the existence of the dead time, the device damage caused by the high-end switch and the low-end switch being turned on at the same time, which causes the power supply to discharge directly to the ground, is avoided.

[0088] In some embodiments, Figure 6 As shown, the high-end switch driving unit includes: a twenty-ninth NOT gate L3 and a high-end switch driving circuit 30, wherein the high-end switch driving circuit is indicated as HDRV, which can be used as follows Figure 3 The circuit structure shown in FIG. Figure 3 The illustrated embodiment adjusts the internal structure of the high-side switch driving circuit, or adopts other high-side switch driving circuits.

[0089] Specifically, the twenty-ninth NOT gate L3 has an input end and an output end, wherein its input end receives the first intermediate control signal ZKL1, and its output end provides a switching signal HS; the high-end switch driving circuit has an input end and an output end, wherein its input end is coupled to the output end of the twenty-ninth NOT gate L3, and its output end is coupled to the control end of the high-end transistor N3 as the first output end of the switch driving circuit 60.

[0090] In some embodiments, the dead time generating unit includes a twentieth NOT gate L5, a twenty-first NOT gate L19, a fifth NAND gate L18, a twenty-second NOT gate L16, a sixth NAND gate L15, a seventh NAND gate L27, a twenty-third NOT gate L6, a twenty-fourth NOT gate L23, a twenty-fifth NOT gate L22, an eighth NAND gate L11, a twenty-sixth NOT gate L14, a twenty-seventh NOT gate L21 and a twenty-eighth NOT gate L20.

[0091] Among them, the twentieth NOT gate L5 has an input terminal and an output terminal, and its input terminal receives the digital input signal DIN; the twenty-first NOT gate L19 has an input terminal and an output terminal, and its input terminal is coupled to the output terminal of the twentieth NOT gate L5; the fifth NAND gate L18 has a first terminal, a second terminal and an output terminal, and its first terminal is coupled to the output terminal of the twenty-first NOT gate L19, and its output terminal provides a first intermediate control signal ZKL1; the twenty-second NOT gate L16 has an input terminal and an output terminal, and its input terminal receives the digital input signal DIN; the sixth NAND gate L15 has a first terminal, a second terminal and an output terminal, and its second terminal is coupled to the output terminal of the twenty-second NOT gate L16, and its output terminal provides a second intermediate control signal ZKL2; the seventh NAND gate L27 has a first terminal, a second terminal and an output terminal, and its first terminal receives the first intermediate control signal ZKL1, and its second terminal is coupled to the first output terminal of the switch driving circuit; the twenty-third NOT gate L6 has an input terminal and an output terminal, and its input terminal is coupled to the output terminal of the twenty-first NOT gate L19, and its output terminal provides a first intermediate control signal ZKL1. The output end of the seventh NAND gate L27 is coupled; the twenty-fourth NAND gate L23 has an input end and an output end, and its input end is coupled to the output end of the twenty-third NAND gate L6; the twenty-fifth NAND gate L22 has an input end and an output end, and its input end is coupled to the output end of the twenty-fourth NAND gate L23, and its output end is coupled to the first end of the sixth NAND gate L15; the eighth NAND gate L11 has a first end, a second end and an output end, and its first end receives the second intermediate control signal ZKL2, and its second end is coupled to the second output end of the switch drive circuit; the twenty-sixth NAND gate L14 has an input end and an output end, and its input end is coupled to the output end of the eighth NAND gate L11; the twenty-seventh NAND gate L21 has an input end and an output end, and its input end is coupled to the output end of the twenty-sixth NAND gate L14; the twenty-eighth NAND gate L20 has an input end and an output end, and its input end is coupled to the output end of the twenty-seventh NAND gate L21, and its output end is coupled to the second end of the fifth NAND gate L18.

[0092] The circuit structure of the dead time generating unit is merely an example given in the present disclosure, and the logic gate elements inside the dead time generating unit may be increased, decreased or adjusted as required, as long as the first intermediate control signal ZKL1 ​​and the second intermediate control signal ZKL2 that meet the requirements can be generated.

[0093] In order to further improve the reliability of driving the control end of the high-end transistor N3 in the switching mode, in some embodiments, a double insurance unit is also provided, and the double insurance unit includes a 50th transistor PP0, a 51st transistor NN0, a second resistor R0, a 52nd transistor PP1, a 53rd transistor NN12, a 30th NOT gate L38, a 31st NOT gate L0, a 9th NAND gate L1, a 10th NAND gate L40, and a 54th transistor N111.

[0094] The fiftieth transistor PP0 has a first terminal, a second terminal and a control terminal, wherein the second terminal is coupled to the control terminal of the high-end transistor N3, and the control terminal is coupled to the second terminal ( Figure 6 SW point shown in ); the fifty-first transistor NN0 has a first end, a second end and a control end, the first end of which is coupled to the first end of the fiftieth transistor PP0, and the control end of which receives the first mode selection signal ABDN; the second resistor R0 has a first end and a second end, the first end of which is coupled to the second end of the fifty-first transistor NN0, and the second end of which is coupled to the reference ground. In a specific embodiment, a diode D0 is also connected in parallel at both ends of the second resistor R0 to protect against damage to the control end / gate of MN12 when the voltage of the second resistor R0 is too high; the fifty-second transistor PP1 has a first end, a second end and a control end, The second end thereof is coupled to the reference voltage signal VDD, and the control end thereof receives the second mode selection signal ABDP; the fifty-third transistor NN12 has a first end, a second end and a control end, the second end thereof is coupled to the reference ground, and the control end thereof is coupled to the second end of the fifty-first transistor NN0; the thirtieth NOT gate L38 has an input end and an output end, and the input end thereof is respectively coupled to the first end of the fifty-second transistor PP1 and the first end of the fifty-third transistor NN12; the thirty-first NOT gate L0 has an input end and an output end, the input end thereof is coupled to the output end of the thirtieth NOT gate L38, and the output end thereof is coupled to the second end of the seventh NAND gate L27;

[0095] The 50th transistor PP0, the 51st transistor NN0, and the second resistor R0 are used to sense the high voltage change of the HG port HDV, and the analog signal is converted into a digital signal through the 52nd transistor PP1 and the 53rd transistor NN12, and provided to the 7th NAND gate L27 of the dead time generating unit through the 31st NOT gate L0 and the 30th NOT gate L38. Through the above settings, the feedback control of the HDV signal on the generation process of the second intermediate control signal ZKL2 is realized, that is, after confirming the execution result of the first intermediate control signal ZKL1 ​​(turning off the high-end switch N3, which is the same device as the high-end transistor N3 above), the second intermediate control signal ZKL2 generated by the dead time generating unit will be converted to the corresponding level to turn on the low-end switch N4 (which is the same device as the low-end transistor N4 above).

[0096] The ninth NAND gate L1 has a first end, a second end and an output end, the first end of which receives the first intermediate control signal ZKL1, and the two ends of which are coupled to the output end of the thirty-first NAND gate L0; the tenth NAND gate L40 has a first end, a second end and an output end, the first end of which is coupled to the output end of the ninth NAND gate L1, and the second end of which receives the second mode selection signal ABDP; the fifty-fourth transistor N111 has a first end, a second end and a control end, the first end of which is coupled to the first output end (HG) of the switch driving circuit, the second end of which is coupled to the reference ground, and the control end of which is coupled to the output end of the tenth NAND gate L40 to enhance the shutdown capability of the HG port.

[0097] In some embodiments, the dual insurance unit also includes a transistor NN9, which has a first end, a second end and a control end. The first end is coupled to the input end of the thirtieth NOT gate L38, the second end is coupled to the reference ground, and the control end receives a second mode selection signal ABDP. When the amplifier circuit enters the linear drive mode, the voltage at the output end of the high-end switch drive circuit can be reliably pulled down.

[0098] Continue reading Figure 6 The low-end switch driving unit includes: a fifty-fifth transistor PP9, a fifty-sixth transistor NN11, a first NOR gate L26, a thirty-second NOR gate L25, a thirty-third NOR gate L8, a thirty-fourth NOR gate L7, an eleventh NAND gate L28, a thirty-fifth NOR gate L29, a thirty-sixth NOR gate L31 and a thirty-seventh NOR gate L30.

[0099] Specifically, the fifty-fifth transistor PP9 has a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the control terminal of the low-end transistor N4, and the second terminal is coupled to the power supply voltage signal VDD; the fifty-sixth transistor NN11 has a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the control terminal of the low-end transistor N4, and the second terminal is coupled to the reference ground. The first NOR gate L26 has a first terminal, a second terminal and an output terminal, wherein the first terminal receives the second mode selection signal ABDP, and the second terminal receives the second intermediate control signal ZKL2; the thirty-second NOR gate L25 has an input terminal and an output terminal, wherein the input terminal is coupled to the output terminal of the first NOR gate L26; the thirty-third NOR gate L8 has an input terminal and an output terminal, wherein the input terminal is coupled to the output terminal of the thirty-second NOR gate L25; the thirty-fourth NOR gate L7 has an input terminal and an output terminal, wherein the input terminal is coupled to the output terminal of the thirty-third NOR gate L8, and the output terminal is coupled to the control terminal of the fifty-fifth transistor PP9; The NOT gate L28 has a first end, a second end and an output end, wherein the first end receives the second intermediate control signal ZKL2, and the second end receives the first mode selection signal ABDN; the thirty-fifth NOT gate L29 has an input end and an output end, wherein the input end is coupled to the output end of the eleventh NAND gate L28; the thirty-sixth NOT gate L31 has an input end and an output end, wherein the input end is coupled to the output end of the thirty-fifth NOT gate L29; the thirty-seventh NOT gate L30 has an input end and an output end, wherein the input end is coupled to the output end of the thirty-sixth NOT gate L31, and the output end is coupled to the control end of the fifty-sixth transistor NN11.

[0100] Among them, the logic gate elements in the low-end switch driving unit can be increased or decreased as needed, so that the control end of the fifty-fifth transistor PP9 can be driven according to the logic state of the mode selection signal and the second intermediate control signal; and the control end of the fifty-sixth transistor NN11 can be driven according to the inverted signal of the mode selection signal and the logic state of the second intermediate control signal. Furthermore, when ABD is at a low level, ABDP is at a low level, ABDN is at a high level, and the second intermediate control signal ZKL2 controls the fifty-fifth transistor PP9 and the fifty-sixth transistor NN11 to turn on and off, thereby controlling the turn-on and turn-off of the low-end transistor N4. When ABD is at a high level, ABDP is at a high level, ABDN is at a low level, the fifty-fifth transistor PP9 and the fifty-sixth transistor NN11 are turned off at the same time, and the common end of the two is suspended (high impedance to ground and to VDD), which can be controlled by Figure 2 The linear driver shown drives the low side switch N4.

[0101] In some embodiments, since the fifty-sixth transistor NN11 adopts an NMOS tube and has a relatively weak pull-down capability, it may cause erroneous opening, and the charging of the Miller capacitor during the opening process of the high-end transistor N3 may easily cause the low-end transistor N4 to be erroneously opened or generate spikes. Therefore, the switch drive circuit is also provided with an enhanced shutoff unit to shut off the low-end transistor N4 according to the gate voltage of the low-end transistor N4 when the fifty-sixth transistor NN11 is turned on. That is, when the gate voltage of the low-end transistor N4 is low, the gate voltage of the low-end transistor N4 is further lowered, and it is also further ensured that the high-end switch N3 is turned on after the low-end switch N4 is turned off.

[0102] In a specific embodiment, the enhanced shutdown unit includes: a thirty-eighth NOT gate L37, having an input terminal and an output terminal, and its input terminal is coupled to the second output terminal of the switch driving circuit; a thirty-ninth NOT gate L9, having an input terminal and an output terminal, and its input terminal is coupled to the output terminal of the thirty-eighth NOT gate L37; a fortieth NOT gate L10, having an input terminal and an output terminal, and its input terminal is coupled to the output terminal of the thirty-ninth NOT gate L9, and its output signal is provided to the eighth NAND gate L11 of the dead time generating unit. Through the above settings, the feedback control of the LS signal on the generation process of the first intermediate control signal ZKL1 ​​is realized, that is, after confirming the execution result of the second intermediate control signal ZKL2 (turning off the low-end switch N4), the first intermediate control signal ZKL1 ​​generated by the dead time generating unit will be converted to the corresponding level to turn on the high-end switch N3.

[0103] The twelfth NAND gate L12 has a first end, a second end and an output end, and its first end is coupled to the output end of the thirty-fifth NAND gate L29, and its second end is coupled to the output end of the fortieth NAND gate L10; the forty-first NAND gate L13 has an input end and an output end, and its input end is coupled to the output end of the twelfth NAND gate L12; the fifty-seventh transistor NN4 has a first end, a second end and a control end, and its first end is coupled to the second output end of the switch driving circuit, its second end is coupled to the reference ground, and its control end is coupled to the output end of the forty-first NAND gate L13, so as to enhance the shutdown capability of the LG port.

[0104] In some embodiments, a fifty-eighth transistor NN14 is further provided in the enhanced turn-off unit, and the fifty-eighth transistor NN14 is used to control the on and off of the fifty-seventh transistor NN4 according to the second mode selection signal ABDP. Specifically, the fifty-eighth transistor NN14 has a first end, a second end and a control end, wherein the first end is coupled to the input end of the thirty-ninth NOT gate L9, the second end is coupled to the reference ground, and the control end receives the second mode selection signal ABDP. After the fifty-eighth transistor NN14 is turned off, the fifty-seventh transistor NN4 is enabled, and the fifty-seventh transistor NN4 is switched on and off according to the gate voltage of the low-end transistor N4. When the gate voltage of the low-end transistor N4 is low, the fifty-seventh transistor NN4 is turned on, and the gate voltage of the low-end transistor is directly pulled down to the ground.

[0105] In some embodiments, a fifty-ninth transistor NN10 is also provided at the output end of the low-end switch driving unit, which has a first end, a second end and a control end, wherein the first end is coupled to the second output end of the switch driving circuit, the second end is coupled to the reference ground, and the control end receives the second enable signal SDP.

[0106] Those skilled in the art can understand that in the embodiments of the present invention, except for the transistors of the specified device type, other switch tubes can adopt any suitable semiconductor switch device type, such as N-type metal semiconductor field effect transistor (Metal Oxide Semiconductor Field Effect Transistor, MOSFET), junction field effect transistor (Junction Field-effect Transistor, JFET), insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT) and double diffusion metal oxide semiconductor (Double Diffusion Metal Oxide Semiconductor, DMOS), etc. Accordingly, in some embodiments, NPN transistors can replace NMOS transistors in this application, and PNP transistors can replace PMOS transistors in this application. N-type field effect transistors or N-type JFETs can also be used to replace NMOS transistors in this application, and P-type field effect transistors or P-type JFETs can be used to replace PMOS transistors in this application.

[0107] In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0108] Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A dual-mode amplifier circuit, characterized in that: include: The high-end transistor is an NMOS transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the second voltage signal; The low-end transistor adopts NMOS and has a first end, a second end and a control end. The first end is coupled to the second end of the high-end transistor, and the second end is coupled to the first voltage signal: A switch driving circuit having an input terminal, a first output terminal and a second output terminal, wherein the first output terminal is coupled to the control terminal of the high-end transistor, and the second output terminal is coupled to the control terminal of the low-end transistor; A linear driving circuit having a first output terminal and a second output terminal, wherein the first output terminal of the linear driving circuit is coupled to the control terminal of the high-end transistor, and the second output terminal is coupled to the control terminal of the low-end transistor; Among them, when the dual-mode amplifier works in the linear working mode, the first output end and the second output end of the switch driving circuit are in a high-impedance state, and the linear driving circuit controls the high-end transistor and the low-end transistor; when the dual-mode amplifier works in the switching mode, the first output end and the second output end of the linear driving circuit are in a high-impedance state, and the switch driving circuit controls the high-end transistor and the low-end transistor.

2. The dual-mode amplifier circuit according to claim 1, characterized in that: The switch driving circuit comprises: A dead time generating unit, comprising a first input terminal, a first output terminal and a second output terminal, wherein the first input terminal is coupled to a digital input signal, and the dead time generating unit generates a first intermediate control signal and a second intermediate control signal according to the digital input signal; wherein the first intermediate control signal participates in the generation of the second intermediate control signal, and the second intermediate control signal participates in the generation of the first intermediate control signal, so as to generate the dead time; and the first intermediate control signal and the second intermediate control signal have complementary effective times; A high-end switch driving unit receives the first intermediate control signal and generates a switch signal, wherein the output end of the high-end switch driving unit serves as the first output end of the switch driving circuit and charges or discharges the control end of the high-end transistor according to the switch signal; The low-end switch driving unit receives the second intermediate control signal, has an output end serving as the second output end of the switch driving circuit, and charges or discharges the control end of the low-end transistor according to the second intermediate control signal.

3. The dual-mode amplifier circuit according to claim 2, characterized in that: The dead time generating unit comprises: A twentieth NOT gate L5, having an input terminal and an output terminal, wherein the input terminal receives a digital input signal; A twenty-first NOT gate L19 having an input terminal and an output terminal, wherein the input terminal is coupled to the output terminal of the twentieth NOT gate L5; a fifth NAND gate L18, having a first terminal, a second terminal and an output terminal, wherein the first terminal is coupled to the output terminal of the twenty-first NAND gate L19, and the output terminal provides a first intermediate control signal; A twenty-second NOT gate L16 has an input terminal and an output terminal, and its input terminal receives a digital input signal; a sixth NAND gate L15, having a first terminal, a second terminal and an output terminal, wherein the second terminal is coupled to the output terminal of the twenty-second NAND gate L16, and the output terminal provides a second intermediate control signal; A seventh NAND gate L27, having a first terminal, a second terminal and an output terminal, wherein the first terminal receives the first intermediate control signal, and the second terminal is coupled to the first output terminal of the switch driving circuit; A twenty-third NOT gate L6 having an input terminal and an output terminal, wherein the input terminal is coupled to the output terminal of the seventh NAND gate L27; A twenty-fourth NOT gate L23 has an input terminal and an output terminal, wherein the input terminal is coupled to the output terminal of the twenty-third NOT gate L6; a twenty-fifth NOT gate L22 having an input terminal and an output terminal, wherein the input terminal is coupled to the output terminal of the twenty-fourth NOT gate L23, and the output terminal is coupled to the first terminal of the sixth NAND gate L15; an eighth NAND gate L11, having a first terminal, a second terminal and an output terminal, wherein the first terminal receives the second intermediate control signal, and the second terminal is coupled to the second output terminal of the switch driving circuit; A twenty-sixth NOT gate L14 has an input terminal and an output terminal, and the input terminal is coupled to the output terminal of the eighth NAND gate L11; A twenty-seventh NOT gate L21 has an input terminal and an output terminal, and the input terminal is coupled to the output terminal of the twenty-sixth NOT gate L14; The twenty-eighth NOT gate L20 has an input terminal and an output terminal, wherein the input terminal is coupled to the output terminal of the twenty-seventh NOT gate L21 , and the output terminal is coupled to the second terminal of the fifth NAND gate L18 .

4. The dual-mode amplifier circuit according to claim 3, characterized in that: The high-end switch driving unit comprises: A twenty-ninth NOT gate L3, having an input terminal and an output terminal, wherein the input terminal receives the first intermediate control signal, and the output terminal provides a switch signal; The high-end switch driving circuit has an input terminal and an output terminal, wherein the input terminal is coupled to the output terminal of the twenty-ninth NOT gate L3, and the output terminal is coupled to the control terminal of the high-end transistor.

5. The dual-mode amplifier circuit according to claim 3, characterized in that: The switch driving circuit further includes a double insurance unit, and the double insurance unit includes: A fiftieth transistor PP0 has a first terminal, a second terminal and a control terminal, wherein the second terminal is coupled to the control terminal of the high-end transistor, and the control terminal is coupled to the second terminal of the high-end transistor; A fifty-first transistor NN0 has a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the first terminal of the fiftieth transistor PP0, and the control terminal receives an inverted signal of the mode selection signal; A second resistor R0 has a first end and a second end, wherein the first end is coupled to the second end of the fifty-first transistor NN0, and the second end is coupled to the reference ground; A fifty-second transistor PP1 has a first terminal, a second terminal and a control terminal, wherein the second terminal is coupled to a reference voltage signal, and the control terminal receives a mode selection signal; a fifty-third transistor NN12 having a first terminal, a second terminal and a control terminal, wherein the second terminal is coupled to the reference ground, and the control terminal is coupled to the second terminal of the fifty-first transistor NN0; a 30th NOT gate L38 having an input terminal and an output terminal, wherein the input terminal is respectively coupled to the first terminal of the 52nd transistor PP1 and the first terminal of the 53rd transistor NN12; a thirty-first NOT gate L0 having an input terminal and an output terminal, wherein the input terminal is coupled to the output terminal of the thirtieth NOT gate L38, and the output terminal is coupled to the second terminal of the seventh NAND gate L27; a ninth NAND gate L1 having a first terminal, a second terminal and an output terminal, wherein the first terminal receives the first intermediate control signal and the second terminal is coupled to the output terminal of the thirty-first NAND gate L0; a tenth NAND gate L40 having a first terminal, a second terminal and an output terminal, wherein the first terminal is coupled to the output terminal of the ninth NAND gate L1, and the second terminal receives a mode selection signal; The fifty-fourth transistor N111 has a first end, a second end and a control end, wherein the first end is coupled to the first output end of the switch driving circuit, the second end is coupled to the reference ground, and the control end is coupled to the output end of the tenth NAND gate L40.

6. The dual-mode amplifier circuit according to claim 3, characterized in that: The low-end switch driving unit comprises: a fifty-fifth transistor PP9, having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the control terminal of the low-side transistor, the second terminal is coupled to the power supply voltage signal, and the control terminal is driven according to the logic states of the mode selection signal and the second intermediate control signal; The fifty-sixth transistor NN11 has a first end, a second end and a control end. The first end is coupled to the control end of the low-end transistor, the second end is coupled to the reference ground, and the control end is driven according to the inverted signal of the mode selection signal and the logic state of the second intermediate control signal.

7. The dual-mode amplifier circuit according to claim 6, characterized in that: The low-end switch driving unit further includes: A first NOR gate L26, having a first terminal, a second terminal and an output terminal, wherein the first terminal receives the mode selection signal, and the second terminal receives the second intermediate control signal; A thirty-second NOT gate L25 having an input terminal and an output terminal, wherein the input terminal is coupled to the output terminal of the first NOR gate L26; A thirty-third NOT gate L8 has an input terminal and an output terminal, and the input terminal is coupled to the output terminal of the thirty-second NOT gate L25; A thirty-fourth NOT gate L7 having an input terminal and an output terminal, wherein the input terminal is coupled to the output terminal of the thirty-third NOT gate L8, and the output terminal is coupled to the control terminal of the fifty-fifth transistor PP9; an eleventh NAND gate L28, having a first terminal, a second terminal and an output terminal, wherein the first terminal receives the second intermediate control signal, and the second terminal receives the inverted signal of the mode selection signal; A thirty-fifth NOT gate L29 having an input terminal and an output terminal, wherein the input terminal is coupled to the output terminal of the eleventh NAND gate L28; A thirty-sixth NOT gate L31 has an input terminal and an output terminal, and the input terminal is coupled to the output terminal of the thirty-fifth NOT gate L29; The thirty-seventh NOT gate L30 has an input terminal and an output terminal, wherein the input terminal is coupled to the output terminal of the thirty-sixth NOT gate L31 , and the output terminal is coupled to the control terminal of the fifty-sixth transistor NN11 .

8. The dual-mode amplifier circuit according to claim 7, characterized in that: The switch driving circuit further includes an enhanced shutdown unit, and the enhanced shutdown unit includes: A thirty-eighth NOT gate L37 having an input terminal and an output terminal, wherein the input terminal is coupled to the second output terminal of the switch driving circuit; A thirty-ninth NOT gate L9 has an input terminal and an output terminal, and the input terminal is coupled to the output terminal of the thirty-eighth NOT gate L37; a fortieth NOT gate L10 having an input terminal and an output terminal, wherein the input terminal is coupled to the output terminal of the thirty-ninth NOT gate L9; A twelfth NAND gate L12 has a first end, a second end and an output end, wherein the first end is coupled to the output end of the thirty-fifth NAND gate L29, and the second end is coupled to the output end of the fortieth NAND gate L10; a forty-first NOT gate L13 having an input terminal and an output terminal, wherein the input terminal is coupled to the output terminal of the twelfth NAND gate L12; The fifty-seventh transistor NN4 has a first end, a second end and a control end, wherein the first end is coupled to the second output end of the switch driving circuit, the second end is coupled to the reference ground, and the control end is coupled to the output end of the forty-first NOT gate L13.

9. The dual-mode amplifier circuit according to claim 1, characterized in that: Also includes: an enable signal for terminating or starting a linear operation mode of the dual-mode amplifier circuit, and terminating and starting a switch mode of the dual-mode amplifier circuit; The switch driving circuit receives an enable signal, and when the enable signal is at a first level, causes the first output terminal and the second output terminal of the switch driving circuit to be in a high impedance state; The linear driving circuit receives an enable signal, and when the enable signal is at a second level, causes the first output terminal and the second output terminal of the linear driving circuit to be in a high impedance state.

10. The dual-mode amplifier circuit according to claim 1, characterized in that: The linear drive circuit comprises: A first transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal of the first transistor is coupled to a high voltage signal through a first current source, and the control terminal of the first transistor is connected to the first terminal of the first transistor; A second transistor having a first end, a second end and a control end, the first end of the second transistor being coupled to the second end of the first transistor, the second end of the second transistor being coupled to a first voltage signal, and the control end of the second transistor receiving a second amplified signal; A first amplifier having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the first amplifier is coupled to the second terminal of the first transistor, the second input terminal of the first amplifier is coupled to the second terminal of the high-end transistor, and the output terminal of the first amplifier provides a first amplified signal; The second amplifier has a first input terminal, a second input terminal and an output terminal. The first input terminal of the second amplifier receives an analog input signal, the second input terminal of the second amplifier receives a voltage output signal, and the output terminal of the second amplifier provides a second amplified signal.

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