Implementation circuit for reducing high-temperature electric leakage of ESD device
By combining a built-in LDO circuit and an ESD protection diode, the problem of leakage current at high temperatures in traditional chip I/O ports is solved, enabling chip protection and reducing leakage current during ESD events, thus ensuring normal chip operation.
Patent Information
- Application Number
- CN202411153410.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-21
- Publication Date
- 2024-12-13
AI Technical Summary
Traditional chip I/O port ESD protection structures suffer from leakage current at high temperatures, affecting the normal function of the chip, especially as the leakage current varies significantly under different I/O voltages.
The combination of built-in LDO circuit and ESD protection diode is adopted. The ESD diode is reverse biased by static power supply bias, and the built-in LDO circuit provides power supply bias to ensure that the ESD diode conducts forward to discharge current in ESD event, while canceling diode leakage current at high temperature.
Protect the chip from damage in ESD events, and reduce leakage current at I/O ports at high temperatures to ensure that the chip's normal function is not affected.
Smart Images
Figure CN119135156A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the technical field of integrated circuits, in particular to a circuit for reducing high-temperature leakage of ESD devices. Background Art
[0002] The chip IO port is the interface between the internal circuit and the outside world. This interface is often accompanied by various ESD discharge events, such as HBM, CDM, MM and other discharge modes. Therefore, the chip IO port needs an ESD protection device. When an ESD event occurs in the chip, since the parasitic capacitance of the chip port is relatively small, the ESD device needs to provide a large current to discharge the large amount of charge flowing into the port, so as to avoid damage to the chip due to excessive port voltage.
[0003] The ESD protection structure of the traditional chip IO port consists of a ground-to-IO diode, an IO-to-power diode, and a power-to-ground clamping circuit. When an ESD event occurs, the IO-to-ground ESD charge injection is forward-conducted to the power clamping circuit for discharge by the ground-to-IO diode; the IO-to-ground ESD charge outflow is forward-conducted to the power diode for discharge. In order to obtain a higher ESD level, such as HBM reaching 4k / 8k, the chip needs a larger ESD device to provide a larger current capacity to discharge the charge. At high temperatures, larger ESD devices will generate a relatively large leakage current. When the ground-to-IO diode and the IO-to-power diode use the same structure, the leakage currents of the two diodes will cancel each other out, but a part of the leakage current will still flow into the IO port. This is because the leakage current of the diode is related to the voltage across it. For different IO voltages, the voltages across the ground-to-IO diode and the IO-to-power diode will not match, so the leakage currents of the two diodes cannot be completely offset. Usually, additional leakage current appears at the chip IO port, which will interact with the current flowing through the port in the chip's own function, thereby affecting the normal function of the chip.
[0004] In short, for different IO voltages, the leakage current of the IO port at high temperature will change. This part of the current flowing into the internal circuit will affect the normal function of the chip. Therefore, a circuit that can reduce the high-temperature leakage of ESD devices is needed to solve practical problems. Summary of the invention
[0005] With regard to the above problems existing in the prior art, the object of the present invention is to provide a circuit for reducing the high temperature leakage of ESD devices, so as to solve the problems raised in the above background technology.
[0006] To achieve the above object, the present invention provides the following technical solutions:
[0007] A circuit for reducing high temperature leakage of ESD devices, including a built-in LDO circuit, an ESD protection diode D1, an ESD protection diode D2, a power ground power clamp circuit and an internal circuit;
[0008] The built-in LDO circuit includes an operational amplifier EA and a voltage-dividing resistor network;
[0009] The positive pole of the power input of the operational amplifier EA is connected to the power supply VIN, and the negative pole of the power input of the operational amplifier EA is grounded;
[0010] The positive input terminal of the operational amplifier EA is connected to the input and output IO port;
[0011] The output end of the operational amplifier EA is connected to the gate of the NMOS tube NM15 and the positive electrode of the polarized capacitor C2; the negative electrode of the polarized capacitor C2 is grounded;
[0012] The drain of the NMOS tube NM15 is connected to the power supply VIN, and the source of the NMOS tube NM15 is connected to the positive electrode of the polar capacitor C1; the negative electrode of the polar capacitor C1 is grounded;
[0013] The voltage-dividing resistor network includes resistor R3 and resistor R4;
[0014] The negative input terminal of the operational amplifier EA is connected to one end of the resistor R3 and one end of the resistor R4;
[0015] The other end of the resistor R3 is connected to the positive electrode of the polarized capacitor C1; the other end of the resistor R4 is connected to the negative electrode of the polarized capacitor C1;
[0016] The source of NMOS tube NM15 is connected to the output end of ESD protection diode D1.
[0017] The input end of the ESD protection diode D1 is connected to the output end of the ESD protection diode D2 and the input and output IO port;
[0018] The input end of the ESD protection diode D2 is grounded;
[0019] The power ground power clamp circuit includes an NMOS tube NM1 and a resistor R1;
[0020] The source of the NMOS tube NM15 is connected to the drain of the NMOS tube NM1, and the source of the NMOS tube NM1 is grounded;
[0021] The gate of the NMOS tube NM1 is connected to one end of the resistor R1, and the other end of the resistor R1 is grounded;
[0022] The input / output IO port is connected to one end of the resistor R2, and the other end of the resistor R2 is connected to the internal circuit;
[0023] The positive terminal of the power input of the internal circuit is connected to the power supply VIN, and the negative terminal of the power input of the internal circuit is grounded.
[0024] As a further solution of the present invention: the operational amplifier EA includes a PMOS tube PM11, a PMOS tube PM12, a PMOS tube PM13, a PMOS tube PM14, an NMOS tube NM11, an NMOS tube NM12, an NMOS tube NM13 and an NMOS tube NM14;
[0025] The power source VIN is connected to the input end of the current source I0, and the output end of the current source I0 is connected to the source of the PMOS tube PM11 and the source of the PMOS tube PM12;
[0026] The drain of the PMOS tube PM11 is simultaneously connected to the drain of the NMOS tube NM11, the gate of the NMOS tube NM11, and the gate of the NMOS tube NM13;
[0027] The drain of the PMOS tube PM12 is simultaneously connected to the drain of the NMOS tube NM12, the gate of the NMOS tube NM12, and the gate of the NMOS tube NM14;
[0028] The drain of the NMOS tube NM13 is connected to the drain of the PMOS tube PM13 and the gate of the PMOS tube PM13, and the source of the PMOS tube PM13 is connected to the power supply VIN; the source of the NMOS tube NM13 is grounded;
[0029] The drain of the NMOS tube NM14 is connected to the drain of the PMOS tube PM14, the source of the PMOS tube PM14 is connected to the power supply VIN, the gate of the PMOS tube PM14 is connected to the gate of the PMOS tube PM13; the source of the NMOS tube NM14 is grounded.
[0030] As a further solution of the present invention: the gate of the PMOS tube PM11 is connected to the input and output IO port as the positive input terminal of the operational amplifier EA.
[0031] As a further solution of the present invention: the gate of the PMOS tube PM11 is connected to one end of the resistor R3 as the negative input terminal of the operational amplifier EA, and the other end of the resistor R3 is connected to the positive electrode of the polar capacitor C1.
[0032] As a further solution of the present invention: the drain of the NMOS tube NM14 is connected to the positive electrode of the polar capacitor C2 as the output end of the operational amplifier EA.
[0033] As a further solution of the present invention:
[0034] Compared with the prior art, the present invention has the following beneficial effects:
[0035] The built-in LDO circuit of the present invention only provides a static bias of the power supply, so that the ESD diode is reverse biased; in the ESD event, the forward ESD event of IO to ground is still discharged through the forward conducting diode D1 and the power clamp circuit, which can not only provide sufficient power output to protect the chip during the ESD event to prevent damage to the internal circuit of the chip, but also can not affect the high-temperature leakage performance requirements of the chip when it is working, avoid the leakage current of the IO port at high temperature, and increase safety. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] Figure 1 The present invention is a schematic diagram of a circuit structure of a circuit for reducing high temperature leakage of an ESD device disclosed in an embodiment.
[0037] Figure 2 The present invention is a schematic diagram of a structure of a built-in LDO circuit in a circuit for reducing high-temperature leakage of an ESD device disclosed in an embodiment. DETAILED DESCRIPTION
[0038] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention; it is obvious that the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0039] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "provided with", "connected", and "connected" should be understood in a broad sense; for example, it can be a fixed connection, a detachable connection, or an integral connection, a mechanical connection, or an electrical connection, a direct connection, or an indirect connection through an intermediate medium, or the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0040] See also Figure 1-2, a circuit for reducing high-temperature leakage of ESD devices, including a built-in LDO circuit, an ESD protection diode D1, an ESD protection diode D2, a power ground power clamp circuit, and an internal circuit; the built-in LDO circuit includes an operational amplifier EA and a voltage-dividing resistor network; the positive power input of the operational amplifier EA is connected to the power supply VIN, and the negative power input of the operational amplifier EA is grounded; the positive input terminal of the operational amplifier EA is connected to the input and output IO port; the output terminal of the operational amplifier EA is connected to the gate of the NMOS tube NM15 and the positive electrode of the polarized capacitor C2; the negative electrode of the polarized capacitor C2 is grounded; the drain of the NMOS tube NM15 is connected to the power supply VIN, and the source of the NMOS tube NM15 is connected to the positive electrode of the polarized capacitor C1; the negative electrode of the polarized capacitor C1 is grounded; the voltage-dividing resistor network includes a resistor R3 and a resistor R4; the negative input terminal of the operational amplifier EA is connected to one end of the resistor R3 and one end of the resistor R4; The other end of the resistor R3 is connected to the positive electrode of the polar capacitor C1; the other end of the resistor R4 is connected to the negative electrode of the polar capacitor C1; the source of the NMOS tube NM15 is connected to the output end of the ESD protection diode D1; the input end of the ESD protection diode D1 is connected to the output end of the ESD protection diode D2 and the input and output IO port; the input end of the ESD protection diode D2 is grounded; the power ground power clamp circuit includes an NMOS tube NM1 and a resistor R1; the source of the NMOS tube NM15 is connected to the drain of the NMOS tube NM1, and the source of the NMOS tube NM1 is grounded; the gate of the NMOS tube NM1 is connected to one end of the resistor R1, and the other end of the resistor R1 is grounded; the input and output IO port is connected to one end of the resistor R2, and the other end of the resistor R2 is connected to the internal circuit; the positive end of the power input of the internal circuit is connected to the power supply VIN, and the negative end of the power input of the internal circuit is grounded;
[0041] In order to achieve lower leakage current of IO port and avoid affecting the normal function of internal circuit, the present invention proposes IO voltage following power supply technology to provide power bias for ESD diode. According to the change of IO port voltage, the voltage across D2 will change. Through voltage bias technology, the voltage across D1 is equal to the voltage across D2, so that the high temperature leakage current of D1 and D2 is equal, thereby achieving better offset effect of leakage current of two ESD diodes. Therefore, through the built-in LDO circuit, the voltage of IO port is amplified by 2 times to generate power rail bias of D1.
[0042] like Figure 2As shown, the operational amplifier EA includes a PMOS tube PM11, a PMOS tube PM12, a PMOS tube PM13, a PMOS tube PM14, an NMOS tube NM11, an NMOS tube NM12, an NMOS tube NM13, and an NMOS tube NM14; the power supply VIN is connected to the input end of the current source I0, the output end of the current source I0 is connected to the source of the PMOS tube PM11 and the source of the PMOS tube PM12, the gate of the PMOS tube PM11 is connected to the input and output IO port as the positive input end of the operational amplifier EA; the gate of the PMOS tube PM11 is connected to one end of the resistor R3 as the negative input end of the operational amplifier EA, and the other end of the resistor R3 is connected to the positive electrode of the polar capacitor C1; the drain of the PMOS tube PM11 is simultaneously connected to the drain of the NMOS tube NM11, the gate of the NMOS tube NM11, The gate of the NMOS tube NM13 is connected; the drain of the PMOS tube PM12 is simultaneously connected to the drain of the NMOS tube NM12, the gate of the NMOS tube NM12, and the gate of the NMOS tube NM14; the drain of the NMOS tube NM13 is connected to the drain of the PMOS tube PM13 and the gate of the PMOS tube PM13, and the source of the PMOS tube PM13 is connected to the power supply VIN; the source of the NMOS tube NM13 is grounded; the drain of the NMOS tube NM14 is connected to the drain of the PMOS tube PM14, the source of the PMOS tube PM14 is connected to the power supply VIN, and the gate of the PMOS tube PM14 is connected to the gate of the PMOS tube PM13; the source of the NMOS tube NM14 is grounded; the drain of the NMOS tube NM14 is connected to the positive electrode of the polar capacitor C2 as the output terminal of the operational amplifier EA;
[0043] The built-in LDO circuit uses a traditional OTA structure op amp as the error amplifier of the built-in LDO circuit. The error amplifier output VA is connected to the gate of the output NMOS tube NM15. The output voltage is provided through the source of NM15. The output voltage generates a feedback voltage VFB through the resistor divider network R3 and R4, and VFB is fed back to the gate of the error amplifier input stage PM11. The gate of another MOS tube PM12 of the input stage is connected to the IO port. The compensation network of the built-in LDO circuit is the error amplifier output terminal VA connected to the ground capacitor C2. The output voltage VCC is connected to the ground output capacitor C1, which can finally provide 2 times the IO voltage.
[0044] The current source I0 constitutes the error amplifier of the built-in LDO circuit 1, the NMOS tube NM15 is used as the output tube, the resistor R3 and the resistor R4 constitute the output voltage divider network, the polar capacitor C2 is the compensation circuit of the error amplifier, and the polar capacitor C1 is the output capacitor of the built-in LDO circuit.
[0045] Aiming at the problem that the leakage of ESD devices at IO ports in low-power OP, LDO and DC-DC chips easily affects the normal operation of the chips, the present invention provides a port ESD solution with lower leakage current, which can not only provide sufficient power output to protect the chip during ESD events, but also does not affect the high-temperature leakage performance requirements of the chip when it is working. The present invention is applied to reduce the high-temperature leakage of port ESD devices, mainly involving application scenarios such as low-power operational amplifiers (OP), low-dropout linear regulators (LDO) and DC-DC switching bucks (DC-DC).
[0046] The built-in LDO circuit in the present invention only provides a static bias of the power supply, so that the ESD diode is reverse biased; in the ESD event, the forward ESD event of IO to ground is still prevented from damaging the internal circuit of the chip by discharging the current through the forward conducting diode D1 and the power clamp circuit.
[0047] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential features of the present invention. Therefore, the embodiments should be considered exemplary and non-restrictive from any point of view. The scope of the present invention is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims be included in the present invention, and any reference numerals in the claims should not be considered as limiting the claims involved.
[0048] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.
Claims
1. A circuit for reducing high temperature leakage of ESD devices, characterized in that: It includes a built-in LDO circuit, an ESD protection diode D1, an ESD protection diode D2, a power ground power clamp circuit and an internal circuit; The built-in LDO circuit includes an operational amplifier EA and a voltage-dividing resistor network; The positive pole of the power input of the operational amplifier EA is connected to the power supply VIN, and the negative pole of the power input of the operational amplifier EA is grounded; The positive input terminal of the operational amplifier EA is connected to the input and output IO port; The output end of the operational amplifier EA is connected to the gate of the NMOS tube NM15 and the positive electrode of the polarized capacitor C2; the negative electrode of the polarized capacitor C2 is grounded; The drain of the NMOS tube NM15 is connected to the power supply VIN, and the source of the NMOS tube NM15 is connected to the positive electrode of the polarized capacitor C1; the negative electrode of the polarized capacitor C1 is grounded; The voltage-dividing resistor network includes resistor R3 and resistor R4; The negative input terminal of the operational amplifier EA is connected to one end of the resistor R3 and one end of the resistor R4; The other end of the resistor R3 is connected to the positive electrode of the polarized capacitor C1; the other end of the resistor R4 is connected to the negative electrode of the polarized capacitor C1; The source of NMOS tube NM15 is connected to the output end of ESD protection diode D1. The input end of the ESD protection diode D1 is connected to the output end of the ESD protection diode D2 and the input and output IO port; The input end of the ESD protection diode D2 is grounded; The power ground power clamp circuit includes an NMOS tube NM1 and a resistor R1; The source of the NMOS tube NM15 is connected to the drain of the NMOS tube NM1, and the source of the NMOS tube NM1 is grounded; The gate of the NMOS tube NM1 is connected to one end of the resistor R1, and the other end of the resistor R1 is grounded; The input / output IO port is connected to one end of the resistor R2, and the other end of the resistor R2 is connected to the internal circuit; The positive terminal of the power input of the internal circuit is connected to the power supply VIN, and the negative terminal of the power input of the internal circuit is grounded.
2. A circuit for reducing high temperature leakage of ESD devices according to claim 1, characterized in that: The operational amplifier EA includes a PMOS tube PM11, a PMOS tube PM12, a PMOS tube PM13, a PMOS tube PM14, an NMOS tube NM11, an NMOS tube NM12, an NMOS tube NM13 and an NMOS tube NM14; The power source VIN is connected to the input terminal of the current source I0, and the output terminal of the current source I0 is connected to the source of the PMOS tube PM11 and the source of the PMOS tube PM12; The drain of the PMOS tube PM11 is simultaneously connected to the drain of the NMOS tube NM11, the gate of the NMOS tube NM11, and the gate of the NMOS tube NM13; The drain of the PMOS tube PM12 is simultaneously connected to the drain of the NMOS tube NM12, the gate of the NMOS tube NM12, and the gate of the NMOS tube NM14; The drain of the NMOS tube NM13 is connected to the drain of the PMOS tube PM13 and the gate of the PMOS tube PM13, and the source of the PMOS tube PM13 is connected to the power supply VIN; the source of the NMOS tube NM13 is grounded; The drain of the NMOS tube NM14 is connected to the drain of the PMOS tube PM14, the source of the PMOS tube PM14 is connected to the power supply VIN, the gate of the PMOS tube PM14 is connected to the gate of the PMOS tube PM13; the source of the NMOS tube NM14 is grounded.
3. A circuit for reducing high temperature leakage of ESD devices according to claim 2, characterized in that: The gate of the PMOS tube PM11 is connected to the input / output IO port as the positive input terminal of the operational amplifier EA.
4. A circuit for reducing high temperature leakage of ESD devices according to claim 3, characterized in that: The gate of the PMOS tube PM11 is connected to one end of the resistor R3 as the negative input terminal of the operational amplifier EA, and the other end of the resistor R3 is connected to the positive electrode of the polarized capacitor C1.
5. A circuit for reducing high temperature leakage of ESD devices according to claim 4, characterized in that: The drain of the NMOS tube NM14 is connected to the positive electrode of the polarized capacitor C2 as the output terminal of the operational amplifier EA.