Analog-to-digital conversion circuit and electronic equipment

Abstract

The invention provides an analog-to-digital conversion circuit and electronic equipment, and relates to the field of integrated circuits. The coarse quantization unit and the fine quantization unit simultaneously sample an input differential signal and store the input differential signal on a capacitor array of the fine quantization unit. The coarse quantization unit firstly uses the resistor string unit to carry out coarse quantization on the voltage quantity to obtain 2M-1-bit thermometer codes, the 2M-1-bit thermometer codes are transmitted to the thermometer code capacitance control logic of the fine quantization unit, and meanwhile transcoding is carried out to obtain M-bit binary codes. And the fine quantization unit is combined with the redundant bit capacitor and resistor string unit to jointly carry out calibration and fine quantization on the residual voltage quantity to obtain an N + 2 bit binary code. And the digital error correction unit performs digital error correction on the M-bit binary code and the N + 2-bit binary code to obtain an M + N-bit binary code and outputs the M + N-bit binary code. According to the method, the problem that coarse quantization and fine quantization of the whole ADC are not matched due to the fact that the coarse quantization precision is limited is successfully solved. Therefore, the analog-to-digital conversion circuit provided by the invention reaches the precision of a traditional high-precision SAR-ADC. And the overall power consumption overhead is saved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to an analog-to-digital conversion circuit and an electronic device. Background Art

[0002] Analog-to-digital converters (ADCs) are the key bridge between the physical world and the virtual world. The development of IoT systems usually requires ADCs with medium to high precision and high energy efficiency. The successive approximation register ADC (SAR ADC) is currently the most widely used ADC.

[0003] At present, there are many improved SAR ADC structures based on the traditional SAR ADC structure, such as the structure type with separate coarse and fine quantization. However, there is a problem of mismatch between the coarse and fine quantization precision in this type of SAR ADC structure, which leads to the problem that the residual voltage is too large during fine quantization and the quantization cannot be completed normally. Summary of the invention

[0004] In view of the above problems, the present invention is proposed to provide an analog-to-digital conversion circuit and an electronic device that solve the above problems or partially solve the above problems.

[0005] A first aspect of an embodiment of the present invention provides an analog-to-digital conversion circuit, the analog-to-digital conversion circuit comprising: a coarse quantization unit, a fine quantization unit, a resistor string unit, and a digital error correction unit;

[0006] The coarse quantization unit and the fine quantization unit simultaneously sample the input differential signal, and both end sampling at the falling edge of the sampling clock, and store the voltage corresponding to the input differential signal on the capacitor array of the fine quantization unit, wherein the capacitor array of the fine quantization unit includes: a thermometer code capacitor, a binary capacitor, and a redundant bit capacitor;

[0007] After sampling is completed, the coarse quantization unit first uses the resistor string unit to coarsely quantize the voltage quantity to obtain 2 M -1-bit thermometer code, and after the coarse quantization is completed, the quantized thermometer code is transmitted to the thermometer code capacitor control logic of the fine quantization unit, and at the same time, the quantized thermometer code is transcoded to obtain an M-bit binary code and transmitted to the digital error correction unit;

[0008] The fine quantization unit performs a subtraction operation based on the thermometer code capacitor control logic and the voltage quantity using the capacitor array to obtain a residual voltage quantity, and calibrates and finely quantizes the residual voltage quantity in combination with the redundant bit capacitor and the resistor string unit to obtain an N+2-bit binary code, and transmits the code to the digital error correction unit;

[0009] The digital error correction unit performs digital error correction on the M-bit binary code and the N+2-bit binary code to obtain and output an M+N-bit binary code, where the M+N-bit binary code is a digital value corresponding to the voltage amount.

[0010] Optionally, the coarse quantization unit comprises: a comparator array, a thermometer code register, and a thermometer code to binary code decoder;

[0011] Each comparator in the comparator array has: a pair of positive and negative input terminals of the comparator connected to two ends of a unit resistor in the resistor string unit, respectively, and another pair of positive and negative input terminals receiving the input differential signal;

[0012] The output terminals of all comparators are connected to the thermometer code register;

[0013] The thermometer code register is connected to the thermometer code to binary code decoder;

[0014] Among them, one end of the resistor string unit receives the reference voltage and the other end is grounded, so the resistor string unit generates 2 M -1 reference voltage, respectively V R1 ,V R2 ,…,V R2 M -1 , said 2 M -1 reference voltage is provided to 2 M - 1 comparator as the reference voltage for each comparator;

[0015] During the coarse quantization, each of the comparators generates a code value of 0 or 1 according to the respective reference voltage and the magnitude of the input differential voltage, and all the comparators generate a total of 2 M -1-bit thermometer code and transmitted to the thermometer code register for storage;

[0016] The thermometer code register will be the 2 M -1 bit of thermometer code is transmitted to the thermometer code capacitor control logic and the thermometer code to binary code decoder;

[0017] The thermometer code to binary code decoder converts the 2 M -1-bit thermometer code is transcoded to obtain M-bit binary code and transmitted to the digital error correction unit;

[0018] The number of unit resistors in the resistor string unit is: 2 M .

[0019] Optionally, the fine quantization unit includes: the capacitor array, the switch array, the fine quantization comparator and the logic unit; the thermometer code capacitor, the binary capacitor and the redundant bit capacitor all include: sub-capacitors;

[0020] The thermometer code capacitor, the sub-capacitor of the redundant bit capacitor, and each sub-capacitor except the target sub-capacitor in the binary capacitor, the lower plate of which is connected to three control switches, respectively connected to the input differential signal, the reference voltage and the ground, and the upper plate is connected to the bias voltage and the two input terminals of the fine quantization comparator, and the output terminal of the fine quantization comparator is connected to the logic unit;

[0021] The lower plate of the target sub-capacitor is connected to three control switches, which are respectively connected to the switch array, the reference voltage and the ground, and the upper plates are connected to the bias voltage and two input terminals of the fine quantization comparator, and the switch array is connected to the resistor string unit;

[0022] The thermometer code capacitor is controlled by the thermometer code capacitor control logic, and the lower plate of the thermometer code capacitor is grounded or connected to the reference voltage according to the thermometer code to perform the subtraction operation, and the coarse quantized voltage is subtracted to obtain the residual voltage;

[0023] The binary capacitor uses the fine quantization comparator and the logic unit to perform a first successive approximation operation from high to low, and after the lower plate of the target unit capacitor is determined to be connected to the reference voltage or grounded, the switch array combines with the resistor string unit to continue to perform a second successive approximation operation, thereby completing fine quantization;

[0024] In the process of fine quantization of the binary capacitor, if an ultra-fine quantization range occurs, the redundant bit capacitor is used to correct and calibrate the erroneous thermometer code to obtain the N+2-bit binary code, and transmit it to the digital error correction unit;

[0025] The size of each sub-capacitor in the thermometer code capacitor is 2 M C, the redundant capacitor includes: two sub-capacitors, both of which are 2 M-1 C, the binary capacitor neutron capacitance size from 2 M-1 C to 1C, decreasing successively by multiples of 2, wherein the smallest 1C sub-capacitor is the target sub-capacitor.

[0026] Optionally, the redundant capacitor further includes: two redundant sub-capacitors each having a size of 1C;

[0027] The sizes are all 2 M-1The lower plates of the two redundant sub-capacitors of size C and the two redundant sub-capacitors of size 1C are respectively connected to two control switches, respectively connected to the reference voltage and ground, and the upper plates are both connected to the bias voltage.

[0028] Optionally, the switch array comprises: a plurality of switches;

[0029] Each of the switches is controlled by the logic unit, and according to different closing and opening conditions of the switch, the lower plate of the target sub-capacitor obtains different voltages generated on the resistor string unit.

[0030] Optionally, in the sampling stage, the sampling signal is effective at a high level, the comparator array in the coarse quantization unit is reset and the output is cleared, and the thermometer code value output by the comparator array is: TH<2 M -1: 1>=00...0000. At the same time, the upper plate of the capacitor array is connected to the bias voltage, and the lower plate is connected to the input differential signal. At this time, the charge on the capacitor array is expressed as:

[0031] Q DACP =(V cM -V in )·2 2M C

[0032] Q DACN =(V CM -V ip )·2 2M C

[0033] In the above formula, Q DACP represents the charge on the capacitor array connected to the positive input terminal of the fine quantization comparator, Q DACN represents the charge on the capacitor array connected to the negative input terminal of the fine quantization comparator;

[0034] The sampling phase ends, the sampling signal is ineffective at a low level, and each comparator in the comparator array in the coarse quantization unit outputs a code value of 0 or 1 according to the magnitude of the input differential voltage and the reference voltage, and latches the code value and transmits it to the thermometer code capacitor control logic;

[0035] When the sampling signal is at a low level and is invalid, the switch of the upper plate of the capacitor array connected to the bias voltage is disconnected, and the lower plates of all sub-capacitors of the capacitor array connected to the positive input terminal of the fine quantization comparator except the thermometer code capacitor and the target sub-capacitor are switched from being connected to the input differential signal to being connected to the reference voltage, and the lower plates of all sub-capacitors of the capacitor array connected to the negative input terminal of the fine quantization comparator except the thermometer code capacitor and the target sub-capacitor are switched from being connected to the input differential signal to being grounded. At this time, the charges at both ends of the capacitor array connected to the positive input terminal and the negative input terminal of the fine quantization comparator are respectively:

[0036] Q DACP =V DACP 2 2M C+V REF ·(2 M -K)·2 M C

[0037] Q DACN =V DACP 2 2M C+V REF ·K·2 M C

[0038] In the above formula, V DACP and V DACN represents the voltage value of the positive and negative input terminals of the fine quantization comparator respectively, K represents that in the quantization output of the coarse quantization, there are K code values ​​of 1 output, and 2 code values ​​of 0 output M -1-K, then according to the charge conservation principle, the voltages at the positive and negative input terminals of the fine quantization comparator are:

[0039]

[0040] Then the following formula is obtained for the fine quantization comparator:

[0041]

[0042] According to the above formula, the thermometer code value completes the subtraction operation on the capacitor array to obtain the residual voltage, where is a coarsely quantized voltage value, and the voltage value corresponding to the differential input signal ranges from a negative reference voltage to a positive reference voltage;

[0043] After the subtraction operation is completed to obtain the residual voltage, the remaining voltage on the capacitor array is the residual voltage, and the fine quantization stage is entered. In the fine quantization stage, first, the binary capacitor with a size of 2 M -1C sub-capacitance begins to change, V DACP Sub-capacitor 2 MThe lower plate of -1C is switched from the reference voltage to ground, and V DACN Sub-capacitor 2 M When the lower plate of -1C switches from ground to the reference voltage, a voltage change occurs on the upper plate of the sub-capacitor, and the expression is as follows:

[0044]

[0045] If the voltage V DACP >V DACN , then the fine quantization comparator outputs a code value of 1, V DACP Sub-capacitor 2 M -1C's lower plate is kept grounded, V DACN Sub-capacitor 2 M The lower plate of -1C is kept connected to the reference voltage. At this time, the total change of the upper and lower plate voltages of the capacitor array is:

[0046] If the voltage V DACP <V DACN , then the fine quantization comparator outputs a code value of 0, V DACP Sub-capacitor 2 M -1C's lower plate is switched back to the reference voltage, V DACN Sub-capacitor 2 M -1C's lower plate is switched back to ground, and the voltages on the upper and lower plates of the capacitor array remain unchanged;

[0047] Size is 2 M After the -1C sub-capacitance change is completed, the next value is 2 M -2C sub-capacitor begins to change, the fine quantization comparator outputs a code value of 0 or 1 according to the above theory, and determines the sub-capacitor 2 M The lower electrode plate of -2C is connected to the reference voltage or grounded, and the above process is repeated until the last sub-capacitor of 1C is reached, completing the first successive approximation operation.

[0048] Optionally, after completing the first successive approximation operation, the switch array in combination with the resistor string unit continues to perform the second successive approximation operation on the target sub-capacitor. When the second successive approximation operation is an L-bit successive approximation operation, first, the switches in the switch array are closed or turned on, so that the voltage received by the lower plate of the first target sub-capacitor connected to the positive input terminal of the fine quantization comparator is switched from the reference voltage to 1 / 2 of the reference voltage, and the voltage received by the lower plate of the second target sub-capacitor connected to the negative input terminal of the fine quantization comparator is switched from ground to 1 / 2 of the reference voltage;

[0049] If V DACP >V DACN , the voltage received by the lower plate of the first target sub-capacitor and the voltage received by the lower plate of the second target sub-capacitor are both maintained at 1 / 2 of the reference voltage, otherwise the received voltage is restored to the reference voltage and grounded, and then an L-1-bit successive approximation operation is performed until the second successive approximation operation is completed.

[0050] Optionally, the size of each sub-capacitor in the thermometer code capacitor is 2 M C. When the thermometer code of the coarse quantization is judged to be wrong, the fine quantization unit exceeds the range, and the error voltage caused on the capacitor array after being transmitted to the fine quantization unit is Then the remaining voltage on the plates of the capacitor array is: residual voltage + error voltage;

[0051] The sub-capacitor size of the redundant capacitor is 2 M-1 C, the highest bit capacitance in the binary capacitor is 2 M -1 C, setting the sum of the sub-capacitor weight of the redundant capacitor and the highest sub-capacitor weight to be equivalent to the weight of a single sub-capacitor in the thermometer code capacitor, then when the thermometer code is erroneous, the code values ​​corresponding to the sub-capacitor of the redundant capacitor and the highest sub-capacitor are both 1 or 0 at the same time, and the weights after the superposition of the two compensate for the error voltage, and the residual voltage is further quantized by the binary capacitor;

[0052] When the coarsely quantized thermometer code is judged to be correct, the fine quantization unit will not exceed the range, the sub-capacitor of the redundant capacitor and the highest sub-capacitor will not participate in quantization at the same time, and the code values ​​corresponding to the two will not be 1 or 0 at the same time, and there will be no error voltage.

[0053] Optionally, the analog-to-digital conversion circuit further includes: an asynchronous clock unit;

[0054] The asynchronous clock unit is configured to generate a quantized clock signal;

[0055] The quantization clock signal is configured to control the switching from the end of the sampling phase to the first successive approximation operation and the second successive approximation operation, and to control the resetting and comparison of the fine quantization comparator;

[0056] The fine quantization comparator is reset during the low level period of the quantization clock signal, the binary code is generated at the rising edge of the fine quantization comparator and the binary code is latched at the high level, the binary code is transmitted to the digital error correction unit, and is also transmitted to the logic unit to control the switch of the capacitor array to complete the first successive approximation operation and the second successive approximation operation.

[0057] A second aspect of an embodiment of the present invention provides an electronic device, comprising: an analog-to-digital conversion circuit as described in any one of the first aspects.

[0058] In the analog-to-digital conversion circuit provided by the present invention, the coarse quantization unit and the fine quantization unit simultaneously sample the input differential signal, and both end sampling at the falling edge of the sampling clock, and store the voltage corresponding to the input differential signal on the capacitor array of the fine quantization unit. After the sampling is completed, the coarse quantization unit first uses the resistor string unit to coarsely quantize the voltage to obtain 2 M -1-bit thermometer code, and after the coarse quantization is completed, the quantized thermometer code is transmitted to the thermometer code capacitor control logic of the fine quantization unit, and at the same time, the quantized thermometer code is transcoded to obtain an M-bit binary code and transmitted to the digital error correction unit.

[0059] The fine quantization unit is based on the thermometer code capacitor control logic and voltage quantity, uses the capacitor array to complete the subtraction operation, obtains the residual voltage quantity, and combines the redundant bit capacitor and the resistor string unit to calibrate and quantize the residual voltage quantity to obtain an N+2-bit binary code, and transmits it to the digital error correction unit. Finally, the digital error correction unit performs digital error correction on the M-bit binary code and the N+2-bit binary code to obtain an M+N-bit binary code and output it. The M+N-bit binary code is the digital value corresponding to the voltage quantity.

[0060] The analog-to-digital conversion circuit proposed in the present invention performs coarse and fine quantization sampling simultaneously when the speed is the same as that of the traditional SAR ADC application. Since coarse quantization can be completed in a very short time after the sampling is completed, under the condition of a certain time, more time will be left for fine quantization, the cycle of a single comparison will be relatively longer, the noise will be lower, and the power consumption will also be lower.

[0061] The redundant bit calibration logic is introduced in the structure, and the redundant bit capacitor is combined to correct and calibrate the fine quantization over-range problem caused by the error in the judgment of the coarse quantization code value, which successfully solves the problem of mismatch between the coarse and fine quantization of the entire ADC due to the limited coarse quantization accuracy, that is, solves the problem that the residual voltage is too large during fine quantization and the quantization cannot be completed normally. The analog-to-digital conversion circuit proposed by the present invention reaches the accuracy of the traditional high-precision SAR ADC.

[0062] In addition, the resistor string unit is multiplexed in time division to achieve coarse quantization while providing a low-bit quantization voltage for fine quantization, saving overall power consumption. Fine quantization uses resistor string units to quantize low bits, which also reduces the total capacitance of the capacitor array of the traditional SAR ADC to a certain extent, and makes up for the high power consumption of the resistor string unit caused by the coarse quantization process to meet the speed requirements. Therefore, the analog-to-digital conversion circuit proposed by the present invention has high practicality. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0064] Figure 1 is a structural diagram of an analog-to-digital conversion circuit according to an embodiment of the present invention;

[0065] Figure 2 is a structural diagram of a coarse quantization unit in an embodiment of the present invention;

[0066] Figure 3 is a structural diagram of a fine quantization unit in an embodiment of the present invention;

[0067] Figure 4 is a working timing diagram of a preferred analog-to-digital conversion circuit in an embodiment of the present invention;

[0068] Figure 5 This is a preferred analog-to-digital conversion circuit structure diagram in an embodiment of the present invention;

[0069] Figure 6 is a schematic diagram of a quantization error of a fine quantization unit caused by low quantization accuracy of a coarse quantization unit in an embodiment of the present invention;

[0070] Figure 7 It is a schematic diagram of a voltage search interval for correcting coarse quantization errors after introducing redundant capacitors in an embodiment of the present invention. DETAILED DESCRIPTION

[0071] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0072] The inventors have found that there are currently a variety of structures that are improved based on the traditional SAR ADC structure, such as: a two-stage pipeline ADC, a structure based on an operational amplifier and an inter-stage amplifier, various coarse and fine quantization combined structures, and the like.

[0073] Among them, the coarse quantization unit in the two-stage pipeline ADC can speed up the conversion speed, but it consumes a lot of power. In addition, the structure needs to use an interstage amplifier based on an operational amplifier, which limits the bandwidth while also having a trade-off between energy efficiency and accuracy. The structure of the interstage amplifier based on an operational amplifier also limits the bandwidth while also having a trade-off between energy efficiency and accuracy.

[0074] In addition, although some new interstage amplifiers improve the overall energy efficiency of two-stage pipeline ADCs, they often have the problem of PVT sensitivity, that is, the performance of the interstage amplifier is affected and degraded due to changes in process, voltage, and temperature.

[0075] In view of the above problems, the inventor has creatively proposed an analog-to-digital conversion circuit and an electronic device of the present invention after in-depth research. The technical solution of the present invention is explained and illustrated in detail below.

[0076] The analog-to-digital conversion circuit of the present invention comprises: a coarse quantization unit, a fine quantization unit, a resistor string unit and a digital error correction unit. Figure 1 The architecture diagram of the analog-to-digital conversion circuit shown in FIG. 1 includes: a coarse quantization unit, a fine quantization unit, a resistor string unit, and a digital error correction unit.

[0077] During the working process, the coarse quantization unit and the fine quantization unit sample the input differential signal at the same time, and both end the sampling at the falling edge of the sampling clock. At this time, the voltage corresponding to the input differential signal is stored in the capacitor array of the fine quantization unit, where the capacitor array of the fine quantization unit includes: thermometer code capacitor, binary capacitor and redundant bit capacitor.

[0078] After sampling, the coarse quantization unit first uses the resistor string unit to coarsely quantize the voltage, and obtains 2 M-1 The quantized thermometer code is transmitted to the thermometer code capacitor control logic of the fine quantization unit after the coarse quantization is completed, and the quantized thermometer code is transcoded to obtain an M-bit binary code and transmitted to the digital error correction unit.

[0079] After the coarse quantization is completed, the fine quantization unit uses the capacitor array to complete the subtraction operation based on the thermometer code capacitor control logic and voltage to obtain the residual voltage, and combines the redundant bit capacitor and the resistor string unit to calibrate and quantize the residual voltage to obtain an N+2-bit binary code, which is then transmitted to the digital error correction unit.

[0080] Finally, the digital error correction unit performs digital error correction on the M-bit binary code and the N+2-bit binary code to obtain and output the M+N-bit binary code. The output M+N-bit binary code is the digital value corresponding to the input differential signal voltage.

[0081] That is, the main working content of the analog-to-digital conversion unit proposed in the present invention can be divided into three stages:

[0082] In the sampling stage: the coarse quantization unit and the fine quantization unit sample the input differential signal at the same time. At the falling edge of the sampling clock, both end the sampling at the same time. At this time, the input differential signal is stored on the capacitor array.

[0083] Then enter the quantization stage: the coarse quantization unit first performs coarse quantization on the input differential signal, and the quantization bit width is M-bit (i.e. M bits). After the coarse quantization unit completes the quantization, the thermometer code generated by it is passed to the thermometer code capacitor control logic of the fine quantization unit (i.e. the logic for controlling the thermometer code capacitor switch), and the capacitor array of the fine quantization unit is used to complete the subtraction operation, subtracting the coarse quantization voltage, leaving the fine quantization residual voltage.

[0084] After the thermometer code is transmitted, the fine quantization unit starts to perform successive approximation quantization operation on the residual voltage, which is the first successive approximation quantization operation. The fine quantization performed by the fine quantization unit consists of two parts, completing a total of N-bit (i.e., N bits) quantization. First, the (NL)-bit quantization is completed by the successive approximation operation of the capacitor array, and the final L-bit quantization is completed by the resistor string unit (i.e., the multiplexed resistor string unit). Due to the existence of redundant bit capacitors, the residual voltage can be calibrated, so the resulting code is N+2 bits of binary code. Finally, the digital error correction unit processes the code to obtain an M+N bit binary code.

[0085] For the coarse quantization unit, a better coarse quantization unit structure includes: a comparator array, a thermometer code register, and a thermometer code to binary code decoder. For the comparator array, each comparator has:

[0086] A pair of positive and negative input terminals of the comparator are respectively connected to the two ends of a unit resistor in the resistor string unit, and another pair of positive and negative input terminals receive the input differential signal; that is, the comparator has a total of 4 input terminals, two pairs of positive and negative input terminals. In order to better understand the preferred coarse quantization unit structure, refer to Figure 2 As shown, Figure 2 In order to better understand the structure of the coarse quantization unit, the resistor string unit and three comparators CMP are shown as examples, which does not mean that there are only three comparators in the comparator array. The output ends of all comparators are connected to the thermometer code register; the thermometer code register is connected to the thermometer code to binary code decoder.

[0087] Among them, one end of the resistor string unit receives the reference voltage V REF , the other end is grounded GND, then the resistor string unit generates 2 M -1 reference voltage, respectively VR1 ,V R2 ,…,V R2 M -1 , these 2 M -1 reference voltage is provided to 2 M -1 comparator as the reference voltage for each comparator. For the resistor string unit, the number of unit resistors is: 2 M .

[0088] During coarse quantization, each comparator generates a voltage proportional to its reference voltage and input differential voltage V IN 、V IP The size of the code generates a value of 0 or 1, and all comparators generate a total of 2 M -1-bit thermometer code and transferred to the thermometer code register for storage. Figure 2 Medium CLK S Represents the sampled signal.

[0089] Thermometer Code Register will be 2 M -1-digit thermometer code ( Figure 2 Middle 2 M -1-bit) is transmitted to the thermometer code capacitor control logic ( Figure 2 Thermometer code to binary code decoder 2 M -1 bit thermometer code is converted into M bit binary code ( Figure 2 M-bit) and transmitted to the digital error correction unit ( Figure 2 not shown).

[0090] The thermometer code transmitted to the thermometer code capacitor control logic is used to control the lower plate of the thermometer code capacitor in the fine quantization unit to connect to GND or the reference voltage V REF , thereby realizing the voltage subtraction operation and obtaining the residual voltage.

[0091] For the fine quantization unit, a preferred structure of the fine quantization unit includes: a capacitor array, a switch array, a fine quantization comparator and a logic unit; the thermometer code capacitor, the binary capacitor and the redundant bit capacitor all include: sub-capacitors.

[0092] To better understand the structure of the fine quantization unit, refer to Figure 3 , shows a structural diagram of a fine quantization unit in an embodiment of the present invention. Figure 3 Medium V IN 、V IP represents the input differential voltage, which is stored on the capacitor array at the end of the sampling phase, Figure 3 In the capacitor array, the sub-capacitors in the rightmost dotted box form a thermometer code capacitor. The size of each sub-capacitor in the thermometer code capacitor is 2M C. Figure 3 The M-bit Flah-Stag is used to represent the thermometer code capacitor. The thermometer code makes the lower plate of the sub-capacitor connected to GND or the reference voltage V REF , thereby realizing the voltage subtraction operation and obtaining the residual voltage.

[0093] The two sizes of the virtual box (middle virtual box) adjacent to the thermometer code capacitor are both 2 M-1 The sub-capacitors of C form redundant capacitors, Figure 3 The figure also preferably shows two redundant sub-capacitors (dashed boxes on the left) of size 1C, which also constitute redundant capacitors of size 2 M-1 The lower plates of the two redundant sub-capacitors of C and the two redundant sub-capacitors of 1C are connected to two control switches and are respectively connected to the reference voltage V REF and ground GND, the top plate is connected to the bias voltage V CM . Figure 3 Redundant Bit indicates that redundant capacitors can play a calibration role when the quantization exceeds the range. Among them, two redundant sub-capacitors of 1C can be arranged or not according to the accuracy requirements. When the accuracy requirements are high, these two redundant sub-capacitors can be arranged. When the accuracy requirements are relatively low, these two redundant sub-capacitors can be not arranged, thereby reducing area overhead.

[0094] The sub-capacitors except the three virtual boxes constitute the binary capacitor, the thermometer code capacitor, the sub-capacitors of the redundant bit capacitor, and the sub-capacitors of the binary capacitor except the target sub-capacitor ( Figure 3 The lower plate of each sub-capacitor is connected to three control switches, which are respectively connected to the input differential signal V IN 、V IP , reference voltage V REF and ground GND, the upper plate is connected to the bias voltage V CM , fine quantization comparator ( Figure 3 The output end of the fine quantization comparator CMP is connected to the logic unit SAR Logic. The size of the sub-capacitor in the binary capacitor ranges from 2 M-1 C to 1C, decreasing gradually by multiples of 2.

[0095] Target subcapacitance( Figure 3 The lower plate of the leftmost 1C capacitor is connected to three control switches, which are connected to the switch array RDAC, the reference voltage V REF and ground GND, the upper plate is connected to the bias voltage V CM , two input ends of the fine quantization comparator CMP, and the switch array RDAC are connected to the resistor string unit Res Ladder.

[0096] Among them, the thermometer code capacitor is controlled by the thermometer code capacitor control logic, and the lower plate of the thermometer code capacitor is grounded to GND or connected to the reference voltage V according to the thermometer code control. REF , to perform a subtraction operation, subtract the coarse quantized voltage amount, and obtain the residual voltage amount.

[0097] The binary capacitor uses the fine quantization comparator CMP and the logic unit SAR Logic to perform the first successive approximation operation from high to low, and determines the reference voltage V at the lower plate of the target unit capacitor. REF Or after grounding GND, the switch array RDAC and the resistor string unit Res Ladder continue to perform the second successive approximation operation, thereby completing the fine quantization. The switch array includes: a plurality of switches;

[0098] Each of the switches is controlled by the logic unit, and according to different closing and opening conditions of the switch, the lower plate of the target sub-capacitor obtains different voltages generated on the resistor string unit.

[0099] In the process of binary capacitor quantization, if the ultra-fine quantization range occurs, the redundant bit capacitor is used to correct and calibrate the erroneous thermometer code to obtain N+2-bit binary code and transmit it to the digital error correction unit ( Figure 3 not shown).

[0100] also, Figure 3 In order to better understand the entire analog-to-digital conversion circuit and the implementation of high-speed quantization, Figure 3 In addition to the detailed quantization unit structure, the asynchronous clock unit ASY_CLK_GNE is also shown. The asynchronous clock unit ASY_CLK_GNE is used to generate a high-speed quantization signal CKC to achieve high-speed quantization, which is different from the sampling information CLK provided by the external clock. S .

[0101] The asynchronous clock unit ASY_CLK_GNE is configured to generate a quantization clock signal CKC; the quantization clock signal CKC is configured to control the switching from the end of the sampling phase to the first successive approximation operation, the second successive approximation operation, and control the resetting and comparison of the fine quantization comparator CMP.

[0102] The fine quantization comparator resets CMP during the low level period of the quantization clock signal, generates a binary code at the rising edge of the fine quantization comparator CMP and latches the binary code at the high level. The binary code is transmitted to the digital error correction unit and also transmitted to the logic unit SAR Logic to control the switch of the capacitor array to complete the first successive approximation operation and the second successive approximation operation. Figure 3RDY represents a start enable signal, which is an enable signal sent by the logic unit SAR Logic to the asynchronous clock unit ASY_CLK_GNE, so that the asynchronous clock unit ASY_CLK_GNE generates a high-speed quantized clock signal CKC.

[0103] The specific working principle of the coarse and fine quantization of the entire analog-to-digital conversion circuit can be combined Figure 4 The timing diagram shown, Figure 5 The preferred analog-to-digital conversion circuit structure diagram shown is described as follows:

[0104] First, in the sampling stage, the sampling signal CLK S High level is effective, the comparator array in the coarse quantization unit resets the output to zero, and the thermometer code value output by the comparator array is: TH<2 M -1:1>=00…0000, at the same time, the upper plate of the capacitor array in the fine quantization unit is connected to the bias voltage V CM , the lower plate is connected to the input differential signal V IN 、V IP , the charge on the capacitor array is expressed as:

[0105] Q DACP =(V CM -V in )·2 2M C

[0106] Q DACN =(V CM -V ip )·2 2M C

[0107] In the above formula, Q DACP Represents the charge on the capacitor array connected to the positive input of the fine quantization comparator CMP, Q DACN Represents the charge on the capacitor array connected to the negative input terminal of the fine quantization comparator CMP.

[0108] The sampling phase ends and the sampling signal CLK S The low level is invalid. At this time, each comparator in the comparator array in the coarse quantization unit is based on the input differential voltage V IN 、V IP and reference voltage V REF The code value is 0 or 1, and the code value is latched and transmitted to the thermometer code capacitor control logic.

[0109] The sampling signal CLK S When the low level is invalid, the upper plate of the capacitor array is connected to the bias voltage V CMThe switch is disconnected, and the lower plates of all sub-capacitors except the thermometer code capacitor and the target sub-capacitor are connected to the capacitor array at the positive input end of the quantization comparator CMP, and the input differential signal V IN 、V IP Switch to the reference voltage V REF , connect the capacitor array of the negative input terminal of the quantization comparator CMP to the lower plate of all sub-capacitors except the thermometer code capacitor and the target sub-capacitor, and connect the input differential signal V IN 、V IP Switch to ground GND. At this time, the charges at both ends of the capacitor array connected to the positive input and negative input of the fine quantization comparator CMP are:

[0110] Q DACP =V DACP 2 2M C+V REF ·(2 M —K)·2 M C

[0111] Q DACN =V DACP 2 2M C+V REF ·K·2 M C

[0112] In the above formula, V DACP and V DACN They represent the voltage values ​​of the positive and negative input terminals of the fine quantization comparator CMP respectively. K means that in the coarse quantization output, there are K 1 code values ​​output and 2 0 code values ​​output. M -1-K, then according to the charge conservation principle, the voltages at the positive and negative input terminals of the fine-scale comparator CMP are:

[0113]

[0114] Then for the fine quantization comparator CMP, there is the following formula:

[0115]

[0116] According to the above formula, the thermometer code value completes the subtraction operation on the capacitor array to obtain the residual voltage, where is the coarse quantized voltage value, the differential input signal V IN 、V IP The corresponding voltage range is within the negative reference voltage -V REF To the positive reference voltage +V REF between.

[0117] After completing the subtraction operation to obtain the residual voltage, the remaining voltage on the capacitor array is the residual voltage, and the fine quantization stage is entered. In the fine quantization stage, first, the binary capacitor with a size of 2 M-1 The sub-capacitance of C begins to change, V DACP Sub-capacitor 2 M-1 The lower plate of C is connected to the reference voltage V REF Switch to ground GND, while V DACN Sub-capacitor 2 M-1 The lower plate of C is switched from ground GND to the reference voltage V REF , then a voltage change is generated on the upper plate of the sub-capacitor, and its expression is as follows:

[0118]

[0119] If the voltage V DACP >V DACN , then the fine quantization comparator CMP outputs a code value of 1, V DACP Sub-capacitor 2 M-1 The lower plate of C is kept grounded GND, V DACN Sub-capacitor 2 M-1 The lower plate of C is kept connected to the reference voltage V REF , at this time, the total change of the upper and lower plate voltages of the capacitor array is: If the voltage V DACP <V DACN , then the fine quantization comparator CMP outputs a code value of 0, V DACP Sub-capacitor 2 M-1 The lower plate of C is switched back to the reference voltage V REF , V DACN Sub-capacitor 2 M-1 The lower plate of C is switched back to ground GND, and the voltages of the upper and lower plates of the capacitor array remain unchanged.

[0120] Size is 2 M-1 After the sub-capacitance change of C is completed, the value is 2 M-2 The sub-capacitance of C begins to change, and the fine-scale comparator is 2 M-1 The same principle as the sub-capacitor of C theoretically outputs the code value 0 or 1, and determines the sub-capacitor 2 M-2 The lower plate of C is connected to the reference voltage V REF Or ground GND, followed by a value of 2 M-2 The above process is repeated for the sub-capacitors of 1C until the last sub-capacitor of 1C (another sub-capacitor of 1C except the target sub-capacitor of 1C), completing the first successive approximation operation.

[0121] After the first successive approximation operation is completed, the second successive approximation operation is continued for the target sub-capacitor 1C by the switch array RDAC combined with the resistor string unit Res Ladder. When the second successive approximation operation is an L-bit successive approximation operation, first, the switch of the RDAC in the switch array is closed or turned on, so that the first target sub-capacitor ( Figure 3 , Figure 5 The lower plate of the 1C sub-capacitor on the left receives a voltage from the reference voltage V REF Switch to 1 / 2 of the reference voltage V REF , that is, cut to 1 / 2V REF , a second target sub-capacitor ( Figure 3 , Figure 5 The voltage received by the lower plate of the 1C sub-capacitor at the bottom left of the figure is switched from ground GND to 1 / 2 of the reference voltage V REF , that is, cut to 1 / 2V REF .

[0122] If V DACP >V DACN , the voltage received by the lower plate of the first target sub-capacitor and the voltage received by the lower plate of the second target sub-capacitor are both maintained at 1 / 2 of the reference voltage, otherwise the received voltage is restored to the reference voltage V REF and ground GND, and then perform the L-1-bit successive approximation operation until the second successive approximation operation is completed.

[0123] It should be noted that Figure 5 Medium CLK D Represents the readout signal, which is used to output the N+M-Bit binary code. FLASH control indicates that the switch of the thermometer code capacitor is controlled by the thermometer code. SAR control indicates that it is controlled by the N+2-Bit code value of the logic unit. VR n and VR p Indicates the voltage value of the connection between the lower plates of the two target sub-capacitors (determined by the switch array RDAC and the resistor string unit Res Ladder), multiple dashed boxes and a dashed box exemplarily show the comparator CMP, which represents the comparator array in the coarse quantization unit, and Encoder represents the thermometer code to binary code decoder, which generates a binary code Binary Code, which is M-Bit and sent to the digital error correction unit DEC. The digital error correction unit DEC performs digital error correction on the M-bit binary code and the N+2-bit binary code, obtains the N+M-bit binary code and outputs it to the register array Register Array.

[0124] The above working process explains the working process of the analog-to-digital conversion circuit, but does not explain the serious precision mismatch problem in the process of passing the code value obtained by the coarse quantization unit to the fine quantization unit. Since the quantization precision of the coarse quantization unit is low, while the quantization precision of the fine quantization unit is high, when the input voltage is at the quantization boundary of the coarse quantization unit, it is very likely that the coarse quantization interval judgment will be wrong due to the misjudgment of the coarse quantization unit, which will cause the code value obtained by the coarse quantization unit to be passed to the fine quantization unit. The residual voltage of the fine quantization is too large and the quantization cannot be completed normally, such as Figure 6 The diagram shown is a schematic diagram of quantization error in a fine quantization unit caused by low quantization accuracy of the coarse quantization unit.

[0125] Figure 6 The left dashed box in the middle shows a schematic diagram when the coarse quantization interval is correctly judged, and the right dashed box shows a schematic diagram when the coarse quantization interval is wrongly judged. It can be seen that when the coarse quantization interval is wrongly judged, the fine quantization residual voltage will exceed the range.

[0126] Since the size of each sub-capacitor in the thermometer code capacitor is 2 M C. When the coarse quantization thermometer code is wrong, the fine quantization unit will exceed the range. The error voltage caused on the capacitor array after being transmitted to the fine quantization unit is The remaining voltage on the plates of the capacitor array is: residual voltage + error voltage. However, the voltage generated by the accumulation of low-order weights in the capacitor array of the traditional SAR ADC structure does not exceed Verror. Therefore, the traditional SAR ADC structure cannot quantify the magnitude of the residual voltage.

[0127] The sub-capacitor size of the redundant capacitor designed by the present invention is 2 M-1 C, the highest bit capacitance in binary capacitance is 2 M-1 C, the sum of the sub-capacitor weights of the redundant capacitor and the highest sub-capacitor weight is set to be equivalent to the weight of a single sub-capacitor in the thermometer code capacitor. When the thermometer code is wrong, the code values ​​corresponding to the sub-capacitors of the redundant capacitor and the highest sub-capacitor are 1 or 0 at the same time. The superposition of the weights compensates the error voltage, and the residual voltage is further quantized by the binary capacitor.

[0128] When the thermometer code of the coarse quantization is judged correctly, the fine quantization unit will not have an over-range situation, then the sub-capacitor of the redundant capacitor and the highest sub-capacitor will not participate in the quantization at the same time, and the code values ​​corresponding to the two will not be 1 or 0 at the same time, and there will be no error voltage. For example: the sub-capacitor size of the redundant capacitor is 16C, and the highest sub-capacitor size in the binary capacitor is 16C. The design of two 16C sub-capacitors takes into account the directionality of the voltage and realizes the weight addition in different directions. The sum of the sub-capacitor and the highest binary capacitor 16C is +32C or -32C, which is equivalent to the thermometer capacitor 32C. Then, when the thermometer code is wrong, the code values ​​corresponding to the sub-capacitor 16C of the redundant capacitor and the highest binary capacitor 16C are 1 or 0 at the same time, and the weight compensation error voltage after the superposition of the two; when the thermometer code of the coarse quantization is judged correctly, the fine quantization unit will not have an over-range situation, then the sub-capacitor 16C of the redundant capacitor and the highest binary capacitor 16C will not participate in the quantization at the same time, and the code values ​​corresponding to the two will not be 1 or 0 at the same time, and there will be no error voltage.

[0129] The schematic diagram of the voltage search interval for correcting the coarse quantization error after introducing redundant capacitors is shown in the figure below. Figure 7 shown. Figure 7 The left side shows the case where the coarse quantization interval judgment is correct when there is redundant capacitance, where B N Indicates the highest binary capacitance, B N-1 It represents the redundant capacitance. When the fine quantization unit does not exceed the range, the redundant capacitance and the highest bit capacitance of the binary are not involved at the same time, so B N and B N-1 Not 1 or 0 at the same time. Figure 7 The right side of the middle shows the situation where the coarse quantization interval judgment is wrong when there is redundant capacitance. When the error occurs, the search voltage interval of the fine quantization unit exceeds the range. N and B N-1 It is 1 or 0 at the same time, thereby correcting the error voltage caused by the thermometer code capacitor and ensuring the correctness of subsequent quantization.

[0130] Based on the above analog-to-digital conversion circuit, an embodiment of the present invention further provides an electronic device, which includes: the above analog-to-digital conversion circuit.

[0131] Through the above embodiments, the analog-to-digital conversion circuit provided by the present invention, the coarse quantization unit and the fine quantization unit simultaneously sample the input differential signal, and both end sampling at the falling edge of the sampling clock, and store the voltage corresponding to the input differential signal on the capacitor array of the fine quantization unit. After the sampling is completed, the coarse quantization unit first uses the resistor string unit to coarsely quantize the voltage to obtain 2 M-1-bit thermometer code, and after the coarse quantization is completed, the quantized thermometer code is transmitted to the thermometer code capacitor control logic of the fine quantization unit, and at the same time, the quantized thermometer code is transcoded to obtain an M-bit binary code and transmitted to the digital error correction unit.

[0132] The fine quantization unit is based on the thermometer code capacitor control logic and voltage quantity, uses the capacitor array to complete the subtraction operation, obtains the residual voltage quantity, and combines the redundant bit capacitor and the resistor string unit to calibrate and quantize the residual voltage quantity to obtain an N+2-bit binary code, and transmits it to the digital error correction unit. Finally, the digital error correction unit performs digital error correction on the M-bit binary code and the N+2-bit binary code to obtain an M+N-bit binary code and output it. The M+N-bit binary code is the digital value corresponding to the voltage quantity.

[0133] The analog-to-digital conversion circuit proposed in the present invention performs coarse and fine quantization sampling simultaneously when the speed is the same as that of the traditional SAR ADC application. Since coarse quantization can be completed in a very short time after the sampling is completed, under the condition of a certain time, more time will be left for fine quantization, the cycle of a single comparison will be relatively longer, the noise will be lower, and the power consumption will also be lower.

[0134] The redundant bit calibration logic is introduced in the structure, and the redundant bit capacitor is combined to correct and calibrate the fine quantization over-range problem caused by the error in the coarse quantization code value judgment, which successfully solves the problem of the mismatch between the coarse and fine quantization of the entire ADC due to the limited coarse quantization accuracy, that is, the problem that the residual voltage is too large during fine quantization and the quantization cannot be completed normally is solved. The analog-to-digital conversion circuit proposed by the present invention reaches the accuracy of the traditional high-precision SAR-ADC.

[0135] In addition, the resistor string unit is multiplexed in time division to achieve coarse quantization while providing a low-bit quantization voltage for fine quantization, saving overall power consumption. Fine quantization uses resistor string units to quantize low bits, which also reduces the total capacitance of the capacitor array of the traditional SAR ADC to a certain extent, and makes up for the high power consumption of the resistor string unit caused by the coarse quantization process to meet the speed requirements. Therefore, the analog-to-digital conversion circuit proposed by the present invention has high practicality.

[0136] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0137] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation modes, which are merely illustrative rather than restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. An analog-to-digital conversion circuit, characterized in that: The analog-to-digital conversion circuit includes: a coarse quantization unit, a fine quantization unit, a resistor string unit and a digital error correction unit; The coarse quantization unit and the fine quantization unit simultaneously sample the input differential signal, and both end sampling at the falling edge of the sampling clock, and store the voltage corresponding to the input differential signal on the capacitor array of the fine quantization unit, wherein the capacitor array of the fine quantization unit includes: a thermometer code capacitor, a binary capacitor, and a redundant bit capacitor; After sampling is completed, the coarse quantization unit first uses the resistor string unit to coarsely quantize the voltage quantity to obtain 2 M -1-bit thermometer code, and after the coarse quantization is completed, the quantized thermometer code is transmitted to the thermometer code capacitor control logic of the fine quantization unit, and at the same time, the quantized thermometer code is transcoded to obtain an M-bit binary code and transmitted to the digital error correction unit; The fine quantization unit performs a subtraction operation based on the thermometer code capacitor control logic and the voltage quantity using the capacitor array to obtain a residual voltage quantity, and calibrates and finely quantizes the residual voltage quantity in combination with the redundant bit capacitor and the resistor string unit to obtain an N+2-bit binary code, and transmits the code to the digital error correction unit; The digital error correction unit performs digital error correction on the M-bit binary code and the N+2-bit binary code to obtain and output an M+N-bit binary code, where the M+N-bit binary code is a digital value corresponding to the voltage amount.

2. The analog-to-digital conversion circuit according to claim 1, characterized in that: The coarse quantization unit comprises: a comparator array, a thermometer code register and a thermometer code to binary code decoder; Each comparator in the comparator array has: a pair of positive and negative input terminals of the comparator connected to two ends of a unit resistor in the resistor string unit, respectively, and another pair of positive and negative input terminals receiving the input differential signal; The output terminals of all comparators are connected to the thermometer code register; The thermometer code register is connected to the thermometer code to binary code decoder; Among them, one end of the resistor string unit receives the reference voltage and the other end is grounded, so the resistor string unit generates 2 M -1 reference voltage, respectively V R1 ,V R2 ,…,V R2 M -1 , said 2 M -1 reference voltage is provided to 2 M - 1 comparator as the reference voltage for each comparator; During the coarse quantization, each of the comparators generates a code value of 0 or 1 according to the respective reference voltage and the magnitude of the input differential voltage, and all the comparators generate a total of 2 M -1-bit thermometer code and transmitted to the thermometer code register for storage; The thermometer code register will be the 2 M -1-bit thermometer code is transmitted to the thermometer code capacitor control logic and the thermometer code to binary code decoder; The thermometer code to binary code decoder converts the 2 M -1-bit thermometer code is transcoded to obtain M-bit binary code and transmitted to the digital error correction unit; The number of unit resistors in the resistor string unit is: 2 M .

3. The analog-to-digital conversion circuit according to claim 1, characterized in that: The fine quantization unit includes: the capacitor array, the switch array, the fine quantization comparator and the logic unit; the thermometer code capacitor, the binary capacitor and the redundant bit capacitor all include: sub-capacitors; The thermometer code capacitor, the sub-capacitor of the redundant bit capacitor, and each sub-capacitor except the target sub-capacitor in the binary capacitor, the lower plate of each sub-capacitor is connected to three control switches, respectively connected to the input differential signal, the reference voltage and the ground, and the upper plate is connected to the bias voltage and the two input terminals of the fine quantization comparator, and the output terminal of the fine quantization comparator is connected to the logic unit; The lower plate of the target sub-capacitor is connected to three control switches, which are respectively connected to the switch array, the reference voltage and the ground, and the upper plates are connected to the bias voltage and two input terminals of the fine quantization comparator, and the switch array is connected to the resistor string unit; The thermometer code capacitor is controlled by the thermometer code capacitor control logic, and the lower plate of the thermometer code capacitor is grounded or connected to the reference voltage according to the thermometer code to perform the subtraction operation, and the coarse quantized voltage is subtracted to obtain the residual voltage; The binary capacitor uses the fine quantization comparator and the logic unit to perform a first successive approximation operation from high to low, and after the lower plate of the target unit capacitor is determined to be connected to the reference voltage or grounded, the switch array combines with the resistor string unit to continue to perform a second successive approximation operation, thereby completing fine quantization; In the process of fine quantization of the binary capacitor, if an ultra-fine quantization range occurs, the redundant bit capacitor is used to correct and calibrate the erroneous thermometer code to obtain the N+2-bit binary code, and transmit it to the digital error correction unit; The size of each sub-capacitor in the thermometer code capacitor is 2 M C, the redundant capacitor includes: two sub-capacitors, both of which are 2 M-1 C, the binary capacitor neutron capacitance size from 2 M-1 C to 1C, decreasing successively by multiples of 2, wherein the smallest 1C sub-capacitor is the target sub-capacitor.

4. The analog-to-digital conversion circuit according to claim 3, characterized in that: The redundant capacitor also includes: two redundant sub-capacitors each having a size of 1C; The sizes are all 2 M-1 The lower plates of the two redundant sub-capacitors of size C and the two redundant sub-capacitors of size 1C are respectively connected to two control switches, respectively connected to the reference voltage and ground, and the upper plates are both connected to the bias voltage.

5. The analog-to-digital conversion circuit according to claim 3, characterized in that: The switch array comprises: a plurality of switches; Each of the switches is controlled by the logic unit, and according to different closing and opening conditions of the switch, the lower plate of the target sub-capacitor obtains different voltages generated on the resistor string unit.

6. The analog-to-digital conversion circuit according to claim 3, characterized in that: In the sampling stage, the sampling signal is effective at a high level, the comparator array in the coarse quantization unit is reset and the output is cleared, and the thermometer code value output by the comparator array is: TH<2 M -1:1>=00…0000, at the same time, the upper plate of the capacitor array is connected to the bias voltage, and the lower plate is connected to the input differential signal. At this time, the charge on the capacitor array is expressed as: Q DACP =(V CM -V in )·2 2M C Q DACN =(V CM -V ip )·2 2M C In the above formula, Q DACP represents the charge on the capacitor array connected to the positive input terminal of the fine quantization comparator, Q DACN represents the charge on the capacitor array connected to the negative input terminal of the fine quantization comparator; The sampling phase ends, the sampling signal is ineffective at a low level, and each comparator in the comparator array in the coarse quantization unit outputs a code value of 0 or 1 according to the magnitude of the input differential voltage and the reference voltage, and latches the code value and transmits it to the thermometer code capacitor control logic; When the sampling signal is at a low level and is invalid, the switch of the upper plate of the capacitor array connected to the bias voltage is disconnected, and the lower plates of all sub-capacitors of the capacitor array connected to the positive input terminal of the fine quantization comparator except the thermometer code capacitor and the target sub-capacitor are switched from being connected to the input differential signal to being connected to the reference voltage, and the lower plates of all sub-capacitors of the capacitor array connected to the negative input terminal of the fine quantization comparator except the thermometer code capacitor and the target sub-capacitor are switched from being connected to the input differential signal to being grounded. At this time, the charges at both ends of the capacitor array connected to the positive input terminal and the negative input terminal of the fine quantization comparator are respectively: Q DACP =V DACP ·2 2M C+V REF ·(2 M -K)·2 M C Q DACN =V DACP ·2 2M C+V REF ·K·2 M C In the above formula, V DACP and V DACN represents the voltage value of the positive and negative input terminals of the fine quantization comparator respectively, K represents that in the quantization output of the coarse quantization, there are K code values ​​of 1 output, and 2 code values ​​of 0 output M -1-K, then according to the charge conservation principle, the voltages at the positive and negative input terminals of the fine quantization comparator are: Then the following formula is obtained for the fine quantization comparator: According to the above formula, the thermometer code value completes the subtraction operation on the capacitor array to obtain the residual voltage, where is a coarsely quantized voltage value, and the voltage value corresponding to the differential input signal ranges from a negative reference voltage to a positive reference voltage; After the subtraction operation is completed to obtain the residual voltage, the remaining voltage on the capacitor array is the residual voltage, and the fine quantization stage is entered. In the fine quantization stage, first, the binary capacitor with a size of 2 M -1C sub-capacitance begins to change, V DACP Sub-capacitor 2 M The lower plate of -1C is switched from the reference voltage to ground, and V DACN Sub-capacitor 2 M When the lower plate of -1C is switched from ground to the reference voltage, a voltage change is generated on the upper plate of the sub-capacitor, and the expression is as follows: If the voltage V DACP >V DACN , then the fine quantization comparator outputs a code value of 1, V DACP Sub-capacitor 2 M -1C's lower plate is kept grounded, V DACN Sub-capacitor 2 M The lower plate of -1C is kept connected to the reference voltage. At this time, the total change of the upper and lower plate voltages of the capacitor array is: If the voltage V DACP <V DACN , then the fine quantization comparator outputs a code value of 0, V DACP Sub-capacitor 2 M -1C's lower plate is switched back to the reference voltage, V DACN Sub-capacitor 2 M -1C's lower plate is switched back to ground, and the voltages on the upper and lower plates of the capacitor array remain unchanged; Size is 2 M After the -1C sub-capacitance change is completed, the next value is 2 M -2C sub-capacitor begins to change, the fine quantization comparator outputs a code value of 0 or 1 according to the above theory, and determines the sub-capacitor 2 M The lower electrode plate of -2C is connected to the reference voltage or grounded, and the above process is repeated until the last sub-capacitor of 1C is reached, completing the first successive approximation operation.

7. The analog-to-digital conversion circuit according to claim 6, characterized in that: After completing the first successive approximation operation, the switch array in combination with the resistor string unit continues to perform the second successive approximation operation on the target sub-capacitor. When the second successive approximation operation is an L-bit successive approximation operation, first, the switches in the switch array are closed or turned on, so that the voltage received by the lower plate of the first target sub-capacitor connected to the positive input terminal of the fine quantization comparator is switched from the reference voltage to 1 / 2 of the reference voltage, and the voltage received by the lower plate of the second target sub-capacitor connected to the negative input terminal of the fine quantization comparator is switched from ground to 1 / 2 of the reference voltage; If V DACP >V DACN , the voltage received by the lower plate of the first target sub-capacitor and the voltage received by the lower plate of the second target sub-capacitor are both maintained at 1 / 2 of the reference voltage, otherwise the received voltage is restored to the reference voltage and grounded, and then an L-1-bit successive approximation operation is performed until the second successive approximation operation is completed.

8. The analog-to-digital conversion circuit according to claim 6, characterized in that: The size of each sub-capacitor in the thermometer code capacitor is 2 M C. When the thermometer code of the coarse quantization is judged to be wrong, the fine quantization unit exceeds the range, and the error voltage caused on the capacitor array after being transmitted to the fine quantization unit is Then the remaining voltage on the plates of the capacitor array is: residual voltage + error voltage; The sub-capacitor size of the redundant capacitor is 2 M-1 C, the highest bit capacitance in the binary capacitor is 2 M-1 C, setting the sum of the sub-capacitor weight of the redundant capacitor and the highest sub-capacitor weight to be equivalent to the weight of a single sub-capacitor in the thermometer code capacitor, then when the thermometer code is wrong, the code values ​​corresponding to the sub-capacitor of the redundant capacitor and the highest sub-capacitor are both 1 or 0 at the same time, and the weights after the superposition of the two compensate for the error voltage, and the residual voltage is further quantized by the binary capacitor; When the coarsely quantized thermometer code is judged to be correct, the fine quantization unit will not exceed the range, the sub-capacitor of the redundant capacitor and the highest sub-capacitor will not participate in quantization at the same time, and the code values ​​corresponding to the two will not be 1 or 0 at the same time, and there will be no error voltage.

9. The analog-to-digital conversion circuit according to claim 7, characterized in that: The analog-to-digital conversion circuit further includes: an asynchronous clock unit; The asynchronous clock unit is configured to generate a quantized clock signal; The quantization clock signal is configured to control the switching from the end of the sampling phase to the first successive approximation operation and the second successive approximation operation, and to control the resetting and comparison of the fine quantization comparator; The fine quantization comparator is reset during the low level period of the quantization clock signal, the binary code is generated at the rising edge of the fine quantization comparator and the binary code is latched at the high level, the binary code is transmitted to the digital error correction unit, and is also transmitted to the logic unit to control the switch of the capacitor array to complete the first successive approximation operation and the second successive approximation operation.

10. An electronic device, characterized in that: The electronic device comprises: an analog-to-digital conversion circuit as described in any one of claims 1-9.

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