High-speed dynamic visual sensor architecture based on column-level circuit sharing

Abstract

The invention discloses a high-speed dynamic vision sensor architecture based on column-level circuit sharing. The high-speed dynamic vision sensor architecture comprises a row driving circuit, a pixel array, a column-level sharing event trigger circuit and a reading system, the row driving circuit is used for providing row selection and switch sequence signals for the pixel array and providing data selection, reset and latch signals for the column-level shared event trigger circuit; the pixel array senses the external light intensity to realize photoelectric conversion, and outputs the voltage at the previous moment and the voltage at the current moment during the row selection period; the column-level shared event trigger circuit enters a reset state at the beginning stage of each row selection, firstly selects the voltage at the previous moment output by the sampling pixel array, then turns into an amplification state after the reset is finished, inputs the voltage at the current moment output by the sampling pixel array, amplifies the step voltage, compares the step voltage to generate an event, and finally outputs the event to the column-level shared event trigger circuit. The event information is stored; and the reading system is used for processing the stored event information and outputting the event information to the outside.

Description

Technical Field

[0001] The present invention relates to the field of analog integrated circuit design, specifically to the field of dynamic perception when image information in a scene changes at a high speed, and more specifically to a high-speed dynamic visual sensor architecture based on column-level circuit sharing. Background Art

[0002] Based on the characteristics of biological vision, people abandoned the concept of "frame" and proposed a dynamic vision sensor (DVS). Compared with the traditional complementary metal oxide semiconductor (CMOS) image sensor, the main feature of DVS is that it can realize continuous light intensity detection, logarithmically map the photocurrent and the output voltage of the light receiving level, significantly increase the photosensitivity dynamic range, and output a high time resolution event stream.

[0003] The DVS pixel with a classic structure introduces a switched capacitor amplifier to accurately amplify the voltage to meet the requirements of time domain sensitivity. The capacitance ratio of 20 to 25 restricts the reduction of pixel size. Domestic and foreign research institutions have proposed methods such as pre-amplification stage circuit sharing the switched capacitor amplification factor, pixel group circuit sharing the switched capacitor amplifier, and process improvement. So far, the back-illuminated + three-dimensional stacking process is the most effective way to reduce the pixel size, but it brings a surge in wafer production costs. How to reduce the pixel size of DVS at a low cost is an urgent problem to be solved.

[0004] The reduction in DVS pixel size also brings about an improvement in spatial resolution. In a high-speed environment with a surge in event information, the use of asynchronous readout technology of Address-Event Representation (AER) may lead to unfair arbitration. Therefore, in recent years, high-resolution DVS cameras have all adopted synchronous readout technology. In order to cope with high-speed motion environments, the frame rate must be increased as much as possible, and the pixel response speed to changes in light intensity must be very fast. The intra-pixel transmission delay is mainly determined by the logarithmic light receiving level of the DVS, and the delay is inversely proportional to the photocurrent. How to reduce the pixel transmission delay is an urgent problem to be solved. Summary of the invention

[0005] The purpose of the present invention is to overcome the deficiencies in the prior art and propose a high-speed dynamic vision sensor architecture based on column-level circuit sharing. A photodiode structure with high photoelectric conversion efficiency is adopted at the pixel photosensing end to generate a larger photocurrent under the same light intensity, thereby achieving the purpose of reducing pixel delay. At the same time, a storage capacitor is introduced into the pixel circuit to realize the function of reading out the voltage at two moments in one row selection. The column-level shared switched capacitor amplifier and comparator circuit can significantly reduce the pixel size.

[0006] The objectives of the present invention are achieved through the following technical solutions.

[0007] The present invention is based on a high-speed dynamic vision sensor architecture with column-level circuit sharing, comprising a row driving circuit, a pixel array, a column-level shared event triggering circuit, and a readout system, wherein the row driving circuit is connected to the pixel array and the column-level shared event triggering circuit respectively, and the column-level shared event triggering circuit is also connected to the pixel array and the readout system respectively;

[0008] The row driving circuit is used to provide row selection and switch timing signals for the pixel array, and provide data selection, reset and latch signals for the column-level shared event trigger circuit; the pixel array senses the external light intensity to realize photoelectric conversion, and outputs the voltage at the previous moment and the voltage at the current moment during the row selection; the column-level shared event trigger circuit enters the reset state at the beginning of each row selection, first selects the voltage at the previous moment output by the sampling pixel array, then switches to the amplification state after the reset ends, inputs the current moment voltage output by the sampling pixel array, amplifies and compares this step voltage to generate an event, and stores the event information; the readout system is used to process the stored event information and output it to the outside.

[0009] Furthermore, the pixel array is composed of M×N pixel units, each pixel unit in each row is connected to the row bus of the corresponding row in the row driving circuit, and each pixel unit in each column is connected to the input end of the corresponding column in the column-level shared event trigger circuit.

[0010] Furthermore, each of the pixel units is composed of a light receiving stage, a source follower, and a row selection circuit. The light receiving stage is composed of a No. 1 NMOS tube, a No. 2 NMOS tube, a No. 3 NMOS tube, and a No. 1 PMOS tube. The source follower is composed of a No. 4 NMOS tube and a No. 5 NMOS tube. The row selection circuit is composed of a storage capacitor, a No. 1 NMOS switch, a transmission gate, a No. 2 NMOS switch, and a dummy switch. The transmission gate is composed of a No. 6 NMOS tube and a No. 2 PMOS tube.

[0011] The source of the No. 1 NMOS tube and the gate of the No. 3 NMOS tube are both connected to the same photodiode, the source of the No. 3 NMOS tube is grounded, the drain and gate of the No. 1 NMOS tube are both connected to the source of the No. 2 NMOS tube, the drain of the No. 2 NMOS tube, the source of the No. 1 PMOS tube, and the drain of the No. 4 NMOS tube are all connected to the power supply, the gate of the No. 2 NMOS tube, the drain of the No. 3 NMOS tube, the drain of the No. 1 PMOS tube, and the gate of the No. 4 NMOS tube are all connected to the output node of the light receiving stage, the source of the No. 4 NMOS tube, the drain of the No. 5 NMOS tube, and the source of the No. 1 NMOS switch are connected to the power supply, and the gate of the No. 2 NMOS tube, the drain of the No. 3 NMOS tube, the drain of the No. 1 PMOS tube, and the gate of the No. 4 NMOS tube are connected to the output node of the light receiving stage, and the source of the No. 4 NMOS tube, the drain of the No. 5 NMOS tube, and the source of the No. 1 NMOS switch are connected to the power supply. The source of the No. 5 NMOS switch and the drain of the No. 2 NMOS switch are all connected to the source follower output node, the source of the No. 5 NMOS tube is grounded, the drain of the No. 1 NMOS switch is connected to the first input port of the corresponding column in the column-level shared event trigger circuit, the source of the No. 2 NMOS switch, the source and drain of the dummy switch, the source of the No. 6 NMOS tube, and the source of the No. 2 PMOS tube are all connected to the storage capacitor node, and the storage capacitor node is grounded via the storage capacitor, and the drain of the No. 6 NMOS tube and the drain of the No. 2 PMOS tube are all connected to the second input port of the corresponding column in the column-level shared event trigger circuit;

[0012] The gate of the No. 1 PMOS tube inputs a No. 1 bias voltage, the gate of the No. 5 NMOS tube inputs a No. 2 bias voltage, the gate of the No. 1 NMOS switch and the gate of the No. 6 NMOS tube both input a row selection signal of the corresponding row output by the row driving circuit, the gate of the No. 2 PMOS tube inputs an inverted signal of the row selection signal of the corresponding row output by the row driving circuit, the gate of the No. 2 NMOS switch inputs a switch timing signal of the corresponding row output by the row driving circuit, and the gate of the dummy switch inputs an inverted signal of the switch timing signal of the corresponding row output by the row driving circuit.

[0013] Furthermore, the photodiode adopts a "PINP" type photodiode structure, which is classified by doping regions into a p substrate region, an intrinsic semiconductor region, an n+ injection region, and a surface p+ injection region. The p substrate region and the intrinsic semiconductor region are both provided with grooves downward from the upper end surface. The p substrate region, the intrinsic semiconductor region, and the n+ injection region are sequentially embedded from the outside to the inside, and the upper end surfaces of the intrinsic semiconductor region and the n+ injection region are flush. The surface p+ injection region is arranged on the top of the intrinsic semiconductor region and the n+ injection region. The surface p+ injection region is flush with the upper end surface of the p substrate region, and a through hole is provided in the middle of the surface p+ injection region. The p substrate region and the surface p+ injection region are both grounded, and the n+ injection region is respectively connected to the source of the No. 1 NMOS tube and the gate of the No. 3 NMOS tube.

[0014] Furthermore, the column-level shared event trigger circuit is composed of N column-level shared event trigger units, each of which is composed of a column data selector and an event trigger storage circuit, each of the column data selector input terminals are connected to the output terminals of each pixel unit in its corresponding column, each of the column data selector output terminals corresponds to the event trigger storage circuit input terminals, and each of the event trigger storage circuit output terminals are connected to the readout system.

[0015] Further, each of the column data selectors is composed of a No. 1 transmission gate and a No. 2 transmission gate, the transmission gate is composed of a No. 7 NMOS tube and a No. 3 PMOS tube, and the No. 2 transmission gate is composed of a No. 8 NMOS tube and a No. 4 PMOS tube; each of the event-triggered storage circuits is composed of a switch capacitor amplifier, an event comparator, and an event latch, the switch capacitor amplifier is composed of a No. 1 amplifier, a No. 5 PMOS tube, a No. 1 capacitor, and a No. 2 capacitor, the event comparator is composed of a No. 2 amplifier and a No. 3 amplifier, and the event latch is composed of an OFF latch unit and an ON latch unit;

[0016] The source of the No. 7 NMOS tube and the source of the No. 3 PMOS tube are both connected to the drain of the No. 6 NMOS tube and the drain of the No. 2 PMOS tube of each pixel unit in the corresponding column, the source of the No. 8 NMOS tube and the source of the No. 4 PMOS tube are both connected to the drain of the No. 1 NMOS switch of each pixel unit in the corresponding column, the gate of the No. 7 NMOS tube and the gate of the No. 4 PMOS tube are both input with the data selection signal provided by the row driving circuit, the gate of the No. 3 PMOS tube and the gate of the No. 8 NMOS tube are both input with the inverted signal of the data selection signal provided by the row driving circuit, and the drain of the No. 7 NMOS tube, the drain of the No. 3 PMOS tube, the drain of the No. 8 NMOS tube, and the drain of the No. 4 PMOS tube are all connected to the negative input terminal of the No. 1 amplifier via the No. 1 capacitor;

[0017] The positive input terminal of the first amplifier inputs a third bias voltage, a second capacitor is connected between the negative input terminal and the output terminal of the first amplifier, the source and drain of the fifth PMOS tube are respectively connected to the negative input terminal and the output terminal of the first amplifier, and the gate of the fifth PMOS tube inputs a reset signal provided by a row drive circuit;

[0018] The negative phase input terminals of the amplifier No. 2 and the amplifier No. 3 are both connected to the output terminal of the amplifier No. 1, the positive phase input terminals of the amplifier No. 2 and the amplifier No. 3 are respectively input with the bias voltage No. 4 and the bias voltage No. 5, the output terminals of the amplifier No. 2 and the amplifier No. 3 are respectively connected to the input terminals of the OFF latch unit and the ON latch unit, the OFF latch unit and the ON latch unit are respectively input with the OFF latch signal and the ON latch signal, and the output terminals of the OFF latch unit and the ON latch unit are respectively connected to the same group of corresponding input ports in the readout system.

[0019] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0020] Based on the requirements of reducing DVS pixel delay and pixel size, the present invention proposes a high-speed dynamic vision sensor architecture based on column-level circuit sharing, which adopts a photodiode structure with high photoelectric conversion efficiency and a column-level shared event trigger circuit structure. Compared with traditional event pixels, under the same light intensity, the present invention can generate a larger photocurrent at the photosensitive end of the pixel, thereby reducing the pixel delay without affecting other parameters. At the same time, only one storage capacitor is retained in the pixel, which significantly reduces the pixel size. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a diagram of the high-speed dynamic vision sensor architecture based on column-level circuit sharing of the present invention.

[0022] Figure 2 It is a schematic diagram of the structure of a "PINP" type photodiode with high photoelectric conversion efficiency in the present invention.

[0023] Figure 3 It is a schematic diagram of the principle of the pixel unit in the present invention.

[0024] Figure 4 It is a schematic diagram of the principle of the column-level shared event trigger circuit in the present invention.

[0025] Figure 5 It is a working timing diagram of the high-speed dynamic vision sensor based on column-level circuit sharing of the present invention. DETAILED DESCRIPTION

[0026] The present invention will be further described below in conjunction with the accompanying drawings.

[0027] Event-based dynamic vision sensors have the disadvantages of large single pixel size and high pixel transmission delay in dim light. In order to overcome the shortcomings of the prior art, the present invention adopts a high-speed dynamic vision sensor architecture based on column-level circuit sharing, which significantly improves the photocurrent and reduces the capacitance area within the pixel, thereby achieving the purpose of reducing pixel delay and reducing pixel size.

[0028] like Figure 1 As shown, the present invention is based on a high-speed dynamic vision sensor architecture with column-level circuit sharing, and is composed of a row driving circuit 1, a pixel array 2, a column-level shared event trigger circuit 3, and a readout system 4. The row driving circuit 1 is connected to the pixel array 2 and the column-level shared event trigger circuit 3, respectively, and the column-level shared event trigger circuit 3 is also connected to the pixel array 2 and the readout system 4, respectively.

[0029] The row drive circuit 1 is used to provide row selection and switch timing signals for the pixel array 2, so that the pixel array can read out and refresh normally, and provide data selection, reset and latch signals for the column-level shared event trigger circuit 3. The pixel array 2 senses the external light intensity to realize photoelectric conversion, and outputs two voltages at the last moment and the current moment during the row selection. The column-level shared event trigger circuit 3 performs periodic reset and amplification operations during each row selection. The last moment voltage and the current moment voltage are determined by the column data selector. The order of transmission is determined by the column data selector. First, it enters the reset state at the beginning of each row selection, selects the last moment voltage output by the sampling pixel array, and then the reset ends and turns to the amplification state. The input selects the current moment voltage output by the sampling pixel array 2. The subsequent circuit amplifies and compares this step voltage to generate an event, and stores the event information, which can be stored in a latch. The readout system 4 is used to process the stored event information and output it to the outside, which can be realized by a high-speed LVDS interface.

[0030] The pixel array 2 is composed of M×N pixel units, M represents rows, N represents columns, each pixel unit in each row is connected to the row bus of the corresponding row in the row driving circuit 1, and each pixel unit in each column is connected to the input terminal of the corresponding column in the column-level shared event trigger circuit 3. Preferably, the row driving circuit 1 has M groups of row buses, each group of row buses includes two signal lines, the first type provides a switch timing signal and its inverted signal, and the second type provides a row selection signal and its inverted signal. In actual circuit connection, each group of row buses can be designed as four signal lines, and the column-level shared event trigger circuit 3 has N groups of input terminals and N groups of output terminals, each group of input terminals includes 2 input ports, and each group of output terminals includes 2 output ports.

[0031] Figure 2 A two-dimensional cross-section of a "PINP" type photodiode structure with high photoelectric conversion efficiency proposed in the present invention is given, which is classified by doping region, including a p substrate region 51, an intrinsic semiconductor region 52, an n+ injection region 53, and a surface p+ injection region 54. The p substrate region 51 and the intrinsic semiconductor region 52 are both provided with grooves downward from the upper end surface, and the p substrate region 51, the intrinsic semiconductor region 52, and the n+ injection region 53 are sequentially embedded from the outside to the inside, and the upper end surfaces of the intrinsic semiconductor region 52 and the n+ injection region 53 are flush, the surface p+ injection region 54 is arranged on top of the intrinsic semiconductor region 52 and the n+ injection region 53, the surface p+ injection region 54 is flush with the upper end surface of the p substrate region 51, and a through hole is provided in the middle of the surface p+ injection region 54. The p substrate region 51 and the surface p+ injection region 54 are both grounded GND, and the n+ injection region 53 is connected to Figure 3 V PDThe node (i.e., the n+ injection region 53 is connected to the source of the first NMOS tube 61 and the gate of the third NMOS tube 63 respectively), and the photodiode is in a reverse bias state. When there is light, due to the photovoltaic effect of the pn junction, the width of the depletion region of the pn junction is increased and a photocurrent from the n region to the p region is formed. When the photodiode structure of the present invention is exposed to light, the entire intrinsic semiconductor region 52 and part of the surface p+ injection region 54 are depleted, which significantly expands the width of the depletion region, thereby achieving a higher photoelectric conversion efficiency, and the surface p+ injection region 54 can effectively suppress the dark current on the surface of the photodiode, thereby suppressing the noise of the photodiode.

[0032] like Figure 3 As shown, each pixel unit is composed of a light receiving stage 6, a source follower 7, and a row selection circuit 8. The light receiving stage 6 is composed of a No. 1 NMOS tube 61, a No. 2 NMOS tube 62, a No. 3 NMOS tube 63, and a No. 1 PMOS tube 64. The basic working principle is that the No. 3 NMOS tube 63 and the No. 1 PMOS tube 64 form a common source amplifier, and the No. 1 NMOS tube 61 and the No. 2 NMOS tube 62 form a negative feedback to convert V PD The node voltage is clamped near a certain value. The source follower 7 is composed of a No. 4 NMOS tube 71 and a No. 5 NMOS tube 72. The basic principle is to filter out part of the noise of the light receiving stage 6 and play the role of low-pass filtering. The row selection circuit 8 is composed of a storage capacitor 81, a No. 1 NMOS switch 82, a transmission gate 83, a No. 2 NMOS switch 84, and a dummy switch 85. The basic principle is that it can output two moment voltages to the column level when the row selection timing arrives, and refresh the voltage of the storage capacitor 81 after the row selection is completed. The transmission gate 83 is composed of a No. 6 NMOS tube 8301 and a No. 2 PMOS tube 8302. The function of the transmission gate 83 is to suppress the voltage V at the previous moment of the row selection transmission. store The first NMOS switch 82, the second NMOS switch 84 and the dummy switch 85 can all be NMOS tubes, and the function of the dummy switch 85 is to suppress the charge injection effect when the storage node is refreshed.

[0033] Specifically, the source of the first NMOS transistor 61 and the gate of the third NMOS transistor 63 are both connected to V PD Node, the V PD Node connected to Figure 2The n+ implantation region 53 of the photodiode shown in the figure adopts a "PINP" type photodiode structure, the source of the third NMOS tube 63 is grounded GND, the drain and gate of the first NMOS tube 61 are connected to the source of the second NMOS tube 62, the drain of the second NMOS tube 62, the source of the first PMOS tube 64, and the drain of the fourth NMOS tube 71 are all connected to the power supply VDD, the gate of the second NMOS tube 62, the drain of the third NMOS tube 63, the drain of the first PMOS tube 64, and the gate of the fourth NMOS tube 71 are all connected to the light receiving stage output node pr, the source of the fourth NMOS tube 71, the drain of the fifth NMOS tube 72, the source of the first NMOS switch 82, and the drain of the second NMOS tube 62 are all connected to the power supply VDD. The drains of the MOS switches 84 are all connected to the source follower output node sf, the source of the fifth NMOS tube 72 is grounded GND, the drain of the first NMOS switch 82 is connected to the first input port of the corresponding column in the column-level shared event trigger circuit 3, the source of the second NMOS switch 84, the source and drain of the dummy switch 85, the source of the sixth NMOS tube 8301, and the source of the second PMOS tube 8302 are all connected to the storage capacitor node store, and the storage capacitor node store is grounded GND through the storage capacitor 81, and the drain of the sixth NMOS tube 8301 and the drain of the second PMOS tube 8302 are all connected to the second input port of the corresponding column in the column-level shared event trigger circuit 3. The gate of the first PMOS tube 64 inputs the first bias voltage V bpr The gate of the fifth NMOS tube 72 inputs the second bias voltage V bsf The gate of the first NMOS switch 82 and the gate of the sixth NMOS tube 8301 are both input with the row selection signal V of the corresponding row output by the row driving circuit 1. sw The gate of the second PMOS tube 8302 inputs the inverted signal nV of the row selection signal of the corresponding row output by the row driving circuit 1 sw The gate of the second NMOS switch 84 inputs the switch timing signal V corresponding to the row output by the row driving circuit 1 fresh The gate of the dummy switch 85 inputs the inverted signal nV of the switch timing signal of the corresponding row output by the row driving circuit 1 fresh .

[0034] The column-level shared event trigger circuit 3 in the present invention is composed of N column-level shared event trigger units, such as Figure 4 As shown, each column-level shared event trigger unit is composed of a column data selector 9 and an event trigger storage circuit 10, each of the column data selector 9 input ends are connected to the output ends of each pixel unit of its corresponding column, each of the column data selector 9 output ends corresponds to the event trigger storage circuit 10 input end, and each of the event trigger storage circuit 10 output ends are connected to the readout system 4.

[0035] Each of the column data selectors 9 is composed of a first transmission gate 91 and a second transmission gate 92. The transmission gate 91 is composed of a seventh NMOS tube 9101 and a third PMOS tube 9102. The second transmission gate 92 is composed of an eighth NMOS tube 9201 and a fourth PMOS tube 9202. Each of the event-triggered storage circuits 10 is composed of a switch capacitor amplifier 101, an event comparator 102, and an event latch 103. The switch capacitor amplifier 101 is composed of a first amplifier 1012, a fifth PMOS tube 1011, a first capacitor C1, and a second capacitor C2. The event comparator 102 is composed of a second amplifier 1021 and a third amplifier 1022. The event latch 103 is composed of an OFF latch unit OFF Latch and an ON latch unit ON Latch.

[0036] The specific circuit connection of each column-level shared event trigger unit is as follows: the source of the seventh NMOS tube 9101 and the source of the third PMOS tube 9102 are connected together with the drain of the sixth NMOS tube 8301 and the drain of the second PMOS tube 8302 of each pixel unit in the corresponding column, the source of the eighth NMOS tube 9201 and the source of the fourth PMOS tube 9202 are connected to the drain of the first NMOS switch 82 of each pixel unit in the corresponding column, and the gate of the seventh NMOS tube 9101 and the gate of the fourth PMOS tube 9202 are both input with the data selection signal V provided by the row driving circuit 1 sel The gate of the third PMOS tube 9102 and the gate of the eighth NMOS tube 9201 are both input with the inverted signal nV of the data selection signal provided by the row driving circuit 1. sel The drain of the seventh NMOS tube 9101, the drain of the third PMOS tube 9102, the drain of the eighth NMOS tube 9201, and the drain of the fourth PMOS tube 9202 are all connected to the negative input terminal of the first amplifier 1012 through the first capacitor C1. The positive input terminal of the first amplifier 1012 inputs the third bias voltage V ref A second capacitor C2 is connected between the negative phase input terminal and the output terminal of the first amplifier 1012, the source and drain of the fifth PMOS tube 1011 are respectively connected to the negative phase input terminal and the output terminal of the first amplifier 1012, and the gate of the fifth PMOS tube 1011 inputs the reset signal V provided by the row driving circuit 1 nrst The negative input terminals of the second amplifier 1021 and the third amplifier 1022 are connected to the output terminal of the first amplifier 1012, and the positive input terminals of the second amplifier 1021 and the third amplifier 1022 are respectively input with the fourth bias voltage V refh and bias voltage V reflThe output ends of the second amplifier 1021 and the third amplifier 1022 are connected to the input ends of the OFF latch unit OFF Latch and the ON latch unit ON Latch, respectively. The OFF latch unit OFF Latch and the ON latch unit ON Latch input the OFF latch signal V loff and ON latch signal V lon The output ends of the OFF latch unit OFF Latch and the ON latch unit ON Latch are respectively connected to the same corresponding group of input ports in the readout system 4.

[0037] The basic working principle of the column-level shared event trigger circuit 3 in the present invention is as follows: at the beginning of the row selection of a certain row of pixels, the switched capacitor amplifier 101 is reset, and at this time, the first transmission gate 91 is turned on, so that the lower plate of the input capacitor of the switched capacitor amplifier 101 samples the voltage V2 at the previous moment. After a certain period of time, the reset ends, the first transmission gate 91 is turned off, and the second transmission gate 92 is turned on. The lower plate of the input capacitor of the switched capacitor amplifier 101 samples the voltage V1 at the current moment. At this time, the event latch 103 is in a transparent state. This step voltage is judged by the switched capacitor amplifier 101 and the event comparator 102 whether an event is generated, and the result is stored in the event latch 103 for Figure 1 The middle readout system 4 performs readout, after which the row selection of pixels in this row ends and the row selection of pixels in the next row begins. The column-level shared event trigger circuit 3 repeats the above-mentioned working process, so its working cycle is one row selection cycle.

[0038] Figure 5 The relevant working timing diagram of the pixel readout process of the i-th row and j-th column of the high-speed dynamic vision sensor of the present invention is given. The switching timing signal V of the full array pixels at time t0 is fresh = is set high, the second NMOS switch 84 is turned on, giving the storage capacitor 81 an initial value. At time t1, the switch timing signal V fresh The high-speed dynamic vision sensor starts to work normally. Assume that the row selection signal V sw Set high, indicating that the pixels in row i have entered the row selection stage. The voltage V store (i.e., the voltage of the storage capacitor node store) and the current voltage V sf (ie, the voltage of the source follower output node sf) is transmitted to the input terminal of the column data selector 9; the reset signal V nrst <j>The low signal is effective, the fifth PMOS tube 1011 is turned on, and the switched capacitor amplifier 101 enters the reset state; the data selection signal V sel <j>The column data selector 9 controls the first transmission gate 91 to be turned on, and the lower plate of the input capacitor of the switched capacitor amplifier 101 samples V2, i.e., V store At t3, the reset signal V nrst <j>Set to high level, the switched capacitor amplifier 101 enters the amplification state; ON latch signal V lon <j>and OFF latch signal V loff <j>The event latch 103 is in a transparent state and receives the event information output by the event comparator 102 at any time. After a short time (nsec level) to time t4, the data selection signal V sel <j>= low, the column data selector 9 controls the second transmission gate 92 to be turned on, and the switched capacitor amplifier 101 inputs the capacitor lower plate to sample the voltage V1 at the current moment, i.e., V sf This step voltage is negatively amplified by the switched capacitor amplifier 101 according to the capacitance ratio, and is judged and generated by the event comparator 102 and stored in the event latch 103. At time t5, the row selection signal V sw Set low, the i-th row of pixels ends the row selection phase; reset signal V nrst <j>Low is effective, the switched capacitor amplifier 101 re-enters the reset state; ON latch signal V lon <j>and OFF latch signal V loff <j>= is set low, so that the event latch 103 is in a latched state for subsequent reading by the reading system 4. After a short time (ns level) to time t6, the switch timing signal V fresh The i-th row of pixels refreshes the voltage of the storage capacitor 81, and the process continues until time t7. The switch timing signal V fresh Set low to stop voltage refresh. After that, the pixels in this row wait for the next frame row selection phase and perform periodic work.

[0039] Although the functions and working processes of the present invention have been described above in conjunction with the accompanying drawings, the present invention is not limited to the above-mentioned specific functions and working processes. The above-mentioned specific implementation methods are merely illustrative rather than restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the purpose of the present invention and the claims, which are all within the protection of the present invention. < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j>

Claims

1. A high-speed dynamic vision sensor architecture based on column-level circuit sharing, characterized in that: The invention comprises a row driving circuit (1), a pixel array (2), a column-level shared event triggering circuit (3), and a readout system (4), wherein the row driving circuit (1) is connected to the pixel array (2) and the column-level shared event triggering circuit (3) respectively, and the column-level shared event triggering circuit (3) is also connected to the pixel array (2) and the readout system (4) respectively; The row drive circuit (1) is used to provide row selection and switch timing signals for the pixel array (2), and at the same time provide data selection, reset and latch signals for the column-level shared event trigger circuit (3); the pixel array (2) senses the external light intensity to realize photoelectric conversion, and outputs the voltage at the previous moment and the voltage at the current moment during the row selection period; the column-level shared event trigger circuit (3) enters a reset state at the beginning of each row selection, first selects the voltage at the previous moment output by the sampling pixel array, then switches to an amplification state after the reset ends, inputs the voltage at the current moment output by the sampling pixel array (2), amplifies and compares the step voltage to generate an event, and stores the event information; the readout system (4) is used to process the stored event information and output it to the outside.

2. The high-speed dynamic vision sensor architecture based on column-level circuit sharing according to claim 1, characterized in that: The pixel array (2) is composed of M×N pixel units, each pixel unit in each row is connected to the row bus of the corresponding row in the row driving circuit (1), and each pixel unit in each column is connected to the input end of the corresponding column in the column-level shared event trigger circuit (3).

3. The high-speed dynamic vision sensor architecture based on column-level circuit sharing according to claim 2, characterized in that: Each of the pixel units is composed of a light receiving stage (6), a source follower (7), and a row selection circuit (8); the light receiving stage (6) is composed of a No. 1 NMOS tube (61), a No. 2 NMOS tube (62), a No. 3 NMOS tube (63), and a No. 1 PMOS tube (64); the source follower (7) is composed of a No. 4 NMOS tube (71) and a No. 5 NMOS tube (72); the row selection circuit (8) is composed of a storage capacitor (81), a No. 1 NMOS switch (82), a transmission gate (83), a No. 2 NMOS switch (84), and a dummy switch (85); the transmission gate (83) is composed of a No. 6 NMOS tube (8301) and a No. 2 PMOS tube (8302); The source of the No. 1 NMOS tube (61) and the gate of the No. 3 NMOS tube (63) are both connected to the same photodiode, the source of the No. 3 NMOS tube (63) is grounded (GND), the drain and gate of the No. 1 NMOS tube (61) are both connected to the source of the No. 2 NMOS tube (62), the drain of the No. 2 NMOS tube (62), the source of the No. 1 PMOS tube (64), and the drain of the No. 4 NMOS tube (71) are all connected to the power supply (VDD), the gate of the No. 2 NMOS tube (62), the drain of the No. 3 NMOS tube (63), the drain of the No. 1 PMOS tube (64), and the gate of the No. 4 NMOS tube (71) are all connected to the light receiving stage output node (pr), the source of the No. 4 NMOS tube (71), the drain of the No. 5 NMOS tube (72), the source of the No. 1 NMOS switch (82), the drain of the No. 2 NMOS tube (62), the source of the No. 1 PMOS tube (64), and the drain of the No. 4 NMOS tube (71) are all connected to the light receiving stage output node (pr), and the source of the No. 4 NMOS tube (71), the drain of the No. 5 NMOS tube (72), the source of the No. 1 NMOS switch (82), the drain of the No. 2 The drains of the NMOS switches (84) are all connected to the source follower output node (sf), the source of the fifth NMOS tube (72) is grounded (GND), the drain of the first NMOS switch (82) is connected to the first input port of the corresponding column in the column-level shared event trigger circuit (3), the source of the second NMOS switch (84), the source and drain of the dummy switch (85), the source of the sixth NMOS tube (8301), and the source of the second PMOS tube (8302) are all connected to the storage capacitor node (store), and the storage capacitor node (store) is grounded (GND) via the storage capacitor (81), and the drain of the sixth NMOS tube (8301) and the drain of the second PMOS tube (8302) are all connected to the second input port of the corresponding column in the column-level shared event trigger circuit (3); The gate of the first PMOS tube (64) inputs a first bias voltage (V bpr ), the gate of the fifth NMOS tube (72) inputs the second bias voltage (V bsf ), the gate of the first NMOS switch (82) and the gate of the sixth NMOS tube (8301) are both input with a row selection signal (V sw ), the gate of the second PMOS tube (8302) inputs the inverted signal (nV) of the row selection signal of the corresponding row output by the row driving circuit (1) sw ), the gate of the second NMOS switch (84) inputs the switch timing signal (V fresh ), the gate of the dummy switch (85) inputs the inverted signal (nV) of the switch timing signal of the corresponding row output by the row driving circuit (1) fresh ).

4. The high-speed dynamic vision sensor architecture based on column-level circuit sharing according to claim 3, characterized in that: The photodiode adopts a "PINP" type photodiode structure, and includes a p substrate region (51), an intrinsic semiconductor region (52), an n+ injection region (53), and a surface p+ injection region (54) according to the classification of doping regions. The p substrate region (51) and the intrinsic semiconductor region (52) are both provided with a groove downward from the upper end surface. The p substrate region (51), the intrinsic semiconductor region (52), and the n+ injection region (53) are sequentially embedded from the outside to the inside, and the intrinsic semiconductor region (52) and the n+ injection region (54) are arranged in a manner that is consistent with the embodiment of the present invention. The upper end surface of the semiconductor region (53) is flush with that of the semiconductor region (53), the surface p+ injection region (54) is arranged on the top of the intrinsic semiconductor region (52) and the n+ injection region (53), the surface p+ injection region (54) is flush with the upper end surface of the p substrate region (51), and a through hole is opened in the middle of the surface p+ injection region (54); the p substrate region (51) and the surface p+ injection region (54) are both grounded (GND), and the n+ injection region 53 is respectively connected to the source of the first NMOS tube (61) and the gate of the third NMOS tube (63).

5. The high-speed dynamic vision sensor architecture based on column-level circuit sharing according to claim 1, characterized in that: The column-level shared event trigger circuit (3) is composed of N column-level shared event trigger units, each of which is composed of a column data selector (9) and an event trigger storage circuit (10), each of the column data selector (9) input ends are connected to the output ends of each pixel unit of its corresponding column, each of the column data selector (9) output ends corresponds to the event trigger storage circuit (10) input end, and each of the event trigger storage circuit (10) output ends is connected to the readout system (4).

6. The high-speed dynamic vision sensor architecture based on column-level circuit sharing according to claim 5, characterized in that: Each of the column data selectors (9) is composed of a No. 1 transmission gate (91) and a No. 2 transmission gate (92), wherein the transmission gate (91) is composed of a No. 7 NMOS tube (9101) and a No. 3 PMOS tube (9102), and the No. 2 transmission gate (92) is composed of a No. 8 NMOS tube (9201) and a No. 4 PMOS tube (9202); each of the event-triggered storage circuits (10) is composed of a switch capacitor amplifier (101), an event comparator (102), and an event latch (103), wherein the switch capacitor amplifier (101) is composed of a No. 1 amplifier (1012), a No. 5 PMOS tube (1011), a No. 1 capacitor (C1), and a No. 2 capacitor (C2), wherein the event comparator (102) is composed of a No. 2 amplifier (1021) and a No. 3 amplifier (1022), and wherein the event latch (103) is composed of an OFF latch unit (OFF Latch) and an ON latch unit (ON Latch); The source of the seventh NMOS tube (9101) and the source of the third PMOS tube (9102) are both connected to the drain of the sixth NMOS tube (8301) and the drain of the second PMOS tube (8302) of each pixel unit in the corresponding column, the source of the eighth NMOS tube (9201) and the source of the fourth PMOS tube (9202) are both connected to the drain of the first NMOS switch (82) of each pixel unit in the corresponding column, and the gate of the seventh NMOS tube (9101) and the gate of the fourth PMOS tube (9202) are both input with the data selection signal (V) provided by the row driving circuit (1). sel ), the gate of the third PMOS tube (9102) and the gate of the eighth NMOS tube (9201) are both input with the inverted signal (nV) of the data selection signal provided by the row driving circuit (1). sel ), the drain of the seventh NMOS tube (9101), the drain of the third PMOS tube (9102), the drain of the eighth NMOS tube (9201), and the drain of the fourth PMOS tube (9202) are all connected to the negative input terminal of the first amplifier (1012) via the first capacitor (C1); The positive input terminal of the first amplifier (1012) inputs a third bias voltage (V ref ), a No. 2 capacitor (C2) is connected between the negative phase input terminal and the output terminal of the No. 1 amplifier (1012), a source and a drain of the No. 5 PMOS tube (1011) are respectively connected to the negative phase input terminal and the output terminal of the No. 1 amplifier (1012), and a gate of the No. 5 PMOS tube (1011) inputs a reset signal (V nrst ); The negative phase input terminals of the second amplifier (1021) and the third amplifier (1022) are both connected to the output terminal of the first amplifier (1012), and the positive phase input terminals of the second amplifier (1021) and the third amplifier (1022) are respectively input with a fourth bias voltage (V refh ) and bias voltage No. 5 (V refl ), the output ends of the second amplifier (1021) and the third amplifier (1022) are respectively connected to the input ends of the OFF latch unit (OFF Latch) and the ON latch unit (ON Latch), and the OFF latch unit (OFF Latch) and the ON latch unit (ON Latch) are respectively input with the OFF latch signal (V loff ) and ON latch signal (V lon ), the output ends of the OFF latch unit (OFF Latch) and the ON latch unit (ON Latch) are respectively connected to the same group of corresponding input ports in the readout system (4).

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