Reading circuit of CMOS image sensor

Abstract

The invention discloses a reading circuit of a CMOS (Complementary Metal Oxide Semiconductor) image sensor, which is realized by adopting a variable gain charge amplifier structure realized based on a switch operational amplifier, and is characterized in that the state of the switch operational amplifier is controlled through a clock signal, so that the switch operational amplifier is started when the CMOS image sensor senses a pixel signal; when the CMOS image sensor does not sense the pixel signal, the reading circuit is closed, so that the dynamic opening and closing of the reading circuit are realized; the device has the advantage of low static power consumption.

Description

Technical Field

[0001] The invention relates to a readout circuit, in particular to a readout circuit of a CMOS image sensor. Background Art

[0002] In recent years, CMOS image sensors have the advantages of high speed, low power consumption, low cost and easy integration, and have been widely used in smart phones, tablet computers, digital cameras, camcorders, automobiles and other industries. In actual applications, CMOS image sensors are used in conjunction with readout circuits. When the CMOS image sensor senses a pixel signal (i.e., a light signal), it converts the pixel signal into an electrical signal and outputs it to the readout circuit. The readout circuit amplifies the electrical signal output by the CMOS image sensor and then outputs it.

[0003] However, the existing readout circuit is usually implemented based on a charge amplifier structure. When used in conjunction with a CMOS image sensor, the readout circuit remains in an on state regardless of whether the CMOS image sensor senses a pixel signal. As a result, its static power consumption is relatively high, especially in low-power application scenarios. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a readout circuit of a CMOS image sensor with lower static power consumption.

[0005] The technical solution adopted by the present invention to solve the above technical problems is: a readout circuit of a CMOS image sensor is implemented by a variable gain charge amplifier structure based on a switching operational amplifier, and the state of the switching operational amplifier is controlled by a clock signal, so that the switching operational amplifier is turned on when the CMOS image sensor senses a pixel signal, and is turned off when the CMOS image sensor does not sense a pixel signal, thereby realizing dynamic opening and closing of the readout circuit.

[0006] The readout circuit of a CMOS image sensor comprises a first capacitor, a second capacitor, a third capacitor, a fourth capacitor and a switching operational amplifier, wherein the switching operational amplifier has a non-inverting input terminal, an inverting input terminal, a first clock terminal, a second clock terminal and an output terminal, wherein the first capacitor and the second capacitor are both variable capacitors, one end of the first capacitor is the positive input terminal of the readout circuit, one end of the second capacitor is the negative input terminal of the readout circuit, an electrical signal output by the CMOS image sensor is connected between the positive input terminal and the negative input terminal of the readout circuit, the other end of the first capacitor and one end of the third capacitor are connected to the inverting input terminal of the switching operational amplifier, and the The other end of the second capacitor and one end of the fourth capacitor are connected to the in-phase input end of the switching operational amplifier, the other end of the third capacitor and the other end of the fourth capacitor are connected to the output end of the switching operational amplifier, and their connection ends are the output ends of the readout circuit, the first clock end of the switching operational amplifier is the first clock end of the readout circuit, and is connected to the first clock signal, the second clock end of the switching operational amplifier is the second clock end of the readout circuit, and is connected to the second clock signal, the first clock signal and the second clock signal are complementary signals to each other, and the first clock signal and the second clock signal can control the opening and closing of the switching operational amplifier.

[0007] The switching operational amplifier comprises a current source, a first resistor, a fifth capacitor and 27 MOS tubes, and the 27 MOS tubes are respectively referred to as a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, an eighth MOS tube, a ninth MOS tube, a tenth MOS tube, an eleventh MOS tube, a twelfth MOS tube, a thirteenth MOS tube, a fourteenth MOS tube, a fifteenth MOS tube, a sixteenth MOS tube, a seventeenth MOS tube, an eighteenth MOS tube, a nineteenth MOS tube, a twentieth MOS tube, a twenty-first MOS tube, a twenty-second MOS tube, a twenty-third MOS tube, a twenty-fourth MOS tube, a The MOS tube, the twenty-fifth MOS tube, the twenty-sixth MOS tube and the twenty-seventh MOS tube, the first MOS tube, the second MOS tube, the third MOS tube, the sixth MOS tube, the seventh MOS tube, the eighth MOS tube, the ninth MOS tube, the tenth MOS tube, the eleventh MOS tube, the sixteenth MOS tube, the seventeenth MOS tube, the eighteenth MOS tube, the nineteenth MOS tube, the twenty-first MOS tube and the twenty-seventh MOS tube are all NMOS tubes, the fourth MOS tube, the fifth MOS tube, the twelfth MOS tube, the The thirteenth MOS tube, the fourteenth MOS tube, the fifteenth MOS tube, the twentieth MOS tube, the twenty-second MOS tube, the twenty-third MOS tube, the twenty-fourth MOS tube, the twenty-fifth MOS tube and the twenty-sixth MOS tube are all PMOS tubes; the drain of the first MOS tube, the drain of the second MOS tube, the source of the seventh MOS tube, the drain of the eighth MOS tube and the drain of the ninth MOS tube are connected, the gate of the first MOS tube, the gate of the second MOS tube and the gate of the eighth MOS tube are connected, and the connection ends are the switch operation The negative input terminal of the operational amplifier, the source of the first MOS tube, the source of the second MOS tube, the source and gate of the fourth MOS tube, and the gate of the fifth MOS tube are connected, the drain of the third MOS tube, the drain of the sixth MOS tube, the drain of the seventh MOS tube, the drain of the sixteenth MOS tube, the drain of the seventeenth MOS tube, the drain of the eighteenth MOS tube, and the source of the twenty-fifth MOS tube are all connected to the power supply voltage; the source and gate of the third MOS tube, the source of the fifth MOS tube, the gate of the tenth MOS tube, and the gate of the eleventh MOS tube are connected,The drain of the fourth MOS tube, the drain of the fifth MOS tube, the negative electrode of the current source, the drain of the fourteenth MOS tube, the drain of the fifteenth MOS tube, the source of the nineteenth MOS tube, the source of the twenty-first MOS tube, the source of the twenty-seventh MOS tube and the source of the twenty-fourth MOS tube are all grounded, the source of the sixth MOS tube is connected to the positive electrode of the current source, the gate of the sixth MOS tube, the gate of the seventh MOS tube, the gate of the seventeenth MOS tube and the gate of the eighteenth MOS tube are connected, the source of the eighth MOS tube is connected to the drain of the tenth MOS tube, and the The source of the ninth MOS tube is connected to the drain of the eleventh MOS tube, the gate of the ninth MOS tube is the positive input terminal of the switch operational amplifier, the source of the tenth MOS tube, one end of the first resistor, the gate of the twelfth MOS tube and the gate of the thirteenth MOS tube are connected, the source of the eleventh MOS tube, the source of the thirteenth MOS tube, the gate of the twenty-first MOS tube, the drain of the twenty-sixth MOS tube and the gate of the twenty-fourth MOS tube are connected, the source of the twelfth MOS tube, the other end of the first resistor, the gate of the fourteenth MOS tube and the gate of the fifteenth MOS tube are connected The drain of the twelfth MOS tube is connected to the source of the fourteenth MOS tube, the drain of the thirteenth MOS tube is connected to the source of the fifteenth MOS tube, the gate of the sixteenth MOS tube, the source of the seventeenth MOS tube and the drain of the nineteenth MOS tube are connected, the source of the sixteenth MOS tube, the gate of the nineteenth MOS tube and the source of the twentieth MOS tube are connected, the source of the eighteenth MOS tube, the gate of the twentieth MOS tube and the gate and source of the twenty-second MOS tube are connected, the drain of the twentieth MOS tube is connected to the drain of the twenty-first MOS tube, the twentieth MOS tube is connected The drain of the second MOS tube and the gate and source of the twenty-third MOS tube are connected, the drain of the twenty-third MOS tube is connected to the drain of the twenty-seventh MOS tube, the drain of the twenty-fourth MOS tube, one end of the fifth capacitor and the drain of the twenty-fifth MOS tube are connected, and the connection end is the output end of the switch operational amplifier, the gate of the twenty-fifth MOS tube is the second clock end of the switch operational amplifier, the gate of the twenty-sixth MOS tube is connected to the gate of the twenty-seventh, and the connection end is the first clock end of the switch operational amplifier, and the source of the twenty-sixth MOS tube is connected to the other end of the fifth capacitor.

[0008] Compared with the prior art, the advantage of the present invention is that a readout circuit is realized by adopting a variable gain charge amplifier structure based on a switching operational amplifier, and the state of the switching operational amplifier is controlled by a clock signal, so that the switching operational amplifier is turned on when the CMOS image sensor senses a pixel signal, and is turned off when the CMOS image sensor does not sense a pixel signal, thereby realizing dynamic turning on and off of the readout circuit. Therefore, the readout circuit of the present invention is turned on only when the CMOS image sensor senses a pixel signal, and has lower static power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 A circuit diagram of a readout circuit of a CMOS image sensor of the present invention;

[0010] Figure 2 The circuit diagram of the switching operational amplifier of the readout circuit of the CMOS image sensor of the present invention is shown in FIG. DETAILED DESCRIPTION

[0011] The present invention is further described in detail below with reference to the accompanying drawings.

[0012] Embodiment 1: A readout circuit of a CMOS image sensor is implemented using a variable gain charge amplifier structure based on a switching operational amplifier. The state of the switching operational amplifier is controlled by a clock signal, so that the switching operational amplifier is turned on when the CMOS image sensor senses a pixel signal, and is turned off when the CMOS image sensor does not sense a pixel signal, thereby realizing dynamic turning on and off of the readout circuit.

[0013] In this embodiment, the readout circuit is implemented by adopting a variable gain charge amplifier structure based on a switching operational amplifier, and the state of the switching operational amplifier is controlled by a clock signal, so that the switching operational amplifier is turned on when the CMOS image sensor senses a pixel signal, and is turned off when the CMOS image sensor does not sense a pixel signal, thereby realizing dynamic turning on and off of the readout circuit. Therefore, the readout circuit of the present invention is turned on only when the CMOS image sensor senses a pixel signal, and has lower static power consumption.

[0014] Embodiment 2: This embodiment is basically the same as Embodiment 1, except that: Figure 1As shown, in this embodiment, a readout circuit of a CMOS image sensor includes a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4 and a switching operational amplifier OP1, the switching operational amplifier OP1 has a non-inverting input terminal, an inverting input terminal, a first clock terminal, a second clock terminal and an output terminal, the first capacitor C1 and the second capacitor C2 are both variable capacitors, one end of the first capacitor C1 is a positive input terminal of the readout circuit, one end of the second capacitor C2 is a negative input terminal of the readout circuit, an electrical signal output by the CMOS image sensor is connected between the positive input terminal and the negative input terminal of the readout circuit, the other end of the first capacitor C1, one end of the third capacitor C3 and the inverting input terminal of the switching operational amplifier OP1 are connected, and the second capacitor C2 is a negative input terminal of the readout circuit. The other end and one end of the fourth capacitor C4 are connected to the in-phase input end of the switching operational amplifier OP1, the other end of the third capacitor C3 and the other end of the fourth capacitor C4 are connected to the output end of the switching operational amplifier OP1, and their connection ends are the output ends of the readout circuit, the first clock end of the switching operational amplifier OP1 is the first clock end of the readout circuit, and the first clock signal Clock is connected, the second clock end of the switching operational amplifier OP1 is the second clock end of the readout circuit, and the second clock signal Clockb is connected, the first clock signal Clock and the second clock signal Clockb are complementary signals to each other, and the first clock signal Clock and the second clock signal Clockb can control the opening and closing of the switching operational amplifier OP1.

[0015] In this embodiment, the first capacitor C1 and the second capacitor C2 are both variable capacitors. By adjusting the capacitance of the first capacitor C1 and the second capacitor C2, the gain of the switching operational amplifier OP1 can be adjusted, so that the gain of the switching operational amplifier OP1 can be adjusted according to actual usage requirements, and the first clock signal Clock and the second clock signal Clockb can control the opening and closing of the switching operational amplifier OP1 to realize dynamic opening and closing of the readout circuit.

[0016] Embodiment 3: This embodiment is basically the same as Embodiment 2, except that: Figure 1As shown, the switching operational amplifier OP1 includes a current source iBias, a first resistor R1, a fifth capacitor C5 and 27 MOS tubes, and the 27 MOS tubes are respectively called a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5, a sixth MOS tube M6, a seventh MOS tube M7, an eighth MOS tube M8, a ninth MOS tube M9, a tenth MOS tube M10, an eleventh MOS tube M11, a twelfth MOS tube M12, a thirteenth MOS tube M13, a fourteenth MOS tube M14, a fifteenth MOS tube M15, a sixteenth MOS tube M16, a seventeenth MOS tube M17, an eighteenth MOS tube M18, a ninth MOS tube M19, a tenth MOS tube M20, a twelfth MOS tube M21, a thirteenth MOS tube M22, a thirteenth MOS tube M23, a fourteenth MOS tube M24, a fifteenth MOS tube M25, a sixteenth MOS tube M26, a seventeenth MOS tube M27, a MOS tube M18, the nineteenth MOS tube M19, the twentieth MOS tube M20, the twenty-first MOS tube M21, the twenty-second MOS tube M22, the twenty-third MOS tube M23, the twenty-fourth MOS tube M24, the twenty-fifth MOS tube M25, the twenty-sixth MOS tube M26 and the twenty-seventh MOS tube M27, the first MOS tube M1, the second MOS tube M2, the third MOS tube M3, the sixth MOS tube M6, the seventh MOS tube M7, the eighth MOS tube M8, the ninth MOS tube M9, the tenth MOS tube M10, the eleventh MOS tube M11, the sixteenth MOS tube M16, the seventeenth MOS tube M17 and the eighteenth MOS tube M18 The nineteenth MOS tube M19, the twenty-first MOS tube M21 and the twenty-seventh MOS tube M27 are all NMOS tubes, the fourth MOS tube M4, the fifth MOS tube M5, the twelfth MOS tube M12, the thirteenth MOS tube M13, the fourteenth MOS tube M14, the fifteenth MOS tube M15, the twentieth MOS tube M20, the twenty-second MOS tube M22, the twenty-third MOS tube M23, the twenty-fourth MOS tube M24, the twenty-fifth MOS tube M25 and the twenty-sixth MOS tube M26 are all PMOS tubes; the drain of the first MOS tube M1, the drain of the second MOS tube M2, the source of the seventh MOS tube M7 and the drain of the eighth MOS tube M8 The first MOS tube M1 is connected to the drain of the ninth MOS tube M9, the gate of the first MOS tube M1, the gate of the second MOS tube M2 and the gate of the eighth MOS tube M8 are connected, and the connection end thereof is the negative input end of the switch operational amplifier OP1, the source of the first MOS tube M1, the source of the second MOS tube M2, the source and gate of the fourth MOS tube M4 and the gate of the fifth MOS tube M5 are connected, the drain of the third MOS tube M3, the drain of the sixth MOS tube M6, the drain of the seventh MOS tube M7, the drain of the sixteenth MOS tube M16, the drain of the seventeenth MOS tube M17, the drain of the eighteenth MOS tube M18 and the source of the twenty-fifth MOS tube M25 are all connected to the power supply voltage;The source and gate of the third MOS tube M3, the source of the fifth MOS tube M5, the gate of the tenth MOS tube M10 and the gate of the eleventh MOS tube M11 are connected, the drain of the fourth MOS tube M4, the drain of the fifth MOS tube M5, the negative electrode of the current source iBias, the drain of the fourteenth MOS tube M14, the drain of the fifteenth MOS tube M15, the source of the nineteenth MOS tube M19, the source of the twenty-first MOS tube M21, the source of the twenty-seventh MOS tube M27 and the source of the twenty-fourth MOS tube M24 are all grounded, the source of the sixth MOS tube M6 and the positive electrode of the current source iBias are connected, the gate of the sixth MOS tube M6, the gate of the seventh MOS tube M7, the gate of the seventeenth MOS tube M17 and the gate of the tenth The gate of the eighth MOS tube M18 is connected, the source of the eighth MOS tube M8 is connected to the drain of the tenth MOS tube M10, the source of the ninth MOS tube M9 is connected to the drain of the eleventh MOS tube M11, the gate of the ninth MOS tube M9 is the positive input end of the switch operational amplifier OP1, the source of the tenth MOS tube M10, one end of the first resistor R1, the gate of the twelfth MOS tube M12 and the gate of the thirteenth MOS tube M13 are connected, the source of the eleventh MOS tube M11, the source of the thirteenth MOS tube M13, the gate of the twenty-first MOS tube M21, the drain of the twenty-sixth MOS tube M26 and the gate of the twenty-fourth MOS tube M24 are connected, the source of the twelfth MOS tube M12, the other end of the first resistor R1 , the gate of the fourteenth MOS tube M14 is connected to the gate of the fifteenth MOS tube M15, the drain of the twelfth MOS tube M12 is connected to the source of the fourteenth MOS tube M14, the drain of the thirteenth MOS tube M13 is connected to the source of the fifteenth MOS tube M15, the gate of the sixteenth MOS tube M16, the source of the seventeenth MOS tube M17 and the drain of the nineteenth MOS tube M19 are connected, the source of the sixteenth MOS tube M16, the gate of the nineteenth MOS tube M19 and the source of the twentieth MOS tube M20 are connected, the source of the eighteenth MOS tube M18, the gate of the twentieth MOS tube M20 and the gate and source of the twenty-second MOS tube M22 are connected, the drain of the twentieth MOS tube M20 and the twenty-first MOS The drain of the twenty-second MOS tube M22 is connected to the gate and source of the twenty-third MOS tube M23, the drain of the twenty-third MOS tube M23 is connected to the drain of the twenty-seventh MOS tube M27, the drain of the twenty-fourth MOS tube M24, one end of the fifth capacitor C5 and the drain of the twenty-fifth MOS tube M25 are connected, and the connection end thereof is the output end of the switch operational amplifier OP1, the gate of the twenty-fifth MOS tube M25 is the second clock end of the switch operational amplifier OP1, the gate of the twenty-sixth MOS tube M26 is connected to the gate of the twenty-seventh MOS tube M27, and the connection end thereof is the first clock end of the switch operational amplifier OP1, and the source of the twenty-sixth MOS tube M26 is connected to the other end of the fifth capacitor C5. ;

[0017] In this embodiment, the first MOS tube M1 and the second MOS tube M2 constitute a first differential pair, the eighth MOS tube M8 and the ninth MOS tube M9 constitute a second differential pair, the first differential pair and the second differential pair constitute the input stage of the switch operational amplifier OP1, the electrical signal output by the CMOS image sensor is a differential signal, one path of the differential signal is output to the ninth MOS tube M9, and the other path is output to the first MOS tube M1, the second MOS tube M2 and the eighth MOS tube M8, the eighth MOS tube M8 and the ninth MOS tube M9 convert the input differential signal into a differential current signal for output, the third MOS tube M3 and the fourth MOS tube M4 are connected to the CMOS image sensor, and the differential signal is transmitted to the CMOS image sensor. 4 forms a current mirror to mirror the differential current signal to the fifth MOS tube M5, the fifth MOS tube M5 mirrors the differential current signal to the sixth MOS tube M6, the sixth MOS tube M6 and the seventh MOS tube M7 form a first-stage differential amplifier to further amplify the differential current signal, the sixteenth MOS tube M16 and the seventeenth MOS tube M17 form a second-stage differential amplifier to achieve amplification and common-mode feedback of the differential current signal together with the twelfth MOS tube M12 and the thirteenth MOS tube M13, the first resistor R1, the twelfth MOS tube M12 and the thirteenth MOS tube M13 form a common-mode feedback circuit to ensure that the common-mode current of the final output signal is stable The sixteenth MOS tube M16 and the seventeenth MOS tube M17 transmit the differential current signal to the twenty-fourth MOS tube M24. The twenty-fourth MOS tube M24 constitutes the output stage of the switch operational amplifier OP1, which is used to output the amplified electrical signal. The twenty-fifth MOS tube M25, the twenty-sixth MOS tube M26 and the twenty-seventh MOS tube M27 constitute the clock control circuit of the switch operational amplifier OP1. Under the control of the first clock signal Clock and the second clock signal Clockb, the dynamic switch of the switch operational amplifier OP1 is realized. When the first clock signal Clock is at a high level and the second clock signal Clockb is at a low level, the first clock signal Clock is at a high level and the second clock signal Clockb is at a low level. The twenty-fifth MOS tube M25 and the twenty-sixth MOS tube M26 are turned on, the switch operational amplifier OP1 is turned on and is in a working state. The twenty-fifth MOS tube M25 and the twenty-sixth MOS tube M26 output the amplified signal, that is, the final output signal, through the output end of the readout circuit. When the first clock signal Clock is at a low level and the second clock signal Clockb is at a high level, the twenty-fifth MOS tube M25 and the twenty-sixth MOS tube M26 are turned off, and the switch operational amplifier OP1 is turned off and is in a dormant state, thereby reducing static power consumption. The fifth capacitor C5 is used to maintain the signal level to prevent sudden changes in the output signal.

[0018] In this embodiment, through the control of the first clock signal Clock and the second clock signal Clockb, the switching operational amplifier OP1 is turned on when the CMOS image sensor senses the pixel signal, and is turned off when the CMOS image sensor does not sense the pixel signal, thereby achieving correct readout and amplification of the output signal and having lower static power consumption.

Claims

1. A readout circuit for a CMOS image sensor, characterized in that The invention adopts a variable gain charge amplifier structure based on a switching operational amplifier, and controls the state of the switching operational amplifier through a clock signal, so that the switching operational amplifier is turned on when the CMOS image sensor senses a pixel signal, and is turned off when the CMOS image sensor does not sense a pixel signal, thereby realizing the dynamic opening and closing of the readout circuit.

2. A readout circuit for a CMOS image sensor according to claim 1, characterized in that The invention comprises a first capacitor, a second capacitor, a third capacitor, a fourth capacitor and a switching operational amplifier, wherein the switching operational amplifier has a non-inverting input terminal, an inverting input terminal, a first clock terminal, a second clock terminal and an output terminal, wherein the first capacitor and the second capacitor are both variable capacitors, one end of the first capacitor is the positive input terminal of the readout circuit, one end of the second capacitor is the negative input terminal of the readout circuit, an electrical signal output by the CMOS image sensor is connected between the positive input terminal and the negative input terminal of the readout circuit, the other end of the first capacitor and one end of the third capacitor are connected to the inverting input terminal of the switching operational amplifier, the other end of the second capacitor, One end of the fourth capacitor is connected to the in-phase input end of the switching operational amplifier, the other end of the third capacitor and the other end of the fourth capacitor are connected to the output end of the switching operational amplifier, and the connection ends are the output ends of the readout circuit, the first clock end of the switching operational amplifier is the first clock end of the readout circuit, and is connected to the first clock signal, the second clock end of the switching operational amplifier is the second clock end of the readout circuit, and is connected to the second clock signal, the first clock signal and the second clock signal are complementary signals to each other, and the first clock signal and the second clock signal can control the opening and closing of the switching operational amplifier.

3. The readout circuit of a CMOS image sensor according to claim 1, characterized in that The switching operational amplifier comprises a current source, a first resistor, a fifth capacitor and 27 MOS tubes, and the 27 MOS tubes are respectively referred to as a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, an eighth MOS tube, a ninth MOS tube, a tenth MOS tube, an eleventh MOS tube, a twelfth MOS tube, a thirteenth MOS tube, a fourteenth MOS tube, a fifteenth MOS tube, a sixteenth MOS tube, a seventeenth MOS tube, an eighteenth MOS tube, a nineteenth MOS tube, a twentieth MOS tube, a twenty-first MOS tube, a twenty-second MOS tube, a twenty-third MOS tube, a twenty-fourth MOS tube, a The MOS tube, the twenty-fifth MOS tube, the twenty-sixth MOS tube and the twenty-seventh MOS tube, the first MOS tube, the second MOS tube, the third MOS tube, the sixth MOS tube, the seventh MOS tube, the eighth MOS tube, the ninth MOS tube, the tenth MOS tube, the eleventh MOS tube, the sixteenth MOS tube, the seventeenth MOS tube, the eighteenth MOS tube, the nineteenth MOS tube, the twenty-first MOS tube and the twenty-seventh MOS tube are all NMOS tubes, the fourth MOS tube, the fifth MOS tube, the twelfth MOS tube, the The thirteenth MOS tube, the fourteenth MOS tube, the fifteenth MOS tube, the twentieth MOS tube, the twenty-second MOS tube, the twenty-third MOS tube, the twenty-fourth MOS tube, the twenty-fifth MOS tube and the twenty-sixth MOS tube are all PMOS tubes; the drain of the first MOS tube, the drain of the second MOS tube, the source of the seventh MOS tube, the drain of the eighth MOS tube and the drain of the ninth MOS tube are connected, the gate of the first MOS tube, the gate of the second MOS tube and the gate of the eighth MOS tube are connected, and the connection ends are the switch operation The negative input terminal of the operational amplifier, the source of the first MOS tube, the source of the second MOS tube, the source and gate of the fourth MOS tube, and the gate of the fifth MOS tube are connected, the drain of the third MOS tube, the drain of the sixth MOS tube, the drain of the seventh MOS tube, the drain of the sixteenth MOS tube, the drain of the seventeenth MOS tube, the drain of the eighteenth MOS tube, and the source of the twenty-fifth MOS tube are all connected to the power supply voltage; the source and gate of the third MOS tube, the source of the fifth MOS tube, the gate of the tenth MOS tube, and the gate of the eleventh MOS tube are connected,The drain of the fourth MOS tube, the drain of the fifth MOS tube, the negative electrode of the current source, the drain of the fourteenth MOS tube, the drain of the fifteenth MOS tube, the source of the nineteenth MOS tube, the source of the twenty-first MOS tube, the source of the twenty-seventh MOS tube and the source of the twenty-fourth MOS tube are all grounded, the source of the sixth MOS tube is connected to the positive electrode of the current source, the gate of the sixth MOS tube, the gate of the seventh MOS tube, the gate of the seventeenth MOS tube and the gate of the eighteenth MOS tube are connected, the source of the eighth MOS tube is connected to the drain of the tenth MOS tube, and the The source of the ninth MOS tube is connected to the drain of the eleventh MOS tube, the gate of the ninth MOS tube is the positive input terminal of the switch operational amplifier, the source of the tenth MOS tube, one end of the first resistor, the gate of the twelfth MOS tube and the gate of the thirteenth MOS tube are connected, the source of the eleventh MOS tube, the source of the thirteenth MOS tube, the gate of the twenty-first MOS tube, the drain of the twenty-sixth MOS tube and the gate of the twenty-fourth MOS tube are connected, the source of the twelfth MOS tube, the other end of the first resistor, the gate of the fourteenth MOS tube and the gate of the fifteenth MOS tube are connected The drain of the twelfth MOS tube is connected to the source of the fourteenth MOS tube, the drain of the thirteenth MOS tube is connected to the source of the fifteenth MOS tube, the gate of the sixteenth MOS tube, the source of the seventeenth MOS tube and the drain of the nineteenth MOS tube are connected, the source of the sixteenth MOS tube, the gate of the nineteenth MOS tube and the source of the twentieth MOS tube are connected, the source of the eighteenth MOS tube, the gate of the twentieth MOS tube and the gate and source of the twenty-second MOS tube are connected, the drain of the twentieth MOS tube is connected to the drain of the twenty-first MOS tube, the twentieth MOS tube is connected The drain of the second MOS tube and the gate and source of the twenty-third MOS tube are connected, the drain of the twenty-third MOS tube is connected to the drain of the twenty-seventh MOS tube, the drain of the twenty-fourth MOS tube, one end of the fifth capacitor and the drain of the twenty-fifth MOS tube are connected, and the connection end is the output end of the switch operational amplifier, the gate of the twenty-fifth MOS tube is the second clock end of the switch operational amplifier, the gate of the twenty-sixth MOS tube is connected to the gate of the twenty-seventh, and the connection end is the first clock end of the switch operational amplifier, and the source of the twenty-sixth MOS tube is connected to the other end of the fifth capacitor.

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