Printed circuit board

Abstract

The present disclosure provides a printed circuit board including: a glass layer having a through hole penetrating between an upper surface and a lower surface of the glass layer; a through via including via metal layers disposed on a wall surface of the through via and a first insulating material disposed in at least a portion of a space between the via metal layers in the through via; a first wiring layer disposed on the upper surface of the glass layer, at least a portion of the first wiring layer being connected to an upper side of the through via; a second wiring layer disposed on the lower surface of the glass layer, at least a portion of the second wiring layer being connected to a lower side of the through via; and a second insulating material covering at least a portion of an outer surface of the glass layer. The first insulating material and the second insulating material comprise substantially the same material.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2023-0075306 filed on June 13, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The present disclosure relates to a printed circuit board. Background Art

[0003] Packaging technology is constantly evolving, and specifically, attempts are being made to use silicon or glass to get rid of organic materials used in conventional substrate manufacturing methods. However, in the case of a printed circuit board using a conventional glass core, the process of forming a through-hole in the glass core may be somewhat complicated, and there may be limitations in achieving fine line widths directly in the glass core. In addition, the possibility of damaging the glass core during the process is very high, and the exposed portion on the side surface of the glass core in the final product may be susceptible to impact. Summary of the invention

[0004] An aspect of the present disclosure is to provide a printed circuit board for forming a wiring layer formed on a glass layer into a microcircuit.

[0005] Another aspect of the present disclosure is to provide a printed circuit board that can simplify the process and facilitate warpage control.

[0006] Another aspect of the present disclosure is to provide a printed circuit board for preventing damage to a glass layer and protecting an outer surface of the glass layer.

[0007] One of the various solutions proposed by the present disclosure is to form a through via in a glass layer and then planarize the through via using chemical mechanical polishing (CMP) to form a microcircuit on the glass layer using a semi-additive process (SAP).

[0008] Another solution among the various solutions proposed by the present disclosure is to simultaneously perform the embedding process of the glass layer and the plugging process of the through-hole of the glass layer.

[0009] Another solution among various solutions proposed by the present disclosure is to perform an embedding process of a glass layer and a plugging process of a through hole using a reinforcement layer such as a copper clad laminate (CCL) as a mold.

[0010] According to one aspect of the present disclosure, a printed circuit board may include: a glass layer having a through hole penetrating between an upper surface and a lower surface of the glass layer; a through hole including a via metal layer disposed on a wall surface of the through hole and a first insulating material disposed in at least a portion of a space between the via metal layers in the through hole; a first wiring layer disposed on the upper surface of the glass layer, at least a portion of the first wiring layer being connected to an upper side of the through hole; a second wiring layer disposed on the lower surface of the glass layer, at least a portion of the second wiring layer being connected to a lower side of the through hole; and a second insulating material covering at least a portion of an outer surface of the glass layer. The first insulating material and the second insulating material may include substantially the same material.

[0011] According to another aspect of the present disclosure, a printed circuit board may include: a through-via including a via metal layer and a first insulating material disposed in at least a portion of a space between the via metal layers; a glass layer having a first through-portion in which the through-via is disposed; a second insulating material having a second through-portion in which the through-via and the glass layer are disposed; a first wiring layer disposed on an upper surface of the glass layer, at least a portion of the first wiring layer being connected to an upper side of the through-via; a second wiring layer disposed on a lower surface of the glass layer, at least a portion of the second wiring layer being connected to a lower side of the through-via; a first insulating layer disposed on an upper surface of each of the glass layer and the second insulating material and covering at least a portion of the first wiring layer; and a second insulating layer disposed on a lower surface of each of the glass layer and the second insulating material and covering at least a portion of the second wiring layer. The first insulating material and the second insulating material may include substantially the same material.

[0012] According to another aspect of the present disclosure, a printed circuit board may include: a glass layer having a first through hole penetrating between an upper surface and a lower surface of the glass layer; a through hole including a via metal layer disposed on a wall surface of the first through hole and a first insulating material disposed in at least a portion of a space between the via metal layers in the first through hole; a first wiring layer disposed on the upper surface of the glass layer, at least a portion of the first wiring layer being connected to an upper side of the through hole; a second wiring layer disposed on the lower surface of the glass layer, at least a portion of the second wiring layer being connected to a lower side of the through hole; and a second insulating material having a second through hole in which the through hole and the glass layer are disposed and the second insulating material is in contact with the glass layer. The upper surfaces of each of the glass layer, the first insulating material, the second insulating material, and the via metal layer may be substantially coplanar with each other.

[0013] One of various effects of the present disclosure is to provide a printed circuit board capable of forming a wiring layer formed on a glass layer as a microcircuit.

[0014] Another of the various effects of the present disclosure is to provide a printed circuit board capable of simplifying the process and facilitating warpage control.

[0015] Another of the various effects of the present disclosure is to provide a printed circuit board capable of preventing damage to a glass layer and protecting an outer surface of the glass layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0017] Figure 1 is a block diagram schematically illustrating an example of an electronic device system;

[0018] Figure 2 is a perspective view schematically showing an example of an electronic device;

[0019] Figure 3 is a cross-sectional view schematically showing an example of a printed circuit board;

[0020] Figure 4 yes Figure 3 A schematic cross-sectional plan view of a printed circuit board taken along line II';

[0021] FIG. 5A to FIG. 5I is a schematic diagram showing the manufacturing Figure 3 An example process diagram of a method for printing a circuit board;

[0022] Figure 6 is a cross-sectional view schematically showing another example of a printed circuit board;

[0023] Figure 7 yes Figure 6 A schematic cross-sectional plan view of a printed circuit board taken along line II-II';

[0024] Fig. 8A and Figure 8B is a schematic diagram showing the manufacturing Figure 6 An example process diagram of a method for printing a circuit board;

[0025] Fig. 9 is a cross-sectional view schematically showing another example of a printed circuit board;

[0026] Fig. 10A and Fig. 10B is a schematic diagram showing the manufacturing Fig. 9 An example process diagram of a method for printing a circuit board;

[0027] Fig.11 is a cross-sectional view schematically showing another example of a printed circuit board; and

[0028] Fig. 12A and Fig. 12B is a schematic diagram showing the manufacturing Fig.11 An example process diagram of a method for printing a circuit board is shown. DETAILED DESCRIPTION

[0029] Hereinafter, the present disclosure will be described with reference to the accompanying drawings. In the accompanying drawings, the shapes and sizes of elements may be exaggerated or reduced for clearer description.

[0030] Electronic Devices

[0031] Figure 1 is a block diagram schematically illustrating an example of an electronic device system.

[0032] Reference Figure 1 , a main board 1010 is housed in the electronic device 1000. Chip-related components 1020, network-related components 1030, and other components 1040 are physically and / or electrically connected to the main board 1010. These components are also combined with other electronic components to be described below through various signal lines 1090.

[0033] The chip-related components 1020 may include: memory chips, such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM, flash memory), etc.; application processor chips, such as central processing units (e.g., CPU), graphics processors (e.g., GPU), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters (ADCs), application-specific ICs (ASICs), etc. However, the chip-related components 1020 are not limited thereto, and may also include other types of chip-related components. In addition, the chip-related components 1020 may be combined with each other. The chip-related components 1020 may be in the form of a package including the above-mentioned chips or electronic components.

[0034] The network-related components 1030 may include components that are compatible with or communicate according to protocols such as: Wireless Fidelity (Wi-Fi) (such as the Institute of Electrical and Electronics Engineers (IEEE) 802.11 series), Worldwide Interoperability for Microwave Access (WiMAX) (such as the IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Evolution-Data Optimized (Ev-DO), High Speed ​​Packet Access + (HSPA+), High Speed ​​Downlink Packet Access + (HSDPA+), High Speed ​​Uplink Packet Access + (HSUPA+), Global System for Mobile Communications (GSM), Enhanced Data Rates for GSM Evolution (EDGE), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Wireless Local Area Network (Wireless LAN), Bluetooth, third generation mobile communication technology (3G) protocol, fourth generation mobile communication technology (4G) protocol, fifth generation mobile communication technology (5G) protocol, and any other wireless standards or protocols and wired standards or protocols specified subsequently. However, the network-related component 1030 is not limited thereto, and may also include a component that is compatible with or communicates according to any of a variety of other wireless standards or protocols and wired standards or protocols. In addition, the network-related component 1030 may be combined with the chip-related component 1020.

[0035] Other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, other components are not limited thereto, and may also include passive components in the form of chip components for various other purposes. In addition, other components 1040 may be combined with chip-related components 1020 and / or network-related components 1030.

[0036] Depending on the type of the electronic device 1000, the electronic device 1000 may include other electronic components that are physically and / or electrically connected to the mainboard 1010 or that are not physically and / or electrically connected to the mainboard 1010. These other electronic components may include, for example, a camera 1050, an antenna 1060, a display 1070, and a battery 1080. However, these other electronic components are not limited thereto, but may also include an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (e.g., a hard disk) drive, a compact disk (CD) drive, and a digital versatile disk (DVD) drive, etc. In addition, depending on the type of the electronic device 1000, the electronic device 1000 may also include other electronic components for various purposes.

[0037] The electronic device 1000 may be a smart phone, a personal digital assistant, a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet computer, a laptop computer, a netbook, a television, a video game console, a smart watch, or an automotive component. However, the electronic device 1000 is not limited thereto, and in addition to the above-mentioned electronic devices, the electronic device 1000 may also be any other electronic device capable of processing data.

[0038] Figure 2 is a perspective view schematically showing an example of an electronic device.

[0039] Reference Figure 2 , the electronic device may be, for example, a smart phone 1100. A mainboard 1110 may be housed in the smart phone 1100, and various components 1120 may be physically and / or electrically connected to the mainboard 1110. In addition, other components (such as a camera module 1130 and / or a speaker 1140) that are physically and / or electrically connected to the mainboard 1110 or that are not physically and / or electrically connected to the mainboard 1110 may be housed in the smart phone 1100. Some of the components 1120 may be the above-mentioned chip-related components (e.g., component packages 1121), but the present disclosure is not limited thereto. The component package 1121 may be in the form of a printed circuit board on which an electronic component including active components and / or passive components is surface mounted. Alternatively, the component package 1121 may be in the form of a printed circuit board in which an electronic component including active components and / or passive components is embedded. In addition, the electronic device is not necessarily limited to the smart phone 1100, and may be other electronic devices as described above.

[0040] Printed Circuit Board

[0041] Figure 3 is a cross-sectional view schematically showing an example of a printed circuit board.

[0042] Figure 4 yes Figure 3 A schematic cross-sectional plan view of a printed circuit board taken along line II'.

[0043] Referring to the drawings, a printed circuit board 100A according to an example embodiment may include: a glass layer 111 having a through hole H penetrating between an upper surface and a lower surface thereof; a through hole 130 including a via metal layer 131 disposed on a wall surface of the through hole H and a space G between the via metal layers 131 filling the through hole H (refer to the space G to be described later). Figure 5C and Figure 5D), a first insulating material 132 covering at least a portion of the through-hole 130; a first wiring layer 121 disposed on the upper surface of the glass layer 111 and at least a portion of the first wiring layer 121 is connected to the upper side of the through-hole 130; a second wiring layer 122 disposed on the lower surface of the glass layer 111 and at least a portion of the second wiring layer 122 is connected to the lower side of the through-hole 130; a second insulating material 112 covering at least a portion of the outer surface of the glass layer 111; and a third insulating material 113 covering at least a portion of the outer surface of the second insulating material 112. In addition, the printed circuit board 100A may further include: a first insulating layer 141 disposed on the upper surface of each of the glass layer 111, the second insulating material 112, and the third insulating material 113 and covering at least a portion of the first wiring layer 121; and a second insulating layer 151 disposed on the lower surface of each of the glass layer 111, the second insulating material 112, and the third insulating material 113 and covering at least a portion of the second wiring layer 122.

[0044] The through hole H of the glass layer 111 may be a first through portion h1. The through via 130 including the via metal layer 131 and the first insulating material 132 may be disposed in the first through portion h1. Similarly, the second insulating material 112 may have a second through portion h2. The through via 130 including the via metal layer 131 and the first insulating material 132 and the glass layer 111 may be disposed in the second through portion h2, and the second insulating material 112 may be in contact with the glass layer 111. From a similar point of view, the third insulating material 113 may have a third through portion h3. The through via 130 including the via metal layer 131 and the first insulating material 132, the glass layer 111, and the second insulating material 112 may be disposed in the third through portion h3, and the third insulating material 113 may be in contact with the second insulating material 112.

[0045] The first insulating material 132 and the second insulating material 112 may include substantially the same material. For example, the first insulating material 132 and the second insulating material 112 may be formed by simultaneously performing an embedding process of the glass layer 111 and a plugging process of the through hole H using an Ajinomoto built-up film (ABF) (as exemplarily disclosed in the process described below), and may include substantially the same material. In addition, the first insulating material 132 and the second insulating material 112 may have substantially the same degree of hardening. Therefore, the process thereof may be further simplified, and further, warpage control may be more advantageous in the process. The fact that embedding and plugging are simultaneously formed with substantially the same material (such as ABF) may be confirmed by analyzing the size and dispersibility of the filler in the ABF or the degree of hardening of the resin (measured by a Fourier transform infrared spectrometer (FT-IR) or the like).

[0046] The third insulating material 113 may include a material different from the materials of the first insulating material 132 and the second insulating material 112. For example, the elastic modulus of the third insulating material 113 may be greater than the elastic modulus of the first insulating material 132 and the elastic modulus of the second insulating material 112. The elastic modulus may represent a ratio of stress to strain, and as a measurement method, for example, the elastic modulus may be measured by a standard tensile test specified in JISC-6481, KS M3001, KS M527-3, ASTM D882, etc. For example, the third insulating material 113 may include a material having excellent rigidity (such as an insulating material of a copper clad laminate (CCL), as exemplarily disclosed in the process described below). In this case, the embedding process of the glass layer 111 and the plugging process of the through hole H may be performed using the third insulating material 113 as a mold. Therefore, the glass layer may be prevented from being damaged during the process, and the outer surface of the glass layer may be protected together with the second insulating material 112.

[0047] The via metal layer 131 may include a first seed layer S1 disposed on the wall surface of the through hole H and a first metal layer M1 disposed on the side surface of the first seed layer S1. The first wiring layer 121 may include a second seed layer S2 disposed on the upper surface of the glass layer 111 and a second metal layer M2 disposed on the upper surface of the second seed layer S2. The second wiring layer 122 may include a third seed layer S3 disposed on the lower surface of the glass layer 111 and a third metal layer M3 disposed on the lower surface of the third seed layer S3. At least a portion of the first wiring layer 121 may be configured so that the second seed layer S2 covers at least a portion of the upper surface of each of the first seed layer S1, the first metal layer M1, and the first insulating material 132. At least a portion of the second wiring layer 122 may be configured so that the third seed layer S3 covers at least a portion of the lower surface of each of the first seed layer S1, the first metal layer M1, and the first insulating material 132. The first seed layer S1 may have boundaries with the second seed layer S2 and the third seed layer S3, respectively.

[0048] The upper surfaces of each of the glass layer 111, the first insulating material 132, the second insulating material 112, the first seed layer S1, and the first metal layer M1 may be substantially coplanar with each other. In addition, the upper surfaces of each of the glass layer 111, the via metal layer 131, the first insulating material 132, the second insulating material 112, and the third insulating material 113 may be substantially coplanar with each other. The lower surfaces of each of the glass layer 111, the first insulating material 132, the second insulating material 112, the first seed layer S1, and the first metal layer M1 may be substantially coplanar with each other. In addition, the lower surfaces of each of the glass layer 111, the via metal layer 131, the first insulating material 132, the second insulating material 112, and the third insulating material 113 may be substantially coplanar with each other. For example, as exemplarily disclosed in the following process, when forming the through via 130, a material for forming the through via 130 may be formed in the first through portion h1 and on the upper and lower surfaces of the glass layer 111, and then chemical mechanical polishing (CMP) is used to planarize the through via 130. In this case, a microcircuit may be formed on the glass layer by a semi-additive process (SAP) instead of a sealing process.

[0049] Therefore, the first wiring layer 121 and the second wiring layer 122 can be formed using a microcircuit. Therefore, the pads of the first wiring layer 121 and the pads of the second wiring layer 122 can be directly formed on the through vias 130 to ensure freedom in design.

[0050] Hereinafter, components of a printed circuit board 100A according to example embodiments will be described in more detail with reference to the accompanying drawings.

[0051] The glass layer 111 may include glass (an amorphous solid). The glass may include, for example, pure silicon dioxide (about 100% SiO2), soda-lime glass, borosilicate glass, and aluminosilicate glass. However, the present disclosure is not limited thereto, and optional glass materials such as fluorine glass, phosphate glass, chalcogenide glass, etc. may also be used as materials for the glass layer 111. Other additives may also be included to form glass with specific physical properties. These additives may include magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, antimony, and carbonates of these elements (e.g., calcium carbonate (e.g., lime) and sodium carbonate (e.g., soda)) and / or oxides of these elements, and optionally, these additives may also include other elements.

[0052] The glass layer 111 may be a layer different from an organic insulating material including glass fiber such as glass fabric exemplified by glass cloth, such as a copper clad laminate (CCL) and a prepreg (PPG). For example, the glass layer 111 may include flat glass. The glass layer 111 may be a core layer, and may be, for example, a glass core.

[0053] The through hole H may penetrate the glass layer 111 in the thickness direction (e.g., the stacking direction of the insulating layer and the glass layer). For example, the through hole H may penetrate between the upper surface and the lower surface of the glass layer 111. The through hole H may have one or more holes. The through hole H may be in the form of an elliptical column or a cylinder, but is not limited thereto, and may be in the form of an hourglass-shaped column, etc.

[0054] The first seed layer S1, the second seed layer S2 and the third seed layer S3 may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or alloys thereof, respectively, and may preferably include copper (Cu), but the present disclosure is not limited thereto. The first seed layer S1, the second seed layer S2 and the third seed layer S3 may be different layers having boundaries with each other. The first seed layer S1, the second seed layer S2 and the third seed layer S3 may be formed by electroless plating (e.g., chemical copper plating) and / or sputtering, respectively. The first seed layer S1 may be thinner than the first metal layer M1, the second seed layer S2 may be thinner than the second metal layer M2, and the third seed layer S3 may be thinner than the third metal layer M3. In addition, each of the first seed layer S1, the second seed layer S2 and the third seed layer S3 may be thinner than each of the first metal layer M1, the second metal layer M2 and the third metal layer M3.

[0055] The first metal layer M1, the second metal layer M2, and the third metal layer M3 may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof, respectively, and may preferably include copper (Cu), but the present disclosure is not limited thereto. Each of the first metal layer M1, the second metal layer M2, and the third metal layer M3 may be formed by electroplating (e.g., copper electroplating). The first metal layer M1 may be thicker than the first seed layer S1, the second metal layer M2 may be thicker than the second seed layer S2, and the third metal layer M3 may be thicker than the third seed layer S3.

[0056] Each of the first wiring layer 121 and the second wiring layer 122 may perform various functions according to the design. For example, the first wiring layer 121 and the second wiring layer 122 may include a signal pattern, a power pattern, and a ground pattern, and each of these patterns may have various shapes (such as a line (or trace) shape, a plane (or plate) shape, and a pad (or pad) shape). Each of the first wiring layer 121 and the second wiring layer 122 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). If necessary, the first wiring layer 121 and the second wiring layer 122 may include a sputtering layer instead of an electroless plating layer (e.g., a chemical copper plating layer), or may include both an electroless plating layer (e.g., a chemical copper plating layer) and a sputtering layer.

[0057] The via metal layer 131 may perform various functions according to the design. For example, the via metal layer 131 may include a ground via, a power via, and a signal via. The via metal layer 131 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). If necessary, the via metal layer 131 may include a sputtering layer instead of an electroless plating layer (e.g., a chemical copper plating layer), or may include both an electroless plating layer (e.g., a chemical copper plating layer) and a sputtering layer.

[0058] The first insulating material 132, the second insulating material 112, and the third insulating material 113 may include organic insulating materials that are the same as or different from each other. The organic insulating material may include a thermosetting resin (such as an epoxy resin), a thermoplastic resin (such as polyimide), or a material prepared by impregnating an inorganic filler, an organic filler, and / or a glass fiber (such as glass fabric exemplified by glass cloth) in a resin. For example, the organic insulating material may be a non-photosensitive insulating material (such as Ajinomoto built-up film (ABF), a prepreg (PPG), and a copper clad laminate (CCL)), but the present disclosure is not limited thereto, and other polymer materials may also be used as organic insulating materials. In addition, the organic insulating material may be a photosensitive insulating material (such as a photosensitive dielectric (PID)).

[0059] The first insulating layer 141 and the second insulating layer 151 may also include the above-mentioned organic insulating material. The first insulating layer 141 and the second insulating layer 151 may include substantially the same material. If necessary, the first insulating layer 141 and the second insulating layer 151 may include substantially the same material as the first insulating material 132 and the second insulating material 112. Even in this case, the first insulating layer 141 and the second insulating layer 151 may be distinguished from the first insulating material 132 and the second insulating material 112 by a boundary.

[0060] FIG. 5A to FIG. 5I is a schematic diagram showing the manufacturing Figure 3 An example process diagram of a method for printing a circuit board is shown.

[0061] Reference Figure 5A , preparing a third insulating material 113 in which a third through-portion h3 is formed. The third insulating material 113 may include a copper clad laminate (CCL) as described above, but the present disclosure is not limited thereto. The first marking pattern m1 and the second marking pattern m2 may be formed on the upper surface and the lower surface of the third insulating material 113, respectively, whereby the third through-portion h3 may be formed more accurately at a desired position. The third insulating material 113 may be a panel-level layer, and in this case, a plurality of third through-portions h3 may be formed. The third insulating material 113 may be used as a mold in a subsequent process.

[0062] Reference Figure 5B, a tape 210 is attached to the lower side of the third insulating material 113. The tape 210 may block the lower side of the third through portion h3. The tape 210 may include a known adhesive (eg, epoxy resin material), but is not limited thereto.

[0063] Reference Figure 5C , a glass layer 111 having a first through-portion h1 (or through-hole H) formed therein is prepared, and a first seed layer S1 and a first metal layer M1 are sequentially formed on the glass layer 111 by electroless plating, electrolytic plating, etc. Next, the glass layer 111 having the first through-portion h1, the first seed layer S1, and the first metal layer M1 formed therein is disposed in a third through-portion h3 of a third insulating material 113 using a tape 210. When a plurality of third through-portions h3 are formed, a plurality of glass layers 111 having the first through-portions h1, the first seed layer S1, and the first metal layer M1 formed therein may be prepared, and then the plurality of glass layers 111 may be disposed in the plurality of third through-portions h3, respectively.

[0064] Reference Figure 5D , the second insulating material 112a is laminated to perform an embedding process of the glass layer 111, and a filling process of the first through-hole h1 is performed at the same time. For example, through the lamination process, the second insulating material 112a may cover at least a portion of each of the glass layer 111 and the third insulating material 113, and may fill at least a portion of the space G located between the first metal layers M1 in the first through-hole h1.

[0065] Reference Figure 5E , after removing the tape 210, the upper and lower surfaces of each of the glass layer 111, the first seed layer S1, the first metal layer M1, the second insulating material 112a, and the third insulating material 113 are planarized by a planarization process such as chemical mechanical polishing (CMP). For example, the second insulating material 112a, the first seed layer S1, the first metal layer M1, and the first marking pattern m1 and the second marking pattern m2 disposed on the upper and lower surfaces of each of the glass layer 111 and the third insulating material 113 may be removed in the planarization process. As a result, a portion of the second insulating material 112a filled in the space G between the first metal layers M1 in the first through-portion h1 is formed as the first insulating material 132, and thus a through via 130 including the via metal layer 131 and the first insulating material 132 may be formed. A portion of the second insulating material 112a filled between the glass layer 111 and the third insulating material 113 is formed as the second insulating material 112. In addition, the second insulating material 112 may have a second through-portion h2.

[0066] Reference Fig. 5FA second seed layer S2 and a third seed layer S3 are formed on the upper surface and the lower surface of each of the planarized glass layer 111, the planarized first seed layer S1, the planarized first metal layer M1, the planarized first insulating material 132, the planarized second insulating material 112 and the planarized third insulating material 113 by electroless plating or the like.

[0067] Reference Figure 5G The second metal layer M2 and the third metal layer M3 are respectively formed on the second seed layer S2 and the third seed layer S3 by electroplating, etc. For example, a semi-additive process (SAP) may be applied, and thus, the first wiring layer 121 and the second wiring layer 122 including the microcircuit may be formed.

[0068] Reference Figure 5H A first insulating layer 141 and a second insulating layer 151 are formed on the upper surface and the lower surface of each of the glass layer 111, the second insulating material 112 and the third insulating material 113 by a lamination process to cover at least a portion of each of the first wiring layer 121 and the second wiring layer 122, respectively.

[0069] Reference Fig.5I , cutting at least a portion of each of the third insulating material 113 and the first insulating layer 141 and the second insulating layer 151. Through a series of processes, the printed circuit board 100A according to the above embodiment can be manufactured. As described above, when the third insulating material 113 is a layer at the panel level, the cutting process may include a singulation process, thereby forming a plurality of printed circuit board units.

[0070] The other contents are substantially the same as those described in the printed circuit board 100A according to the aforementioned example embodiment, and thus a repeated description thereof is omitted.

[0071] Figure 6 is a cross-sectional view schematically showing another example of a printed circuit board.

[0072] Figure 7 yes Figure 6 A schematic cross-sectional plan view of a printed circuit board taken along line II-II'.

[0073] Referring to the drawings, in a printed circuit board 100B according to another exemplary embodiment, the difference from the printed circuit board 100A according to the aforementioned exemplary embodiment is that the third insulating material 113 is omitted. For example, the second insulating material 112 may be disposed at the outermost side of the printed circuit board 100B. Therefore, the printed circuit board can be made more compact.

[0074] The other contents are substantially the same as those described in the printed circuit board 100A according to the aforementioned example embodiment, and thus a repeated description thereof is omitted.

[0075] Fig. 8A and Figure 8B is a schematic diagram showing the manufacturing Figure 6 An example process diagram of a method for printing a circuit board is shown.

[0076] Reference Fig. 8A , through the above FIG. 5A to FIG. 5H The stacked body before the cutting process is formed by a process basically the same as the process of the cutting process.

[0077] Reference Figure 8B , at least a portion of each of the third insulating material 113 and the first insulating layer 141 and the second insulating layer 151 is cut so that the third insulating material 113 does not remain on the printed circuit board 100B. Through a series of processes, the printed circuit board 100B according to the above-mentioned another exemplary embodiment can be manufactured. As described above, when the third insulating material 113 is a layer at the panel level, the cutting process may include a singulation process, thereby forming a plurality of printed circuit board units.

[0078] The other contents are substantially the same as those described in the printed circuit board 100A and the method for manufacturing the same according to the aforementioned example embodiment, and thus a repeated description thereof is omitted.

[0079] Fig. 9 is a cross-sectional view schematically illustrating another example embodiment of a printed circuit board.

[0080] Reference Fig. 9 , a printed circuit board 100C according to another exemplary embodiment is configured such that, compared with the printed circuit board 100A according to the above exemplary embodiment, the first insulating layer 141 and the second insulating layer 151 are respectively provided as a plurality of layers. In addition, the printed circuit board 100C further includes: a plurality of third wiring layers 142 provided on and / or in the plurality of first insulating layers 141; and a plurality of fourth wiring layers 152 provided on and / or in the plurality of second insulating layers 151. In addition, the printed circuit board 100C further includes: a plurality of first via layers 143 penetrating at least one of the plurality of first insulating layers 141; and a plurality of second via layers 153 penetrating at least one of the plurality of second insulating layers 151. In addition, the printed circuit board 100C also includes: a first anti-etching layer 161, which is arranged on the upper surface of the first insulating layer 141 arranged on the uppermost side among the multiple first insulating layers 141, and has a first opening 161h that exposes at least a portion of the third wiring layer 142 arranged on the uppermost side among the multiple third wiring layers 142; and a second anti-etching layer 162, which is arranged on the lower surface of the second insulating layer 151 arranged on the lowermost side among the multiple second insulating layers 151 and has a second opening 162h that exposes at least a portion of the fourth wiring layer 152 arranged on the lowermost side among the multiple fourth wiring layers 152.

[0081] Each of the plurality of third wiring layers 142 and the plurality of fourth wiring layers 152 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or their alloys. The metal may preferably include copper (Cu), but is not limited thereto. Each of the plurality of third wiring layers 142 and the plurality of fourth wiring layers 152 may perform various functions according to the design. For example, the plurality of third wiring layers 142 and the plurality of fourth wiring layers 152 may include a signal pattern, a power pattern and a ground pattern. Each of these patterns may have various shapes (such as a line shape, a plane shape and a pad shape). Each of the plurality of third wiring layers 142 and the plurality of fourth wiring layers 152 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). Alternatively, each of the plurality of third wiring layers 142 and the plurality of fourth wiring layers 152 may include a metal foil (e.g., a copper foil) and an electroplating layer (e.g., an electroplated copper layer). Alternatively, each of the plurality of third wiring layers 142 and the plurality of fourth wiring layers 152 may include a metal foil (e.g., a copper foil), an electroless plating layer (e.g., a chemical copper plating layer), and an electrolytic plating layer (e.g., an electrolytic copper plating layer). Each of the plurality of third wiring layers 142 and the plurality of fourth wiring layers 152 may include a sputtering layer instead of an electroless plating layer (e.g., a chemical copper plating layer), or may include both an electroless plating layer (e.g., a chemical copper plating layer) and a sputtering layer.

[0082] Each of the plurality of first via layers 143 and the plurality of second via layers 153 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or their alloys. The metal may preferably include copper (Cu), but is not limited thereto. Each of the plurality of first via layers 143 and the plurality of second via layers 153 may include a filled via formed by filling the via hole with a metal material, but may also include a conformal via formed by arranging a metal material along the wall surface of the via hole. The first via layer 143 and the second via layer 153 may perform various functions according to the design. For example, the first via layer 143 and the second via layer 153 may include a ground via, a power via, and a signal via. The plurality of first via layers 143 and the plurality of second via layers 153 may taper in opposite directions in cross section. Each of the plurality of first via layers 143 and the plurality of second via layers 153 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). Each of the plurality of first via layers 143 and the plurality of second via layers 153 may include a sputtering layer instead of an electroless plating layer (e.g., a chemical copper plating layer), or may include both an electroless plating layer (e.g., a chemical copper plating layer) and a sputtering layer.

[0083] The first resist layer 161 and the second resist layer 162 may include a liquid solder resist or a film solder resist, but are not limited thereto, and other types of insulating materials may be used. Surface treatment layers P1 and P2 may be formed on the pattern exposed to the first opening 161h and / or the second opening 162h as needed.

[0084] The other contents are substantially the same as those described in the printed circuit board 100A according to the aforementioned example embodiment, and thus a repeated description thereof is omitted.

[0085] Furthermore, it is understandable that Figure 3 The printed circuit board 100A and Figure 6 The printed circuit board 100B may also include at least one of the third wiring layer 142, the fourth wiring layer 152, the first via layer 143, the second via layer 153, the first resist layer 161, and the second resist layer 162 as described above.

[0086] Fig. 10A and Fig. 10B is a schematic diagram showing the manufacturing Fig. 9 An example process diagram of a method for printing a circuit board is shown.

[0087] Reference Fig. 10A , through the above FIG. 5A to FIG. 5H The stacked body before the cutting process is formed by a process basically the same as the process of the cutting process.

[0088] Reference Fig. 10B , a plurality of first insulating layers 141 and a plurality of second insulating layers 151, a plurality of third wiring layers 142 and a plurality of fourth wiring layers 152, a plurality of first via layers 143 and a plurality of second via layers 153, and a first resist layer 161 and a second resist layer 162 are formed by a buildup process. Next, at least a portion of each of the third insulating material 113, the plurality of first insulating layers 141 and the plurality of second insulating layers 151, and the first resist layer 161 and the second resist layer 162 is cut. Through a series of processes, the printed circuit board 100C according to the above-mentioned another exemplary embodiment can be manufactured. As described above, when the third insulating material 113 is a layer at the panel level, the cutting process may include a singulation process, thereby forming a plurality of printed circuit board units.

[0089] The other contents are substantially the same as those described in the printed circuit board 100A and the method for manufacturing the same according to the aforementioned example embodiment, and thus a repeated description thereof is omitted.

[0090] Fig.11 is a cross-sectional view schematically illustrating another example embodiment of a printed circuit board.

[0091] Reference Fig.11, a printed circuit board 100D according to another exemplary embodiment is configured such that the first insulating layer 141 and the second insulating layer 151 are respectively provided as a plurality of layers, compared to the printed circuit board 100B according to the above exemplary embodiment. In addition, the printed circuit board 100D further includes: a plurality of third wiring layers 142 provided on and / or in the plurality of first insulating layers 141; and a plurality of fourth wiring layers 152 provided on and / or in the plurality of second insulating layers 151. In addition, the printed circuit board 100D further includes: a plurality of first via layers 143 penetrating at least one of the plurality of first insulating layers 141; and a plurality of second via layers 153 penetrating at least one of the plurality of second insulating layers 151. In addition, the printed circuit board 100D also includes: a first resist layer 161, which is arranged on the upper surface of the first insulating layer 141 arranged on the uppermost side among the multiple first insulating layers 141 and has a first opening 161h that exposes at least a portion of the third wiring layer 142 arranged on the uppermost side among the multiple third wiring layers 142; and a second resist layer 162, which is arranged on the lower surface of the second insulating layer 151 arranged on the lowermost side among the multiple second insulating layers 151 and has a second opening 162h that exposes at least a portion of the fourth wiring layer 152 arranged on the lowermost side among the multiple fourth wiring layers 152.

[0092] The other contents are substantially the same as those described in the above-mentioned printed circuit boards 100A, 100B, and 100C, and thus a repeated description thereof will be omitted.

[0093] Fig. 12A and Fig. 12B is a schematic diagram showing the manufacturing Fig.11 An example process diagram of a method for printing a circuit board is shown.

[0094] Reference Fig. 12A , through the above FIG. 5A to FIG. 5H The stacked body before the cutting process is formed by a process basically the same as the process of the cutting process.

[0095] Reference Fig. 12B, a plurality of first insulating layers 141 and a plurality of second insulating layers 151, a plurality of third wiring layers 142 and a plurality of fourth wiring layers 152, a plurality of first via layers 143 and a plurality of second via layers 153, and a first resist layer 161 and a second resist layer 162 are formed by a buildup process. Next, at least a portion of each of the third insulating material 113, the plurality of first insulating layers 141 and the plurality of second insulating layers 151, and the first resist layer 161 and the second resist layer 162 is cut so that the third insulating material 113 does not remain on the printed circuit board 100D. Through a series of processes, the printed circuit board 100D according to the above-mentioned another exemplary embodiment can be manufactured. As described above, when the third insulating material 113 is a layer at the panel level, the cutting process may include a singulation process, thereby forming a plurality of printed circuit board units.

[0096] The other contents are substantially the same as those described in the above-mentioned printed circuit boards 100A, 100B, and 100C and the manufacturing method thereof, and thus a repeated description thereof is omitted.

[0097] In the printed circuit board according to the present disclosure, the wiring layer formed on the glass layer may be formed as a microcircuit.

[0098] The printed circuit board according to the present disclosure can simplify the process and facilitate warpage control.

[0099] The printed circuit board according to the present disclosure can prevent damage to the glass layer and protect the outer surface of the glass layer.

[0100] In the present disclosure, the depth, thickness, width, and length can be measured by a scanning microscope or an optical microscope based on a cross section obtained by polishing or cutting a printed circuit board. The cut section can be a vertical section or a horizontal section, and each numerical value can be measured based on a desired cut section. If the numerical value is not constant, the numerical value can be determined as the average value of the values ​​measured at any five random points.

[0101] In the present disclosure, the expression "covering" may include the case of covering at least a part as well as the case of covering the whole, and may include not only the case of direct covering but also the case of indirect covering. In addition, the expression "filling" may include not only the case of complete filling but also the case of approximately filling, and may include, for example, the case of the presence of some holes or gaps.

[0102] In the present disclosure, "substantially" may be a concept including process errors or positional deviations occurring in the manufacturing process and errors during measurement. For example, "substantially coplanar" may include not only a case where components exist on exactly the same plane, but also a case where components exist on substantially the same plane. In addition, "substantially the same material" may include not only a case where the composition and degree of cure of the material are exactly the same, but also a case where the composition and degree of cure of the material are substantially the same.

[0103] In the present disclosure, the meaning of "cross section" may refer to the cross-sectional shape when an object is cut vertically, or the cross-sectional shape when the object is viewed from a side perspective. In addition, the meaning of "plane" may refer to the plane shape when an object is cut horizontally, or the plane shape when the object is viewed from a top or bottom perspective.

[0104] In the present disclosure, the lower side, the lower part, and the lower surface are used to refer to the downward direction relative to the cross section of the drawings, and the upper side, the upper part, and the upper surface are used to refer to the opposite direction thereof. However, the above directions are defined for convenience of explanation, and the scope of the claims is not particularly limited by the description of such directions, and the concepts of upper and lower may be changed at any time.

[0105] In the present disclosure, the meaning of "connection" is a concept including not only direct connection but also indirect connection through an adhesive layer or the like. In addition, the meaning of "electrical connection" is a concept including physical connection and non-physical connection. In addition, expressions such as "first" and "second" are used to distinguish one component from another component and do not limit the order and / or importance of the components. In some cases, a first component may be referred to as a second component, or similarly, a second component may be referred to as a first component without departing from the scope of the claims.

[0106] The expression "exemplary embodiment" used in the present disclosure does not mean the same embodiment, and is provided to illustrate different unique features. However, the exemplary embodiments presented above do not exclude being implemented in combination with features of other exemplary embodiments. For example, even if the content described in a specific exemplary embodiment is not described in other exemplary embodiments, unless there is a description contrary to or contradictory to the content in other exemplary embodiments, the content can also be understood as a description related to other exemplary embodiments.

[0107] The terms used in the present disclosure are only used to describe example embodiments and are not intended to limit the present disclosure. In this case, unless clearly indicated as a different meaning in the context, a singular expression includes a plural expression.

[0108] While example embodiments have been shown and described above, it will be readily apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A printed circuit board, comprising: a glass layer having a through hole penetrating between an upper surface and a lower surface of the glass layer; a through via, comprising a via metal layer disposed on a wall surface of the through via and a first insulating material disposed in at least a portion of a space between the via metal layers in the through via; a first wiring layer disposed on the upper surface of the glass layer, at least a portion of the first wiring layer being connected to an upper side of the through via; a second wiring layer disposed on the lower surface of the glass layer, at least a portion of the second wiring layer being connected to a lower side of the through via; as well as a second insulating material covering at least a portion of the outer surface of the glass layer, Wherein, the first insulating material and the second insulating material comprise substantially the same material.

2. The printed circuit board according to claim 1, wherein: The glass layer includes flat glass.

3. The printed circuit board according to claim 1, wherein: The via metal layer includes a first seed layer disposed on the wall surface of the through hole and a first metal layer disposed on a side surface of the first seed layer. The first wiring layer includes a second seed layer disposed on the upper surface of the glass layer and a second metal layer disposed on the upper surface of the second seed layer, and The second wiring layer includes a third seed layer disposed on the lower surface of the glass layer and a third metal layer disposed on a lower surface of the third seed layer.

4. The printed circuit board according to claim 3, wherein: The second seed layer covers at least a portion of an upper surface of each of the first seed layer, the first metal layer, and the first insulating material, and The third seed layer covers at least a portion of a lower surface of each of the first seed layer, the first metal layer, and the first insulating material.

5. The printed circuit board according to claim 4, wherein: The first seed layer has boundaries with the second seed layer and the third seed layer, respectively.

6. The printed circuit board according to claim 4, wherein: The upper surfaces of each of the glass layer, the first insulating material, the second insulating material, the first seed layer, and the first metal layer are substantially coplanar with each other, and A lower surface of each of the glass layer, the first insulating material, the second insulating material, the first seed layer, and the first metal layer is substantially coplanar with one another.

7. The printed circuit board according to any one of claims 1 to 6, further comprising: a third insulating material covering at least a portion of an outer surface of the second insulating material, The third insulating material includes a material different from that of the first insulating material and the second insulating material.

8. The printed circuit board according to claim 7, wherein: The elastic modulus of the third insulating material is greater than the elastic modulus of the first insulating material and the elastic modulus of the second insulating material.

9. The printed circuit board according to claim 7, wherein: The upper surface of each of the glass layer, the via metal layer, the first insulating material, the second insulating material, and the third insulating material is substantially coplanar with each other, and A lower surface of each of the glass layer, the via metal layer, the first insulating material, the second insulating material, and the third insulating material is substantially coplanar with each other.

10. The printed circuit board according to any one of claims 1 to 6, further comprising: one or more first insulating layers disposed on an upper surface of each of the glass layer and the second insulating material and covering at least a portion of the first wiring layer; as well as One or more second insulating layers are disposed on a lower surface of each of the glass layer and the second insulating material and cover at least a portion of the second wiring layer.

11. The printed circuit board according to claim 10, further comprising: One or more third wiring layers, disposed on the one or more first insulating layers and / or disposed within the one or more first insulating layers; One or more first via layers, penetrating at least one first insulating layer; One or more fourth wiring layers, disposed on the one or more second insulating layers and / or disposed within the one or more second insulating layers; as well as One or more second via layers penetrate at least one second insulating layer.

12. The printed circuit board according to claim 11, further comprising: a first resist layer disposed on an upper surface of a first insulating layer disposed at an uppermost side among the one or more first insulating layers and having a first opening exposing at least a portion of a third wiring layer disposed at an uppermost side among the one or more third wiring layers; as well as The second resist layer is disposed on a lower surface of a lowermost second insulating layer among the one or more second insulating layers and has a second opening exposing at least a portion of a lowermost fourth wiring layer among the one or more fourth wiring layers.

13. A printed circuit board, comprising: a through via including a via metal layer and a first insulating material disposed in at least a portion of a space between the via metal layers; The glass layer has a first through portion, wherein the through hole is disposed in the first through portion; A second insulating material having a second through-portion, wherein the through-hole and the glass layer are disposed in the second through-portion; a first wiring layer disposed on an upper surface of the glass layer, at least a portion of the first wiring layer being connected to an upper side of the through via; a second wiring layer disposed on a lower surface of the glass layer, at least a portion of the second wiring layer being connected to a lower side of the through via; a first insulating layer disposed on an upper surface of each of the glass layer and the second insulating material and covering at least a portion of the first wiring layer; as well as a second insulating layer disposed on a lower surface of each of the glass layer and the second insulating material and covering at least a portion of the second wiring layer, Wherein, the first insulating material and the second insulating material comprise substantially the same material.

14. The printed circuit board according to claim 13, wherein: The first insulating material and the second insulating material include an Ajinomoto stacked film.

15. The printed circuit board according to claim 13 or 14, further comprising: The third insulating material has a third through-hole, and the through-hole, the glass layer and the second insulating material are arranged in the third through-hole. The third insulating material includes a material different from the first insulating material and the second insulating material.

16. The printed circuit board according to claim 15, wherein The third insulating material includes a copper clad laminate.

17. A printed circuit board comprising: a glass layer having a first through hole penetrating between an upper surface and a lower surface of the glass layer; a through via including a via metal layer disposed on a wall surface of the first through via and a first insulating material disposed in at least a portion of a space between the via metal layers in the first through via; a first wiring layer disposed on the upper surface of the glass layer, at least a portion of the first wiring layer being connected to an upper side of the through via; a second wiring layer disposed on the lower surface of the glass layer, at least a portion of the second wiring layer being connected to a lower side of the through via; as well as a second insulating material having a second through hole in which the through via and the glass layer are disposed and in contact with the glass layer, Wherein, upper surfaces of each of the glass layer, the first insulating material, the second insulating material and the via metal layer are substantially coplanar with each other.

18. The printed circuit board according to claim 17, wherein: Lower surfaces of each of the glass layer, the first insulating material, the second insulating material, and the via metal layer are substantially coplanar with each other.

19. The printed circuit board according to claim 17, wherein: The glass layer includes flat glass.

20. The printed circuit board according to claim 17, wherein The via metal layer includes a first seed layer disposed on the wall surface of the first through hole and a first metal layer disposed on a side surface of the first seed layer. The first wiring layer includes a second seed layer disposed on the upper surface of the glass layer and a second metal layer disposed on the upper surface of the second seed layer, and The second wiring layer includes a third seed layer disposed on the lower surface of the glass layer and a third metal layer disposed on a lower surface of the third seed layer.

21. The printed circuit board according to claim 20, wherein The second seed layer covers at least a portion of an upper surface of each of the first seed layer, the first metal layer, and the first insulating material, and The third seed layer covers at least a portion of a lower surface of each of the first seed layer, the first metal layer, and the first insulating material.

22. The printed circuit board according to any one of claims 17 to 21, further comprising: A third insulating material has a third through hole in which the through via, the glass layer, and the second insulating material are provided and the third insulating material is in contact with the second insulating material.

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