Superconducting quantum bit and superconducting quantum chip

Abstract

The invention provides a superconducting quantum bit and a superconducting quantum chip, the superconducting quantum bit comprises a Josephson junction and a core particle, the core particle comprises a slide glass, a deep groove capacitor and a filling dielectric layer, the deep groove capacitor is embedded in the slide glass, the filling dielectric layer covers the slide glass and the deep groove capacitor, and the deep groove capacitor is embedded in the filling dielectric layer. And the deep trench capacitor is electrically connected with the Josephson junction. According to the superconducting quantum bit and the superconducting quantum chip provided by the embodiment of the invention, the plane size of the superconducting quantum bit can be reduced, and the integration level of the superconducting quantum bit is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a superconducting quantum bit and a superconducting quantum chip. Background Art

[0002] In the field of superconducting quantum computing, superconducting quantum bits and the corresponding on-chip measurement and control elements usually have large physical sizes, posing great challenges to the large-scale integration of quantum processors.

[0003] In superconducting qubits, a bypass capacitor is usually added to suppress the noise caused by charge fluctuations, which can help significantly extend the decoherence time of the qubit. In the currently widely used Transmon / Xmon structure design, the bypass capacitor in the qubit is generally a coplanar capacitor, that is, the two plates of the capacitor are in the same plane. Coplanar capacitors require a large plane area, which is not conducive to the integration of superconducting qubits. Summary of the invention

[0004] In view of the problems in the prior art, the embodiments of the present invention provide a superconducting quantum bit and a superconducting quantum chip, which can at least partially solve the problems in the prior art.

[0005] On the one hand, an embodiment of the present invention provides a superconducting quantum bit, including a Josephson junction and a core particle, wherein:

[0006] The core particle includes a carrier, a deep trench capacitor and a filling dielectric layer, wherein the deep trench capacitor is embedded in the carrier, the filling dielectric layer covers the carrier and the deep trench capacitor, and the deep trench capacitor is electrically connected to the Josephson junction.

[0007] Furthermore, the superconducting quantum bit provided in an embodiment of the present invention also includes a transfer plate, the Josephson junction is arranged on the transfer plate, the transfer plate is bonded to the filling dielectric layer, the first electrode of the Josephson junction is electrically connected to the first conductive layer of the deep trench capacitor through a first bump and a first conductive part, and the second electrode of the Josephson junction is electrically connected to the second conductive layer of the deep trench capacitor through a second bump and a second conductive part; the first conductive part is arranged in the filling dielectric layer and connects the first bump and the first conductive layer; the second conductive part is arranged in the filling dielectric layer and connects the second bump and the second conductive layer.

[0008] Furthermore, the superconducting quantum bit provided in an embodiment of the present invention also includes a transfer plate, there are multiple core particles, the filling dielectric layer of each core particle is bonded to the transfer plate, the deep trench capacitor of each core particle corresponds to at least one Josephson junction, and each Josephson junction is arranged on the transfer plate.

[0009] Furthermore, the Josephson junction is arranged on the filling dielectric layer, the first electrode of the Josephson junction is electrically connected to the first conductive layer of the deep trench capacitor through the third conductive part, and the second electrode of the Josephson junction is electrically connected to the second conductive layer of the deep trench capacitor through the fourth conductive part; the third conductive part and the fourth conductive part are respectively arranged in the filling dielectric layer.

[0010] Furthermore, the Josephson junction is arranged on the filling dielectric layer, the first electrode of the Josephson junction is electrically connected to the second conductive layer of the deep trench capacitor through a fifth conductive part, and the second electrode of the Josephson junction is electrically connected to the first conductive layer of the deep trench capacitor through a sixth conductive part; the fifth conductive part and the sixth conductive part are arranged in the filling dielectric layer; and the deep trench capacitor is located below the second electrode.

[0011] Furthermore, the deep trench capacitor corresponds to a plurality of Josephson junctions.

[0012] Furthermore, the core particle includes a plurality of deep trench capacitors, each of which corresponds to at least one Josephson junction.

[0013] Furthermore, among the plurality of deep trench capacitors, there are deep trench capacitors with different structures.

[0014] Furthermore, the deep trench capacitor includes 2n conductive layers, and the deep trench capacitor corresponds to n Josephson junctions.

[0015] Furthermore, there are multiple Josephson junctions, and each Josephson junction is communicatively connected via a corresponding coupling structure.

[0016] On the other hand, an embodiment of the present invention provides a superconducting quantum chip, comprising the superconducting quantum bit, a packaging substrate and a PCB board according to any one of the above embodiments, wherein:

[0017] The superconducting quantum bit is arranged on the packaging substrate through a spacer column; a resonant cavity is arranged on a surface of the packaging substrate close to the superconducting quantum bit, and the resonant cavity corresponds to the Josephson junction one by one;

[0018] The PCB board is arranged at the bottom of the packaging substrate;

[0019] The Josephson junction of the superconducting quantum bit receives a control signal through a first data transmission link and outputs data through a second data transmission link, wherein the second data transmission link passes through a resonant cavity corresponding to the Josephson junction of the superconducting quantum bit.

[0020] Furthermore, there are multiple superconducting quantum bits.

[0021] Furthermore, there are superconducting qubits with different structures among the multiple superconducting qubits.

[0022] Furthermore, the first data transmission link includes a first transmission line, a first superconducting conductive part, a first superconducting coaxial bump, a second superconducting conductive part, a second transmission line and a control coaxial line which are connected in sequence; the first transmission line is coupled to the first electrode of the Josephson junction, the control coaxial line is arranged on the PCB board, the second superconducting conductive part passes through the packaging substrate, and the first superconducting conductive part passes through the adapter board or passes through the carrier and the filling medium layer.

[0023] Further, the second data transmission link includes a third transmission line, a third superconducting conductive portion, a fourth superconducting conductive portion, a fourth transmission line and a reading coaxial line, wherein:

[0024] The first end of the third transmission line is coupled to the second electrode plate of the Josephson junction, the second end of the third transmission line is connected to the first end of the third superconducting conductive portion, the second end of the third superconducting conductive portion is coupled to the resonant cavity corresponding to the Josephson junction, the resonant cavity corresponding to the Josephson junction is coupled to the first end of the fourth superconducting conductive portion, the second end of the fourth superconducting conductive portion is connected to the first end of the fourth transmission line, and the second end of the fourth transmission line is connected to the reading coaxial line;

[0025] The reading coaxial line is arranged on the PCB board, the fourth superconducting conductive part passes through the packaging substrate, and the third superconducting conductive part passes through the adapter board or passes through the carrier and the dielectric layer.

[0026] Furthermore, the resonant cavity adopts a coplanar helical structure.

[0027] The superconducting quantum bit and superconducting quantum chip provided by the embodiments of the present invention include a Josephson junction and a core particle, wherein the core particle includes a carrier, a deep trench capacitor and a dielectric layer, wherein the deep trench capacitor is embedded in the carrier, and the filling dielectric layer covers the carrier and the deep trench capacitor, wherein the deep trench capacitor is electrically connected to the Josephson junction, and the deep trench capacitor is used as a bypass capacitor, thereby reducing the planar size of the superconducting quantum bit and improving the integration of the superconducting quantum bit. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the prior art descriptions. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0029] Figure 1 It is a schematic diagram of the cross-sectional structure of a superconducting quantum bit provided in the first embodiment of the present invention.

[0030] Figure 2 It is a schematic diagram of the cross-sectional structure of a superconducting quantum bit provided in the second embodiment of the present invention.

[0031] Figure 3 It is a schematic diagram of the cross-sectional structure of a superconducting quantum bit provided in the third embodiment of the present invention.

[0032] Figure 4 It is a schematic diagram of the cross-sectional structure of a superconducting quantum bit provided in the fourth embodiment of the present invention.

[0033] Figure 5 It is a schematic diagram of the cross-sectional structure of a superconducting quantum bit provided in the fifth embodiment of the present invention.

[0034] Fig. 6A Schematic diagram of the top view of the superconducting quantum bit provided in the sixth embodiment of the present invention.

[0035] Figure 6B It is a schematic cross-sectional structure diagram of a superconducting quantum bit provided in the sixth embodiment of the present invention.

[0036] Figure 6C 2 is another schematic cross-sectional structure diagram of a superconducting quantum bit provided in the sixth embodiment of the present invention.

[0037] Figure 7 It is a schematic diagram of the cross-sectional structure of a superconducting quantum bit provided in the seventh embodiment of the present invention.

[0038] Figure 8 Schematic diagram of the cross-sectional structure of a superconducting quantum chip provided in the eighth embodiment of the present invention.

[0039] Fig. 9 Schematic diagram of the cross-sectional structure of a superconducting quantum chip provided by the ninth embodiment of the present invention. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical scheme and advantages of the embodiments of the present invention clearer, the embodiments of the present invention are further described in detail with reference to the accompanying drawings. Here, the illustrative embodiments of the present invention and their descriptions are used to explain the present invention, but are not intended to limit the present invention. It should be noted that, in the absence of conflict, the embodiments in this application and the features in the embodiments can be combined with each other arbitrarily. The acquisition, storage, use, and processing of data in the technical scheme in this application comply with the relevant provisions of laws and regulations. The user information in the embodiments of the present application is obtained through legal and compliant channels, and the acquisition, storage, use, and processing of user information are authorized and agreed by the customer.

[0041] In order to facilitate understanding of the technical solution provided by this application, the relevant contents of the technical solution of this application are first explained below.

[0042] In a typical superconducting qubit structure, the superconducting resonator consists of a meandering section of a coplanar waveguide transmission line, with both ends of the resonator terminated in an open or short-circuited manner to ground. To achieve readout multiplexing, multiple resonators are coupled to a shared feed line, with one end of each resonator close to the shared transmission line and the other end close to the readout end of the qubit. In the case of weak external coupling and high internal quality factor, the frequency of the resonator is determined by the inductance and capacitance per unit length and the total length of the resonator. Although using coplanar waveguide resonators is very simple from a design and manufacturing perspective, these resonators occupy a large area.

[0043] In the Transmon / Xmon structure design that is currently widely used, the bypass capacitor in the quantum bit is generally a coplanar capacitor, that is, the two plates of the capacitor are in the same plane. In this case, the distribution of the electric field is uneven, and the plane area occupancy rate is too large, which limits the integration density of the quantum bit to a certain extent. In the prior art, a parallel plate capacitor with a vacuum gap has also appeared as a bypass capacitor for the quantum bit. Although this technology initially transforms the capacitor into a vertical structure, the plane size of the parallel plate capacitor is still too large, and the size advantage is limited.

[0044] Therefore, the present invention proposes a new three-dimensional quantum bit, three-dimensional resonant cavity and core-grained structure based on advanced packaging technology, and replaces the capacitor structure in the planar design with a deep trench capacitor (DTC) to achieve the three-dimensionalization and core-grained transformation of the superconducting quantum bit. It breaks the area limitation in the planar design and proposes a new three-dimensional quantum bit architecture, making the superconducting quantum bit itself more compatible with the needs of core-grained integration. It is also conducive to the realization of scalable and large-scale superconducting quantum chips based on core-grained design methodology.

[0045] Taking the commonly used Transmon qubit as an example, the shunt capacitor of its high quality factor is generally realized by a large-size coplanar capacitor, and the superconducting microwave resonator used for qubit state readout is composed of millimeter-level coplanar waveguides, both of which occupy a large amount of plane area. In this application, DTC has a vertical structure with a high aspect ratio, which can be used to construct a large self-capacitance, so it can replace the coplanar capacitor required for the qubit, and is more conducive to the vertical interconnection structure of FC, TSV, etc. as a qubit, The vertical coupling node of the three-dimensional transformation of the resonant cavity. Under the guidance of this idea, the planar size of the superconducting qubit is expected to be reduced by dozens of times. When the diameter of the DTC is very small and reaches the order of hundreds of nanometers, the Josephson junction itself will limit the integration density, rather than the bypass capacitor. The pitch between qubits can be further reduced, which helps to achieve a quantum processor with a larger integration scale.

[0046] Furthermore, the novel superconducting quantum bit based on DTC proposed in the embodiment of the present invention can provide a very high capacitance value in a very small planar size. Relevant research shows that the use of DTC can save about 90% of the silicon area, greatly improving the design efficiency.

[0047] Figure 1 is a schematic cross-sectional structure diagram of a superconducting quantum bit provided by the first embodiment of the present invention, such as Figure 1 As shown, the superconducting quantum bit provided by the embodiment of the present invention includes a Josephson junction 1 and a core particle 2, wherein:

[0048] The core particle 2 includes a carrier 2-1, a deep trench capacitor 2-2 and a filling dielectric layer 2-3. The deep trench capacitor 2-2 is embedded in the carrier 2-1. The filling dielectric layer 2-3 covers the carrier 2-1 and the deep trench capacitor 2-2. The deep trench capacitor 2-2 is electrically connected to the Josephson junction 1.

[0049] Specifically, the Josephson junction 1 can be selected for Al-based, Nb-based, Ta-based and other materials, and the Josephson junction 1 and other necessary functional auxiliary structures are used to construct various types of quantum bits. The constructed quantum bits can be quantum bit types such as flux, charge, phase, Transmon, etc. The carrier 2-1 can select intrinsic silicon, epitaxially grown silicon, sapphire, silicon on insulator (SOI), quartz, germanium, silicon germanium, silicon carbide, indium phosphide, gallium arsenide, gallium nitride, crystalline quartz, sapphire, diamond and one or more ceramics. The deep trench capacitor 2-2 is a vertical capacitor structure with multiple parallel conductive layers-dielectric layers-conductive layers formed in a blind hole with a high aspect ratio. The deep trench capacitor 2-2 is used as a bypass capacitor for superconducting quantum bits. While being able to significantly extend the decoherence time of the quantum bits, it can also reduce the occupied area, thereby being able to reduce the planar size of the superconducting quantum bits. When the size of the deep trench capacitor 2-2 is very small and reaches the order of hundreds of nanometers, the Josephson junction itself, rather than the bypass capacitor, will limit the integration density. The deep trench capacitor 2 - 2 can provide a very high capacitance value at a small planar size, thereby saving silicon area.

[0050] The deep trench capacitor 2-2 is electrically connected to the Josephson junction 1. For example, Figure 1 As shown, the first conductive layer 2-2-1 of the deep trench capacitor 2-2 is electrically connected to the first plate 1-1 of the Josephson junction 1, and the second conductive layer 2-2-2 of the deep trench capacitor 2-2 is electrically connected to the second plate 1-2 of the Josephson junction 1.

[0051] The superconducting quantum bit provided by the embodiment of the present invention includes a Josephson junction and a core particle, wherein the core particle includes a carrier, a deep trench capacitor and a dielectric layer, the deep trench capacitor is embedded in the carrier, the filling dielectric layer covers the carrier and the deep trench capacitor, the deep trench capacitor is electrically connected to the Josephson junction, and the deep trench capacitor is used as a bypass capacitor, which can reduce the planar size of the superconducting quantum bit and improve the integration of the superconducting quantum bit.

[0052] Figure 2 is a schematic cross-sectional structure diagram of a superconducting quantum bit provided by the second embodiment of the present invention, such as Figure 2As shown, on the basis of the above embodiments, further, the superconducting quantum bit provided in the embodiment of the present invention also includes a transfer plate 3, the Josephson junction 1 is arranged on the transfer plate 3, the transfer plate 3 is bonded to the filling dielectric layer 2-3, the first electrode 1-1 of the Josephson junction 1 is electrically connected to the first conductive layer 2-2-1 of the deep trench capacitor 2-2 through the first bump 4 and the first conductive part 5, and the second electrode 1-2 of the Josephson junction 1 is electrically connected to the second conductive layer 2-2-2 of the deep trench capacitor 2-2 through the second bump 6 and the second conductive part 7; the first conductive part 5 is arranged in the filling dielectric layer 2-3, and connects the first bump 4 and the first conductive layer 2-2-1; the second conductive part 7 is arranged in the filling dielectric layer 2-3, and connects the second bump 6 and the second conductive layer 2-2-2.

[0053] Specifically, the adapter plate 3 can be made of intrinsic silicon, epitaxially grown silicon, sapphire, silicon on insulator (SOI), quartz, germanium, silicon germanium, silicon carbide, indium phosphide, gallium arsenide, gallium nitride, crystalline quartz, sapphire, diamond and other materials. A Josephson junction 1 is arranged on the adapter plate 3. The adapter plate 3 is bonded to the filling dielectric layer 2-3 so that the core particle 2 can be flip-chip bonded to the adapter plate 3. The adapter plate 3 can be bonded to the filling dielectric layer 2-3 through the first bump 4 and the second bump 6.

[0054] The Josephson junction 1 includes a first electrode 1-1 and a second electrode 1-2. The deep trench capacitor 2-2 includes a first conductive layer 2-2-1 and a second conductive layer 2-2-2. The first electrode 1-1 is connected to the first bump 4, the first bump 4 is connected to the first conductive part 5, and the first conductive part 5 is connected to the first conductive layer 2-2-1. The second electrode 1-2 is connected to the second bump 6, the second bump 6 is connected to the second conductive part 7, and the second conductive part 7 is connected to the second conductive layer 2-2-2. Among them, the first conductive part 5 can be obtained by punching a hole in the filling dielectric layer 2-3 and filling it with a conductive material, and the conductive material includes but is not limited to tungsten, copper, etc., and is selected according to actual needs. The structure of the second conductive part 7 is similar to that of the first conductive part 5, and will not be repeated here.

[0055] For example, Figure 2As shown, two "W"-shaped grooves for accommodating deep trench capacitors 2-2 are provided in the carrier 2-1, and each "W" groove accommodates a deep trench capacitor 2-2. The deep trench capacitor 2-2 includes a first dielectric layer 2-2-4, a first conductive layer 2-2-1, and a second dielectric layer 2-2-3 and a second conductive layer 2-2-2 stacked in sequence along the "W"-shaped groove, the first dielectric layer 2-2-4 isolates the carrier 2-1 and the first conductive layer 2-2-1, and the second dielectric layer 2-2-3 is located between the second conductive layer 2-2-2 and the first conductive layer 2-2-1. A filling dielectric layer 2-3 can be deposited on the carrier 2-1 and the deep trench capacitor 2-2, so that the filling dielectric layer 2-3 covers the carrier 2-1 and the deep trench capacitor 2-2.

[0056] Figure 3 is a schematic cross-sectional structure diagram of a superconducting quantum bit provided in the third embodiment of the present invention, such as Figure 3 As shown, on the basis of the above embodiments, further, the superconducting quantum bit provided in the embodiment of the present invention also includes a transfer plate 3, there are multiple core particles 2, the filling dielectric layer 2-3 of each core particle 2 is bonded to the transfer plate 3, the deep trench capacitor 2-2 of each core particle 2 corresponds to at least one Josephson junction 1, and each Josephson junction 1 is arranged on the transfer plate 3.

[0057] Specifically, the adapter plate 3 can carry multiple core particles 2, and the filling dielectric layer 2-3 of each core particle 2 is bonded to the adapter plate 3. The filling dielectric layer 2-3 can be bonded to the adapter plate 3 through the corresponding first bump 4 and second bump 6. The deep trench capacitor 2-2 of each core particle 2 corresponds to at least one Josephson junction 1, and the first conductive layer 2-2-1 of the deep trench capacitor 2-2 can be electrically connected to the first plate 1-1 of the Josephson junction 1 through the corresponding first conductive part 5 and the first bump 4; the second conductive layer 2-2-2 of the deep trench capacitor 2-2 can be electrically connected to the second plate 1-2 of the Josephson junction 1 through the corresponding second conductive part 7 and the second bump 6. The specific number of core particles 2 is set according to actual needs, and the embodiment of the present invention is not limited.

[0058] When the deep trench capacitor 2-2 corresponds to n Josephson junctions 1, the deep trench capacitor 2-2 may include 2n conductive layers, and every two conductive layers correspond to one Josephson junction. n is a natural number.

[0059] Figure 4 is a schematic cross-sectional structure diagram of a superconducting quantum bit provided by the fourth embodiment of the present invention, such as Figure 4As shown, on the basis of the above embodiments, further, the Josephson junction 1 is arranged on the filling dielectric layer 2-3, the first electrode 1-1 of the Josephson junction 1 is electrically connected to the first conductive layer 2-2-1 of the deep trench capacitor 2-2 through the third conductive part 8, and the second electrode 1-2 of the Josephson junction 1 is electrically connected to the second conductive layer 2-2-2 of the deep trench capacitor 2-2 through the fourth conductive part 9; the third conductive part 8 is arranged in the filling dielectric layer 2-3, and the fourth conductive part 9 is arranged in the filling dielectric layer 2-3.

[0060] Specifically, in order to reduce the size of the superconducting quantum bit, the Josephson junction 1 can be set on the filling dielectric layer 2-3. The Josephson junction 1 includes a first electrode 1-1 and a second electrode 1-2. The deep trench capacitor 2-2 includes a first conductive layer 2-2-1 and a second conductive layer 2-2-2. The third conductive part 8 connects the first electrode 1-1 and the first conductive layer 2-2-1, and the fourth conductive part 9 connects the second conductive layer 2-2-2 and the second electrode 1-2. Among them, the third conductive part 8 can be obtained by engraving a hole in the filling dielectric layer 2-3 and filling it with a conductive material. The conductive material includes but is not limited to tungsten, copper, etc., and is selected according to actual needs. The structure of the fourth conductive part 9 is similar to that of the third conductive part 8, and will not be repeated here.

[0061] Figure 5 is a schematic cross-sectional structure diagram of a superconducting quantum bit provided in the fifth embodiment of the present invention, such as Figure 5 As shown, on the basis of the above embodiments, further, the Josephson junction 1 is arranged on the filling dielectric layer 2-3, the first electrode 1-1 of the Josephson junction 1 is electrically connected to the first conductive layer 2-2-1 of the deep trench capacitor 2-2 through the fifth conductive part 10, and the second electrode 1-2 of the Josephson junction 1 is electrically connected to the second conductive layer 2-2-2 of the deep trench capacitor 2-2 through the sixth conductive part 11; the fifth conductive part 10 is arranged in the filling dielectric layer 2-3, and the sixth conductive part 11 is arranged in the filling dielectric layer 2-3; the deep trench capacitor 2-2 is located below the second electrode 1-2.

[0062] Specifically, in order to further reduce the size of the superconducting quantum bit, while the Josephson junction 1 is set on the filling dielectric layer 2-3, the deep trench capacitor 2-2 is set below the second plate 1-2 of the Josephson junction 1. The Josephson junction 1 includes a first plate 1-1 and a second plate 1-2. The deep trench capacitor 2-2 includes a first conductive layer 2-2-1 and a second conductive layer 2-2-2. The fifth conductive portion 10 connects the first plate 1-1 and the first conductive layer 2-2-1, and the sixth conductive portion 11 connects the second conductive layer 2-2-2 and the second plate 1-2. Among them, the sixth conductive portion 11 can be obtained by drilling a hole in the filling dielectric layer 2-3 and filling it with a conductive material, and the conductive material includes but is not limited to tungsten, copper, etc., which is selected according to actual needs. The fifth conductive portion 10 can be gradually realized by a multi-step photolithography and a multi-step dielectric deposition process.

[0063] For example, Figure 5 As shown, two grooves for accommodating deep trench capacitors 2-2 are provided in the carrier 2-1, and each groove accommodates a deep trench capacitor 2-2. The deep trench capacitor 2-2 includes a first dielectric layer 2-2-4, a second conductive layer 2-2-2, a first conductive layer 2-2-1, and a second dielectric layer 2-2-3 stacked in sequence along one groove, the first dielectric layer 2-2-4 isolates the carrier 2-1 and the first conductive layer 2-2-1, and the second dielectric layer 2-2-3 is located between the second conductive layer 2-2-2 and the first conductive layer 2-2-1. A filling dielectric layer 2-3 can be deposited on the carrier 2-1 and the deep trench capacitor 2-2, so that the filling dielectric layer 2-3 covers the carrier 2-1 and the deep trench capacitor 2-2.

[0064] Fig. 6A is a schematic diagram of a top view of a superconducting quantum bit provided in a sixth embodiment of the present invention, Figure 6B is a schematic cross-sectional structure diagram of a superconducting quantum bit provided by the sixth embodiment of the present invention, Figure 6C is another cross-sectional structural diagram of a superconducting quantum bit provided by the sixth embodiment of the present invention, Figure 6B yes Fig. 6A The cross-sectional view of AA in the figure, Figure 6C yes Fig. 6A The cross-sectional view of BB is as follows: Fig. 6A , Figure 6B and Figure 6C As shown, based on the above embodiments, further, the deep trench capacitor 602-2 corresponds to a plurality of Josephson junctions. The deep trench capacitor 602-2 is electrically connected to each Josephson junction.

[0065] For example, Fig. 6A , Figure 6B and Figure 6CAs shown, the superconducting quantum bit includes two Josephson junctions and a core particle 602. The core particle 602 includes a carrier 602-1, a deep trench capacitor 602-2 and a filling dielectric layer 602-3. The deep trench capacitor 602-2 is embedded in the carrier 602-1. The filling dielectric layer 602-3 covers the carrier 602-1 and the deep trench capacitor 602-2. The deep trench capacitor 602-2 corresponds to two Josephson junctions 601-1 and 601-2. The Josephson junctions 601-1 and 601-2 are electrically connected through a coupling structure 12.

[0066] The deep trench capacitor 602-2 includes a first conductive layer 602-2-1, a second conductive layer 602-2-2, a third conductive layer 602-2-3 and a fourth conductive layer 602-2-4, and a dielectric layer is arranged between the connected conductive layers. The Josephson junction 601-1 includes a first electrode plate 601-1-1 and a second electrode plate 601-1-2. The Josephson junction 601-2 includes a first electrode plate 601-2-1 and a second electrode plate 601-2-2. The seventh conductive portion 603 connects the first electrode plate 601-1-1 and the third conductive layer 602-2-3, and the eighth conductive portion 604 connects the fourth conductive layer 602-2-4 and the second electrode plate 601-1-2. The ninth conductive portion 605 connects the first electrode plate 601-2-1 and the second conductive layer 602-2-2, and the tenth conductive portion 606 connects the first conductive layer 602-2-1 and the second electrode plate 601-2-2.

[0067] The seventh conductive part 603, the eighth conductive part 604, the ninth conductive part 605 and the tenth conductive part 606 are all arranged in the filling dielectric layer 602-3. The seventh conductive part 603 can be obtained by drilling holes in the filling dielectric layer 602-3 and filling the conductive material. The eighth conductive part 604, the ninth conductive part 605 and the tenth conductive part 606 have similar structures to the seventh conductive part 603, and are not described in detail here.

[0068] like Figure 1 As shown, the core particle 2 includes a plurality of deep trench capacitors 2-2, and each deep trench capacitor 2-2 corresponds to at least one Josephson junction 1. The number of deep trench capacitors 2-2 and the number of Josephson junctions 1 are set according to actual needs, and are not limited in the embodiment of the present invention.

[0069] Figure 7 is a schematic cross-sectional structure diagram of a superconducting quantum bit provided by the seventh embodiment of the present invention, such as Figure 7 As shown, on the basis of the above embodiments, further, the plurality of deep trench capacitors 2 - 2 include deep trench capacitors with different structures.

[0070] The difference in the structure of the deep trench capacitor 2 - 2 may be the difference in the number of corresponding trenches or the difference in the number of conductive layers included, which is configured according to actual needs and is not limited in the embodiment of the present invention.

[0071] For example, Figure 7 As shown, one deep trench capacitor 2 - 2 corresponds to one trench, and another deep trench capacitor 2 - 2 corresponds to two trenches.

[0072] like Figure 2 and Figure 4 As shown, there are multiple Josephson junctions 1, and each Josephson junction 1 is connected to each other through a corresponding coupling structure 12. The coupling structure 12 includes but is not limited to a capacitive coupling structure, a resonator coupling structure, etc., which is selected according to actual needs and is not limited in the embodiment of the present invention. The specific position of the coupling structure 12 is set according to actual needs and is not limited in the embodiment of the present invention.

[0073] For example, Figure 4 As shown, the coupling structure 12 is bonded to the two Josephson junctions 1 through corresponding electrical bumps.

[0074] For example, Figure 2 As shown, the coupling structure 12 is prepared on the surface of the filling dielectric layer 2 - 3 facing the Josephson junction 1 , and can connect a first bump 4 corresponding to one Josephson junction 1 and a second bump 6 corresponding to another Josephson junction 1 .

[0075] Figure 8 is a schematic cross-sectional structure diagram of a superconducting quantum chip provided in the eighth embodiment of the present invention, Fig. 9 is a schematic cross-sectional structure diagram of a superconducting quantum chip provided by the ninth embodiment of the present invention, such as Figure 8 and Fig. 9 As shown, the superconducting quantum chip provided in an embodiment of the present invention includes the superconducting quantum bit 801, the packaging substrate 802 and the PCB board 803 described in any of the above embodiments, wherein:

[0076] The superconducting quantum bit 801 is arranged on the packaging substrate 802 through the spacer 804; a resonant cavity 805 is arranged on a surface of the packaging substrate 802 close to the superconducting quantum bit 801, and the resonant cavity 805 corresponds to the Josephson junction 801-1 one by one;

[0077] The PCB board 803 is arranged at the bottom of the packaging substrate 802;

[0078] The Josephson junction 801 - 1 of the superconducting quantum bit 801 receives a control signal through a first data transmission link 806 and outputs data through a second data transmission link 807 , and the second data transmission link 807 passes through a resonant cavity 805 corresponding to the Josephson junction 801 - 1 of the superconducting quantum bit 801 .

[0079] Specifically, the superconducting quantum bit 801 includes a Josephson junction 801-1 and a core particle 801-2, and the core particle 801-2 includes a carrier 801-2-1, a deep trench capacitor 801-2-2, and a filling dielectric layer 801-2-3. When the Josephson junction 801-1 can be arranged on the filling dielectric layer 801-2-3, the filling dielectric layer 801-2-3 is arranged on the packaging substrate 802 through a spacer column 804, and the introduction of the spacer column 804 helps to accurately define the chip spacing and improve the uniformity of the entire chip.

[0080] The superconducting quantum bit 801 may further include a transfer plate 801-3, which is disposed on a packaging substrate 802 through a spacer 804, and a Josephson junction 801-1 is disposed on the transfer plate 801-3. The packaging substrate 802 may be made of intrinsic silicon, epitaxially grown silicon, sapphire, silicon on insulator, quartz, lithium niobate, and the like.

[0081] A resonant cavity 805 is disposed on a surface of the packaging substrate 802 close to the superconducting quantum bit 801 , and the resonant cavity 805 corresponds to the Josephson junction 801 - 1 one by one; the resonant cavity 805 is used to realize data reading of the Josephson junction 801 - 1 .

[0082] The PCB board 803 is arranged at the bottom of the packaging substrate 802. A coaxial line can be arranged between the PCB board 803 and the packaging substrate 802 to transmit an external control signal, which is finally provided to the superconducting quantum bit 801, and the data from the superconducting quantum bit 801 can also be outputted externally.

[0083] The Josephson junction 801-1 of the superconducting quantum bit 801 can receive a control signal through a first data transmission link 806 and output data through a second data transmission link 807. The second data transmission link 807 passes through a resonant cavity 805 corresponding to the Josephson junction 801-1 of the superconducting quantum bit 801. The specific structures of the first data transmission link 806 and the second data transmission link 807 are described below and will not be repeated here.

[0084] A superconducting quantum chip provided by an embodiment of the present invention comprises a superconducting quantum bit, a packaging substrate and a PCB board, wherein the superconducting quantum bit is arranged on the packaging substrate through a spacer column; a resonant cavity is arranged on a surface of a side of the packaging substrate close to the superconducting quantum bit, and the resonant cavity corresponds to a Josephson junction one by one; the PCB board is arranged at the bottom of the packaging substrate; the Josephson junction of the superconducting quantum bit receives a control signal through a first data transmission link, and outputs data through a second data transmission link, and the second data transmission link passes through the resonant cavity corresponding to the Josephson junction of the superconducting quantum bit, so as to reduce the planar size of the superconducting quantum chip and improve the integration of the superconducting quantum chip.

[0085] On the basis of the above embodiments, there are multiple superconducting quantum bits 801. Each superconducting quantum bit 801 is fixed on the packaging substrate 802 through a corresponding spacer 804.

[0086] On the basis of the above embodiments, further, the plurality of superconducting qubits 801 include superconducting qubits with different structures.

[0087] For example, the plurality of superconducting qubits 801 include superconducting qubits including the adapter plate 801 - 3 and superconducting qubits not including the adapter plate 801 - 3. The plurality of superconducting qubits 801 include qubit implementations of different physical structures including Transmon, Xmon, charge, flux, phase, etc.

[0088] For example, the plurality of superconducting qubits 801 include superconducting qubits 801 having different deep trench capacitor structures.

[0089] like Figure 8 and Fig. 9 As shown, the first data transmission link 806 includes a first transmission line 806-1, a first superconducting conductive part 806-2, a first superconducting coaxial bump 806-3, a second superconducting conductive part 806-4, a second transmission line 806-5 and a control coaxial line 806-6 which are connected in sequence; the first transmission line 806-1 is coupled to the first electrode 801-1-1 of the Josephson junction 801-1, the control coaxial line 806-6 is arranged on the PCB board 803, the second superconducting conductive part 806-4 passes through the packaging substrate 802, and the first superconducting conductive part 806-2 passes through the adapter board 801-3 or passes through the carrier 801-2-1 and the filling medium layer 801-2-3.

[0090] Specifically, the external control signal is transmitted to the first plate 801-1-1 of the Josephson junction 801-1 through the control coaxial line 806-6, the second transmission line 806-5, the second superconducting conductive part 806-4, the first superconducting coaxial bump 806-3, the first superconducting conductive part 806-2 and the first transmission line 806-1 in sequence. The first transmission line 806-1 is coupled to the first plate 801-1-1 of the Josephson junction 801-1. The second superconducting conductive part 806-4 can be obtained by drilling a hole on the packaging substrate 802 and filling it with superconducting metal. When the Josephson junction 1 is set on the adapter plate 801-3, the first superconducting conductive part 806-2 can be obtained by drilling a hole on the adapter plate 801-3 and filling it with superconducting metal-dielectric layer-superconducting metal-dielectric layer by superconducting coaxial silicon through via (TSV) filling technology. When the Josephson junction 1 is arranged on the filling dielectric layer 801-2-3, the first superconducting conductive portion 806-2 can be obtained by filling the through hole penetrating the carrier 801-2-1 and the filling dielectric layer 801-2-3 with superconducting metal-dielectric layer-superconducting metal-dielectric layer through the superconducting coaxial TSV preparation technology. The superconducting metal includes but is not limited to aluminum, niobium, titanium nitride, etc., which can be selected according to actual needs and is not limited in the embodiment of the present invention.

[0091] like Figure 8 and Fig. 9 As shown, the second data transmission link 807 includes a third transmission line 807-1, a third superconducting conductive portion 807-2, a fourth superconducting conductive portion 807-3, a fourth transmission line 807-4 and a reading coaxial line 807-5, wherein:

[0092] A first end of the third transmission line 807-1 is coupled to the second electrode 801-1-2 of the Josephson junction 801-1, a second end of the third transmission line 807-1 is connected to a first end of the third superconducting conductive portion 807-2, a second end of the third superconducting conductive portion 807-2 is coupled to a resonant cavity 805 corresponding to the Josephson junction 801-1, a resonant cavity 805 corresponding to the Josephson junction 801-1 is coupled to a first end of a fourth superconducting conductive portion 807-3, a second end of the fourth superconducting conductive portion 807-3 is connected to a first end of a fourth transmission line 807-4, and a second end of the fourth transmission line 807-4 is connected to a reading coaxial line 807-5;

[0093] The reading coaxial line 807-5 is arranged on the PCB board 803, the fourth superconducting conductive part fourth transmission line 807-4 passes through the packaging substrate 802, and the third superconducting conductive part 807-2 passes through the adapter board 801-3 or passes through the carrier 801-2-1 and the filling medium layer 801-2-3.

[0094] If the package substrate 802 is made of semiconductor materials such as silicon, a dielectric region needs to be provided between the resonant cavity 805 corresponding to the Josephson junction 801-1 and the first end of the fourth superconducting conductive portion 807-3 to achieve coupling connection between the resonant cavity 805 and the first end of the fourth superconducting conductive portion 807-3. The resonant cavity 805 and the first end of the fourth superconducting conductive portion 807-3 can be capacitively coupled. The second end of the third superconducting conductive portion 807-2 and the resonant cavity 805 can be capacitively coupled. When the Josephson junction 1 is provided on the adapter plate 801-3, the third superconducting conductive portion 807-2 can be obtained by drilling a through hole on the adapter plate 801-3 and filling the superconducting metal-dielectric layer-superconducting metal-dielectric layer. When the Josephson junction 1 is disposed on the filling dielectric layer 801-2-3, the third superconducting conductive portion 807-2 can be obtained by filling a superconducting metal-dielectric layer-superconducting metal-dielectric layer in a through hole penetrating the carrier 801-2-1 and the filling dielectric layer 801-2-3.

[0095] On the basis of the above embodiments, further, the resonant cavity 805 adopts a coplanar helical structure.

[0096] Specifically, the coplanar resonant cavity based on the meandering transmission line in the prior art can be transformed into a resonant cavity 805 based on the coplanar helical line, and the performance of the resonant cavity 805 is determined by the inner diameter, outer diameter, helical line pitch p, etc. of the helical line. Compared with the coplanar resonant cavity based on the meandering transmission line in the prior art, the resonant cavity 805 in the embodiment of the present invention can significantly reduce the size of the resonant cavity, which is conducive to improving the integration of the superconducting quantum chip.

[0097] It should be noted that all inter-chip interconnections allow the use of solder bumps, stud bumps, etc. The adapter board can be silicon-based, glass-based, etc., and each conductive part can be made using through silicon via technology (TSV), through glass via technology (TGV), molded through via technology (TMV), etc.

[0098] In the process of three-dimensional transformation of superconducting quantum bits, this application directly introduces a three-dimensional structure based on DTC inside the core quantum components, which makes it have significant advantages in three-dimensional integration process compatibility and modular assembly, and is more conducive to the physical realization of the core particle architecture. Through the screening of known good core particles (KGC), the high yield of the core particles used in the system integration stage can be guaranteed, thereby solving the problem that the overall yield of superconducting quantum bits and superconducting quantum chips decreases rapidly as the integration scale increases.

[0099] The core particle bonding and core particle-adapter board package bonding steps can be completed in one bonding process after placement, shortening the process steps and reducing the adverse effects of repeated heating and cooling processes on the Josephson junction. The package substrate allows multiple adapter boards to be mounted, and different types of quantum bit core particles can be mounted between different adapter boards, which greatly improves the large-scale scalability of the system while ensuring the yield rate, and helps to provide a more convenient test platform for the horizontal comparison of the performance of different types of quantum bits.

[0100] The superconducting quantum bit and superconducting quantum chip provided by the embodiments of the present invention have the following advantages:

[0101] (1) The physical size of components is significantly reduced and the integration density is significantly increased. The vertical structure with a high aspect ratio can be used to construct a DTC structure with a small footprint and a large capacitance value, so it can replace the large-size coplanar capacitors required for quantum bits. At the same time, it is more conducive to the vertical interconnection structure of FC, TSV, etc. as the vertical coupling node after the three-dimensional transformation of quantum bits and resonant cavities.

[0102] (2) For new DTC-based bits, DTC can provide very high capacitance values ​​in a very small planar size, greatly improving design efficiency and flexibility.

[0103] (3) The three-dimensional transformation process directly introduces a three-dimensional interconnection structure into the core quantum components, which gives them significant advantages in three-dimensional integration process compatibility and modular assembly, and is more conducive to the physical realization of the core particle architecture.

[0104] (4) A complete multi-chip integrated packaging architecture was designed, taking into account the comprehensive needs of superconducting quantum chips such as cost control, decoherence suppression, and electrical signal transmission links.

[0105] (5) By screening known good core particles, the high yield of the core particles used in the system integration stage can be guaranteed, thereby solving the problem that the overall yield of superconducting quantum processors decreases rapidly as the integration scale increases.

[0106] (6) When manufacturing superconducting quantum bits, the core particle bonding and the core particle-adapter plate package bonding steps can be completed as a whole through a one-time bonding process after placement, shortening the process steps and reducing the adverse effects of repeated heating and cooling processes on the Josephson junction.

[0107] (7) The packaging substrate allows the installation of multiple adapter plates, and different types of quantum bit cores can be installed between different adapter plates. This greatly improves the large-scale scalability of the system while ensuring the yield rate. At the same time, it helps to provide a convenient testing platform for the horizontal comparison of the performance of different types of quantum bits.

[0108] In the description of this specification, the description with reference to the terms "one embodiment", "a specific embodiment", "some embodiments", "for example", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0109] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A superconducting quantum bit, characterized in that: It includes Josephson junctions and core particles, where: The core particle includes a carrier, a deep trench capacitor and a filling dielectric layer, wherein the deep trench capacitor is embedded in the carrier, the filling dielectric layer covers the carrier and the deep trench capacitor, and the deep trench capacitor is electrically connected to the Josephson junction.

2. The superconducting quantum bit according to claim 1, characterized in that: It also includes a transfer plate, the Josephson junction is arranged on the transfer plate, the transfer plate is bonded to the filling dielectric layer, the first electrode of the Josephson junction is electrically connected to the first conductive layer of the deep trench capacitor through a first bump and a first conductive part, and the second electrode of the Josephson junction is electrically connected to the second conductive layer of the deep trench capacitor through a second bump and a second conductive part; the first conductive part is arranged in the filling dielectric layer and connects the first bump and the first conductive layer; the second conductive part is arranged in the filling dielectric layer and connects the second bump and the second conductive layer.

3. The superconducting quantum bit according to claim 1, characterized in that: It also includes a transfer board, there are multiple core particles, the filling dielectric layer of each core particle is bonded to the transfer board, the deep trench capacitor of each core particle corresponds to at least one Josephson junction, and each Josephson junction is arranged on the transfer board.

4. The superconducting quantum bit according to claim 1, characterized in that: The Josephson junction is arranged on the filling dielectric layer, the first electrode of the Josephson junction is electrically connected to the first conductive layer of the deep trench capacitor through the third conductive part, and the second electrode of the Josephson junction is electrically connected to the second conductive layer of the deep trench capacitor through the fourth conductive part; the third conductive part and the fourth conductive part are respectively arranged in the filling dielectric layer.

5. The superconducting quantum bit according to claim 1, characterized in that: The Josephson junction is arranged on the filling dielectric layer, the first electrode of the Josephson junction is electrically connected to the second conductive layer of the deep trench capacitor through the fifth conductive part, and the second electrode of the Josephson junction is electrically connected to the first conductive layer of the deep trench capacitor through the sixth conductive part; the fifth conductive part and the sixth conductive part are arranged in the filling dielectric layer; the deep trench capacitor is located below the second electrode.

6. The superconducting quantum bit according to claim 1, characterized in that: The deep trench capacitor corresponds to a plurality of Josephson junctions.

7. The superconducting quantum bit according to claim 1, characterized in that: The core particle includes a plurality of deep trench capacitors, each deep trench capacitor corresponding to at least one Josephson junction.

8. The superconducting quantum bit according to claim 7, characterized in that: Among the plurality of deep trench capacitors, there are deep trench capacitors with different structures.

9. The superconducting quantum bit according to claim 1, characterized in that: The deep trench capacitor includes 2n conductive layers, and the deep trench capacitor corresponds to n Josephson junctions.

10. The superconducting quantum bit according to any one of claims 1 to 9, characterized in that: There are multiple Josephson junctions, and each Josephson junction is communicatively connected via a corresponding coupling structure.

11. A superconducting quantum chip, characterized in that: The method comprises the superconducting quantum bit, the packaging substrate and the PCB board according to any one of claims 1 to 10, wherein: The superconducting quantum bit is arranged on the packaging substrate through a spacer column; a resonant cavity is arranged on a surface of the packaging substrate close to the superconducting quantum bit, and the resonant cavity corresponds to the Josephson junction one by one; The PCB board is arranged at the bottom of the packaging substrate; The Josephson junction of the superconducting quantum bit receives a control signal through a first data transmission link and outputs data through a second data transmission link, wherein the second data transmission link passes through a resonant cavity corresponding to the Josephson junction of the superconducting quantum bit.

12. The superconducting quantum chip according to claim 11, characterized in that: There are multiple superconducting quantum bits.

13. The superconducting quantum chip according to claim 12, characterized in that: Among the plurality of superconducting qubits, there are superconducting qubits with different structures.

14. The superconducting quantum chip according to claim 11, characterized in that: The first data transmission link includes a first transmission line, a first superconducting conductive part, a first superconducting coaxial bump, a second superconducting conductive part, a second transmission line and a control coaxial line connected in sequence; the first transmission line is coupled to the first electrode of the Josephson junction, the control coaxial line is arranged on the PCB board, the second superconducting conductive part passes through the packaging substrate, and the first superconducting conductive part passes through the adapter board or passes through the carrier and the filling medium layer.

15. The superconducting quantum chip according to claim 11, characterized in that: The second data transmission link comprises a third transmission line, a third superconducting conductive portion, a fourth superconducting conductive portion, a fourth transmission line and a reading coaxial line, wherein: The first end of the third transmission line is coupled to the second electrode plate of the Josephson junction, the second end of the third transmission line is connected to the first end of the third superconducting conductive portion, the second end of the third superconducting conductive portion is coupled to the resonant cavity corresponding to the Josephson junction, the resonant cavity corresponding to the Josephson junction is coupled to the first end of the fourth superconducting conductive portion, the second end of the fourth superconducting conductive portion is connected to the first end of the fourth transmission line, and the second end of the fourth transmission line is connected to the reading coaxial line; The reading coaxial line is arranged on the PCB board, the fourth superconducting conductive part passes through the packaging substrate, and the third superconducting conductive part passes through the adapter board or passes through the carrier and the dielectric layer.

16. The superconducting quantum chip according to any one of claims 11 to 15, characterized in that: The resonant cavity adopts a coplanar helical structure.

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