Dynamic clock and voltage scaling (DCVS) look-ahead bandwidth voting using feed-forward compression ratio

Abstract

In a computing device having a pipeline of image processing components, DCVS bandwidth voting may be based on a feed-forward compression ratio determined by the first image processing component in the pipeline. The DCVS bandwidth voting may be based on the comparison of a change in the feed-forward compression ratio to a threshold. Transaction launcher components in the pipeline may select their votes for bandwidth from a value based on a feed-forward compression ratio and one or more other values based on the comparison to the threshold. DCVS parameters may be selected based on a bandwidth vote received from a transactional launcher component.

Description

Technical Field

[0001] The following relates generally to computing devices and components thereof, and more particularly to dynamic clock and voltage scaling ("DCVS") bandwidth voting in such devices.

[0002] Related technical description

[0003] A computing device may include multiple subsystems, cores, or other components. Such a computing device may be, for example, a portable computing device ("PCD") such as a laptop or palmtop computer, a cellular or smart phone, a portable digital assistant, a portable game console, or the like.

[0004] Multiple subsystems, cores, or other components of a computing device may be included within the same integrated circuit chip or in different chips. A "system on a chip" or "SoC" is an example of a chip that integrates numerous components to provide system-level functionality. For example, a SoC may include one or more types of processors, such as a central processing unit ("CPU"), a graphics processing unit ("GPU"), a digital signal processor ("DSP"), and a neural processing unit ("NPU"). A SoC may include other processing subsystems, such as a transceiver or "modem" subsystem that provides wireless connectivity, a memory subsystem, and the like.

[0005] Power management is an important consideration when a PCD is battery powered. "Power management" refers to techniques used to balance power consumption and performance in a PCD and to manage thermal energy (i.e., heat) generation. Dynamic clock and voltage scaling ("DCVS") is a technique that dynamically adjusts the frequency and voltage at which a processor or processing subsystem operates (i.e., in real time in response to changes in operating conditions) to provide a desired balance or tradeoff between power consumption and performance levels. When lower power consumption has a higher priority than higher performance, the DCVS level (i.e., clock frequency and voltage) can be reduced, and when higher performance has a higher priority than lower power consumption, the DCVS level can be increased. The DCVS level can be selected using a voting scheme in which components can submit votes on the amount of bandwidth they estimate they will need to achieve a performance level that supports the use case in which the component will subsequently operate.

[0006] At the beginning of a multimedia use case (such as capturing a video image), a processing component or subsystem (such as a camera or image capture and processing subsystem, a video subsystem, a display subsystem, or a GPU) may submit a vote for a worst-case bandwidth estimate because the content of the incoming image is initially unknown. Bandwidth requirements may vary depending on the content. For example, while a processing system may require very little bandwidth to compress or decompress solid colors, a processing system may require a large amount of bandwidth to attempt to compress or decompress a high-noise image. Image resolution is also a factor in compression. For the same image, a lower resolution may achieve a lower compression ratio than a higher resolution. It may also be noted that while solid colors are highly compressible, i.e., very high compression ratios can be achieved, higher-noise images are relatively incompressible, i.e., only low compression ratios can be achieved. In addition, at times during multimedia use cases other than the beginning of image capture, image content may change dramatically from the previous frame to the current frame. When a component determines a new bandwidth requirement and submits a vote accordingly, the corresponding DCVS level change takes a finite amount of time. "Look-ahead" voting, in which the bandwidth estimate required to process the next frame is based on the results of processing one or more previous frames, may be employed to try to reduce this delay. However, it is desirable to further reduce the delay between a change in image content (or the start of a multimedia use case) and a change in the DCVS level. Summary of the invention

[0007] Systems, methods, computer-readable media, and other examples for DCVS bandwidth voting are disclosed.

[0008] An exemplary system for DCVS bandwidth voting may include a bandwidth voting aggregator and multiple image processing components coupled together in a pipeline. A first image processing component in the pipeline may be configured to determine a feedforward compression ratio based on a current frame of an image. The multiple image processing components may include multiple transaction initiator components. One or more transaction initiator components may be configured to determine a change in the feedforward compression ratio from a previous frame to a current frame, and to compare the change in the feedforward compression ratio with a threshold, and to select a bandwidth vote from a value based on the feedforward compression ratio and one or more other values ​​based on the comparison result. The bandwidth voting aggregator may be configured to determine a DCVS level based on multiple bandwidth votes received from the multiple transaction initiator components.

[0009] An exemplary method for DCVS bandwidth voting may include determining a feed-forward compression ratio based on a current frame of an image. A first image processing component in a pipeline including a plurality of image processing components may perform this determination of the feed-forward compression ratio. The exemplary method may also include determining a change in the feed-forward compression ratio from a previous frame to the current frame. The exemplary method may also include comparing the change in the feed-forward compression ratio with a threshold. A transaction initiator component in a plurality of transaction initiator components in the pipeline may perform this determination of the change in the feed-forward compression ratio and the comparison of the change with the threshold. The exemplary method may further include selecting a bandwidth vote from a value based on the feed-forward compression ratio and one or more other values ​​based on a comparison of the change in the feed-forward compression ratio with the threshold. The transaction initiator component may perform this bandwidth vote selection. The exemplary method may further include determining a DCVS level based on a plurality of bandwidth votes received from the plurality of transaction initiator components. A bandwidth vote aggregator may perform this determination of the DCVS level.

[0010] Another exemplary system for DCVS bandwidth voting may include means for determining a feedforward compression ratio based on a current frame of an image. The exemplary system may also include means for determining a change in the feedforward compression ratio from a previous frame to the current frame. The exemplary system may also include means for comparing the change in the feedforward compression ratio with a threshold. The exemplary system may further include means for selecting a bandwidth vote from a value based on the feedforward compression ratio and one or more other values ​​based on a comparison of the change in the feedforward compression ratio with the threshold. The exemplary system may further include means for determining a DCVS level based on a plurality of bandwidth votes received from a plurality of transaction initiator components.

[0011] An exemplary computer-readable medium for DCVS bandwidth voting may be provided. The computer-readable medium may include a non-transitory computer-readable medium having instructions stored thereon in a computer-executable form. These instructions, when executed by a processing system of a computing device, may configure the processing system to control the following operations. These instructions may configure the processing system to control determining a feedforward compression ratio based on a current frame of an image. These instructions may also configure the processing system to control determining a change in the feedforward compression ratio from a previous frame to the current frame. These instructions may also configure the processing system to control comparing the change in the feedforward compression ratio with a threshold. These instructions may further configure the processing system to control selecting a bandwidth vote from a value based on the feedforward compression ratio and one or more other values ​​based on the comparison result of the change in the feedforward compression ratio with the threshold. These instructions may further configure the processing system to control determining a DCVS level based on multiple bandwidth votes received from multiple transaction initiator components. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In the drawings, like reference numerals refer to like parts throughout the various views unless otherwise indicated. For reference numerals with letter character designations, such as "102A" or "102B," the letter character designations may distinguish between two similar parts or elements in the same figure. The letter character designations of reference numerals may be omitted when it is intended that a reference numeral encompass all parts having the same reference numeral in all figures.

[0013] Figure 1A is a block diagram illustrating a system for DCVS bandwidth voting according to an exemplary embodiment.

[0014] Figure 1B is another block diagram illustrating a system for DCVS bandwidth voting according to an exemplary embodiment.

[0015] Figure 2 is a conceptual logic diagram illustrating the selection of a bandwidth voting type based selection algorithm.

[0016] Figure 3 is a flow chart illustrating a method for DCVS bandwidth voting.

[0017] Figure 4 is a signal diagram illustrating the operation of the DCVS bandwidth voting method on an input image signal.

[0018] Figure 5 is a block diagram of a computing device according to an exemplary embodiment. DETAILED DESCRIPTION

[0019] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." The word "exemplary" may be used herein synonymously with "exemplary." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0020] like Figure 1A As shown in , system 100 may include an image sensor 102, a sensor interface 104, and an image processor 106 in a pipeline arrangement of image processing components. System 100 may also include a graphics processing unit (“GPU”) 108, a video subsystem 110, and a display subsystem 112. In the pipeline arrangement of image processing components: an input of sensor interface 104 may be coupled to an output of image sensor 102; an input of image processor 106 may be coupled to an output of sensor interface 104; and an input of each of GPU 108, video subsystem 110, and display subsystem 112 may be coupled to an output of image processor 106.

[0021] System 100 may also include system cache 116, memory controller 118, and system memory 120. In a pipeline arrangement of image processing components, system cache 116 may be configured in some operating modes (e.g., operating modes that stream captured image data to memory) to receive image data from any of GPU 108, video subsystem 110, and display subsystem 112. In such operating modes, system memory 120 may be configured to receive image data from system cache 116 via memory controller 118.

[0022] The sensor interface 104 may be configured to receive image data in the form of a frame stream representing the captured image from the image sensor 102. The sensor interface 104 may be configured to perform image preprocessing, such as, for example, compressing the image, correcting exposure, focusing, white balance, etc. The image processor 106 may be configured to receive the data processed by the sensor interface 104 and perform further processing, such as, for example, image scaling. The GPU 108 may be configured to receive the data processed by the image processor 106 and perform yet another other image processing. The video subsystem 110, which may include a codec, may be configured to receive the data processed by the image processor 106 and perform further data compression. The display subsystem 112 may be configured to receive the data processed by the image processor 106 and display the results (such as preview frames) for the user to view. This data flow direction from the sensor interface 104 through the image processor 106 and then through one or more of the GPU 108, the video subsystem 110, and the display subsystem 112 may be referred to as "downstream". According to this terminology, the location of, for example, image processor 106 may be described as downstream of sensor interface 104 in the pipeline. Similarly, the location of, for example, GPU 108 may be described as downstream of image processor 106 in the pipeline. However, in other operating modes, any of GPU 108, video subsystem 110, and display subsystem 112 may be configured to operate on data processed by further downstream components. In such operating modes, data may flow upstream.

[0023] Sensor interface 104, image processor 106, GPU 108, video subsystem 110, and display subsystem 112 may be referred to as transaction initiator components because they may initiate memory transactions with system memory 120 (e.g., via memory controller 118, system cache 116, etc.). Other transaction initiator components such as a central processing unit ("CPU") may also be included, but are not shown for clarity. Instead, only examples of transaction initiator components that are image processing components (such as GPU 108, video subsystem 110, and display subsystem 112) and that may be configured in a pipeline are shown in the illustrated embodiment. System memory 120, memory controller 118, and system cache 116 may be referred to as "shared components" because their use may be shared between transaction initiator components.

[0024] System 100 may include power management circuitry, such as a power management integrated circuit or "PMIC" 122. PMIC 122 may be configured to provide a selected supply voltage level to the transaction initiator and shared components, as indicated by the dashed arrows. A clock signal having a selected frequency may be provided to the transaction initiator component and the shared components through associated clock signal distribution circuitry. As will be appreciated by one of ordinary skill in the art, PMIC 122 and associated circuitry may implement dynamic clock and voltage scaling ("DCVS"). In response to a request indicating a requested or selected supply voltage and a requested or selected clock frequency, PMIC 122 may provide a selected level of supply voltage and a selected frequency of clock signals to the transaction initiator component and the shared components.

[0025] The system 100 may include a bandwidth ("BW") voting aggregator 124. As described below, the BW voting aggregator 124 may be configured to obtain BW votes provided by one or more of the sensor interface 104, the image processor 106, the GPU 108, the video subsystem 110, and the display subsystem 112 (which are transaction initiator components in the illustrated example). The BW vote represents the amount of bandwidth requested by the transaction initiator component (e.g., in gigabytes per second). The BW voting aggregator 124 may be configured to aggregate the BW votes, and based on the results of the aggregation operation, at least one DCVS level may be selected. The DCVS level represents or corresponds to the BW level, which is expressed as a combination of a power supply voltage level and a clock frequency. As understood by those of ordinary skill in the art, the aggregation operation may be implemented using, for example, a lookup table (not shown). The sensor interface 104, the image processor 106, the GPU 108, the video subsystem 110, and the display subsystem 112 may each provide a BW vote for each of the shared components. The BW voting aggregator 124 may select a DCVS level for each of the shared components and the transaction initiator components based on the BW voting and provide indications of these selected DCVS levels to the PMIC 122 .

[0026] When capturing video images, a stream or succession of image frames may be processed. The sensor interface 104 may be configured to compress each successive image frame in the stream received from the image sensor 102. The sensor interface 104 may compress each image frame according to a compression ratio ("CR"). As will be appreciated by those of ordinary skill in the art, the CR may be related to the image content. For example, an image with noise characteristics may be less compressible (i.e., able to achieve a lower CR) than an image with less noise characteristics. For example, an image consisting of one or only a few pure color areas may be highly compressible (i.e., able to achieve a high CR). In addition, an image captured at a lower resolution may be less compressible than the same image captured at a higher resolution. The CR achieved by the sensor interface 104 may therefore vary frame by frame. The sensor interface 104 may provide an indication to the image processor 106 of the CR that the sensor interface 104 is able to achieve on the frame before the image processor 106 sequentially receives the current frame. This CR that the sensor interface 104 is able to achieve on the current frame may be referred to herein as a "feedforward CR". The image processor 106 may in turn propagate this feed-forward CR to image processing components further downstream in the processing pipeline, such as the GPU 108, the video subsystem 110, and the display subsystem 112. Some or all (but at least one) of the transaction initiator components may be configured to calculate a change in the feed-forward CR from a previous frame to a current frame. In some examples, the calculated change in the feed-forward CR may be propagated to image processing components further downstream in the processing pipeline. Each of the transaction initiator components may be configured to determine a change in the feed-forward CR from a previous frame to a current frame by calculating the change directly from the feed-forward CRs of the previous frame and the current frame or by receiving the change calculated by an upstream transaction initiator component.

[0027] like Figure 1B As shown in , in some examples, the transaction initiator components can be functionally coupled in a pipeline arrangement in addition to being physically interconnected via an on-chip network ("NoC") 114 or other data interconnect. That is, the sensor interface 104, the image processor 106, the GPU 108, the video subsystem 110, and the display subsystem 112 can each be connected to the NoC 114, which enables bidirectional data communication between any of them. As understood by those of ordinary skill in the art, the NoC 114 can be an active interconnection of a matrix or one or more data communication buses similar to one or more data communication buses. However, in other embodiments (not shown), a direct data communication bus may be alternatively employed. The NoC 114 is another shared component, and the power supply voltage and clock frequency can be provided by the PMIC 122 in the same manner as described above for other shared components.

[0028] In operation, system 100 may dynamically configure itself (e.g., by executing software) to the Figure 1A 104 is a processing pipeline of the type described. For example, the system 100 may dynamically (i.e., in operation) configure the output of the sensor interface 104 to be functionally coupled to the input of the image processor 106, configure the output of the image processor 106 to be functionally coupled to the input of the GPU 108 or the video subsystem 110 or the display subsystem 112, etc. In some examples, the coupling between components in the pipeline may be static (e.g., hardwired), while in other examples, the coupling may be dynamic (e.g., via an interconnect such as the NoC 114), and in yet other examples, some components may be statically coupled and other components dynamically coupled. Unless otherwise stated with respect to a particular example, the term "coupling" as used herein encompasses all such configurations. In addition, although the data flow may be functionally pipelined between two components, the data may be physically routed through one or more intermediate components, which may include not only the NoC 114, but also the system memory 120 or other memory, such as the cache 116.

[0029] The data may be stored in compressed form in the system memory 120. Each image processing component in the pipeline (e.g., the sensor interface 104, the image processor 106, the GPU 108, the video subsystem 110, or the display subsystem 112) may include data compression and decompression logic. With the exception of the sensor interface 104, which may receive its input data directly from the sensor 102, the image processing component may read its input data from the system memory 120 and decompress the data. The image processing component may perform processing on the decompressed data, compress the resulting processed data, and store the processed and compressed data in the system memory 120. Such compressed data stored in the system 120 may form input data for the next (i.e., downstream) image processing component in the pipeline,

[0030] In some examples, there may be two or more memories 120A-120N, and there may be two or more memory controllers 118A-118N. Note that for clarity, PMIC 122 and BW voting aggregator 124 are shown in FIG. Figure 1B is not shown, but may be included and may be as described with respect to Figure 1A Works as described.

[0031] about Figure 1AThe described example in which the sensor interface 104 is the first image processing component in the pipeline may correspond to a video capture use case. However, in other examples (not shown) corresponding to other use cases, components other than the sensor interface 104 may be the first image processing component in the pipeline. For example, under the video playback use case, the video subsystem 110 may be the first image processing component in the pipeline, and under the video gaming use case, the GPU 108 may be the first image processing component in the pipeline, etc. In view of the description herein, one of ordinary skill in the art will readily recognize yet other use cases, image processing components, and pipeline arrangements.

[0032] Sensor interface 104, image processor 106, GPU 108, video subsystem 110, display subsystem 112, NoC 114, system cache 116, and memory controller 118 may be coupled with various other components and subsystems (e.g., CPU) (for clarity, not shown in FIG. Figure 1A to Figure 1B 126). However, in other embodiments, such components may be arranged on one or more chips in any other manner. For example, in another embodiment, one or more image sensors may be included on the same SoC as the image processing components.

[0033] like Figure 2 As shown in FIG. , the selection logic 200 may be configured based on the above feed-forward CR ( Figure 2 The BW vote may be selected from the BW based on a fixed worst-case value (i.e., a constant); a measurement of the amount of bandwidth used to process the previous frame ("N-1_frame_BW_vote"); or an estimate of the bandwidth used to process the next frame ("Look_ahead_BW_vote"). The Feedforward_CR-based_BW_vote may be, for example, the result of multiplying the feedforward CR by the uncompressed BW (as described below), or the result of other calculations based on the feedforward CR. The "other values" are described in more detail below. Feedforward_CR-based_BW_vote, the fixed worst-case value, N-1_frame_BW_vote, and Look_ahead_BW_vote may also be referred to as four types of BW votes. The selection logic 200 may be configured to select one of the four types of BW votes per frame.

[0034] The selection logic 200 may be included in each of the transaction initiator components described above that are configured to provide BW voting, such as the GPU 108, the video subsystem 110, and the display subsystem 112. For clarity, the selection logic 200 is described in detail in the following sections. Figure 2 The selection algorithm is depicted conceptually in FIG. 1 , but may be implemented in any manner, such as, for example, a processor is configured (eg, via software, firmware, etc.) with a selection algorithm.

[0035] Fixed worst-case value ( Figure 2 The "worst_case" in ) may be the minimum CR or maximum BW required by the transaction initiator component (e.g., due to high noise frames, low resolution frames, etc.). The fixed worst-case value is a fixed value or constant, i.e., the value is the same regardless of the image content or the type of processing operation. Typically, the fixed worst-case value may be equal to the uncompressed BW. The "uncompressed BW" is the BW used by the component to process a frame of data (e.g., an image processing operation performed by the image processor 106, a graphics processing operation performed by the GPU 108, etc.). As described above, in addition to the sensor interface 104 that receives data in an uncompressed or raw form directly from the sensor 102, the component may also receive data from the system memory 120 ( Figure 1A to Figure 1B ) reads the compressed data and decompresses it before processing the data. The component may then compress the processed data and write the processed, compressed data to the system memory 120. As will be appreciated by one of ordinary skill in the art, the component may determine the uncompressed BW based on factors that may include image resolution, frame rate, etc. Note that the compressed BW is the uncompressed BW divided by the CR.

[0036] The transaction initiator component processes the measurement of the amount of bandwidth used by the previous frame ( Figure 2 The "N-1_frame_BW_vote" in the transaction initiator component may be based on a count of the number of beats in all transactions initiated by the transaction initiator component while processing the previous ("N-1") frame (where the "N" frame is the frame that the transaction initiator component was processing when the transaction initiator component provided the above BW vote). Alternatively, the N-1_frame_BW_vote may be based on other measures of performance, etc., such as measured by instruments (not shown) in shared components downstream of the transaction initiator component (such as NoC 114, system cache 116, memory controller 118, system memory 120, etc.), as understood by one of ordinary skill in the art.

[0037] The estimated bandwidth used to process the next frame ( Figure 2108 , "Look_ahead_BW_vote" in the selection logic 200 of the GPU 108 may be determined by the transaction initiator component in various ways, which may depend on the type of the transaction initiator component, as understood by one of ordinary skill in the art. For example, the GPU 108 may perform a scaling operation on an image frame provided by the image processor 106. In such examples (i.e., where the transaction initiator component reads data from an upstream component and writes data to a downstream component), the feedforward CR provided by the sensor interface 104 may represent the read-side BW requirement of the GPU 108. The write-side BW requirement of the GPU 108 may be based on the scaling value and the compression ratio implemented by the GPU 108. In such examples, the Look_ahead_BW_vote that the selection logic 200 of the GPU 108 may select may be the sum of the read-side and write-side BW requirements of the GPU 108.

[0038] exist Figure 3 , a method 300 for selecting a BW vote is illustrated. The selection logic 200 ( Figure 2 ) may be configured to control some or all of method 300. Each transaction initiator component or its selection logic 200 may be an example of a means for performing the functions set forth in method 300. Method 300 may include the following.

[0039] As indicated at block 302, method 300 may include determining whether image processing has just begun, i.e., whether the first image processing component in the pipeline has not yet processed the first frame of the image. If this is the beginning of image processing, each transaction initiator component may select the fixed worst-case value described above as its BW vote, as indicated at block 304. Note that in exemplary method 300, the BW vote is set to the fixed worst-case value only at the beginning of image processing. At other times, the BW vote is set to other values ​​as follows.

[0040] As indicated at block 306, method 300 may include comparing a change in feedforward CR from a previous frame to a current frame to a threshold and determining whether the change is greater than the threshold. As described above, a first image processing component in the pipeline may determine the feedforward CR. For example, in the case of video capture, sensor interface 104 ( Figure 1A to Figure 1B ) may determine a feed-forward CR. A change in the feed-forward CR that exceeds a threshold indicates that the image content has changed significantly from the previous frame to the current frame. If the transaction initiator component determines (block 306) that the change in the feed-forward CR is greater than the threshold, the transaction initiator component may select the Look_ahead_BW_vote described above as its BW vote, as indicated by block 308.

[0041] If it is determined (block 306) that the change in the feedforward CR is not greater than the threshold, then Feedforward_CR-based_BW_vote or N-1_frame_BW_vote may be selected. For example, the selection of Feedforward_CR-based_BW_vote or N-1_frame_BW_vote may be based on the following. As indicated at block 310, the method 300 may include determining whether this is the first time that the change in the feedforward CR is less than the threshold (according to block 306), that is, whether the change in the feedforward CR is less than the threshold in less than two consecutive frames. If the transaction initiator component determines (block 310) that this is the first time that the change in the feedforward CR is less than the threshold, then the transaction initiator component may select Feedforward_CR-based_BW_vote as its BW vote, as indicated at block 312. If the transaction initiator component determines (block 310) that this is not the first time that the change in the feedforward CR is less than the threshold, then the transaction initiator component may perform the determination indicated at block 314.

[0042] As indicated by block 314, it may be determined whether Feedforward_CR-based_BW_vote is greater than N-1_frame_BW_vote. If the transaction initiator component determines (block 314) that Feedforward_CR-based_BW_vote is greater than N-1_frame_BW_vote, the transaction initiator component may select N-1_frame_BW_vote as its BW vote, as indicated by block 316. However, if the transaction initiator component determines (block 314) that Feedforward_CR-based_BW_vote is not greater than N-1_frame_BW_vote, the transaction initiator component may select Feedforward_CR-based_BW_vote as its BW vote, as indicated by block 318. It may be noted that the selection of Feedforward_CR-based_BW_vote as the BW vote (via block 312 or block 318) is broadly based on the determination or condition indicated in block 306 that the feedforward CR is less than (or equal to) a threshold. The selection of Feedforward_CR-based_BW_vote as the BW vote may also be based on additional conditions, such as, for example, the conditions indicated in blocks 310 and 314. In either case (i.e., Feedforward_CR-based_BW_vote is selected as the BW vote via block 312 or block 318), Feedforward_CR-based_BW_vote is selected when the change in the feedforward CR is less than (or equal to) a threshold value.

[0043] Each transaction initiator component, such as sensor interface 104, image processor 106, GPU 108, video subsystem 110, display subsystem 112, etc. ( Figure 1A to Figure 1B ), can be configured as described above with respect to method 300 ( Figure 3 ) to select a BW vote and provide its selected BW vote to the BW vote aggregator 124 ( Figure 1A to Figure 1B Based on the BW votes collectively received from the transaction initiator components, the BW vote aggregator 124 may be configured to select or determine a DCVS level. The DCVS level may be characterized by one or more DCVS parameters, such as a power supply voltage level, a clock signal frequency, or a combination of a power supply voltage level and a clock signal frequency.

[0044] The BW voting aggregator 124 may employ any method for determining (i.e., selecting) a DCVS level. For example, the BW voting aggregator 124 may select a DCVS level corresponding to the sum of the received BW votes. In an example in which the BW vote received by the BW voting aggregator 124 consists of a first BW vote indicating a bandwidth of 2 gigabytes per second (GB / s) and a second BW vote indicating a bandwidth of 1 GB / s, the BW bandwidth voting aggregator 124 may select or determine a DCVS level corresponding to a BW of 3 GB / s, which is the sum of the 2 GB / s and 1 GB / s BW votes. As will be appreciated by one of ordinary skill in the art, the BW voting aggregator 124 may, for example, employ a lookup table (not shown) or other data structure or algorithm that associates multiple combinations of power supply voltage levels and clock signal frequencies with corresponding bandwidths.

[0045] Again briefly refer to Figure 1A to Figure 1B , PMIC 122 (or a combination of PMIC 122 and clock signal distribution related components (not shown for clarity)) can provide power supply voltages and clock signals to shared components in the image processing pipeline. For example, as indicated by the dashed arrows, power supply voltages and clock signals that collectively characterize the DCVS level can be provided to each of NoC 114, system cache 116, memory controller 118, and system memory 120. BW voting aggregator 124 can receive BW votes for each shared component (i.e., shared between transaction initiator components) from each transaction initiator component. The above description of method 300 ( Figure 3) may be applied to each of the shared components independently of the other components. Thus, different DCVS levels (i.e., supply voltages and / or clock signal frequencies) may be applied to different shared components. In other words, method 300 may be used to determine a DCVS level for NoC 114 based on a received vote for NoC BW, and method 300 may be used again to determine a DCVS level for system cache 116 based on a received vote for system cache BW, and again to determine a DCVS level for memory controller 118 based on a received vote for memory controller BW, and further again to determine a DCVS level for system memory 120 based on a received vote for system memory BW.

[0046] exist Figure 4 4 , timeline 400 illustrates an example of selecting or determining a DCVS level (ie, BW (vertical axis)) based on BW votes received from a transaction initiator component in consecutive frames (horizontal or time axis). Figure 4 The example shown in FIG. 1 may represent the system 100 ( Figure 1A to Figure 1B ), select logic 200( Figure 2 )、Method 300( Figure 3 ) etc. Also shown is an incoming image BW 402. It should be understood that for clarity, the incoming image BW 402 is Figure 4 4. It is shown in conceptual form in FIG. 4 and may have any waveform that may vary in any manner from frame to frame. It should be understood that the incoming image BW 402 corresponds to an incoming image stream comprising consecutive frames.

[0047] At the beginning of the first frame Frame_N, the first image processing component in the pipeline has not yet processed any image data frame. Figure 1A ), the sensor interface 104 has not yet captured the first frame received from the sensor 102. In this case (e.g., starting image capture), each transaction initiator component can provide a BW vote representing a fixed worst-case BW amount. The BW vote aggregator 124 ( Figure 1A to Figure 1B ) may determine a BW level 404 corresponding to the sum of BW votes received by the BW vote aggregator 124 from the transaction initiator component at the beginning of the first frame. Figure 41, but such BW levels may be expressed in system 100 (FIG. 1) as DCVS levels (i.e., a combination of voltage level and clock frequency). The first image processing component in the pipeline (e.g., sensor interface 104 in the case of a video capture use case) may calculate or determine the feed-forward CR when it completes processing the first frame, and thereafter may calculate or determine the feed-forward CR each time it completes processing a successive frame. This feed-forward CR may be propagated to each downstream transaction initiator component.

[0048] At the beginning of the next frame Frame_N+1, each transaction initiator component may provide a BW vote that does not represent the worst-case BW amount. Figure 3 ), the transaction initiator component provides a BW vote representing a fixed worst-case value only when the first image processing component in the pipeline has not yet processed the first frame of the incoming image stream. In contrast, in the second frame and other frames, each transaction initiator component may provide a BW vote representing one of the following: a measurement of the amount of BW used to process the previous frame; an estimate of the amount of BW required to process the next frame; or a value based on the feedforward CR. Each transaction initiator component may calculate or otherwise maintain a value representing the change in the feedforward CR from the previous frame to the current frame. Which of the aforementioned values ​​the transaction initiator component selects as its BW vote may be based on a comparison between the change in the feedforward CR and a threshold, as described above with respect to method 300. In the illustrated example, the BW vote aggregator 124 ( Figure 1A to Figure 1B ) may determine a BW level 406 corresponding to the sum of BW votes received by the BW vote aggregator 124 from the transaction initiator component at the beginning of the second frame Frame_N+1.

[0049] At the beginning of the next frame, Frame_N+2, each transaction initiator component may again provide a BW vote that does not represent the worst-case BW amount, but instead represents one of the following: a measurement of the BW amount used to process the previous frame; an estimate of the BW required to process the next frame; or a value based on the feedforward CR. In the illustrated example, the BW vote aggregator 124 ( Figure 1A to Figure 1B ) may determine to maintain the BW level 406 for the duration of the next frame.

[0050] The selection of BW may continue in the manner described above during the next frame Frame_N+3. In the illustrated example, each transaction initiator component may provide a BW vote representing zero bandwidth. Thus, the BW vote aggregator 124 ( Figure 1A ) may select a (zero) BW level 408. During the next frame Frame_N+4, the BW vote aggregator 124 may select a BW level 410 based on the BW votes received from the transaction initiator component.

[0051] The BW selected by the BW voting aggregator 124 may be provided to the PMIC 122 in the form of a DCVS level (ie, a selected power supply voltage level and a clock signal frequency). Figure 1A ). According to the DCVS principle, PMIC 122 can provide a power signal with a selected voltage level and a clock signal with a selected frequency to the transaction initiator component and the shared component. Bandwidth selection and accompanying DCVS adjustment can continue in this manner until the image capture is completed.

[0052] Figure 5 An example of a portable computing device ("PCD") 500, such as a mobile phone or smart phone, is illustrated in which exemplary embodiments of systems, methods, computer-readable media, and other examples of DCVS BW voting may be provided. For clarity, some data buses, interconnects, signals, etc. are not shown in FIG. Figure 5 For example, the NoC is not shown, but may be described above with respect to Figure 1A to Figure 1B The described method is included. Figure 1B Compared with the NoC-centric block diagram, Figure 5 Although PCD 500 is shown as an example, other embodiments of the systems, methods, computer-readable media, and other examples of DCVS BW voting may be provided in other types of computing devices or systems.

[0053] PCD 500 may include SoC 502. SoC 502 may be SoC 126 ( Figure 1A to Figure 1B ) example. SoC 502 may include a central processing unit ("CPU") 504, a neural processing unit ("NPU") 505, a graphics processing unit ("GPU") 506, a digital signal processor ("DSP") 507, an analog signal processor 508, a modem / modem subsystem or RF transceiver 554, or other processors. CPU 504 may include one or more CPU cores, such as a first CPU core 504A, a second CPU core 504B, and so on to an Nth CPU core 504N. GPU 506 may be the CPU core described above with respect to Figure 1A to Figure 1B An example of GPU 108 is described.

[0054] The PCD 500 may include a display controller 510 and a touch screen controller 512 coupled to the CPU 504. A touch screen display 514 external to the SoC 502 may be coupled to the display controller 510 and the touch screen controller 512. The PCD 500 may also include a video decoder 516 coupled to the CPU 504. A video amplifier 518 may be coupled to the video decoder 516 and the touch screen display 514. A video port 520 may be coupled to the video amplifier 518. A universal serial bus (“USB”) controller 522 may also be coupled to the CPU 504, and a USB port 524 may be coupled to the USB controller 522. A subscriber identity module (“SIM”) card 526 may also be coupled to the CPU 504.

[0055] One or more memories may be coupled to CPU 504. The one or more memories may include both volatile memory and non-volatile memory. Examples of volatile memory include static random access memory ("SRAM") 528 and dynamic random access memory ("DRAM") 530 and 531. Such memories may be located external to SoC 502 (such as DRAM 530) or internal to SoC 502 (such as DRAM 531). A DRAM controller 532 coupled to CPU 504 may control writing data to and reading data from DRAM 530 and 531. DRAM controller 532 may be a memory controller 118 ( Figure 1A to Figure 1B ) is an example of DRAM 530 or 531. DRAM 530 or 531 may be a system memory 120 ( Figure 1A to Figure 1B ) example.

[0056] A stereo audio codec 534 may be coupled to the analog signal processor 508. Further, an audio amplifier 536 may be coupled to the stereo audio codec 534. A first stereo speaker 538 and a second stereo speaker 540 may be coupled to the audio amplifier 536, respectively. In addition, a microphone amplifier 542 may be coupled to the stereo audio codec 534, and a microphone 544 may be coupled to the microphone amplifier 542. A frequency modulation ("FM") radio tuner 546 may be coupled to the stereo audio codec 534. An FM antenna 548 may be coupled to the FM radio tuner 546. Further, a stereo headset 550 may be coupled to the stereo audio codec 534. Other devices that may be coupled to the CPU 504 include one or more digital (e.g., CCD or CMOS) cameras 552. The digital camera 552 may be a sensor 102 ( Figure 1A to Figure 1B ). In addition to GPU 506, other image processing components may include, for example, a sensor interface 551 and an image processor 553, which may be respectively Figure 1A to Figure 1BExamples of sensor interface 104 and image processor 106 are described above. Figure 1A to Figure 1B Still other image processing components of the type described may be included in PCD 500, but are not described here for clarity. Figure 5 Not shown.

[0057] A modem or RF transceiver 554 may be coupled to the analog signal processor 508 and the CPU 504. An RF switch 556 may be coupled to the RF transceiver 554 and the RF antenna 558. Additionally, a keypad 560, a mono headset with a microphone 562, and a vibrator device 564 may be coupled to the analog signal processor 508.

[0058] SoC 502 may have one or more internal or on-chip thermal sensors 570A and may be coupled to one or more external or off-chip thermal sensors 570B. Analog-to-digital converter controller 572 may convert the voltage drop generated by thermal sensors 570A and 570B into a digital signal. Power supply 574 and PMIC 576 may provide power to SoC 502.

[0059] The firmware or software may be stored in any of the above memories, such as DRAM 530 or 531, SRAM 528, etc., or may be stored in local memory directly accessible by the processor hardware on which the software or firmware is executed. The execution of such firmware or software may control aspects of any of the above methods or configure aspects of any of the above systems. Any such memory or other non-transitory storage medium having firmware or software stored therein in a computer-readable form for execution by processor hardware may be an example of a "computer-readable medium" as that term is understood in the patent dictionary.

[0060] Specific implementation examples are described in the following numbered clauses:

[0061] 1. A system for dynamic clock and voltage scaling (DCVS) bandwidth voting, the system comprising:

[0062] a pipeline comprising a plurality of image processing components, a first image processing component in the pipeline being configured to determine a feed-forward compression ratio based on a current frame of an image, the plurality of image processing components comprising a plurality of transaction initiator components, a transaction initiator component in the plurality of transaction initiator components being configured to select a bandwidth vote from a value based on the feed-forward compression ratio and one or more other values ​​based on a comparison of the change in the feed-forward compression ratio with the threshold; and

[0063] A bandwidth vote aggregator is configured to determine a DCVS level based on a plurality of bandwidth votes received from the plurality of transaction initiator components.

[0064] 2. A system according to clause 1, wherein the transaction initiator component is configured to determine a change in the feed-forward compression ratio from a previous frame to the current frame, and compare the change in the feed-forward compression ratio with a threshold, and select the bandwidth vote based on the comparison result of the change in the feed-forward compression ratio with the threshold.

[0065] 3. A system according to clause 1 or 2, wherein the one or more other values ​​include: a fixed worst-case value; a measurement of the amount of bandwidth used to process a previous frame; and an estimate of the bandwidth used to process a next frame.

[0066] 4. A system according to any one of clauses 1 to 3, wherein the transaction initiator component is configured to select the bandwidth vote by being configured to select the fixed worst-case value only when the first image processing component has not yet processed the first frame of the image.

[0067] 5. A system according to any of clauses 2 to 4, wherein the transaction initiator component is configured to select the bandwidth vote by being configured to select a bandwidth estimator to process a next frame when the change in the feed-forward compression ratio is greater than the threshold.

[0068] 6. A system according to any of clauses 2 to 5, wherein the transaction initiator component is configured to select the bandwidth vote by being configured to select the feed-forward compression ratio-based value when the change in the feed-forward compression ratio is less than the threshold.

[0069] 7. A system according to any of clauses 2 to 6, wherein the transaction initiator component is configured to select the bandwidth vote by being configured to select the feedforward compression ratio-based value when the change in the feedforward compression ratio is less than the threshold in less than two consecutive frames.

[0070] 8. A system according to any one of clauses 2 to 7, wherein the transaction initiator component is configured to select the bandwidth vote by being configured to select the measurement result of the amount of bandwidth used to process the previous frame when the change in the feedforward compression ratio is less than the threshold and the value based on the feedforward compression ratio is greater than the amount of bandwidth used to process the previous frame.

[0071] 9. A system according to any one of clauses 2 to 8, wherein the transaction initiator component is configured to select the bandwidth vote by being configured to select the feedforward compression ratio-based value when the change in the feedforward compression ratio is less than the threshold and the feedforward compression ratio-based value is not greater than the amount of bandwidth used to process the previous frame.

[0072] 10. A system according to any one of clauses 1 to 9, the system further comprising a power management circuit configured to provide a power supply voltage and a clock signal corresponding to the DCVS level to at least one shared processing component among the plurality of image processing components.

[0073] 11. A system according to any one of clauses 1 to 10, wherein the plurality of image processing components include: a sensor interface having a sensor interface input coupled to an image sensor; an image processor having an image processor input coupled to a sensor interface output; and a display subsystem having a display input coupled to an image processor output.

[0074] 12. The system of any one of clauses 1 to 11, wherein the plurality of transaction initiator components comprises a graphics processing unit (GPU) having a GPU input coupled to the image processor output.

[0075] 13. A method for dynamic clock and voltage scaling (DCVS) bandwidth voting, the method comprising:

[0076] determining, by a first image processing component in a pipeline including a plurality of image processing components, a feed-forward compression ratio based on a current frame of an image, the plurality of image processing components including a plurality of transaction initiator components;

[0077] selecting, by the transaction initiator component, a bandwidth vote from a value based on a feed-forward compression ratio and one or more other values; and

[0078] A DCVS level is determined by a bandwidth vote aggregator based on a plurality of bandwidth votes received from the plurality of transaction initiator components.

[0079] 14. The method of clause 13, wherein selecting the bandwidth vote comprises:

[0080] determining a change in the feedforward compression ratio from a previous frame to the current frame;

[0081] comparing the change in the feedforward compression ratio with a threshold; and

[0082] The bandwidth vote is selected based on a comparison of the change in the feed-forward compression ratio with the threshold.

[0083] 15. A method according to clause 13 or 14, wherein the one or more other values ​​include: a fixed worst-case value; a measurement of the amount of bandwidth used to process a previous frame; and an estimate of the bandwidth used to process a next frame.

[0084] 16. A method according to any of clauses 13 to 15, wherein selecting the bandwidth vote comprises selecting the fixed worst-case value only when the first image processing component has not yet processed a first frame of the image.

[0085] 17. A method according to any of clauses 14 to 16, wherein selecting the bandwidth vote comprises selecting a bandwidth estimator to process a next frame when the change in the feed-forward compression ratio is greater than the threshold.

[0086] 18. The method of any of clauses 14 to 17, wherein selecting the bandwidth vote comprises selecting the feed-forward compression ratio-based value when the change in the feed-forward compression ratio is less than the threshold.

[0087] 19. A method according to any of clauses 14 to 18, wherein selecting the bandwidth vote comprises selecting the feed-forward compression ratio-based value when the change in the feed-forward compression ratio is less than the threshold in less than two consecutive frames.

[0088] 20. A method according to any one of clauses 14 to 19, wherein selecting the bandwidth vote includes selecting a measurement result of the amount of bandwidth used to process the previous frame when the change in the feedforward compression ratio is less than the threshold and the value based on the feedforward compression ratio is greater than the amount of bandwidth used to process the previous frame.

[0089] 21. A method according to any one of clauses 14 to 20, wherein selecting the bandwidth vote includes selecting the feedforward compression ratio-based value when the change in the feedforward compression ratio is less than the threshold and the feedforward compression ratio-based value is not greater than the amount of bandwidth used to process the previous frame.

[0090] 22. A system for dynamic clock and voltage scaling (DCVS) bandwidth voting, the system comprising:

[0091] means for determining a feed-forward compression ratio based on a current frame of an image;

[0092] means for selecting a bandwidth vote from a value based on a feed-forward compression ratio and one or more other values; and

[0093] The DCVS level is determined based on multiple bandwidth votes.

[0094] 23. The system of clause 22, wherein the means for selecting the bandwidth vote comprises:

[0095] means for determining a change in the feed-forward compression ratio from a previous frame to the current frame;

[0096] means for comparing the change in the feed-forward compression ratio to a threshold, wherein the bandwidth vote is selected based on a result of the means for comparing.

[0097] 24. A system according to clause 22 or 23, wherein the one or more other values ​​include: a fixed worst-case value; a measurement of the amount of bandwidth used to process a previous frame; and an estimate of the bandwidth used to process a next frame.

[0098] 25. The system of any of clauses 22 to 24, wherein selecting the bandwidth vote comprises selecting the fixed worst-case value only when the first image processing component has not yet processed a first frame of the image.

[0099] 26. The system of any of clauses 23 to 25, wherein selecting the bandwidth vote comprises selecting a bandwidth estimator to process a next frame when the change in the feed-forward compression ratio is greater than the threshold.

[0100] 27. The system of any of clauses 23 to 26, wherein selecting the bandwidth vote comprises selecting the feed-forward compression ratio-based value when the change in the feed-forward compression ratio is less than the threshold.

[0101] 28. The system of any of clauses 23 to 27, wherein selecting the bandwidth vote comprises selecting the feedforward compression ratio-based value when the change in the feedforward compression ratio is less than the threshold in less than two consecutive frames.

[0102] 29. A system according to any of clauses 23 to 28, wherein selecting the bandwidth vote comprises selecting a measurement of the amount of bandwidth used to process the previous frame when the change in the feedforward compression ratio is less than the threshold and the value based on the feedforward compression ratio is greater than the amount of bandwidth used to process the previous frame,

[0103] 30. A system according to any one of clauses 23 to 29, wherein selecting the bandwidth vote includes selecting the feedforward compression ratio-based value when the change in the feedforward compression ratio is less than the threshold and the feedforward compression ratio-based value is not greater than the amount of bandwidth used to process the previous frame.

[0104] 31. A computer readable medium for dynamic clock and voltage scaling (DCVS) bandwidth voting, the computer readable medium comprising a non-transitory computer readable medium having instructions stored thereon in a computer executable form, the instructions, when executed by a processing system of a computing device, configure the processing system to control:

[0105] determining, by a first image processing component in a pipeline including a plurality of image processing components, a feed-forward compression ratio based on a current frame of an image, the plurality of image processing components including a plurality of transaction initiator components;

[0106] selecting, by a transaction initiator component of the plurality of transaction initiator components, a bandwidth vote from a value based on a feed-forward compression ratio and one or more other values; and

[0107] A DCVS level is determined by a bandwidth vote aggregator based on a plurality of bandwidth votes received from the plurality of transaction initiator components.

[0108] 32. The computer-readable medium of clause 31, wherein selecting the bandwidth vote comprises:

[0109] determining a change in the feedforward compression ratio from a previous frame to the current frame;

[0110] comparing, by a transaction initiator component of the plurality of transaction initiator components, the change in the feed-forward compression ratio to a threshold value; and

[0111] The bandwidth vote is selected based on a comparison of the change in the feed-forward compression ratio with the threshold.

[0112] 33. A computer-readable medium according to clause 31 or 32, wherein the one or more other values ​​include: a fixed worst-case value; a measurement of the amount of bandwidth used to process a previous frame; and an estimate of the bandwidth used to process a next frame.

[0113] 34. The computer-readable medium of any one of clauses 31 to 33, wherein selecting the bandwidth vote comprises selecting the fixed worst-case value only when the first image processing component has not yet processed a first frame of the image.

[0114] Alternative embodiments will become apparent to those skilled in the art to which the invention pertains.Thus, while selected aspects have been illustrated and described in detail, it should be appreciated that various substitutions and changes may be made therein.

Claims

1. A system for dynamic clock and voltage scaling (DCVS) bandwidth voting, the system include: a pipeline, the pipeline comprising a plurality of image processing components, a first image processing component in the pipeline being configured to determine a feed-forward compression ratio based on a current frame of an image, the plurality of image processing components comprising a plurality of transaction initiator components, a transaction initiator component in the plurality of transaction initiator components being configured to select a bandwidth vote from a value based on the feed-forward compression ratio and one or more other values; and A bandwidth vote aggregator is configured to determine a DCVS level based on a plurality of bandwidth votes received from the plurality of transaction initiator components.

2. The system of claim 1 , wherein each transaction initiator component is configured to determine a change in the feed-forward compression ratio from a previous frame to the current frame, and compare the change in the feed-forward compression ratio with a threshold, and select the bandwidth vote based on a result of comparing the change in the feed-forward compression ratio with the threshold.

3. The system of claim 2, wherein the one or more other values include: Fixed worst-case value; A measurement of the amount of bandwidth used to process the previous frame; and an estimate of the bandwidth used to process the next frame.

4. The system of claim 3, wherein the transaction initiator component is configured to select the bandwidth vote by being configured to select the fixed worst-case value only when the first image processing component has not yet processed a first frame of the image.

5. The system of claim 2, wherein the transaction initiator component is configured to select the bandwidth vote by being configured to select a bandwidth estimator to process a next frame when the change in the feed-forward compression ratio is greater than the threshold.

6. The system of claim 2, wherein the transaction initiator component is configured to select the bandwidth vote by being configured to select the feed-forward compression ratio-based value when the change in the feed-forward compression ratio is less than the threshold.

7. The system of claim 6, wherein the transaction initiator component is configured to select the bandwidth vote by being configured to select the feed-forward compression ratio-based value when the change in the feed-forward compression ratio is less than the threshold in less than two consecutive frames.

8. The system of claim 6, wherein the transaction initiator component is configured to select the bandwidth vote by being configured to select the measurement result of the amount of bandwidth used to process the previous frame when the change in the feed-forward compression ratio is less than the threshold and the value based on the feed-forward compression ratio is greater than the amount of bandwidth used to process the previous frame.

9. The system of claim 8, wherein the transaction initiator component is configured to select the bandwidth vote by being configured to select the feed-forward compression ratio-based value when the change in the feed-forward compression ratio is less than the threshold and the feed-forward compression ratio-based value is not greater than the amount of bandwidth used to process the previous frame.

10. The system of claim 1, further comprising a power management circuit configured to provide a power supply voltage and a clock signal corresponding to the DCVS level to at least one shared processing component among the plurality of image processing components.

11. The system of claim 1, wherein the plurality of image processing components include: a sensor interface having a sensor interface input coupled to an image sensor; an image processor having an image processor input coupled to the sensor interface output; and a display subsystem having a display input coupled to the image processor output.

12. The system of claim 1, wherein the plurality of transaction initiator components comprises a graphics processing unit (GPU) having a GPU input coupled to the image processor output.

13. A method for dynamic clock and voltage scaling (DCVS) bandwidth voting, the method include: determining, by a first image processing component in a pipeline including a plurality of image processing components, a feed-forward compression ratio based on a current frame of an image, the plurality of image processing components including a plurality of transaction initiator components; selecting, by a transaction initiator component of the plurality of transaction initiator components, a bandwidth vote from a value based on a feed-forward compression ratio and one or more other values; as well as A DCVS level is determined by a bandwidth vote aggregator based on a plurality of bandwidth votes received from the plurality of transaction initiator components.

14. The method of claim 13, wherein the bandwidth vote is selected include: determining a change in the feedforward compression ratio from a previous frame to the current frame; comparing the change in the feedforward compression ratio with a threshold; as well as The bandwidth vote is selected based on a comparison of the change in the feed-forward compression ratio with the threshold.

15. The method of claim 14, wherein the one or more other values include: Fixed worst-case value; A measurement of the amount of bandwidth used to process the previous frame; and an estimate of the bandwidth used to process the next frame.

16. The method of claim 15, wherein selecting the bandwidth vote comprises selecting the fixed worst-case value only when the first image processing component has not yet processed a first frame of the image.

17. The method of claim 14, wherein selecting the bandwidth vote comprises selecting a bandwidth estimator to process a next frame when the change in the feed-forward compression ratio is greater than the threshold.

18. The method of claim 14, wherein selecting the bandwidth vote comprises selecting the feed-forward compression ratio-based value when the change in the feed-forward compression ratio is less than the threshold.

19. The method of claim 18, wherein selecting the bandwidth vote comprises selecting the feed-forward compression ratio-based value when the change in the feed-forward compression ratio is less than the threshold in less than two consecutive frames.

20. The method of claim 18, wherein selecting the bandwidth vote comprises selecting a measurement of the amount of bandwidth used to process the previous frame when the change in the feedforward compression ratio is less than the threshold and the value based on the feedforward compression ratio is greater than the amount of bandwidth used to process the previous frame.

21. The method of claim 20, wherein selecting the bandwidth vote comprises selecting the feedforward compression ratio-based value when the change in the feedforward compression ratio is less than the threshold and the feedforward compression ratio-based value is not greater than the amount of bandwidth used to process the previous frame.

22. A system for dynamic clock and voltage scaling (DCVS) bandwidth voting, the system include: means for determining a feed-forward compression ratio based on a current frame of an image; means for selecting a bandwidth vote from a value based on a feed-forward compression ratio and one or more other values; and The DCVS level is determined based on multiple bandwidth votes.

23. The system of claim 22, wherein the means for selecting the bandwidth vote include: means for determining a change in the feed-forward compression ratio from a previous frame to the current frame; and means for comparing the change in the feed-forward compression ratio to a threshold, wherein the bandwidth vote is selected based on a result of the means for comparing.

24. The system of claim 23, wherein the one or more other values include: Fixed worst-case value; A measurement of the amount of bandwidth used to process the previous frame; and an estimate of the bandwidth used to process the next frame.

25. The system of claim 24, wherein selecting the bandwidth vote comprises selecting the fixed worst-case value only when the first image processing component has not yet processed a first frame of the image.

26. The system of claim 23, wherein selecting the bandwidth vote comprises selecting a bandwidth estimator to process a next frame when the change in the feed-forward compression ratio is greater than the threshold.

27. The system of claim 23, wherein selecting the bandwidth vote comprises selecting the feed-forward compression ratio-based value when the change in the feed-forward compression ratio is less than the threshold.

28. The system of claim 27, wherein selecting the bandwidth vote comprises selecting the feed-forward compression ratio-based value when the change in the feed-forward compression ratio is less than the threshold in less than two consecutive frames.

29. The system of claim 27, wherein selecting the bandwidth vote comprises selecting a measurement of the amount of bandwidth used to process the previous frame when the change in the feedforward compression ratio is less than the threshold and the value based on the feedforward compression ratio is greater than the amount of bandwidth used to process the previous frame.

30. The system of claim 29, wherein selecting the bandwidth vote comprises selecting the feedforward compression ratio-based value when the change in the feedforward compression ratio is less than the threshold and the feedforward compression ratio-based value is not greater than the amount of bandwidth used to process the previous frame.

31. A computer readable medium for dynamic clock and voltage scaling (DCVS) bandwidth voting, the computer readable medium comprising a non-transitory computer readable medium having instructions stored thereon in a computer executable form, the instructions, when executed by a processing system of a computing device, configure the processing system to control: determining, by a first image processing component in a pipeline including a plurality of image processing components, a feed-forward compression ratio based on a current frame of an image, the plurality of image processing components including a plurality of transaction initiator components; selecting, by a transaction initiator component of the plurality of transaction initiator components, a bandwidth vote from a value based on a feed-forward compression ratio and one or more other values; as well as A DCVS level is determined by a bandwidth vote aggregator based on a plurality of bandwidth votes received from the plurality of transaction initiator components.

32. The computer-readable medium of claim 31, wherein the bandwidth vote is selected include: determining a change in the feedforward compression ratio from a previous frame to the current frame; comparing the change in the feedforward compression ratio with a threshold; as well as The bandwidth vote is selected based on a comparison of the change in the feed-forward compression ratio with the threshold.

33. The computer readable medium of claim 32, wherein the one or more other values include: Fixed worst-case value; A measurement of the amount of bandwidth used to process the previous frame; and an estimate of the bandwidth used to process the next frame.

34. The computer-readable medium of claim 33, wherein selecting the bandwidth vote comprises selecting the fixed worst-case value only when the first image processing component has not yet processed a first frame of the image.

Images