Method for manufacturing semiconductor element

Abstract

This method for manufacturing a semiconductor element comprises: a step for preparing a laminated body in which each of a plurality of semiconductor chips is fixed to a carrier by means of an adhesive layer, the respective connection terminals of the plurality of semiconductor chips being fixed to a first carrier surface of the carrier so as to face the opposite side from the carrier; forming a rewiring layer connected to each of the connection terminals of the plurality of semiconductor chips; and grinding the carrier in the laminate from a second carrier surface opposite to the first carrier surface toward the first carrier surface. In the grinding step, the carrier and the adhesive layer are scraped to expose a second chip surface on the opposite side to a first chip surface on which the rewiring layer is provided of the plurality of semiconductor chips.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor element. Background Art

[0002] An example of a fan-out type semiconductor element is disclosed in Patent Document 1. In this semiconductor element, a redistribution layer is provided between a semiconductor chip and external connection terminals, and the terminals of the semiconductor chip are spaced apart by the redistribution layer to be connected to the external connection terminals.

[0003] Previous technical literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2019-029557 Summary of the invention

[0006] Technical issues to be solved by the invention

[0007] In conventional methods of manufacturing semiconductor devices, for example, Figure 5 As shown in (a), a plurality of semiconductor chips 110 are temporarily fixed on a glass carrier 120 using a temporary fixing material 112, and sealed using a sealing material 130. The sealing material 130 is then polished until the connection terminals of the semiconductor chips 110 are exposed, and a redistribution layer 140 is formed thereon (see Figure 5 (b)). However, in the manufacturing method of the semiconductor element, the semiconductor chip 110 is temporarily fixed to the carrier 120 by the temporary fixing material 112. Therefore, when the sealing material 130 is formed by the mold molding machine, the semiconductor chip 110 may move from the original setting position under the pressure of the die, and the so-called die shift S1 may occur. In the case of die shift, a separate alignment operation is required for the subsequent process (such as the exposure process).

[0008] Furthermore, the outer peripheral portion S2 of the temporary fixing material 112 sandwiched between the glass carrier 120 and the sealing material 130 is exposed, and thus may be damaged by the used chemical solution. As a result, there is a tendency for the glass carrier 120 and the sealing material 130 to be peeled off during the manufacturing process. Figure 5 As shown in (b), when the temporary fixing material 112 is peeled off from the sealing material 130, cracks may be generated between the semiconductor chip 110 and the sealing material 130 due to the force during peeling. Resin residues of the temporary fixing material 112 may remain on the surface of the sealing material 130 or the semiconductor chip 110 (S3), or microcracks S4 may be generated on the glass carrier 120 during the process, or metal S5 used in the process may be mixed into the microcracks S4.

[0009] An object of the present invention is to provide a method for manufacturing a semiconductor element which can easily improve the cleanliness of the chip surface while suppressing the positional deviation of the semiconductor chip.

[0010] Means for solving technical problems

[0011] As one aspect of the present invention, a method for manufacturing a semiconductor element is provided. The manufacturing method includes the following steps: preparing a stacked body, wherein each of a plurality of semiconductor chips is fixed on a carrier via an adhesive layer, wherein each connection terminal of the plurality of semiconductor chips is fixed to a first carrier surface of the carrier in a manner facing the opposite side of the carrier; forming a redistribution layer connected to each connection terminal of the plurality of semiconductor chips; and grinding the carrier in the stacked body from a second carrier surface on the opposite side of the first carrier surface toward the first carrier surface. In the grinding step, the carrier and the adhesive layer are scraped off to expose the second chip surface on the opposite side of the first chip surface of the plurality of semiconductor chips on which the redistribution layer is provided.

[0012] In the method for manufacturing the semiconductor element, a plurality of semiconductor chips are fixed to a carrier via an adhesive layer. In this way, the semiconductor chip is fixed to the carrier by an adhesive layer that is formally fixed rather than temporarily fixed. In this case, the positional displacement of the semiconductor chip can be reliably suppressed. Furthermore, in the method for manufacturing the semiconductor element, in the grinding step, the carrier is scraped to expose the second chip surface that is opposite to the first chip surface of the plurality of semiconductor chips provided with a redistribution layer. In this case, the carrier is scraped, so that no resin residue or the like remains, and the cleanliness of the chip surface can be improved.

[0013] In the method for manufacturing the semiconductor element, the adhesive layer is a layer formed by curing a thermosetting adhesive, and may be provided corresponding to each of the plurality of semiconductor chips. In this case, the adhesive layer can be easily ground in the step of grinding the carrier.

[0014] In the method for manufacturing the semiconductor element, the thickness of the adhesive layer is preferably 50 μm or less. In this case, the adhesive layer can be easily ground in the step of grinding the carrier. In addition, the thickness of the adhesive layer is further preferably 20 μm or less. In this case, the adhesive layer can be more easily ground.

[0015] In the manufacturing method of the semiconductor element, the adhesive layer contains a curable resin component and an inorganic filler, and the content of the inorganic filler is preferably 50% by mass to 95% by mass based on the total amount of the adhesive before the adhesive layer is cured. In this case, the adhesive layer can be easily ground in the process of grinding the carrier. In addition, based on the total amount of the adhesive before the adhesive layer is cured, the content of the inorganic filler is more preferably 80% by mass to 95% by mass. In this case, the adhesive layer can be more easily ground in the process of grinding the carrier.

[0016] In the manufacturing method of the semiconductor element, the step of preparing the laminate may include the following steps: fixing each of the plurality of semiconductor chips to a carrier with an adhesive layer; and sealing with a sealing material in a manner covering the plurality of semiconductor chips on the carrier to form a sealing material layer. In this manner, the sealing material contains a curable resin component and an inorganic filler, and the content of the inorganic filler in the sealing material may be 50% by mass or more, preferably 80% by mass or more, based on the total amount of the sealing material. In this case, the grinding of the sealing material layer can be performed reliably.

[0017] In the method for manufacturing a semiconductor element, the step of preparing a stacked body may further include a step of grinding the sealing material layer covering the plurality of semiconductor chips until the first chip surfaces of the plurality of semiconductor chips are exposed after the sealing step.

[0018] In the above-mentioned method for manufacturing a semiconductor element, the step of grinding the carrier preferably includes the following steps: rough grinding the second carrier surface of the carrier with a first grindstone; and fine grinding the roughly ground carrier with a second grindstone having a higher grain size than the first grindstone. In this case, the grinding speed of the carrier can be increased by rough grinding, and the fine grinding of the ground surface can be improved by fine grinding. In this mode, the first grindstone is a grindstone with a grain size of ﹟200 to ﹟1000, and the second grindstone can be a grindstone with a grain size of ﹟2000 to ﹟6000. As a result, the grinding speed can be increased and the fine grinding accuracy of the ground surface can be improved more reliably. In this mode, in the rough grinding step, the first grindstone can be used to scrape at least a portion of the carrier and the adhesive layer, and in the fine grinding step, the second grindstone can be used to grind the sealing material layer and the second chip surface of the semiconductor chip. This makes it possible to more reliably improve the grinding speed and the finishing accuracy of the ground surface.

[0019] In the above-mentioned method for manufacturing a semiconductor element, the carrier is a silicon carrier, and the grinding step may further include a step of recycling the ground silicon mud (silicon scraps) for reuse. In this case, the used silicon can be reused, and it can be an environmentally friendly manufacturing method. For example, according to this manufacturing method, impurities can be removed from the ground silicon mud, and it can be used as recycled silicon.

[0020] Effects of the Invention

[0021] According to the present invention, it is possible to provide a method for manufacturing a semiconductor element which can easily improve the cleanliness of the chip surface while suppressing the positional deviation of the semiconductor chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a cross-sectional view showing an example of a semiconductor element.

[0023] Figure 2 In the figure, (a) to (c) are diagrams sequentially showing a method for manufacturing a semiconductor element.

[0024] Figure 3 In the figure, (a) and (b) are diagrams showing the manufacturing method of the semiconductor element in sequence, and show Figure 2 The process performed after the process.

[0025] Figure 4 In the figure, (a) to (c) are diagrams showing the manufacturing method of the semiconductor element in sequence, and show Figure 3 The process performed after the process.

[0026] Figure 5 In the drawings, (a) and (b) are diagrams showing a method for manufacturing a semiconductor element according to a comparative example. DETAILED DESCRIPTION

[0027] Hereinafter, the present embodiment will be described in detail with reference to the accompanying drawings. In the following description, the same symbols are marked on the same or equivalent parts, and repeated descriptions are omitted. In addition, unless otherwise specified, the positional relationships such as up, down, left, and right are based on the positional relationships shown in the accompanying drawings. In addition, the dimensional ratios of the accompanying drawings are not limited to the ratios shown in the drawings.

[0028] In this specification and the scope of the patent application, when using terms such as "left", "right", "front", "back", "up", "down", "above", "below", "first", "second", etc., these are terms used for explanation and do not necessarily permanently mean the relative position. Furthermore, the term "layer" includes not only structures of shapes formed on the entire surface when observed in a top view, but also structures of shapes formed locally. Furthermore, the term "process" not only includes independent processes, but also includes them in this term as long as the desired purpose of the process is achieved even if it cannot be clearly distinguished from other processes. Furthermore, the numerical range expressed by "to" indicates a range that includes the numerical values ​​recorded before and after the "to" as the minimum and maximum values, respectively. In addition, within the numerical range recorded in stages in this specification, the upper limit or lower limit of the numerical range of a certain stage can be replaced by the upper limit or lower limit of the numerical range of other stages.

[0029] Figure 1 FIG. 1 is a cross-sectional view showing an example of a semiconductor element. Figure 1 As shown, the semiconductor element 1 includes a semiconductor chip 2, a protection portion 3, a redistribution layer 4, and a bump 5. The semiconductor chip 2 is, for example, a semiconductor chip such as a processor or a memory. The protection portion 3 is a portion composed of a sealing resin or the like, and protects the semiconductor chip 2. The redistribution layer 4 (RDL: Re-distribution Layer) is a wiring layer having an insulating portion and wiring (for example, copper wiring) formed in the insulating portion. The redistribution layer 4 connects the connection terminal of the semiconductor chip 2 and the bump 5. The bump 5 is formed of, for example, a metal material such as solder.

[0030] Next, refer to Figure 2 to Figure 4 , a method for manufacturing the semiconductor element 1 is described. Figure 2 to Figure 4 The figures sequentially show the method for manufacturing the semiconductor element 1. The semiconductor element 1 is manufactured through, for example, the following steps (a) to (d).

[0031] (a) A step of preparing a stacked body T1 in which each of the plurality of semiconductor chips 10 is fixed to the carrier 20 via the adhesive layer 12. In this step (a), the connection terminals 10c of the plurality of semiconductor chips 10 are fixed to the first carrier surface 20a of the carrier 20 so as to face the opposite side of the carrier 20.

[0032] (b) A step of forming a redistribution layer 40 connected to each of the connection terminals 10 c of the plurality of semiconductor chips 10 .

[0033] (c) A step of grinding the carrier 20 in the stacked body T2 from the second carrier surface 20b on the opposite side to the first carrier surface 20a toward the first carrier surface 20a. In this step (c), the carrier 20 and the adhesive layer 12 are scraped to expose the second chip surface 10b on the opposite side to the first chip surface 10a on which the redistribution layer 40 of the plurality of semiconductor chips 10 is provided.

[0034] (d) A step of singulating the stacked body T3 of the scraped carrier 20 to obtain a semiconductor device having the semiconductor chip 10. In this step (d), a predetermined number of bumps (with the same number of bumps as the semiconductor chip 10) are formed on the redistribution layer 40 before singulation. Figure 1 5 in the figure).

[0035] In step (a), first, Figure 2 As shown in (a), a plurality of semiconductor chips 10 are prepared. An adhesive layer 12 is bonded to each semiconductor chip 10. Figure 1The semiconductor chip 2 in the semiconductor element 1 shown in the figure corresponds to the semiconductor chip 2. The semiconductor chip 10 has a first chip surface 10a provided with a connection terminal 10c and a second chip surface 10b on the opposite side of the first chip surface 10a. An adhesive layer 12 is attached to the second chip surface 10b. That is, the adhesive layer 12 is provided corresponding to each semiconductor chip 10. The adhesive layer 12 is in an uncured state in the preparation stage.

[0036] The adhesive layer 12 is, for example, a film containing a thermosetting adhesive such as a chip attachment film (DAF). The thermosetting adhesive constituting the adhesive layer 12 contains, for example, a polymer resin component and a thermosetting component. The thickness of the adhesive layer 12 is, for example, 50 μm or less. Since the thickness of the adhesive layer 12 is 50 μm or less, the adhesive layer 12 can be easily scraped off during cutting in step (c). The thickness of the adhesive layer 12 can be less than 20 μm, less than 10 μm, less than 9 μm, less than 8 μm, or less than 7 μm, and can also be more than 1 μm, more than 2 μm, more than 3 μm, more than 4 μm, or more than 5 μm. In addition, the thickness of the adhesive layer 12 described here refers to the thickness after curing.

[0037] The high molecular weight resin component contained in the adhesive layer 12 may include, for example, at least one resin selected from the group consisting of acrylic rubber, polyimide and phenoxy resin. The high molecular weight resin component may have a reactive group such as an epoxy group. The weight average molecular weight (based on the standard polystyrene conversion value of the GPC method) of the high molecular weight resin component may be 100,000 to 3,000,000. The content of the high molecular weight resin component may be 30 to 80 parts by mass relative to 10 parts by mass of the total mass of the adhesive layer 12.

[0038] The thermosetting component contained in the adhesive layer 12 is a compound having a reactive group that forms a crosslinked structure by self-polymerization and / or reaction with a curing agent. The thermosetting component may include, for example, at least one selected from the group consisting of epoxy resin, bismaleimide resin, triazine resin, and phenolic resin. The content of the thermosetting component may be 1 to 30 parts by mass relative to 100 parts by mass of the adhesive layer 12.

[0039] The thermosetting adhesive constituting the adhesive layer 12 may contain other components as needed. Examples of other components include a curing agent that reacts with the thermosetting component, a curing accelerator that promotes the reaction between the thermosetting component and the curing agent, a coupling agent (e.g., a silane coupling agent), and a filler (e.g., silica).

[0040] The filler contained in the adhesive layer 12 can be an inorganic filler. Specific examples of inorganic fillers include aluminum hydroxide, magnesium hydroxide, calcium carbonate, magnesium carbonate, calcium silicate, magnesium silicate, calcium oxide, magnesium oxide, aluminum oxide, aluminum nitride, aluminum borate whisker, boron nitride, crystalline silica, amorphous silica, etc. These can be used alone or in combination of two or more. Based on the total amount of the adhesive layer 12 (adhesive) before curing, the content of the filler contained in the adhesive layer 12 can be 50% by mass to 95% by mass. In addition, based on the total amount of the adhesive layer 12 (adhesive) before curing, the content of the filler contained in the adhesive layer 12 is preferably 60% by mass or more, more preferably 70% by mass or more, particularly preferably 80% by mass or more, and preferably 80% by mass to 95% by mass.

[0041] Furthermore, in step (a), a carrier 20 is prepared. The carrier 20 can be, for example, a silicon carrier or the like. The silicon carrier can be single crystal silicon or polycrystalline silicon. The carrier 20 has, for example, a thickness of 0.6 to 1.1 mm and a flatness with an average roughness of 50 nm or less. The carrier 20 is, for example, wafer-shaped or plate-shaped, and is not particularly limited. For example, it can be a circular wafer with a diameter of 200 mm, a diameter of 300 mm, or a diameter of 450 mm, or a rectangular plate with a side of 200 to 700 mm or less. As the carrier 20, a prepreg without copper foil can be used.

[0042] Then, if the preparation of the plurality of semiconductor chips 10 and the carrier 20 is completed, Figure 2 As shown in (b), the plurality of semiconductor chips 10 are fixed to the first carrier surface 20a of the carrier 20 in a manner such that the connection terminals 10c of the plurality of semiconductor chips 10 face the opposite side to the carrier 20 (in a so-called face-up state). This fixing is performed by attaching each semiconductor chip 10 to the carrier 20 through the adhesive layer 12 before curing, and then curing the adhesive layer 12 attached to each semiconductor chip 10. Since this fixing is strong, the semiconductor chip 10 cannot move after being fixed to the first carrier surface 20a of the carrier 20. In addition, the surface of the carrier 20 opposite to the first carrier surface 20a is the second carrier surface 20b.

[0043] Then, if the semiconductor chip 10 is fixed to the carrier 20, Figure 2As shown in (c), the plurality of semiconductor chips 10 on the carrier 20 are sealed by a sealing material in a manner covering the plurality of semiconductor chips 10. The sealing based on the sealing material can be performed, for example, by molding with a mold. In the manufacturing method involved in this embodiment, the semiconductor chip 10 is firmly fixed to the carrier 20 by the adhesive layer 12, so even when the sealing material is sealed with a mold molding machine, the semiconductor chip 10 will not be offset (chip displacement). Thus, a sealing material layer 30 covering the semiconductor chip 10 is formed.

[0044] The sealing material used as the sealing material layer 30 can be, for example, a sealing material containing epoxy resin, or it can contain a curable resin component and an inorganic filler. Based on the total amount of the sealing material before curing, the content of the inorganic filler in the sealing material can be 50% by mass or more. Based on the total amount of the sealing material before curing, the content of the inorganic filler in the sealing material is preferably 60% by mass or more, more preferably 70% by mass or more, and particularly preferably 80% by mass or more. As an example, based on the total amount of the sealing material before curing, the content of the inorganic filler in the sealing material can be 60% by mass to 90% by mass. The filler contained in the sealing material layer 30 can be an inorganic filler. As a specific example of an inorganic filler, for example, aluminum hydroxide, magnesium hydroxide, calcium carbonate, magnesium carbonate, calcium silicate, magnesium silicate, calcium oxide, magnesium oxide, aluminum oxide, aluminum nitride, aluminum borate whisker, boron nitride, crystalline silica, amorphous silica, etc. can be cited. These can be used alone or in combination of two or more.

[0045] Then, if the semiconductor chip 10 is sealed with a sealing material, Figure 3 As shown in (a), the sealing material layer 30 is ground until the connection terminal 10c (first chip surface 10a) of the semiconductor chip 10 is exposed, and is set as the sealing material layer 30A. In this grinding process, the sealing material layer 30 can be ground to a grinding amount of, for example, 30 μm or more. In addition, the thickness of the ground sealing material layer 30A can be 50 μm or more, 100 μm or more, or 150 μm or more. Through the above, in step (a), a stacked body T1 is formed in which each of the plurality of semiconductor chips 10 is fixed to the carrier 20 via the adhesive layer 12.

[0046] In step (b), if Figure 3 As shown in (b), a redistribution layer 40 connected to each connection terminal 10c of the plurality of semiconductor chips 10 is formed. In the process of forming the redistribution layer 40, the distance between the wirings as the conductor parts is gradually widened as they are away from the semiconductor chip 10 (as they go upward in the figure). Figure 3In the example shown in (b), the redistribution layer 40 is formed on the first chip surface 10a of the plurality of semiconductor chips 10 and the surface of the sealing material layer 30A. In addition, the redistribution layer 40 is formed using a conventional method, so a detailed description is omitted. Through the above, a stacked body T2 provided with the redistribution layer 40 is formed.

[0047] In step (c), once the redistribution layer 40 is formed, the redistribution layer 40 is protected by a BG tape 45 (back grinding tape) or the like, and the carrier 20 in the stacked body T2 is ground from the second carrier surface 20b toward the first carrier surface 20a. In this grinding step, first, Figure 4 As shown in (a) and (b), the carrier 20 is roughly ground from the second carrier surface 20b toward the first carrier surface 20a by the first grindstone 50. The first grindstone 50 is, for example, a grindstone with a grain size of ﹟200 to ﹟1000. During the rough grinding, the carrier 20 is first scraped, and then the surface portion of the adhesive layer 12 and the sealing material layer 30A (the region on the same layer as the adhesive layer 12) is scraped. At this time, the grinding can be performed until the second chip surface 10b of the semiconductor chip 10 is exposed, or it can be performed until the second chip surface 10b of the semiconductor chip 10 is about to be exposed. In addition, when grinding the carrier 20 made of silicon, the silicon mud (shavings) ground by the rough grinding can be mainly recovered and reused.

[0048] Next, if the second chip surface 10b of the semiconductor chip 10 is about to be exposed or exposed by rough grinding, Figure 4 As shown in (c), the carrier 20A that has been roughly ground is finish-ground with a second grindstone 55 having a higher grain size than the first grindstone 50. The second grindstone 55 has a grain size of ﹟2000 to ﹟6000. In the finish-ground process, the second chip surface 10b of the semiconductor chip 10 and the surface of the sealing material layer 30A are ground. Thus, the cleanliness of the second chip surface 10b of the semiconductor chip 10 sealed in the sealing material layer 30A is improved. By the above, a stacked body T3 containing a plurality of semiconductor chips 10 provided with a redistribution layer 40 is formed.

[0049] In step (d), the laminated body T3 of the scraped carrier 20 is singulated to obtain a semiconductor element having the semiconductor chip 10. In addition, bumps may be mounted on the redistribution layer 40 before singulation. Figure 1 The semiconductor component 1 is shown.

[0050] As described above, in the method for manufacturing a semiconductor element according to the present embodiment, a plurality of semiconductor chips 10 are fixed to a carrier 20 by means of an adhesive layer 12. In this way, the semiconductor chip 10 is firmly fixed to the carrier 20 by means of the adhesive layer 12 which is not temporarily fixed but is formally fixed. In this case, the positional displacement of the semiconductor chip 10 can be reliably suppressed. Furthermore, in the method for manufacturing a semiconductor element, in the grinding step, the carrier 20 is scraped to expose the second chip surface 10b which is opposite to the first chip surface 10a of the plurality of semiconductor chips 10 on which the redistribution layer 40 is provided. In this case, the carrier 20 is scraped, so that no resin residue or the like remains, and the cleanliness of the chip surface can be improved.

[0051] In the method for manufacturing a semiconductor element according to the present embodiment, the adhesive layer 12 is a layer formed by curing a thermosetting adhesive, and can be provided corresponding to each of the plurality of semiconductor chips 10. Thus, when grinding the carrier 20, the adhesive layer 12 can be easily ground.

[0052] In the method for manufacturing a semiconductor device according to the present embodiment, the thickness of the adhesive layer 12 can be set to 50 μm or less. In this case, when the carrier 20 is ground, the adhesive layer 12 can be easily ground.

[0053] In the method for manufacturing a semiconductor element according to the present embodiment, the adhesive layer 12 contains a curable resin component and an inorganic filler, and the content of the inorganic filler can be set to 50% to 95% by mass based on the total amount of the adhesive before curing of the adhesive layer 12. In this case, when grinding the carrier 20, the adhesive layer 12 can be easily ground.

[0054] In the method for manufacturing a semiconductor element according to the present embodiment, the step of preparing the stacked body T1 includes the following steps: fixing each of the plurality of semiconductor chips 10 on the carrier 20 with the adhesive layer 12; and sealing with a sealing material in a manner covering the plurality of semiconductor chips 10 on the carrier 20 to form a sealing material layer 30. The sealing material contains a curable resin component and an inorganic filler, and the content of the inorganic filler in the sealing material can be 50% by mass or more based on the total amount of the sealing material before curing. In this case, the grinding of the sealing material layer 30 can be performed reliably.

[0055] In the method for manufacturing a semiconductor element according to the present embodiment, the step of preparing the stacked body T1 may further include a step of grinding the sealing material layer 30 covering the plurality of semiconductor chips 10 until the first chip surfaces 10 a of the plurality of semiconductor chips 10 are exposed after the sealing step.

[0056] In the method for manufacturing a semiconductor element according to the present embodiment, the step of grinding the carrier 20 includes the following steps: rough grinding the second carrier surface 20b of the carrier 20 with the first grindstone 50; and finish grinding the roughly ground carrier 20A with the second grindstone 55 having a higher grain size than the first grindstone 50. The grinding speed of the carrier 20 can be increased by the rough grinding, and the finish of the ground surface can be improved by the finish grinding. The first grindstone may be a grindstone with a grain size of ﹟200 to ﹟1000, and the second grindstone may be a grindstone with a grain size of ﹟2000 to ﹟6000. Thus, the grinding speed can be increased and the finish accuracy of the ground surface can be improved more reliably. In addition, in the rough grinding step, at least a portion of the carrier 20 and the adhesive layer 12 can be scraped by the first grindstone 50. In the finish grinding step, the sealing material layer 30A and the second chip surface 10b of the semiconductor chip 10 can be ground with the second grindstone 55. This can more reliably improve the grinding speed and the finish grinding accuracy of the ground surface.

[0057] In the method for manufacturing a semiconductor element according to the present embodiment, the carrier 20 may be a silicon carrier. The grinding step may further include a step of recovering the ground silicon sludge for reuse. In this case, the silicon used can be reused, and the manufacturing method can be environmentally friendly.

[0058] As mentioned above, the manufacturing method of the semiconductor element which concerns on one embodiment of this invention was demonstrated, but this invention is not limited to the said embodiment, It can change suitably within the range which does not deviate from the summary.

[0059] Explanation of symbols

[0060] 1-semiconductor element, 10-semiconductor chip, 10a-first chip surface, 10b-second chip surface, 10c-connecting terminal, 12-adhesive layer, 20, 20A-carrier, 20a-first carrier surface, 20b-second carrier surface, 30, 30A-sealing material layer, 40-rewiring layer, 50-first grindstone, 55-second grindstone, T1, T2-laminated body.

Claims

1. A method for manufacturing a semiconductor element, comprising the following steps: preparing a stacked body in which each of a plurality of semiconductor chips is fixed on a carrier via an adhesive layer, in, The connection terminals of the plurality of semiconductor chips are fixed to a first carrier surface of the carrier in a manner facing the opposite side of the carrier; forming a redistribution layer connected to the connection terminals of the plurality of semiconductor chips; and grinding the carrier in the stacked body from a second carrier surface opposite to the first carrier surface toward the first carrier surface, In the grinding step, the carrier and the adhesive layer are scraped off to expose second chip surfaces of the plurality of semiconductor chips that are opposite to first chip surfaces on which the redistribution layer is provided.

2. The method for manufacturing a semiconductor device according to claim 1, in, The adhesive layer is a layer formed by curing a thermosetting adhesive, and is provided corresponding to each of the plurality of semiconductor chips.

3. The method for manufacturing a semiconductor element according to claim 1 or 2, in, The adhesive layer has a thickness of 50 μm or less.

4. The method for manufacturing a semiconductor device according to claim 3, in, The adhesive layer has a thickness of 20 μm or less.

5. The method for manufacturing a semiconductor element according to any one of claims 1 to 4, in, The adhesive layer contains a curable resin component and an inorganic filler. The content of the inorganic filler is 50% to 95% by mass based on the total amount of the adhesive before the adhesive layer is cured.

6. The method for manufacturing a semiconductor device according to claim 5, in, The content of the inorganic filler is 80 mass % to 95 mass % based on the total amount of the adhesive before the adhesive layer is cured.

7. The method for manufacturing a semiconductor element according to any one of claims 1 to 6, in, The step of preparing the laminate comprises the following steps: fixing each of the plurality of semiconductor chips to the carrier using the adhesive layer; and The plurality of semiconductor chips on the carrier are sealed with a sealing material to form a sealing material layer.

8. The method for manufacturing a semiconductor device according to claim 7, in, The sealing material contains a curable resin component and an inorganic filler. The content of the inorganic filler in the sealing material is 50% by mass or more based on the total amount of the sealing material.

9. The method for manufacturing a semiconductor element according to claim 7 or 8, in, The step of preparing the laminate further comprises the following steps: After the step of forming the sealing material layer, the sealing material layer covering the plurality of semiconductor chips is ground until the first chip surfaces of the plurality of semiconductor chips are exposed.

10. The method for manufacturing a semiconductor element according to any one of claims 1 to 9, in, The process of grinding the carrier includes the following steps: Roughly grinding the second carrier surface of the carrier with a first grindstone; and The roughly ground carrier is finish-ground using a second grindstone having a higher grain size than the first grindstone.

11. The method for manufacturing a semiconductor device according to claim 10, in, The first grinding stone is a grinding stone with a particle size of ﹟200 to ﹟1000, The second grinding stone has a grain size of ﹟2000 to ﹟6000.

12. The method for manufacturing a semiconductor element according to claim 10 or 11, in, In the rough grinding step, at least a portion of the carrier and the adhesive layer is scraped by the first grindstone.

13. The method for manufacturing a semiconductor element according to any one of claims 10 to 12, in, In the finish grinding step, the sealing material layer and the second chip surface of the semiconductor chip are ground using the second grindstone.

14. The method for manufacturing a semiconductor element according to any one of claims 1 to 13, in, The carrier is a silicon carrier, The grinding step further includes a step of recovering the ground silicon sludge for reuse.

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