Semiconductor device

Abstract

The present invention provides a semiconductor device (10) comprising a metal oxide layer (130) comprising aluminum over an insulating surface and an oxide semiconductor layer (140) over the metal oxide layer, the oxide semiconductor layer comprising: a first crystalline region (144) in contact with the metal oxide layer; and a second crystal region (145) that is in contact with the first crystal region and has a larger area than the first crystal region in a cross-sectional view of the oxide semiconductor layer. The first crystal region and the second crystal region differ from each other in crystal structure and / or crystal orientation. The oxide semiconductor layer may contain two or more metals including indium, and the ratio of indium to the two or more metals in the oxide semiconductor layer may be 50% or more.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device. In particular, one embodiment of the present invention relates to a semiconductor device using an oxide semiconductor for a channel. Background Art

[0002] In recent years, the development of semiconductor devices using oxide semiconductors for channels instead of amorphous silicon, low-temperature polycrystalline silicon, and single-crystal silicon has been continuously developed (see, for example, Patent Documents 1 to 6). Semiconductor devices using oxide semiconductors for channels have simple structures similar to semiconductor devices using amorphous silicon for channels and can be manufactured by low-temperature processes. In addition, semiconductor devices using oxide semiconductors for channels are known to have higher mobility than semiconductor devices using amorphous silicon for channels.

[0003] In order to make a semiconductor device using an oxide semiconductor for a channel operate stably, it is important to supply oxygen to the oxide semiconductor layer during its manufacturing process to reduce oxygen vacancies formed in the oxide semiconductor layer. For example, as one method of supplying oxygen to the oxide semiconductor layer, a technology of forming an oxide semiconductor layer under the condition that the insulating layer contains more oxygen is disclosed.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2021-141338

[0007] Patent Document 2: Japanese Patent Application Publication No. 2014-099601

[0008] Patent Document 3: Japanese Patent Application Publication No. 2021-153196

[0009] Patent Document 4: Japanese Patent Application Publication No. 2018-006730

[0010] Patent Document 5: Japanese Patent Application Publication No. 2016-184771

[0011] Patent Document 6: Japanese Patent Application Publication No. 2021-108405 Summary of the invention

[0012] Problems to be solved by the invention

[0013] However, the insulating layer formed under the condition of containing more oxygen will contain many defects. In this case, since the electrons in the defects of the insulating layer are captured, the electrical characteristics of the semiconductor device or the characteristics in the reliability test will change. On the other hand, if the insulating layer has fewer defects, the oxygen contained in the insulating layer is not much, and oxygen cannot be fully supplied from the insulating layer to the oxide semiconductor layer. Therefore, it is required to realize a structure that can reduce the defects in the insulating layer that cause the characteristics of the semiconductor device to change and repair the oxygen defects formed in the oxide semiconductor layer.

[0014] In addition, it is known that a semiconductor device with high mobility can be obtained by relatively increasing the ratio of indium contained in the oxide semiconductor layer. However, when the ratio of indium contained in the oxide semiconductor layer is high, oxygen vacancies are easily formed in the oxide semiconductor layer. Therefore, in order to achieve high mobility while maintaining high reliability, it is necessary to work on the structure of the oxide semiconductor layer and the insulating layer around the oxide semiconductor layer.

[0015] One object of one embodiment of the present invention is to provide a semiconductor device having high mobility and high reliability.

[0016] Means for solving problems

[0017] A semiconductor device according to one embodiment of the present invention includes: an oxide metal layer containing aluminum on an insulating surface; and an oxide semiconductor layer on the oxide metal layer, the oxide semiconductor layer including a first crystalline region connected to the oxide metal layer; and a second crystalline region connected to the first crystalline region and having an area larger than the first crystalline region when the oxide semiconductor layer is cross-sectionally observed, the first crystalline region and the second crystalline region having at least one of a crystal structure and a crystal orientation different from each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a cross-sectional view showing the structure of a semiconductor device according to one embodiment of the present invention.

[0019] Figure 2 It is a plan view showing the structure of a semiconductor device according to one embodiment of the present invention.

[0020] Figure 3 Schematic cross-sectional view illustrating the crystal structure of an oxide semiconductor layer of a semiconductor device according to an embodiment of the present invention.

[0021] Figure 4 Schematic cross-sectional view illustrating the crystal structure of an oxide semiconductor layer of a semiconductor device according to an embodiment of the present invention.

[0022] Figure 5It is a flowchart showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0023] Figure 6 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0024] Figure 7 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0025] Figure 8 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0026] Fig. 9 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0027] Fig.10 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0028] Fig.11 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0029] Fig.12 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0030] Fig.13 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0031] Fig.14 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0032] Fig.15 It is a plan view schematically showing a display device according to one embodiment of the present invention.

[0033] Fig.16 This is a block diagram showing a circuit configuration of a display device according to an embodiment of the present invention.

[0034] Fig.17 : is a circuit diagram showing a pixel circuit of a display device according to an embodiment of the present invention.

[0035] Fig.18 It is a cross-sectional view schematically showing a display device according to an embodiment of the present invention.

[0036] Fig.19 It is a plan view of a pixel electrode and a common electrode of a display device according to an embodiment of the present invention.

[0037] Fig. 20 : is a circuit diagram showing a pixel circuit of a display device according to an embodiment of the present invention.

[0038] Fig.21 It is a cross-sectional view schematically showing a display device according to an embodiment of the present invention.

[0039] Fig. 22 It is a graph showing the electrical characteristics of the semiconductor device of the example.

[0040] Fig.23 It is a figure which shows the reliability test of the semiconductor device of Example.

[0041] Fig.24A This is a cross-sectional TEM image of the semiconductor device of the example.

[0042] Fig. 24B It is used to illustrate Fig.24A Schematic diagram of a cross-sectional TEM image.

[0043] Fig.25 This is an electron diffraction image of the semiconductor device of the example.

[0044] Fig.26 This is an electron diffraction image of the semiconductor device of the example.

[0045] Fig. 27 It is a graph showing the electrical characteristics of a semiconductor device of a comparative example.

[0046] Fig.28 It is a diagram showing a reliability test of a semiconductor device of a comparative example.

[0047] Fig.29 This is a cross-sectional TEM image of a semiconductor device of a comparative example.

[0048] Fig.30 This is an electron diffraction image of a semiconductor device of a comparative example.

[0049] Fig.31 This is an electron diffraction image of a semiconductor device of a comparative example. DETAILED DESCRIPTION

[0050] Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings. The following disclosure is only an example. A person skilled in the art can appropriately change the configuration of the embodiment while maintaining the gist of the invention so that the configuration that can be easily conceived is of course included in the scope of the present invention. With respect to the accompanying drawings, in order to make the description clearer, the width, thickness, shape, etc. of each part are sometimes schematically indicated compared to the actual method. However, the shape shown in the figure is only an example and does not limit the interpretation of the present invention. In this specification and each figure, the same figure mark is marked for the same configuration as that described in the accompanying drawings that have appeared, and the detailed description is sometimes appropriately omitted.

[0051] In each embodiment of the present invention, the direction from the substrate toward the oxide semiconductor layer is referred to as up or above. Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as down or below. Thus, for ease of explanation, the above or below phrases are used for explanation, but for example, the up-and-down relationship between the substrate and the oxide semiconductor layer may be configured in a different direction than that shown in the figure. In the following description, for example, the expression "oxide semiconductor layer on the substrate" is only used to illustrate the up-and-down relationship between the substrate and the oxide semiconductor layer as described above, and other components may be configured between the substrate and the oxide semiconductor layer. Above or below means the stacking order in a structure having multiple layers stacked, and in the case of a pixel electrode described as above a transistor, it may also be a positional relationship in which the transistor and the pixel electrode do not overlap when viewed from above. On the other hand, in the case of a pixel electrode described as vertically above a transistor, it means a positional relationship in which the transistor and the pixel electrode overlap when viewed from above.

[0052] A "display device" refers to a structure that uses an electro-optical layer to display an image. For example, the term display device sometimes refers to a display panel including an electro-optical layer, or sometimes refers to a structure that is equipped with other optical components (such as polarization components, backlight sources, touch panels, etc.) relative to a display unit. As long as there is no technical contradiction, the "electro-optical layer" may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer. Therefore, with respect to the embodiments described later, a liquid crystal display device including a liquid crystal layer and an organic EL display device including an organic EL layer are exemplified as display devices for explanation, but the structure in this embodiment can be applied to display devices including the above-mentioned other electro-optical layers.

[0053] In this specification, unless otherwise specified, expressions such as “α includes A, B, or C”, “α includes any one of A, B, and C”, and “α includes one selected from the group consisting of A, B, and C” do not exclude the case where α includes a plurality of combinations of A to C. In addition, the above expressions do not exclude the case where α includes other elements.

[0054] It should be noted that the following embodiments can be combined with each other as long as no technical contradiction occurs.

[0055] <First embodiment>

[0056] Reference Figure 1 to Figure 14 For example, the semiconductor device according to the embodiment described below can be used not only as a transistor for a display device but also as an integrated circuit (IC) such as a microprocessor (Micro-Processing Unit: MPU) or a memory circuit.

[0057] [Configuration of Semiconductor Device 10]

[0058] Reference Figure 1 and Figure 2 Next, a configuration of a semiconductor device 10 according to an embodiment of the present invention will be described. Figure 1 2 is a cross-sectional view showing the structure of a semiconductor device 10 according to an embodiment of the present invention. Figure 2 It is a plan view showing the structure of a semiconductor device 10 according to an embodiment of the present invention.

[0059] like Figure 1 As shown, the semiconductor device 10 is provided on a substrate 100. The semiconductor device 10 includes a gate electrode 105, gate insulating layers 110 and 120, an oxide metal layer 130, an oxide semiconductor layer 140, a gate insulating layer 150, a gate electrode 160, insulating layers 170 and 180, a source electrode 201, and a drain electrode 203. It should be noted that when the source electrode 201 and the drain electrode 203 are not particularly distinguished, they are sometimes collectively referred to as a source / drain electrode 200.

[0060] The gate electrode 105 is provided on the substrate 100. The gate insulating layer 110 and the gate insulating layer 120 are provided on the substrate 100 and the gate electrode 105. The metal oxide layer 130 is provided on the gate insulating layer 120. The metal oxide layer 130 is in contact with the gate insulating layer 120. The oxide semiconductor layer 140 is provided on the metal oxide layer 130. The oxide semiconductor layer 140 is in contact with the metal oxide layer 130. The surface of the main surface of the oxide semiconductor layer 140 that is in contact with the metal oxide layer 130 is referred to as a lower surface 142. The side surface of the metal oxide layer 130 is substantially consistent with the side surface of the oxide semiconductor layer 140.

[0061] In this embodiment, no semiconductor layer or oxide semiconductor layer is provided between the metal oxide layer 130 and the substrate 100 .

[0062] exist Figure 1In the embodiment, the side surface of the metal oxide layer 130 and the side surface of the oxide semiconductor layer 140 are arranged in a straight line, but the present invention is not limited to this configuration. The angle of the side surface of the metal oxide layer 130 relative to the main surface of the substrate 100 may be different from the angle of the side surface of the oxide semiconductor layer 140 relative to the main surface of the substrate 100. The side surface of at least one of the metal oxide layer 130 and the oxide semiconductor layer 140 may be curved.

[0063] The gate electrode 160 is opposite to the oxide semiconductor layer 140. The gate insulating layer 150 is provided between the oxide semiconductor layer 140 and the gate electrode 160. The gate insulating layer 150 is in contact with the oxide semiconductor layer 140. The surface in contact with the gate insulating layer 150 among the main surfaces of the oxide semiconductor layer 140 is referred to as an upper surface 141. The surface between the upper surface 141 and the lower surface 142 is referred to as a side surface 143. The insulating layers 170 and 180 are provided on the gate insulating layer 150 and the gate electrode 160. The insulating layers 170 and 180 are provided with openings 171 and 173 reaching the oxide semiconductor layer 140. The source electrode 201 is provided inside the opening 171. The source electrode 201 is in contact with the oxide semiconductor layer 140 at the bottom of the opening 171. The drain electrode 203 is provided inside the opening 173. The drain electrode 203 is in contact with the oxide semiconductor layer 140 at the bottom of the opening 173.

[0064] The gate electrode 105 has a function as a bottom gate of the semiconductor device 10 and a function as a light shielding film for the oxide semiconductor layer 140. The gate insulating layer 110 has a function as a barrier film for shielding impurities diffusing from the substrate 100 toward the oxide semiconductor layer 140. The gate insulating layers 110 and 120 have a function as a gate insulating layer for the bottom gate. The metal oxide layer 130 is a layer containing a metal oxide having aluminum as a main component, and has a function as a gas barrier film for shielding gases such as oxygen and hydrogen.

[0065] The oxide semiconductor layer 140 is divided into a source region S, a drain region D, and a channel region CH. The channel region CH is a region vertically below the gate electrode 160 in the oxide semiconductor layer 140. The source region S is a region of the oxide semiconductor layer 140 that does not overlap with the gate electrode 160 and is closer to the source electrode 201 than the channel region CH. The drain region D is a region of the oxide semiconductor layer 140 that does not overlap with the gate electrode 160 and is closer to the drain electrode 203 than the channel region CH. The oxide semiconductor layer 140 in the channel region CH has physical properties as a semiconductor. The oxide semiconductor layer 140 in the source region S and the drain region D has physical properties as a conductor.

[0066] The gate electrode 160 has the function of serving as the top gate of the semiconductor device 10 and as a light shielding film for the oxide semiconductor layer 140. The gate insulating layer 150 has the function of serving as a gate insulating layer for the top gate and has the function of releasing oxygen through heat treatment in the manufacturing process. The insulating layers 170 and 180 have the function of insulating the gate electrode 160 from the source / drain electrode 200 to reduce the parasitic capacitance therebetween. The operation of the semiconductor device 10 is mainly controlled by the voltage supplied to the gate electrode 160. An auxiliary voltage is supplied to the gate electrode 105. However, in the case where the gate electrode 105 is used only as a light shielding film, it is also possible to place the gate electrode 105 in a floating state instead of supplying a specific voltage to the gate electrode 105. That is, the gate electrode 105 may also be simply referred to as a "light shielding film".

[0067] In this embodiment, a dual-gate transistor in which gate electrodes are provided both above and below the oxide semiconductor layer is used as an example of the semiconductor device 10, but the present invention is not limited to this configuration. For example, a bottom-gate transistor in which the gate electrode is provided only below the oxide semiconductor layer or a top-gate transistor in which the gate electrode is provided only above the oxide semiconductor layer may be used as the semiconductor device 10. The above configuration is only one embodiment, and the present invention is not limited to the above configuration.

[0068] like Figure 2 As shown, in a top view, the top view pattern of the metal oxide layer 130 is substantially the same as the top view pattern of the oxide semiconductor layer 140. Figure 1 and Figure 2 , the lower surface 142 of the oxide semiconductor layer 140 is covered by the oxide metal layer 130. In particular, in the present embodiment, the entire lower surface 142 of the oxide semiconductor layer 140 is covered by the oxide metal layer 130. In the D1 direction, the width of the gate electrode 105 is greater than the width of the gate electrode 160. The D1 direction is a direction connecting the source electrode 201 and the drain electrode 203, and is a direction indicating the channel length L of the semiconductor device 10. Specifically, the length in the D1 direction in the region (channel region CH) where the oxide semiconductor layer 140 and the gate electrode 160 overlap is the channel length L, and the width in the D2 direction of the channel region CH is the channel width W.

[0069] In this embodiment, a configuration in which the entire lower surface 142 of the oxide semiconductor layer 140 is covered by the oxide metal layer 130 is exemplified, but the present invention is not limited to this configuration. For example, a portion of the lower surface 142 of the oxide semiconductor layer 140 may not be in contact with the oxide metal layer 130. For example, the entire lower surface 142 of the oxide semiconductor layer 140 in the channel region CH may be covered by the oxide metal layer 130, and the entire or a portion of the lower surface 142 of the oxide semiconductor layer 140 in the source region S and the drain region D may not be covered by the oxide metal layer 130. That is, the entire or a portion of the lower surface 142 of the oxide semiconductor layer 140 in the source region S and the drain region D may not be in contact with the oxide metal layer 130. However, in the above configuration, a portion of the lower surface 142 of the oxide semiconductor layer 140 in the channel region CH may not be covered by the oxide metal layer 130, and the other portion of the lower surface 142 may be in contact with the oxide metal layer 130.

[0070] In this embodiment, a configuration in which the gate insulating layer 150 is formed on the entire surface and the openings 171 and 173 are provided in the gate insulating layer 150 is exemplified, but the present invention is not limited to this configuration. The gate insulating layer 150 may also be patterned. For example, the gate insulating layer 150 may be patterned in such a manner that the oxide semiconductor layer 140 in the source region S and the drain region D is exposed. That is, the gate insulating layer 150 in the source region S and the drain region D may be removed, and the oxide semiconductor layer 140 may be in contact with the insulating layer 170 in these regions.

[0071] exist Figure 2 , the structure in which the source / drain electrode 200 does not overlap with the gate electrode 105 and the gate electrode 160 in a plan view is illustrated, but the present invention is not limited to this structure. For example, the source / drain electrode 200 may overlap with at least one of the gate electrode 105 and the gate electrode 160 in a plan view. The above structure is only one embodiment, and the present invention is not limited to the above structure.

[0072] [Material of Each Component of Semiconductor Device 10]

[0073] As the substrate 100, a glass substrate, a quartz substrate, a sapphire substrate, or other light-transmitting rigid substrate can be used. When the substrate 100 needs to be flexible, a substrate containing resin, such as a polyimide substrate, an acrylic substrate, a siloxane substrate, or a fluororesin substrate can be used as the substrate 100. When a substrate containing resin is used as the substrate 100, impurities can be introduced into the above-mentioned resin in order to improve the heat resistance of the substrate 100. In particular, when the semiconductor device 10 is a top-emitting display, since the substrate 100 does not need to be transparent, impurities that reduce the transparency of the substrate 100 can also be used. When the semiconductor device 10 is used in an integrated circuit that is not a display device, as the substrate 100, a semiconductor substrate such as a silicon substrate, a silicon carbide substrate, or a compound semiconductor substrate, or a substrate that is not light-transmitting, such as a conductive substrate such as a stainless steel substrate, can be used.

[0074] As the gate electrode 105, the gate electrode 160, and the source / drain electrode 200, a common metal material can be used. For example, as these members, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys thereof or compounds thereof can be used. As the gate electrode 105, the gate electrode 160, and the source / drain electrode 200, the above-mentioned materials can be used in a single layer form, or in a stacked form.

[0075] It should be noted that the gate electrode 160 and the source / drain electrode 200 may be made of the same metal material or different metal materials. For example, the gate electrode 160 may not contain aluminum, while the source / drain electrode 200 may contain aluminum.

[0076] A common insulating material is used as the gate insulating layers 110 and 120 and the insulating layers 170 and 180. For example, silicon oxide (SiO x ), silicon oxide nitride (SiO x N y ), silicon nitride (SiN x ), silicon oxide nitride (SiN x O y ), aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), aluminum nitride (AlN x O y ), aluminum nitride (AlN x ) and other inorganic insulating layers.

[0077] The above SiO x N yand AlO x N y It is a silicon compound or aluminum compound containing nitrogen (N) at a ratio (x>y) less than oxygen (O). x O y and AlN x O y These are silicon compounds and aluminum compounds containing oxygen at a ratio smaller than that of nitrogen (x>y).

[0078] As the gate insulating layer 150, an insulating layer containing oxygen among the above insulating layers can be used. For example, as the gate insulating layer 150, silicon oxide (SiO x ), silicon oxide nitride (SiO x N y ) and other inorganic insulating layers.

[0079] An insulating layer having a function of releasing oxygen by heat treatment is used as the gate insulating layer 120. For example, the temperature of the heat treatment for releasing oxygen from the gate insulating layer 120 is 600° C. or less, 500° C. or less, 450° C. or less, or 400° C. or less. That is, for example, when a glass substrate is used as the substrate 100, the gate insulating layer 120 releases oxygen at the heat treatment temperature performed in the manufacturing process of the semiconductor device 10.

[0080] As the gate insulating layer 150, an insulating layer with few defects is used. For example, when the composition ratio of oxygen in the gate insulating layer 150 is compared with the composition ratio of oxygen in an insulating layer having the same composition as the gate insulating layer 150 (hereinafter referred to as "other insulating layer"), the composition ratio of oxygen in the gate insulating layer 150 is closer to the stoichiometric ratio for the insulating layer than the composition ratio of oxygen in the other insulating layer. Specifically, silicon oxide (SiO x ), the oxygen composition ratio of silicon oxide used as the gate insulating layer 150 is closer to the stoichiometric ratio of silicon oxide than the oxygen composition ratio of silicon oxide used as the insulating layer 180. For example, as the gate insulating layer 150, a layer in which no defects are observed when evaluated by an electron spin resonance method (ESR) may be used.

[0081] As the metal oxide layer 130 and the metal oxide layer 190 used in the manufacturing process described later, a metal oxide containing aluminum as a main component is used. For example, aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), aluminum nitride (AlN x O y ), aluminum nitride (AlNx ) or other inorganic insulating layers. “A metal oxide layer mainly composed of aluminum” means that the ratio of aluminum contained in the metal oxide layer 130 (or metal oxide layer 190) is greater than 1% of the total metal oxide layer 130 (or metal oxide layer 190). The ratio of aluminum contained in the metal oxide layer 130 (or metal oxide layer 190) may also be greater than 5% and less than 70%, greater than 10% and less than 60%, or greater than 30% and less than 50% of the total metal oxide layer 130. The above ratio may be a mass ratio or a weight ratio.

[0082] At least a portion of the oxide semiconductor layer 140 is in contact with the metal oxide layer 130. Therefore, when OS annealing is performed, aluminum contained in the metal oxide layer 130 diffuses into the oxide semiconductor layer 140, and the details are described later. Therefore, the oxide semiconductor layer 140 includes a region with a high aluminum concentration near the interface between the metal oxide layer 130 and the oxide semiconductor layer 140. The aluminum concentration can be detected by, for example, SIMS (Secondary Ion Mass Spectrometry) analysis.

[0083] In addition, when the metal oxide layer 190 is formed on the gate insulating layer 150 and an oxidation annealing is performed, the aluminum contained in the metal oxide layer 190 diffuses into the gate insulating layer 150, and the details will be described later. Therefore, even if the metal oxide layer 190 is removed, the surface of the gate insulating layer 150 (the surface on the opposite side of the oxide semiconductor layer 140) includes a region with a high aluminum concentration.

[0084] As the oxide semiconductor layer 140, an oxide metal having semiconductor characteristics is used. For example, as the oxide semiconductor layer 140, an oxide semiconductor containing two or more metals including indium (In) is used. In the oxide semiconductor layer 140, the ratio of indium to the two or more metals is 50% or more. As the oxide semiconductor layer 140, in addition to indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium oxide (Zr), and lanthanide elements can also be used. As the oxide semiconductor layer 140, other elements other than the above can also be used.

[0085] The oxide semiconductor layer 140 has crystallinity. The crystalline oxide semiconductor layer 140 has less oxygen deficiency than the amorphous oxide semiconductor layer. The crystalline oxide semiconductor layer 140 may also include an amorphous region, but the proportion of the amorphous region in the oxide semiconductor layer 140 is smaller than the proportion of the crystalline region in the oxide semiconductor layer 140. For example, the proportion of the crystalline region in the oxide semiconductor layer 140 is 70% or more, preferably 80% or more, and more preferably 90% or more.

[0086] Here, refer to Figure 3 Next, the crystal structure of the oxide semiconductor layer 140 of the semiconductor device 10 according to one embodiment of the present invention will be described. Figure 3 1 is a schematic cross-sectional view illustrating the crystal structure of the oxide semiconductor layer 140 of the semiconductor device 10 according to the embodiment of the present invention.

[0087] like Figure 3 As shown, the oxide semiconductor layer 140 includes a first crystalline region 144 having a first crystal structure and a second crystalline region 145 having a second crystal structure. The first crystalline region 144 is formed only near the interface between the metal oxide layer 130 and the oxide semiconductor layer 140. That is, the first crystalline region 144 is formed in contact with the metal oxide layer 130 and does not exist at a position away from the metal oxide layer 130. In the oxide semiconductor layer 140, one first crystalline region 144 may be formed, or a plurality of first crystalline regions 144 may be formed. The second crystalline region 145 is in contact with the metal oxide layer 130 and the first crystalline region 144, and the second crystalline region 145 is formed in a manner covering the first crystalline region 144. In other words, in a cross-sectional observation of the oxide semiconductor layer 140, the first crystalline region 144 is surrounded by the metal oxide layer 130 and the second crystalline region 145, and a grain boundary is formed between the first crystalline region 144 and the second crystalline region 145.

[0088] As described above, the first crystal region 144 is formed only near the interface between the metal oxide layer 130 and the oxide semiconductor layer 140, and does not exist at a position away from the metal oxide layer 130, so the proportion of the first crystal region 144 in the oxide semiconductor layer 140 is significantly smaller than the proportion of the second crystal region 145 in the oxide semiconductor layer 140. In other words, in a cross-sectional view of the oxide semiconductor layer 140, the area of ​​the first crystal region 144 is significantly smaller than the area of ​​the second crystal region. That is, most of the oxide semiconductor layer 140 is formed by the second crystal region 145, and the crystal structure of the oxide semiconductor layer 140 is the same as the second crystal structure of the second crystal region 145.

[0089] The second crystal structure of the second crystalline region 145 is, for example, a pyroxenite structure, a corundum structure, a spinel structure or a homologous structure. The pyroxenite structure is one of the stable crystal structures of indium oxide. In addition, the corundum structure and the spinel structure are one of the stable crystal structures of aluminum oxide or gallium oxide structures. In addition, the homologous structure is one of the stable crystal structures of indium gallium zinc oxide. The second crystal structure varies according to the composition of the elements contained in the second crystalline region 145. It should be noted that, for homologous structures, the composition formula is expressed using a certain index m (m is a natural number), and various periodic structures can be used. Therefore, compared with the homologous structure, the second crystal structure is more preferably a pyroxenite structure, a corundum structure or a spinel structure. The first crystal structure of the first crystalline region 144 may be the same as or different from the second crystal structure of the second crystalline region 145. However, when the first crystal structure is the same as the second crystal structure, the crystal orientation of the first crystalline region 144 is different from the crystal orientation of the second crystalline region 145 under cross-sectional observation of the oxide semiconductor layer 140. That is, the oxide semiconductor layer 140 includes at least two regions (a first crystal region 144 and a second crystal region 145 ) having different crystallinity, and a grain boundary is formed between the first crystal region 144 and the second crystal region 145 .

[0090] The reason for forming the first crystalline region 144 in the oxide semiconductor layer 140 is as follows. As described above, when the oxide semiconductor layer 140 in contact with the metal oxide layer 130 is subjected to OS annealing, aluminum contained in the metal oxide layer 130 diffuses into the oxide semiconductor layer 140. The first crystalline region 144 is formed near the interface between the metal oxide layer 130 and the oxide semiconductor layer 140 using the diffused aluminum as a crystal nucleus. However, the diffusion rate of the diffused aluminum in the oxide semiconductor layer 140 is not so high, so the first crystalline region 144 does not grow crystals to a large extent. Therefore, the first crystalline region 144, which has grown to a certain size, is used as a crystal nucleus to form the second crystalline region 145. Therefore, the first crystalline region 144 contains aluminum diffused from the metal oxide layer 130, so the aluminum concentration of the first crystalline region 144 is greater than that of the second crystalline region 145. In addition, since the diffused aluminum is easily combined with oxygen, the conductivity of the first crystalline region 144 can also be smaller than that of the second crystalline region.

[0091] The crystalline oxide semiconductor layer has fewer oxygen vacancies than the amorphous oxide semiconductor layer, but the crystalline region of the oxide semiconductor layer also contains a lot of oxygen vacancies. Therefore, even for a crystalline oxide semiconductor layer, it is preferred to further reduce oxygen vacancies. In the oxide semiconductor layer 140, the second crystalline region 145 uses the first crystalline region 144 as a crystal nucleus for crystal growth, and the first crystalline region 144 functions as a so-called buffer region. Therefore, compared with the crystalline region obtained by direct crystal growth from the metal oxide layer 130 or the gate insulating layer 120, the oxygen vacancies in the second crystalline region 145 of the oxide semiconductor layer 140 are further reduced. In addition, since the first crystalline region 144 functions as a buffer region between the metal oxide layer 130 and the second crystalline region 145, the interface energy level density of the oxide semiconductor layer 140 is reduced.

[0092] It should be noted that the crystal structure of the oxide semiconductor layer 140 is not limited to Figure 3 Here, refer to Figure 4 Another crystal structure of the oxide semiconductor layer 140 of the semiconductor device 10 according to the embodiment of the present invention will be described. Figure 4 1 is a schematic cross-sectional view illustrating the crystal structure of the oxide semiconductor layer 140A of the semiconductor device 10 according to the embodiment of the present invention.

[0093] like Figure 4 As shown, the oxide semiconductor layer 140A includes a first crystalline region 144A having a first crystal structure and a second crystalline region 145A having a second crystal structure. The first crystalline region 144A contains aluminum diffused from the metal oxide layer 130 and is formed as a layer at the interface between the metal oxide layer 130 and the oxide semiconductor layer 140. That is, the second crystalline region 145A is not in contact with the metal oxide layer 130. In addition, in the film thickness direction of the oxide semiconductor layer, the film thickness of the second crystalline region 145A is greater than the film thickness of the first crystalline region 144A. In this case, since the first crystalline region 144A also functions as a buffer region (buffer layer), the oxygen vacancies in the second crystalline region 145A are reduced, and the interface energy level density of the oxide semiconductor layer 140A is reduced.

[0094] By making the ratio of indium in the oxide semiconductor layer greater than 50%, the oxide semiconductor layer has crystallinity. However, even if it is a crystalline oxide semiconductor layer, if oxygen vacancies are formed in the crystalline region of the oxide semiconductor layer, sufficient electrical properties and reliability cannot be obtained. In this embodiment, the oxide semiconductor layer 140 includes a first crystalline region 144 that functions as a buffer layer, and includes a second crystalline region 145 in which oxygen vacancies are reduced. Therefore, the oxygen vacancies and interface energy level density of the oxide semiconductor layer 140 are reduced, and the semiconductor device 10 has high mobility and high reliability.

[0095] It should be noted that in order to reduce oxygen vacancies in the second crystal region 145 of the oxide semiconductor layer 140 , it is important to perform not only OS annealing but also oxidation annealing. Therefore, the method for manufacturing the semiconductor device 10 will be described in detail below.

[0096] [Method of Manufacturing Semiconductor Device 10]

[0097] Reference Figures 5 to 14 A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described. Figure 5 It is a flowchart showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figure 6 to Figure 14 1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. In the following description of the manufacturing method, a method for manufacturing the semiconductor device 10 using aluminum oxide as the metal oxide layers 130 and 190 will be described.

[0098] like Figure 5 and Figure 6 As shown, a gate electrode 105 is formed on the substrate 100 as a bottom gate, and gate insulating layers 110 and 120 are formed on the gate electrode 105 ( Figure 3 The bottom GI / GE is formed in step S2001. For example, silicon nitride is formed as the gate insulating layer 110. For example, silicon oxide is formed as the gate insulating layer 120. The gate insulating layers 110 and 120 are formed by CVD (Chemical Vapor Deposition). Sometimes, one or both of the gate insulating layers 110 and 120 are referred to as the "first insulating layer".

[0099] By using silicon nitride as the gate insulating layer 110, the gate insulating layer 110 can block, for example, impurities diffusing from the substrate 100 side toward the oxide semiconductor layer 140. Silicon oxide used as the gate insulating layer 120 has a property of releasing oxygen by heat treatment.

[0100] like Figure 5 and Figure 7 As shown, a metal oxide layer 130 and an oxide semiconductor layer 140 are formed on the gate insulating layer 120 ( Figure 5 In this process, there is a case where gate insulating layers 110 and 120 are formed on the substrate 100 and a metal oxide layer 130 is formed on the gate insulating layers 110 and 120. Alternatively, there is a case where the metal oxide layer 130 is formed on the substrate 100 and an oxide semiconductor layer 140 is formed on the metal oxide layer 130. Specifically, the oxide semiconductor layer 140 is formed in contact with the metal oxide layer 130. The metal oxide layer 130 and the oxide semiconductor layer 140 are formed by sputtering or atomic layer deposition (ALD: Atomic Layer Deposition).

[0101] For example, the thickness of the metal oxide layer 130 is 1 nm to 100 nm, 1 nm to 50 nm, 1 nm to 30 nm or 1 nm to 10 nm. In this embodiment, aluminum oxide is used as the metal oxide layer 130. Aluminum oxide has a high barrier property against gas. In this embodiment, aluminum oxide used as the metal oxide layer 130 blocks hydrogen and oxygen released from the gate insulating layer 120 and inhibits the released hydrogen and oxygen from reaching the oxide semiconductor layer 140.

[0102] For example, the thickness of the oxide semiconductor layer 140 is 10 nm to 100 nm, 15 nm to 70 nm, or 20 nm to 40 nm. In this embodiment, an oxide containing indium (In) and gallium (Ga) is used as the oxide semiconductor layer 140. The oxide semiconductor layer 140 before the heat treatment (OS annealing) described later is amorphous.

[0103] When the oxide semiconductor layer 140 is crystallized by OS annealing described later, it is preferable that the oxide semiconductor layer 140 after film formation and before OS annealing is in an amorphous state (a state in which the crystalline component of the oxide semiconductor is small). That is, the film formation conditions of the oxide semiconductor layer 140 are preferably conditions under which the oxide semiconductor layer 140 immediately after film formation is not crystallized as much as possible. For example, when the oxide semiconductor layer 140 is formed by sputtering, the oxide semiconductor layer 140 is formed under a state in which the temperature of the film formation object (the substrate 100 and the structure formed thereon) is controlled.

[0104] When a film is formed on a film-forming object by sputtering, ions generated in the plasma and atoms recoiled from the sputtering target will collide with the film-forming object. Therefore, the temperature of the film-forming object will rise along with the film-forming process. If the temperature of the film-forming object rises during the film-forming process, the oxide semiconductor layer 140 contains microcrystals in the state just after the film is formed. Due to the microcrystals, the subsequent crystallization based on OS annealing is hindered. In order to control the temperature of the film-forming object as described above, the film can also be formed while cooling the film-forming object. For example, the film-forming object can also be cooled from the opposite side of the film-forming surface in a manner such that the temperature of the film-forming surface (surface) of the film-forming object (hereinafter referred to as "film-forming temperature") is below 100°C, below 70°C, below 50°C or below 30°C. By forming the oxide semiconductor layer 140 while cooling the film-forming object as described above, an oxide semiconductor layer 140 with a small crystalline component can be formed in the state just after the film is formed.

[0105] like Figure 5 and Figure 8 As shown, the pattern of the oxide semiconductor layer 140 is formed ( Figure 5 Although not shown in the figure, a resist mask is formed on the oxide semiconductor layer 140, and the oxide semiconductor layer 140 is etched using the resist mask. The oxide semiconductor layer 140 can be etched by wet etching or dry etching. As wet etching, an acidic etchant can be used for etching. For example, oxalic acid or hydrofluoric acid can be used as an etchant.

[0106] After the patterning of the oxide semiconductor layer 140, the oxide semiconductor layer 140 is subjected to a heat treatment (OS annealing) ( Figure 5 In the present embodiment, the oxide semiconductor layer 140 is crystallized by the OS annealing. When the OS annealing is performed, the aluminum contained in the metal oxide layer 130 diffuses into the oxide semiconductor layer 140, and a first crystal region 144 is formed near the interface between the metal oxide layer 130 and the oxide semiconductor layer 140. In addition, the second crystal region 145 is formed using the first crystal region 144 as a crystal nucleus.

[0107] like Figure 5 and Fig. 9 As shown, the pattern of the oxidized metal layer 130 is formed ( Figure 5The metal oxide layer 130 is etched using the oxide semiconductor layer 140 patterned in the above process as a mask. The metal oxide layer 130 may be etched by wet etching or dry etching. For example, diluted hydrofluoric acid (DHF) is used as a wet etching. As described above, the metal oxide layer 130 is etched by using the oxide semiconductor layer 140 as a mask, thereby omitting the photolithography process.

[0108] like Figure 5 and Fig.10 As shown, a gate insulating layer 150 is formed on the oxide semiconductor layer 140 ( Figure 5 'GI formation' in step S2006). For example, as the gate insulating layer 150, silicon oxide is formed. The gate insulating layer 150 is formed by a CVD method. For example, as the gate insulating layer 150, in order to form an insulating layer with few defects as described above, the gate insulating layer 150 may be formed at a film forming temperature of 350°C or higher. For example, the thickness of the gate insulating layer 150 is between 50nm and 300nm, between 60nm and 200nm, or between 70nm and 150nm. After forming the gate insulating layer 150, a process of injecting oxygen into a portion of the gate insulating layer 150 may also be performed. The gate insulating layer 150 is sometimes referred to as a "second insulating layer". A metal oxide layer 190 ( Fig. 22 The metal oxide layer 190 is formed by a sputtering method. Oxygen is injected into the gate insulating layer 150 by the formation of the metal oxide layer 190.

[0109] For example, the thickness of the metal oxide layer 190 is 5 nm to 100 nm, 5 nm to 50 nm, 5 nm to 30 nm, or 7 nm to 15 nm. In this embodiment, aluminum oxide is used as the metal oxide layer 190. Aluminum oxide has a high barrier property against gas. In this embodiment, aluminum oxide used as the metal oxide layer 190 is used to suppress the diffusion of oxygen injected into the gate insulating layer 150 to the outside when the metal oxide layer 190 is formed.

[0110] For example, when the metal oxide layer 190 is formed by sputtering, the process gas used for sputtering may remain in the film of the metal oxide layer 190. For example, when Ar is used as the process gas for sputtering, Ar may remain in the film of the metal oxide layer 190. The remaining Ar can be detected by SIMS analysis performed on the metal oxide layer 190.

[0111] In a state where the gate insulating layer 150 is formed on the oxide semiconductor layer 140 and the metal oxide layer 190 is formed on the gate insulating layer 150, a heat treatment (oxidation annealing) for supplying oxygen to the oxide semiconductor layer 140 is performed ( Figure 5 In other words, the metal oxide layer 130 and the oxide semiconductor layer 140 patterned as described above are subjected to heat treatment (oxidation annealing). In the process from the formation of the oxide semiconductor layer 140 to the formation of the gate insulating layer 150 on the oxide semiconductor layer 140, a large number of oxygen vacancies are generated on the upper surface 141 and the side surface 143 of the oxide semiconductor layer 140. The oxygen released from the gate insulating layers 120 and 150 by the above-mentioned oxidation annealing is supplied to the oxide semiconductor layer 140, and the oxygen vacancies are repaired.

[0112] Oxygen released from the gate insulating layer 120 by the oxidation annealing is blocked by the oxidized metal layer 130. Therefore, it is difficult to supply oxygen to the lower surface 142 of the oxide semiconductor layer 140. Oxygen released from the gate insulating layer 120 diffuses from the region where the oxidized metal layer 130 is not formed to the gate insulating layer 150 provided on the gate insulating layer 120, and reaches the oxide semiconductor layer 140 via the gate insulating layer 150. As a result, oxygen released from the gate insulating layer 120 is not easily supplied to the lower surface 142 of the oxide semiconductor layer 140, but is mainly supplied to the side surface 143 and the upper surface 141 of the oxide semiconductor layer 140. In addition, oxygen released from the gate insulating layer 150 by the oxidation annealing is supplied to the upper surface 141 and the side surface 143 of the oxide semiconductor layer 140. Although hydrogen may be released from the gate insulating layers 110 and 120 due to the above-mentioned oxidation annealing, the hydrogen is blocked by the oxidized metal layer 130.

[0113] As described above, the oxidation annealing step can suppress supply of oxygen to the lower surface 142 of the oxide semiconductor layer 140 having a small amount of oxygen vacancies, while supplying oxygen to the upper surface 141 and the side surface 143 of the oxide semiconductor layer 140 having a large amount of oxygen vacancies.

[0114] Similarly, in the above-mentioned oxidation annealing, oxygen injected into the gate insulating layer 150 is blocked by the oxide metal layer 190 and is therefore suppressed from being released into the atmosphere. Therefore, the oxidation annealing efficiently supplies the oxygen to the oxide semiconductor layer 140, and oxygen deficiencies are repaired.

[0115] like Figure 5 and Fig.11 As shown, after the oxidation annealing, the oxide metal layer 190 is etched (removed) ( Figure 5As the etching of the metal oxide layer 190, wet etching or dry etching can be used. For example, as wet etching, diluted hydrofluoric acid (DHF) is used. The formed metal oxide layer 190 is removed entirely by this etching. In other words, the removal of the metal oxide layer 190 is performed without using a mask. In further other words, the entire metal oxide layer 190 in the area overlapping with the oxide semiconductor layer 140 formed into a certain pattern when viewed from above is removed by this etching.

[0116] When the oxidation annealing is performed, aluminum contained in the oxidized metal layer 190 diffuses into the gate insulating layer 150. Therefore, even if the oxidized metal layer 190 is removed, aluminum diffused from the oxidized metal layer 190 remains in the gate insulating layer 150.

[0117] like Figure 5 and Fig.12 As shown, a gate electrode 160 is formed on the gate insulating layer 150 ( Figure 5 The gate electrode 160 is formed by sputtering or atomic layer deposition and patterned by photolithography. As described above, the gate electrode 160 is formed in contact with the gate insulating layer 150 exposed by removing the oxidized metal layer 190.

[0118] When etching the gate electrode 160, a portion of the gate insulating layer 150 is sometimes also etched. That is, the gate insulating layer 150 includes regions with different film thicknesses. Specifically, the gate insulating layer 150 includes a first region overlapping with the gate electrode 160 and a second region not overlapping with the gate electrode 160. The first region overlaps with the channel region CH of the oxide semiconductor layer 140. The second region overlaps with the source region S or the drain region D of the oxide semiconductor layer 140. The film thickness of the second region is smaller than the film thickness of the first region.

[0119] In a state where the gate electrode 160 is patterned, the resistance of the source region S and the drain region D of the oxide semiconductor layer 140 is reduced ( Figure 5 Specifically, impurities are injected into the oxide semiconductor layer 140 from the gate electrode 160 side through the gate insulating layer 150 by ion implantation. For example, argon (Ar), phosphorus (P), and boron (B) are injected into the oxide semiconductor layer 140 by ion implantation. Oxygen vacancies are formed in the oxide semiconductor layer 140 by ion implantation, thereby reducing the resistance of the oxide semiconductor layer 140. Since the gate electrode 160 is provided above the oxide semiconductor layer 140 that functions as the channel region CH of the semiconductor device 10, impurities are not injected into the oxide semiconductor layer 140 in the channel region CH.

[0120] like Figure 5 and Fig.13 As shown, insulating layers 170 and 180 are formed on the gate insulating layer 150 and the gate electrode 160 as interlayer films ( Figure 5 The insulating layers 170 and 180 are formed by CVD. For example, silicon nitride is formed as the insulating layer 170, and silicon oxide is formed as the insulating layer 180. The materials used as the insulating layers 170 and 180 are not limited to the above. The thickness of the insulating layer 170 is not less than 50 nm and not more than 500 nm. The thickness of the insulating layer 180 is not less than 50 nm and not more than 500 nm.

[0121] like Figure 5 and Fig.14 As shown, openings 171 and 173 are formed in the gate insulating layer 150 and the insulating layers 170 and 180 ( Figure 5 The oxide semiconductor layer 140 in the source region S is exposed through the opening 171. The oxide semiconductor layer 140 in the drain region D is exposed through the opening 173. The source / drain electrodes 200 ( Figure 5 Step S2014 of "SD formation"), thereby completing Figure 1 A semiconductor device 10 is shown.

[0122] The semiconductor device 10 manufactured by the above manufacturing method can obtain a mobility of 50 cm-1 within the range of 2 μm to 4 μm for the channel length L of the channel region CH and 2 μm to 25 μm for the channel width of the channel region CH. 2 / Vs or above, 55cm 2 / Vs or above or 60cm 2 / Vs or above. The mobility in this embodiment refers to the field effect mobility in the saturation region of the semiconductor device 10, which means the maximum value of the field effect mobility in the region where the potential difference (Vd) between the source electrode and the drain electrode is greater than the value (Vg-Vth) obtained by subtracting the threshold voltage (Vth) of the semiconductor device 10 from the voltage supplied to the gate electrode (Vg).

[0123] <Second embodiment>

[0124] Reference Figure 15 to Figure 19 A display device using a semiconductor device according to an embodiment of the present invention will be described. In the embodiment shown below, a circuit configuration in which the semiconductor device 10 described in the first embodiment is applied to a liquid crystal display device will be described.

[0125] [Overview of Display Device 20]

[0126] Fig.15 1 is a top view showing an overview of a display device according to an embodiment of the present invention. Fig.15 As shown, the display device 20 includes an array substrate 300, a sealing portion 310, an opposing substrate 320, a flexible printed circuit substrate 330 (FPC 330), and an IC chip 340. The array substrate 300 and the opposing substrate 320 are bonded together by the sealing portion 310. In the liquid crystal region 22 surrounded by the sealing portion 310, a plurality of pixel circuits 301 are arranged in a matrix. The liquid crystal region 22 is a region that overlaps with a liquid crystal element 311 described later in a plan view.

[0127] The sealing region 24 provided with the sealing portion 310 is the region around the liquid crystal region 22. The FPC 330 is provided in the terminal region 26. The terminal region 26 is the region where the array substrate 300 is exposed from the counter substrate 320 and is provided outside the sealing region 24. The outside of the sealing region 24 means the region provided with the sealing portion 310 and the outside of the region surrounded by the sealing portion 310. The IC chip 340 is provided on the FPC 330. The IC chip 340 supplies a signal for driving each pixel circuit 301.

[0128] [Circuit Configuration of Display Device 20]

[0129] Fig.16 FIG. 1 is a block diagram showing a circuit configuration of a display device according to an embodiment of the present invention. Fig.16 As shown, a source driving circuit 302 is provided at a position adjacent to the liquid crystal region 22 in the D1 direction (column direction) with respect to the pixel circuit 301, and a gate driving circuit 303 is provided at a position adjacent to the liquid crystal region 22 in the D2 direction (row direction). The source driving circuit 302 and the gate driving circuit 303 are provided in the above-mentioned sealing region 24. However, the region where the source driving circuit 302 and the gate driving circuit 303 are provided is not limited to the sealing region 24, and may be any region as long as it is outside the region where the pixel circuit 301 is provided.

[0130] The source wiring 304 extends from the source driver circuit 302 along the D1 direction and is connected to the plurality of pixel circuits 301 arranged in the D1 direction. The gate wiring 305 extends from the gate driver circuit 303 along the D2 direction and is connected to the plurality of pixel circuits 301 arranged in the D2 direction.

[0131] The terminal region 26 is provided with a terminal portion 306. The terminal portion 306 and the source driver circuit 302 are connected via a connection wiring 307. Similarly, the terminal portion 306 and the gate driver circuit 303 are connected via a connection wiring 307. By connecting the FPC 330 to the terminal portion 306, an external device connected to the FPC 330 is connected to the display device 20, and each pixel circuit 301 provided in the display device 20 is driven by a signal from the external device.

[0132] The semiconductor device 10 described in the first embodiment is used as a transistor included in the pixel circuit 301 , the source driver circuit 302 , and the gate driver circuit 303 .

[0133] [Pixel Circuit 301 of Display Device 20]

[0134] Fig.17 FIG. 1 is a circuit diagram showing a pixel circuit of a display device according to an embodiment of the present invention. Fig.17 As shown, the pixel circuit 301 includes elements such as the semiconductor device 10, the holding capacitor 350, and the liquid crystal element 311. The semiconductor device 10 has a gate electrode 160, a source electrode 201, and a drain electrode 203. The gate electrode 160 is connected to the gate wiring 305. The source electrode 201 is connected to the source wiring 304. The drain electrode 203 is connected to the holding capacitor 350 and the liquid crystal element 311. In this embodiment, for the sake of convenience of description, the electrode represented by the figure mark "201" is called the source electrode, and the electrode represented by the figure mark "203" is called the drain electrode, but it is also possible that the electrode represented by the figure mark "201" functions as a drain electrode and the electrode represented by the figure mark "203" functions as a source electrode.

[0135] [Cross-sectional structure of display device 20]

[0136] Fig.18 FIG. 1 is a cross-sectional view of a display device according to an embodiment of the present invention. Fig.18 As shown in FIG. 1 , the display device 20 is a display device using the semiconductor device 10. In this embodiment, the semiconductor device 10 is used in the pixel circuit 301, but the semiconductor device 10 can also be used in peripheral circuits including the source driver circuit 302 and the gate driver circuit 303. In the following description, the semiconductor device 10 is used in the pixel circuit 301. Figure 1 The semiconductor device 10 shown is the same and therefore its description is omitted.

[0137] An insulating layer 360 is provided on the source electrode 201 and the drain electrode 203. A common electrode 370 provided in common to a plurality of pixels is provided on the insulating layer 360. An insulating layer 380 is provided on the common electrode 370. An opening 381 is provided on the insulating layers 360 and 380. A pixel electrode 390 is provided on the insulating layer 380 and inside the opening 381. The pixel electrode 390 is connected to the drain electrode 203.

[0138] In the display device 20, a wiring layer 162 is provided as the same layer as the gate electrode 160. The wiring layer 162 is made of the same material as the gate electrode 160. The wiring layer 162 is provided on an insulating layer corresponding to the gate insulating layer 150. On this insulating layer, the metal oxide layer 190 is also formed and oxidized annealed. The aluminum concentration of the region of the insulating layer that does not overlap with the wiring layer 162 is lower than the aluminum concentration of the region of the insulating layer that overlaps with the wiring layer 162.

[0139] Fig.19 FIG. 1 is a top view of a pixel electrode and a common electrode of a display device according to an embodiment of the present invention. Fig.19 As shown, the common electrode 370 has an overlapping region that overlaps with the pixel electrode 390 in a plan view and a non-overlapping region that does not overlap with the pixel electrode 390. When a voltage is supplied between the pixel electrode 390 and the common electrode 370, a transverse electric field is formed from the pixel electrode 390 in the overlapping region toward the common electrode 370 in the non-overlapping region. The liquid crystal molecules included in the liquid crystal element 311 are moved by the transverse electric field, thereby determining the grayscale of the pixel.

[0140] <Third embodiment>

[0141] Reference Fig. 20 and Fig.21 A display device using a semiconductor device according to an embodiment of the present invention will be described. In this embodiment, a circuit configuration in which the semiconductor device 10 described in the first embodiment is applied to an organic EL display device will be described. The overview and circuit configuration of the display device 20 are related to Fig.15 and Fig.16 The outline and structure shown are the same, so the description is omitted.

[0142] [Pixel Circuit 301 of Display Device 20]

[0143] Fig. 20 FIG. 1 is a circuit diagram showing a pixel circuit of a display device according to an embodiment of the present invention. Fig. 20As shown, the pixel circuit 301 includes components such as a driving transistor 11, a selection transistor 12, a holding capacitor 210 and a light-emitting element DO. The driving transistor 11 and the selection transistor 12 have the same structure as the semiconductor device 10. The source electrode of the selection transistor 12 is connected to the signal line 211, and the gate electrode of the selection transistor 12 is connected to the gate line 212. The source electrode of the driving transistor 11 is connected to the anode power line 213, and the drain electrode of the driving transistor 11 is connected to one end of the light-emitting element DO. The other end of the light-emitting element DO is connected to the cathode power line 214. The gate electrode of the driving transistor 11 is connected to the drain electrode of the selection transistor 12. The holding capacitor 210 is connected to the gate electrode and the drain electrode of the driving transistor 11. A grayscale signal that determines the light intensity of the light-emitting element DO is supplied to the signal line 211. A signal for selecting a pixel row to which the above-mentioned grayscale signal is to be written is supplied to the gate line 212.

[0144] [Cross-sectional structure of display device 20]

[0145] Fig.21 It is a cross-sectional view of a display device according to one embodiment of the present invention. Fig.21 The display device 20 shown in FIG. Fig.18 The display device 20 shown is similar, but Fig.21 The structure above the insulating layer 360 in the display device 20 and Fig.18 The structure above the insulating layer 360 in the display device 20 is different. Fig.21 The display device 20 is configured as follows: Fig.18 The description of the same structure as the display device 20 is omitted, and the differences between the two are described.

[0146] like Fig.21 As shown, the display device 20 has a pixel electrode 390, a light-emitting layer 392 and a common electrode 394 (light-emitting element DO) above the insulating layer 360. The pixel electrode 390 is arranged on the insulating layer 360 and inside the opening 381. An insulating layer 362 is arranged on the pixel electrode 390. An opening 363 is arranged in the insulating layer 362. The opening 363 corresponds to the light-emitting area. That is, the insulating layer 362 divides the pixel. The light-emitting layer 392 and the common electrode 394 are arranged on the pixel electrode 390 exposed by the opening 363. The pixel electrode 390 and the light-emitting layer 392 are arranged separately with respect to each pixel. On the other hand, the common electrode 394 is arranged in common with respect to a plurality of pixels. Different materials are used for the light-emitting layer 392 according to the display color of the pixel.

[0147] In the second and third embodiments, the semiconductor device described in the first embodiment is applied to a liquid crystal display device and an organic EL display device, but the semiconductor device can also be applied to display devices other than the above display devices (for example, a self-luminous display device or an electronic paper display device other than an organic EL display device). In addition, unless otherwise specified, the semiconductor device can be applied to display devices ranging from small and medium-sized to large display devices.

[0148] Example

[0149] As an example, the semiconductor device 10 described in the first embodiment was manufactured and evaluated. In addition, as a comparative example, a semiconductor device without the metal oxide layer 130 in contact with the oxide semiconductor layer 140, that is, a semiconductor device in which the oxide semiconductor layer 140 was in contact with the gate insulating layer 120, was manufactured.

[0150] It should be noted that in both the semiconductor device 10 of the embodiment and the semiconductor device of the comparative example, an aluminum oxide layer is formed as the metal oxide layer 190 by sputtering before forming the gate electrode 160 , and the aluminum oxide layer is removed after oxidation annealing.

[0151] [1. Electrical characteristics]

[0152] Fig. 22 is a diagram showing the electrical characteristics of the semiconductor device 10 of the embodiment. Fig. 27 It is a graph showing the electrical characteristics of a semiconductor device of a comparative example. Fig. 22 and Fig. 27 The measurement conditions of the electrical characteristics are shown in Table 1.

[0153] [Table 1]

[0154]

[0155] exist Fig. 22 and Fig. 27 In the figure, not only the electrical characteristics (Id-Vg characteristics) but also the mobility (refer to Fig. 22 and Fig. 27 ). Fig. 22 and Fig. 27 In the figure, the vertical axis for the drain current (Id) is shown on the left side of the figure, and the vertical axis for the mobility calculated based on the drain current is shown on the right side of the figure.

[0156] like Fig. 22 As shown, the electrical characteristics of the semiconductor device 10 of the embodiment show so-called normally off (enhancement type) characteristics in which the drain current Id starts to flow when the gate voltage Vg is higher than 0 V. The mobility calculated from the electrical characteristics is 59 cm2 / Vs.

[0157] like Fig. 27 As shown, the electrical characteristics of the semiconductor device of the comparative example also show so-called normally off (enhancement mode) characteristics. The mobility calculated from the electrical characteristics is 34 cm 2 / Vs.

[0158] As can be seen from the above, the mobility of the semiconductor device 10 of the embodiment is about twice that of the semiconductor device of the comparative example, and the semiconductor device 10 of the embodiment has high mobility.

[0159] [2. Reliability test]

[0160] Fig.23 1 is a diagram showing a reliability test of the semiconductor device 10 of the embodiment. Fig.28 It is a graph showing the reliability of a semiconductor device of a comparative example. Fig.23 and Fig.28 The measurement conditions of the reliability test are shown in Table 2. That is, as the reliability test, the reliability evaluation based on Negative Bias Temperature Illumination Stress (NBTIS) was performed.

[0161] [Table 2]

[0162]

[0163] exist Fig.23 and Fig.28 The electrical characteristics measured at stress times of 0 sec, 100 sec, 500 sec, 1000 sec, 1500 sec, 2000 sec, and 3600 sec are shown in FIG. Here, the time before stress application is 0 sec, and the time after stress application is 3600 sec. Fig.23 and Fig.28 In FIG. 1 , the electrical characteristics before stress application (0 sec) are represented by a thick dotted line, and the electrical characteristics after stress application (3600 sec) are represented by a thick solid line.

[0164] It should be noted that the measurement conditions of the electrical characteristics before and after the stress application are shown in Table 3.

[0165] [Table 3]

[0166] The size of the channel area W / L=3.0μm / 3.0μm Source-drain voltage 0.1V、10V Gate voltage -15V~+15V Measurement environment 60℃, dark room

[0167] like Fig.23As shown in FIG. 1 , in the semiconductor device 10 of the embodiment, the electrical characteristics before and after stress application in the NBTIS test are almost unchanged. The change in threshold voltage before and after stress application is -0.05 V. That is, after stress application, the threshold voltage only shifts in the negative direction by 0.05 V. In addition, the normally off characteristic is also shown after stress application.

[0168] like Fig.28 As shown, in the semiconductor device of the comparative example, changes in electrical characteristics before and after stress application were observed in the NBTIS test. The change in threshold before and after stress application was -1.14 V. That is, after stress application, the threshold voltage shifted further in the negative direction by 1.14 V.

[0169] As can be seen from the above, the reliability of the semiconductor device 10 of the embodiment is stable and the semiconductor device 10 of the embodiment has high reliability.

[0170] [3. Cross-sectional TEM observation]

[0171] Fig.24A TEM image of a cross section of the semiconductor device 10 according to the embodiment. Fig. 24B It is used to illustrate Fig.24A Schematic diagram of the cross-sectional TEM image. Fig.29 is a cross-sectional TEM image of a semiconductor device of a comparative example. Fig.24A , a cross-sectional TEM image of the vicinity of the interface between the metal oxide layer 130 and the oxide semiconductor layer 140 in the semiconductor device 10 of the embodiment is shown. Fig.29 2 shows a cross-sectional TEM image of the vicinity of the interface between the gate insulating layer 120 and the oxide semiconductor layer 140 in the semiconductor device of the comparative example.

[0172] like Fig.24A As shown in FIG. 1 , in the semiconductor device 10 of the embodiment, two different crystal regions can be confirmed. Specifically, Fig. 24B As shown, in the vicinity of the interface between the metal oxide layer 130 and the oxide semiconductor layer 140 , a first crystal region 144 in contact with the metal oxide layer 130 and a second crystal region 145 covering the first crystal region 144 can be confirmed.

[0173] like Fig.29 As shown, in the semiconductor device of the comparative example, although the oxide semiconductor layer 140 has crystallinity, a crystalline region different from the crystalline region occupying most of the oxide semiconductor layer 140 is not observed near the interface between the gate insulating layer 120 and the oxide semiconductor layer 140 .

[0174] [4. Electron diffraction measurement]

[0175] Fig.25 and Fig.26 is an electron diffraction image of the semiconductor device 10 of the embodiment. Fig.25 , an electron diffraction image of the oxide semiconductor layer 140 at a position away from the interface between the metal oxide layer 130 and the oxide semiconductor layer 140 is shown. Fig.26 , an electron diffraction image near the interface between the metal oxide layer 130 and the oxide semiconductor layer 140 is shown. Fig.30 and Fig.31 is an electron diffraction image of a semiconductor device of a comparative example. Fig.30 , an electron diffraction image of the oxide semiconductor layer 140 at a position away from the interface between the gate insulating layer 120 and the oxide semiconductor layer 140 is shown. Fig.31 2 shows an electron diffraction image near the interface between the gate insulating layer 120 and the oxide semiconductor layer 140 .

[0176] exist Fig.25 In FIG. 1 , a clear spot due to the crystal structure can be confirmed. Therefore, it can be seen that the oxide semiconductor layer 140 (the second crystal region 145) in the semiconductor device 10 of the embodiment has a crystal structure. Fig.26 In Fig.25 The spots identified in the Fig.26 The spots observed in derive from the crystal structure of the first crystal region 144. Therefore, in the semiconductor device 10 of the embodiment, the first crystal region 144 near the interface between the metal oxide layer 130 and the oxide semiconductor layer 140 is different from the second crystal region 145 in crystal structure or crystal orientation.

[0177] exist Fig.30 In FIG. 1 , clear spots due to the crystal structure can be confirmed. Therefore, it can be seen that the oxide semiconductor layer 140 in the semiconductor device of the comparative example also has a crystal structure. Fig.31 In Fig.30 Therefore, in the semiconductor device of the comparative example, Fig.29 Similarly, in the cross-sectional TEM image of , in the vicinity of the interface between the gate insulating layer 120 and the oxide semiconductor layer 140 , no crystalline region different from the crystalline region occupying most of the oxide semiconductor layer 140 can be confirmed.

[0178] As described above, according to the results of cross-sectional TEM observation and electron diffraction, in the semiconductor device 10 of the embodiment, the first crystal region 144 having different crystallinity from the second crystal region 145 occupying most of the oxide semiconductor layer 140 is formed near the interface between the metal oxide layer 130 and the oxide semiconductor layer 140. Furthermore, the semiconductor device 10 having the first crystal region 144 has high mobility and high reliability as described above.

[0179] The various embodiments described above as embodiments of the present invention can be appropriately combined and implemented as long as they do not contradict each other. In addition, solutions obtained by adding, deleting or designing components or adding, omitting or changing conditions of processes based on the various embodiments by those skilled in the art are also included in the scope of the present invention as long as they have the gist of the present invention.

[0180] Even if there are other effects different from the effects brought about by the schemes of the above-mentioned embodiments, if they are clearly known from the description of this specification or can be easily predicted by those skilled in the art, they are of course understood to be the effects brought about by the present invention.

[0181] Description of Reference Numerals

[0182] 10: semiconductor device, 11: driving transistor, 12: selecting transistor, 20: display device, 22: liquid crystal region, 24: sealing region, 26: terminal region, 100: substrate, 105, 160: gate electrode, 110, 120, 150: gate insulating layer, 130, 190: oxide metal layer, 140: oxide semiconductor layer, 141: upper surface, 142: lower surface, 143: side surface, 144, 144A: first crystal region, 145, 145A: second crystal region, 162: wiring layer, 170, 180: insulating layer, 171, 173: opening, 200: source / drain electrode, 201: source electrode, 203: drain electrode, 210: holding capacitor, 21 1: signal line, 212: gate line, 213: anode power line, 214: cathode power line, 220: resist mask, 300: array substrate, 301: pixel circuit, 302: source drive circuit, 303: gate drive circuit, 304: source wiring, 305: gate wiring, 306: terminal portion, 307: connection wiring, 310: sealing portion, 311: liquid crystal element, 320: opposing substrate, 330: flexible printed circuit substrate (FPC), 340: IC chip, 350: holding capacitor, 360, 362: insulating layer, 363, 381: opening, 370: common electrode, 380: insulating layer, 390: pixel electrode, 392: light-emitting layer, 394: common electrode

Claims

1. A semiconductor device comprising: an oxidized metal layer comprising aluminum over an insulating surface; and an oxide semiconductor layer on the oxide metal layer, The oxide semiconductor layer includes: a first crystalline region in contact with the oxidized metal layer; and a second crystal region which is in contact with the first crystal region and has a larger area than the first crystal region in cross-sectional observation of the oxide semiconductor layer, The first crystallized region and the second crystallized region are different in at least one of crystal structure and crystal orientation.

2. The semiconductor device according to claim 1, wherein The oxide semiconductor layer contains two or more metals including indium, In the oxide semiconductor layer, a ratio of the indium to the two or more metals is 50% or more.

3. The semiconductor device according to claim 1, wherein The aluminum concentration of the first crystal region is greater than the aluminum concentration of the second crystal region.

4. The semiconductor device according to claim 1, wherein In a film thickness direction of the oxide semiconductor layer, the second crystal region has a film thickness greater than a film thickness of the first crystal region.

5. The semiconductor device according to claim 1, wherein In the cross-sectional observation of the oxide semiconductor layer, a grain boundary exists between the first crystal region and the second crystal region.

6. The semiconductor device according to claim 1, wherein The electrical conductivity of the first crystalline region is lower than the electrical conductivity of the second crystalline region.

7. The semiconductor device according to claim 1, wherein In the cross-sectional observation of the oxide semiconductor layer, the first crystal region is surrounded by the metal oxide layer and the second crystal region.

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