Timing correction electronic control system of photoelectric theodolite and image timing correction method

Abstract

The present invention belongs to the field of photoelectric measurement technology, and in particular, relates to a timing correction electric control system of a photoelectric theodolite and an image timing correction method. The method comprises: S1: putting the timing correction electric control system in an image timing test mode; S2: the timing control system of the photoelectric theodolite sends a second synchronization signal to a second synchronization signal receiving module; S3: the whitening module sets all pixel values ​​contained in the first frame image received after receiving the second synchronization signal to 1, and obtains a whitened image; S4: the character overlay module replaces the pixels at the first row of the specified position of all images of the digital image frame sequence containing the whitened image with character overlay information; S5: the off-machine storage software also calculates the image frame difference of the photoelectric theodolite based on the time code of the whitened image and the whole second moment actually corresponding to the whitened image, and corrects the image timing of the photoelectric theodolite based on the image frame difference. The present invention can effectively improve the measurement accuracy of the equipment.

Description

Technical Field

[0001] The invention belongs to the technical field of photoelectric measurement, and in particular relates to a timing correction electric control system of a photoelectric theodolite and an image timing correction method. Background Art

[0002] Photoelectric theodolite is an optical measuring instrument used in modern shooting ranges to measure the motion characteristics, geometric characteristics and physical characteristics of space targets. It has been widely used in scientific research and military fields such as aviation, aerospace, and weapon experiments. In recent years, photoelectric theodolites are developing in the direction of high speed, simplification and localization. Shooting range experiments have developed from conventional, single-type weapon experiments to new experiments with high measurement accuracy and multiple measurement methods. A single photoelectric theodolite is increasingly unable to meet the experimental requirements. It is necessary to set up multiple photoelectric theodolites at different locations to form a measurement and control network. The field of view intersection measurement is performed from all directions of the space target to obtain the motion trajectory, posture, and radiation characteristics of the space target. Angular measurement accuracy is an important indicator to effectively improve the reliability of the measurement and control network. In order to effectively improve the reliability and dynamic angular measurement accuracy of the measurement and control network, the photoelectric theodolite needs to be imaged for timing correction. However, the existing timing correction method requires the use of other camera timing calibration equipment. The image timing correction is costly and complex to operate, and has high technical requirements for operators. Summary of the invention

[0003] In view of this, the present invention aims to provide an electronic control system for a photoelectric theodolite lens to solve the problems of high cost and complex operation of existing image timing correction methods. The present invention can effectively improve the measurement accuracy of the equipment.

[0004] To achieve the above object, the technical solution created by the present invention is implemented as follows:

[0005] A timing correction electric control system for a photoelectric theodolite is implemented by using FPGA. An image timing test signal receiving module, a second synchronization signal receiving module, a whitening module and a character superposition module are arranged on the FPGA. The main control system of the photoelectric theodolite sends an image timing test signal to the image timing test signal receiving module, so that the timing correction electric control system is in an image timing test mode; the timing control system of the photoelectric theodolite sends a second synchronization signal to the second synchronization signal receiving module, and the second synchronization signal receiving module sends the second synchronization signal to the whitening module; the whitening module averages the pixel values ​​contained in the first frame of digital image received after receiving the second synchronization signal is set to 1 to obtain a whitened image; the character overlay module receives the character overlay information of the photoelectric theodolite through the optical fiber, and replaces the pixels at the specified positions of the first row of all images of the digital image frame sequence containing the whitened image with the character overlay information; the off-machine storage software of the photoelectric theodolite stores the digital image frame sequence containing the character overlay information, and plays back the digital image frame sequence containing the character overlay information to obtain the time code of the whitened image overlay, and the off-machine storage software also calculates the image frame difference of the photoelectric theodolite based on the time code of the whitened image and the whole second moment actually corresponding to the whitened image, and corrects the image timing of the photoelectric theodolite based on the image frame difference.

[0006] Furthermore, when the timing correction electronic control system is in the image timing test mode, the second synchronization signal receiving module and the whitening module start to work.

[0007] Furthermore, the character overlay information includes an azimuth value, a pitch value and a time code.

[0008] Furthermore, a digital image frame sequence is acquired using a camera of the photoelectric theodolite.

[0009] A method for image timing correction is implemented by using a timing correction electronic control system of a photoelectric theodolite, and specifically comprises the following steps:

[0010] S1: The main control system of the photoelectric theodolite sends an image timing test signal to the image timing test signal receiving module, so that the timing correction electronic control system is in the image timing test mode;

[0011] S2: The timing control system of the photoelectric theodolite sends a second synchronization signal to the second synchronization signal receiving module, and the second synchronization signal receiving module sends the second synchronization signal to the whitening module;

[0012] S3: the whitening module sets all pixel values ​​contained in the first frame of the digital image received after receiving the second synchronization signal to 1, thereby obtaining a whitening image;

[0013] S4: The character overlay module receives the character overlay information from the photoelectric theodolite through the optical fiber, and replaces the pixels at the designated positions of the first row of all images of the digital image frame sequence containing the whitened image with the character overlay information;

[0014] S5: The off-machine storage software of the photoelectric theodolite stores the digital image frame sequence containing the character overlay information, and plays back the digital image frame sequence containing the character overlay information to obtain the time code of the white-out image overlay. The off-machine storage software also calculates the image frame difference of the photoelectric theodolite based on the time code of the white-out image and the whole second moment actually corresponding to the white-out image, and corrects the image timing of the photoelectric theodolite based on the image frame difference.

[0015] Furthermore, in step S5, the calculation formula of the image frame difference N of the photoelectric theodolite is:

[0016] N=F / T f ;

[0017] Among them, F is the difference between the time code of the white-out image superimposed and the whole second time actually corresponding to the white-out image, T f is the period of the digital image frame sequence.

[0018] Furthermore, the second synchronization signal is a whole second, and the image frame difference is an integer.

[0019] Compared with the prior art, the invention can achieve the following beneficial effects:

[0020] (1) The timing correction method created by the present invention does not require the use of other camera timing calibration equipment. It only needs to set the timing correction electronic control system to the image test mode in the main control system to perform the test. The operation is convenient and the algorithm is simple.

[0021] (2) The timing correction method created by the present invention can effectively improve the flexibility, reliability, stability and measurement accuracy of optoelectronic devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The drawings constituting part of the present invention are used to provide a further understanding of the present invention. The exemplary embodiments and descriptions of the present invention are used to explain the present invention and do not constitute an improper limitation on the present invention. In the drawings:

[0023] Figure 1 A block diagram of the timing correction electronic control system of the photoelectric theodolite described in the embodiment of the present invention;

[0024] Figure 2 A timing diagram of the superposition mechanism described in the embodiment of the present invention;

[0025] Figure 3 A flowchart of an image timing correction method according to an embodiment of the present invention;

[0026] Figure 4A timing diagram of the image timing test scheme described in the embodiment of the present invention;

[0027] Figure 5 The present invention creates a block diagram of the electronic control system of the photoelectric theodolite lens described in the embodiment.

[0028] Description of reference numerals:

[0029] 1. FPGA; 1-1. Image timing test signal receiving module; 1-2. Second synchronization signal receiving module; 1-3. Whitening module; 1-4. Character overlay module; 2. Optocoupler isolation circuit; 3. Drive circuit; 4. AD acquisition circuit; 5. Voltage conversion circuit; 6. Cameralink interface circuit; 7. Power supply module; 8. Test monitoring module; 9. DIP switch; 10. J30J connector; 11. DSP module; 12. JTAG circuit; 13. SFP optical module. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solution and advantages of the invention more clear, the invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described here are only used to explain the invention and do not constitute a limitation of the invention.

[0031] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0032] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first", "second", etc. are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0033] In the description of the invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the invention can be understood according to specific circumstances.

[0034] The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments.

[0035] like Figure 1 As shown, the timing correction electric control system of the photoelectric theodolite proposed in the present invention is implemented by using FPGA1, and an image timing test signal receiving module 1-1, a second synchronization signal receiving module 1-2, a whitening module 1-3 and a character superposition module 1-4 are provided on the FPGA1, wherein the main control system of the photoelectric theodolite sends an image timing test signal to the image timing test signal receiving module 1-1, so that the timing correction electric control system is in an image timing test mode (when the timing correction electric control system is in the image timing test mode, the second synchronization signal receiving module 1-2 and the whitening module 1-3 start working); the timing control system of the photoelectric theodolite sends a second synchronization signal to the second synchronization signal receiving module 1-2, and the second synchronization signal receiving module 1-2 sends the second synchronization signal to the whitening module 1-3; the whitening module 1-3 will The pixel values ​​contained in the first frame of digital image received are all set to 1 to obtain a white-painted image; the character overlay module 1-4 receives the character overlay information of the photoelectric theodolite through the optical fiber (the character overlay information includes the azimuth value, the pitch value and the time code), and replaces the pixels at the specified positions of the first row of all images of the digital image frame sequence containing the white-painted image (the digital image frame sequence is obtained by using the camera of the photoelectric theodolite) with the character overlay information; the off-machine storage software of the photoelectric theodolite stores the digital image frame sequence containing the character overlay information, and plays back the digital image frame sequence containing the character overlay information to obtain the time code of the white-painted image overlay, and the off-machine storage software also calculates the image frame difference of the photoelectric theodolite based on the time code of the white-painted image and the whole second time actually corresponding to the white-painted image, and corrects the image timing of the photoelectric theodolite based on the image frame difference.

[0036] The operations related to image timing correction require understanding of the character overlay method of digital images. Character overlay of digital images refers to replacing pixels at specified positions of digital images with other information (including time encoders, etc.) for subsequent accuracy settlement and other applications.

[0037] There are many ways to overlay characters on digital images. Here we only introduce one form of character overlay on digital images: To ensure the integrity of the received overlay information, the received overlay information needs to be cached. When the digital image is output, the overlay information is read from the cache, and some pixels in the first line of the image are replaced with the information that needs to be overlaid. Two FIFOs are set here to cache the overlay information. The cache mechanism uses reading FIFOB when writing FIFOA, and reading FIFOA when writing FIFOB, to avoid timing competition and risk problems. The timing relationship diagram of the overlay mechanism is as follows: Figure 2 As shown, taking the timing before and after the camera is externally triggered at time T(N) as an example, before the camera is triggered at time T(N), the S(N-1) superimposed information data packet is written into the FIFOB. When the camera is triggered to output a digital image at time T(N), the S(N-2) superimposed information data packet cached in the FIFOA is read out, and the S(N-2) superimposed information data packet is superimposed at a fixed position of the first line of the digital image; before the camera is triggered, the received S(N) superimposed information data packet is written into the FIFOA. When the camera is triggered to output a digital image at time T(N+1), the S(N-1) superimposed information data packet cached in the FIFOB is read out, and the S(N-1) superimposed information data packet is superimposed at a fixed position of the first line of the digital image.

[0038] like Figure 3-Figure 4 As shown, in order to effectively improve the reliability of the measurement and control network and the dynamic angle measurement accuracy, the present invention proposes an image timing correction method, which is implemented by using the timing correction electronic control system of the photoelectric theodolite, and specifically includes the following steps:

[0039] S1: The main control system of the photoelectric theodolite sends an image timing test signal to the image timing test signal receiving module 1-1, so that the timing correction electronic control system is in the image timing test mode;

[0040] S2: The time control system of the photoelectric theodolite sends a second synchronization signal (the second synchronization signal is the whole second moment) to the second synchronization signal receiving module 1-2, and the second synchronization signal receiving module 1-2 sends the second synchronization signal to the whitening module 1-3;

[0041] S3: the whitening module 1-3 sets all pixel values ​​contained in the first frame of the digital image received after receiving the second synchronization signal to 1, thereby obtaining a whitening image;

[0042] S4: the character superimposition module 1-4 receives the character superimposition information of the photoelectric theodolite through the optical fiber, and replaces the pixels at the designated positions of the first row of all images of the digital image frame sequence containing the whitened image with the character superimposition information;

[0043] S5: The off-machine storage software of the photoelectric theodolite stores the digital image frame sequence containing the character overlay information, and plays back the digital image frame sequence containing the character overlay information to obtain the time code of the white-out image overlay. The off-machine storage software also calculates the image frame difference of the photoelectric theodolite based on the time code of the white-out image and the whole second moment actually corresponding to the white-out image, and corrects the image timing of the photoelectric theodolite based on the image frame difference.

[0044] The calculation formula of the image frame difference N of the photoelectric theodolite is:

[0045] N=F / T f ;

[0046] Among them, F is the difference between the time code of the white-out image superimposed and the whole second time actually corresponding to the white-out image, T f is the period of the digital image frame sequence. The image frame difference is an integer.

[0047] The electronic control system of most theodolite tubes is composed of control boards and driver boards. Due to the limited space in the tube, multiple boards are installed in a compact arrangement, which can easily cause electromagnetic interference, circuit board damage, and difficulty in disassembly and debugging after installation. In addition, the image acquisition and transmission of the photoelectric theodolite are important components of the equipment. Although the current electronic control system has image acquisition and status monitoring functions, it does not monitor the status of the received optical fiber data and image data, nor does it have image timing test functions.

[0048] In order to save the internal space of the lens barrel, facilitate troubleshooting, achieve independent technical control, and effectively improve the flexibility, reliability, stability and measurement accuracy of the equipment, an electronic control system for the photoelectric theodolite lens is designed. Figure 5 As shown, it includes a high-power area and a low-power area arranged on the same board. The high-power area mainly includes an optocoupler isolation circuit 2 and a drive circuit 3, and the low-power area mainly includes an AD acquisition circuit 4, a voltage conversion circuit 5, a Cameralink interface circuit 6, a power module 7, a test monitoring module 8, a dip switch 9, a J30J connector 10, an FPGA 1 and a DSP module 11, a JTAG circuit 12 and an SFP optical module 13.

[0049] The following is a detailed introduction to some components:

[0050] The electronic control system of the photoelectric theodolite lens combines the advantages of the parallel processing of FPGA1 and the calculation processing of DSP module 11. DSP is responsible for processing the dimming and focusing related data in the electronic control system, FPGA1 is responsible for optical fiber transmission, character overlay of digital images, acquisition of various images and image testing, and XINTF interface and dual-port RAM are used for data transmission between DSP module 11 and FPGA1. The high-power module is used to drive the stepper motor and DC motor to complete the dimming and focusing operation. The high-power module can drive 4 DC motors and 2 stepper motors at the same time. The optocoupler isolation circuit 2 plays an isolation and protection role for the circuit of the low-power module. The low-power module is used to collect the status of each sensor, digital images, serial port information, test monitoring, image testing and optical fiber transmission.

[0051] FPGA1 receives the position commands of lens dimming and focusing through optical fiber, as well as communication signals such as time synchronization, overlay information, camera external synchronization, camera control, image timing test function control, etc., and sends relevant information such as dimming and focusing distance to DSP module 11. FPGA1 receives the feedback information from DSP module 11, and converts the received feedback information and Cameralink image data into optical fiber data packets of AXI4-stream protocol through optical fiber and sends them out.

[0052] FPGA1 uses the JFM7K325T chip of Shanghai Fudan Microelectronics Co., Ltd., which has field programmable features and includes CLB modules, I / O, Block RAM, MMCM, GTX and other programmable modules that can be used to implement conventional digital logic and distributed RAM. It can be widely used in communications, information processing, industrial control, instrument measurement and other fields.

[0053] DSP module 11 adopts the AVP32F335 chip of Hunan Jinxin Company, which has high-performance static CMOS technology, high-performance 32-bit CPU, 6-channel DMA processor, 16-channel 12-bit analog-to-digital converter (ADC), 16-bit or 32-bit external interface (XINTF), enhanced control peripherals, etc.

[0054] The input voltage of the power module 7 is 24V and 5V, and the voltage conversion circuit 5 uses a DC-DC step-down module to convert the input voltage into other voltage values.

[0055] The dip switch 9 is used to monitor the status of the received optical fiber serial port information and image line field signals, and to number the received optical fiber serial port information and image line field signals. When the dip switch 9 is turned to the corresponding number, an oscilloscope can be used to monitor the test monitoring module 8, which is convenient for developers and users to troubleshoot problems during use.

[0056] The AD acquisition circuit 4 is used for analog-to-digital conversion. In the actual AD acquisition scenario, periodic changes and occasional pulse fluctuation interferences will occur, and these interferences will affect AD acquisition. In order to avoid these effects, the present invention adopts a median average filtering algorithm. The principle is: continuously sample N data, remove a maximum value and a minimum value, and then calculate the arithmetic mean of N-2 data. The algorithm combines the advantages of the median filtering algorithm and the arithmetic mean filtering algorithm. For occasional pulse interference, the sampling value deviation caused by the pulse interference can be eliminated. The present invention improves the algorithm in combination with actual experimental conditions. The improvement method is to adjust the number M of large and small values ​​to be removed according to the actual situation of the collected data, and then calculate the arithmetic mean of NM data. Generally, the number of data removed does not exceed six. The improved algorithm is more suitable for the electronic control system of the present invention, has a better inhibitory effect on periodic interference, and has higher smoothness.

[0057] The Cameralink interface circuit 6 includes two SDR Cameralink connectors, which can be connected to common image transmission formats such as Base, Medium, and Full modes.

[0058] The SFP optical module 13 is used to receive and send optical fiber signals, that is, to receive lens dimming and focusing position commands, time synchronization signals, overlay information, original camera external synchronization signals, camera control and other communication signals through optical fiber, and to send image data packets of AXI4-stream protocol through optical fiber.

[0059] The J30J connector 10 can transmit motor drive signals, limit switch signals, serial port signals, etc. The JTAG circuit 12 includes a connection circuit between the FPGA 1 and the DSP module 11 .

[0060] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the disclosure of the present invention can be performed in parallel, sequentially or in different orders, as long as the desired results of the technical solution disclosed in the present invention can be achieved, and this document does not limit this.

[0061] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A timing correction electronic control system for a photoelectric theodolite, implemented using FPGA, characterized in that: An image timing test signal receiving module, a second synchronization signal receiving module, a whitening module and a character superposition module are arranged on the FPGA, wherein the main control system of the photoelectric theodolite sends an image timing test signal to the image timing test signal receiving module, so that the timing correction electric control system is in an image timing test mode; the timing control system of the photoelectric theodolite sends a second synchronization signal to the second synchronization signal receiving module, and the second synchronization signal receiving module sends the second synchronization signal to the whitening module; the whitening module sets the pixel values ​​contained in the first frame of digital image received after receiving the second synchronization signal to 1 to obtain a whitening image; The character superposition module receives the character superposition information of the photoelectric theodolite through the optical fiber, and replaces the pixels at the specified positions of the first row of all images of the digital image frame sequence containing the white-painted image with the character superposition information; the off-machine storage software of the photoelectric theodolite stores the digital image frame sequence containing the character superposition information, and plays back the digital image frame sequence containing the character superposition information to obtain the time code of the white-painted image superposition; the off-machine storage software also calculates the image frame difference of the photoelectric theodolite based on the time code of the white-painted image and the whole second moment actually corresponding to the white-painted image, and corrects the image timing of the photoelectric theodolite based on the image frame difference.

2. The timing correction electronic control system of the photoelectric theodolite according to claim 1, characterized in that: When the timing correction electronic control system is in the image timing test mode, the second synchronization signal receiving module and the whitening module start to work.

3. The timing correction electronic control system of the photoelectric theodolite according to claim 1, characterized in that: The character overlay information includes an azimuth value, a pitch value and a time code.

4. The timing correction electronic control system of the photoelectric theodolite according to claim 1, characterized in that: A digital image frame sequence is acquired using the camera of the electro-optical theodolite.

5. A method for image timing correction, implemented by using the timing correction electronic control system of the photoelectric theodolite according to any one of claims 1 to 4, characterized in that: The specific steps include: S1: The main control system of the photoelectric theodolite sends an image timing test signal to the image timing test signal receiving module, so that the timing correction electronic control system is in an image timing test mode; S2: the timing control system of the photoelectric theodolite sends a second synchronization signal to the second synchronization signal receiving module, and the second synchronization signal receiving module sends the second synchronization signal to the whitening module; S3: the whitening module sets all pixel values ​​contained in the first frame of digital image received after receiving the second synchronization signal to 1, thereby obtaining a whitening image; S4: the character superimposition module receives the character superimposition information of the photoelectric theodolite through the optical fiber, and replaces the pixels at the designated positions of the first row of all images of the digital image frame sequence containing the whitened image with the character superimposition information; S5: The off-machine storage software of the photoelectric theodolite stores a digital image frame sequence containing character overlay information, and plays back the digital image frame sequence containing character overlay information to obtain a time code for the white-out image overlay. The off-machine storage software also calculates an image frame difference of the photoelectric theodolite based on the time code of the white-out image and the whole second moment actually corresponding to the white-out image, and corrects the image timing of the photoelectric theodolite based on the image frame difference.

6. The image timing correction method according to claim 5, characterized in that: In step S5, the calculation formula of the image frame difference N of the photoelectric theodolite is: N=F / T f ; Wherein, F is the difference between the time code of the white-out image superimposed and the whole second time actually corresponding to the white-out image, T f is the period of the digital image frame sequence.

7. The image timing correction method according to claim 5, characterized in that: The second synchronization signal is a whole second, and the image frame difference is an integer.

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