Surface detection method and device for chip stacking package

Abstract

The present application relates to the field of chip stacking packaging technology, and discloses a surface detection method and device for chip stacking packaging. The method includes: performing multiple thermal cycle tests on the chip stacking package and collecting target high-resolution surface images; performing surface roughness detection on the chip stacking package to obtain surface roughness data; performing three-dimensional thermal mechanical finite element analysis modeling and crack strength analysis to obtain crack strength data; constructing a target relationship influence curve and performing curve feature extraction and vector encoding to obtain a relationship influence feature vector; inputting the relationship influence feature vector into a chip stacking package performance detection model to perform chip stacking package performance detection to obtain a chip stacking package performance index; performing chip stacking package process optimization on the chip stacking package according to the chip stacking package performance index, and outputting the corresponding target chip stacking package process strategy. The present application improves the surface detection accuracy of chip stacking packages.

Description

Technical Field

[0001] The present application relates to the technical field of chip stacking packaging, and in particular to a surface detection method and device for chip stacking packaging. Background Art

[0002] In the electronics manufacturing industry, especially in the field of high-performance computing and mobile devices, chip stacking packaging technology has become increasingly important because it can significantly improve integration and performance. With the advancement of technology, the performance requirements for chips are getting higher and higher, which not only involves the computing power of the chip, but also its reliability and durability. Especially when performing multiple thermal cycle tests, various defects such as cracks and delamination may appear on the surface of the chip stacking package, which greatly affects the reliability and performance of the chip.

[0003] Traditional chip surface inspection methods mainly rely on artificial vision or simple image processing technology, which are often time-consuming and inefficient, and cannot meet the current needs of high-performance chip production. In addition, these methods often fail to meet the requirements of high accuracy and high reliability when detecting tiny defects or identifying defects in complex backgrounds. Summary of the invention

[0004] The present application provides a surface detection method and device for a chip stack package, and the present application improves the surface detection accuracy of the chip stack package.

[0005] In a first aspect, the present application provides a surface detection method for a chip stack package, the surface detection method for a chip stack package comprising:

[0006] Performing multiple thermal cycle tests on the chip stack package, and collecting images of the chip stack package by atomic force microscopy to obtain a target high-resolution surface image for each thermal cycle test;

[0007] The target high-resolution surface image of each thermal cycle test is input into the preset YOLOv7 model to detect the surface roughness of the chip stack package, and the surface roughness data of each thermal cycle test is obtained;

[0008] Based on the multiple thermal cycle tests, three-dimensional thermal mechanical finite element analysis modeling is performed on the chip stack package to obtain a chip stack finite element model for each thermal cycle test, and crack strength analysis is performed on the chip stack finite element model to obtain crack strength data for each thermal cycle test;

[0009] Constructing a target relationship influence curve of the chip stack package according to the surface roughness data and the crack strength data, and performing curve feature extraction and vector encoding on the target relationship influence curve to obtain a relationship influence feature vector;

[0010] Inputting the relationship influence feature vector into a preset chip stacking package performance detection model to perform chip stacking package performance detection to obtain a chip stacking package performance index;

[0011] According to the chip stacking packaging performance index, the chip stacking packaging process is optimized for the chip stacking package, and a corresponding target chip stacking packaging process strategy is output.

[0012] In a second aspect, the present application provides a surface detection device for a chip stack package, the surface detection device for the chip stack package comprising:

[0013] An acquisition module is used to perform multiple thermal cycle tests on the chip stack package, and to acquire images of the chip stack package through an atomic force microscope to obtain a target high-resolution surface image for each thermal cycle test;

[0014] A detection module is used to input the target high-resolution surface image of each thermal cycle test into a preset YOLOv7 model to perform surface roughness detection of the chip stack package to obtain surface roughness data of each thermal cycle test;

[0015] An analysis module, configured to perform three-dimensional thermomechanical finite element analysis modeling on the chip stack package based on the multiple thermal cycle tests to obtain a chip stack finite element model for each thermal cycle test, and perform crack strength analysis on the chip stack finite element model to obtain crack strength data for each thermal cycle test;

[0016] A construction module, used to construct a target relationship influence curve of the chip stack package according to the surface roughness data and the crack strength data, and perform curve feature extraction and vector encoding on the target relationship influence curve to obtain a relationship influence feature vector;

[0017] A processing module, used for inputting the relationship impact feature vector into a preset chip stacking package performance detection model to perform chip stacking package performance detection to obtain a chip stacking package performance index;

[0018] An output module is used to optimize the chip stacking packaging process of the chip stacking package according to the chip stacking packaging performance index, and output a corresponding target chip stacking packaging process strategy.

[0019] The third aspect of the present application provides a computer device, comprising: a memory and at least one processor, wherein the memory stores instructions; the at least one processor calls the instructions in the memory so that the computer device executes the above-mentioned surface detection method for chip stacking packaging.

[0020] A fourth aspect of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores instructions, which, when executed on a computer, enable the computer to execute the above-mentioned surface detection method for chip stacking packages.

[0021] In the technical solution provided by the present application, by combining thermal cycle testing with atomic force microscope image acquisition technology, the microscopic changes of the surface of the chip stacking package after undergoing temperature cycling can be accurately captured. This not only improves the accuracy of the evaluation of the surface state of the package, but also enables the discovery of potential defects and failure risks at an early stage, thereby greatly improving the reliability and performance stability of the chip. The automatic detection and analysis of surface roughness using the YOLOv7 model greatly improves the detection efficiency and accuracy compared to the traditional manual evaluation method. The introduction of the YOLOv7 model not only reduces human errors, but also enables rapid and large-scale surface defect detection, providing a strong guarantee for high-quality chip packaging production. Through the three-dimensional thermal mechanical finite element analysis modeling and crack strength evaluation, combined with the extraction and encoding of the relationship-affecting feature vector, the specific impact of thermal cycles on the performance of the chip stacking package, as well as the relationship between surface roughness and crack strength can be deeply analyzed. This in-depth analysis provides a scientific basis for the optimization of the packaging process, enabling targeted adjustment of packaging parameters, further improving packaging quality, and thus improving the surface detection accuracy of the chip stacking package. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0023] Figure 1 A schematic diagram of an embodiment of a surface detection method for a chip stack package in an embodiment of the present application;

[0024] Figure 2 It is a schematic diagram of an embodiment of a surface detection device for a chip stack package in an embodiment of the present application. DETAILED DESCRIPTION

[0025] The embodiment of the present application provides a surface detection method and device for a chip stack package. The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments described here can be implemented in an order other than that illustrated or described here. In addition, the terms "including" or "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0026] For ease of understanding, the specific process of the embodiment of the present application is described below. Figure 1 , an embodiment of the surface detection method of the chip stack package in the embodiment of the present application includes:

[0027] Step 101, performing multiple thermal cycle tests on the chip stack package, and collecting images of the chip stack package through an atomic force microscope to obtain a target high-resolution surface image of each thermal cycle test;

[0028] It is understandable that the execution subject of the present application may be a surface detection device for a chip stack package, or a terminal or a server, which is not limited here. The present application embodiment is described by taking a server as the execution subject as an example.

[0029] Specifically, the thermal cycle parameters of multiple thermal cycle tests are set, including the temperature range, duration, and heating and cooling rate of the thermal cycle, to ensure that these parameters can simulate various thermal stress conditions that may be encountered in actual use. Among them, the number of thermal cycles: each chip stacking package sample is subjected to 50 thermal cycle tests. Temperature range: The temperature range of each thermal cycle is -40°C to 125°C. Heating and cooling rate: The temperature change rate is set to 10°C / minute. Holding time: 15 minutes at the highest temperature (125°C) and the lowest temperature (-40°C). Sampling frequency: Surface image acquisition and analysis are performed after the 1st, 10th, 20th, 30th, 40th and 50th cycles to track the changes in the chip surface state with the number of thermal cycles. Through the set thermal cycle parameters, the chip stacking package is subjected to multiple thermal stress tests to simulate the possible impact of the temperature change of the chip on the package surface in actual work. After each thermal cycle test, an atomic force microscope is used to collect images. The device can capture tiny changes on the chip surface with nanometer resolution, thereby obtaining the initial high-resolution surface image after each thermal cycle test. The initial high-resolution surface image is subjected to image standardization to eliminate the variation introduced by different acquisition conditions (such as lighting, angle, etc.) between images, ensuring that all images are under the same standardized conditions for subsequent analysis. The first high-resolution surface image of each thermal cycle test is subjected to image enhancement processing to further improve the image quality. By enhancing the details such as edges and textures in the image, the tiny defects and features on the chip surface are more obvious, which facilitates accurate analysis. By applying various image processing algorithms, such as sharpening and contrast enhancement, the image details are highlighted. The second high-resolution surface image of each thermal cycle test is subjected to denoising processing to eliminate the noise introduced during image acquisition and processing and retain the effective information in the image. Denoising techniques include the use of low-pass filters, median filters or advanced algorithms such as wavelet transform denoising to ensure that the final image obtained is as clear and accurate as possible.

[0030] Step 102: Input the target high-resolution surface image of each thermal cycle test into a preset YOLOv7 model to perform surface roughness detection of the chip stack package to obtain surface roughness data of each thermal cycle test;

[0031] Specifically, the high-resolution surface image of the target for each thermal cycle test is input into the preset YOLOv7 model, and the high-resolution surface image of the target for each thermal cycle test is resized through the input layer in the YOLOv7 model to meet the requirements of the input layer of the YOLOv7 model, ensuring that each image is adjusted to a uniform size so that it can be effectively processed by the model. Among them, the specific YOLOv7 model includes: 1. Network structure: YOLOv7 uses the improved CSPDarknet53 as the backbone network and introduces the E-ELAN structure to enhance the feature extraction capability. 2. Attention mechanism: YOLOv7 integrates the CBAM attention mechanism to increase the focus on key features. 3. Multi-scale prediction: YOLOv7 uses a combination of FPN and PAN to achieve multi-scale feature fusion to better handle targets of different sizes. 4. Loss function: YOLOv7 uses an improved CIOU loss function to optimize the positioning accuracy of the bounding box. 5. Data enhancement: YOLOv7 introduces advanced data enhancement technologies such as Mosaic and MixUp to improve the generalization ability of the model. 6. Reasoning optimization: YOLOv7 uses reparameterization technology and dynamic calculation graph optimization to improve the reasoning speed. In this embodiment, the YOLOv7 model is used for surface roughness detection of chip stacking package. The input of the model is a 224x224x3 RGB image, and the output is the classification result of surface roughness (such as "smooth", "slightly rough", "moderately rough", "severely rough") and the corresponding confidence score. The model training uses a data set containing 10,000 labeled chip surface images. After 200 epochs of training, it achieves 95% accuracy on the validation set. In practical applications, the model can complete the roughness detection of a single image within 0.02 seconds, meeting the needs of real-time detection. Through the convolutional attention layer in the YOLOv7 model, feature extraction is performed on each standardized high-resolution surface image, and subtle textures and edges in the image are identified and analyzed to obtain the initial surface feature map, which contains the roughness-related features of various areas on the chip surface. The initial surface feature map is processed by the receptive field block of the YOLOv7 model, and the key information in the image, such as surface defects and texture differences, is enhanced through feature enhancement technology, so as to obtain a clearer and more prominent target surface feature map. Feature enhancement directly affects the model's ability to identify surface roughness, ensuring the accuracy and reliability of the test results. The output layer in the YOLOv7 model is used to detect the surface of the chip stacking package for each thermal cycle test, and this information is converted into quantifiable data to obtain the target surface detection results for each thermal cycle test, and then calculate the specific surface roughness data.

[0032] Step 103: Perform three-dimensional thermomechanical finite element analysis modeling on the chip stack package based on multiple thermal cycle tests to obtain a chip stack finite element model for each thermal cycle test, and perform crack strength analysis on the chip stack finite element model to obtain crack strength data for each thermal cycle test;

[0033] Specifically, the specific packaging parameters of the chip stack package are obtained, including information such as chip size, material properties, and stacking levels. Based on the obtained packaging parameters and specific test parameters of multiple thermal cycle tests, such as temperature range, heating rate, and holding time, a three-dimensional thermal mechanical finite element analysis model is performed on the chip stack package. The modeling process is completed through professional finite element analysis software. Each thermal cycle test will generate a corresponding chip stack finite element model, which can depict the physical state of the chip under different thermal cycle conditions. The boundary conditions and loading are set for each generated chip stack finite element model to simulate the actual thermal cycle test environment, including setting the temperature boundary conditions of the model and applying corresponding thermal loading. The temperature boundary conditions are set according to the temperature changes of the thermal cycle test, and the thermal loading is determined according to the thermal stress that the chip may withstand during the test. Through these settings, each model can be accurately simulated in the finite element analysis software to simulate its behavior during the thermal cycle. Through the thermal mechanical analysis module in the finite element analysis software, thermal deformation and thermal stress analysis are performed on each chip stack finite element model according to the set boundary conditions and thermal loading. The analysis results will show the deformation and stress distribution of the chip during the thermal cycle. Based on the thermal deformation and thermal stress parameters, the crack strength analysis is performed using finite element analysis software to evaluate the crack formation tendency and crack extension ability of the chip stack package in each thermal cycle test, thereby obtaining the crack strength data for each thermal cycle test. These data are key indicators for measuring the structural integrity and reliability of the chip stack package under thermal stress, and provide an important quantitative basis for the surface inspection and performance evaluation of the chip stack package.

[0034] Step 104: construct a target relationship influence curve of the chip stack package according to the surface roughness data and the crack strength data, and perform curve feature extraction and vector encoding on the target relationship influence curve to obtain a relationship influence feature vector;

[0035] Specifically, curve fitting is performed on the surface roughness data and crack strength data to find the curve equation that best represents the data distribution trend, and the mathematical description of the relationship between surface roughness and crack strength is obtained, that is, the target relationship influence curve. Curve feature extraction is performed on the target relationship influence curve, and representative first curve feature points are identified from the constructed target relationship influence curve. These feature points are key nodes of the curve, such as extreme points, inflection points, etc., which can reflect the main change characteristics of the curve. By identifying these points, the basic form of the curve and the physical meaning it represents can be better understood. In order to quantify the overall trend and distribution range of the curve, the curve mean and curve standard deviation are calculated. The curve mean provides the average level of the curve as a whole, while the curve standard deviation reflects the degree of dispersion of each data point relative to the curve mean. Based on the curve standard deviation, the first curve feature points are screened, and those points that deviate too far from the average level are eliminated, and the more representative second curve feature points are retained to ensure that the final analysis focuses on those feature points that best reflect the main change trend of the curve, thereby improving the analysis accuracy and reliability of the model. The screened second curve feature points are vector encoded and converted into numerical forms that can be processed by computers. Each feature point is encoded as a vector with a specific dimension, which together form a relational influence feature vector. This feature vector not only contains the main feature information of the curve, but can also be directly used in subsequent machine learning and data analysis to predict the performance of the chip stack package under different conditions.

[0036] Step 105, inputting the relationship influence feature vector into a preset chip stacking package performance detection model to perform chip stacking package performance detection to obtain a chip stacking package performance index;

[0037] Specifically, the relationship influence feature vector is input into the preset chip stacking package performance detection model to predict the performance of the chip stacking package. The performance detection model includes an input layer, multiple threshold recurrent networks (RNNs) layers, and an output layer. The relationship influence feature vector is vector-normalized through the input layer to ensure the uniform scale of the input data and improve the efficiency of model training and the accuracy of prediction. The input influence feature vector is feature extracted through multiple threshold recurrent networks. The threshold recurrent network is a neural network specially used for processing sequence data, which can capture the time series characteristics and long-term dependencies in the data. Through the processing of the network layer, the model can extract deeper and more detailed feature information from the input feature vector. Each threshold recurrent network layer outputs a target influence feature vector, which contains important features and patterns extracted from the original data. The target influence feature vector of each threshold recurrent network is vector-fused through the output layer, and the information from different threshold recurrent networks is integrated to comprehensively predict the performance of the chip stacking package. The fused influence feature vector is processed through the sigmoid function in the output layer to predict the performance index of the chip stacking package. The Sigmoid function is a commonly used activation function that can map any value between 0 and 1 and is suitable for classification and probability prediction tasks. The Sigmoid function calculates the possibility of chip stacking package performance from the fusion influence feature vector, and the output performance index reflects the expected performance of the chip stacking package under specific conditions.

[0038] Step 106 : Optimize the chip stacking packaging process for the chip stacking package according to the chip stacking packaging performance index, and output a corresponding target chip stacking packaging process strategy.

[0039] Specifically, the initial process strategies of the chip stacking package are obtained. These strategies cover key process parameters such as inlet pressure, solder bump support height, chip thickness and aspect ratio, which together define the basic process flow of the chip stacking package. By analyzing the initial process strategy, the specific role of each process parameter and the relationship between them are clarified, and a complete set of first chip stacking package process flows is formed. The first chip stacking package process flow is encoded and converted into a format that can be processed by a computer algorithm, that is, process flow encoding information. The encoding not only contains the values ​​of all key process parameters, but also retains the logical relationship between them. The process optimization function of the genetic algorithm is defined according to the chip stacking package performance index. The genetic algorithm is a search algorithm that simulates natural selection and genetic mechanism, and finds the optimal solution to the problem through iterative evolution. The chip stacking package process is optimized by the genetic algorithm, and the process flow encoding information is initialized to generate multiple second chip stacking package process flows. These processes are generated on the basis of the initial process flow through the selection, crossover and mutation operations of the genetic algorithm, and they represent different combinations of process parameters. Afterwards, the second chip stacking package process flow is optimized by the process optimization function. Select the target process flow that best meets the performance index requirements from all possible process flows. The algorithm will evaluate the performance of each process flow, such as its impact on chip performance, production cost and efficiency, to determine the optimal solution. According to the obtained target chip stacking packaging process flow, the initial chip stacking packaging process strategy is optimized. According to the results of the genetic algorithm solution, the parameters such as inlet pressure, solder bump support height, chip thickness and aspect ratio are adjusted to achieve higher performance indicators. Through the above steps, the final target chip stacking packaging process strategy is output.

[0040] In the embodiment of the present application, by combining thermal cycle test with atomic force microscope image acquisition technology, the microscopic changes of the surface of the chip stack package after experiencing temperature cycle can be accurately captured. This not only improves the accuracy of the evaluation of the surface state of the package, but also enables the discovery of potential defects and failure risks in the early stage, thereby greatly improving the reliability and performance stability of the chip. The automatic detection and analysis of surface roughness using the YOLOv7 model greatly improves the detection efficiency and accuracy compared to the traditional manual evaluation method. The introduction of the YOLOv7 model not only reduces human errors, but also enables rapid and large-scale surface defect detection, providing a strong guarantee for high-quality chip packaging production. Through the three-dimensional thermal mechanical finite element analysis modeling and crack strength evaluation, combined with the extraction and encoding of the relationship-affecting feature vector, the specific impact of thermal cycles on the performance of the chip stack package, as well as the relationship between surface roughness and crack strength can be deeply analyzed. This in-depth analysis provides a scientific basis for the optimization of the packaging process, enabling targeted adjustment of packaging parameters, further improving packaging quality, and thus improving the surface detection accuracy of the chip stack package.

[0041] In a specific embodiment, the process of executing step 101 may specifically include the following steps:

[0042] (1) Setting thermal cycle parameters for multiple thermal cycle tests and performing multiple thermal cycle tests on the chip stack package;

[0043] (2) After each thermal cycle test, the chip stack package is imaged using an atomic force microscope to obtain an initial high-resolution surface image of each thermal cycle test;

[0044] (3) performing image standardization processing on the initial high-resolution surface image of each thermal cycle test to obtain a first high-resolution surface image of each thermal cycle test;

[0045] (4) performing image enhancement processing on the first high-resolution surface image of each thermal cycle test to obtain a second high-resolution surface image of each thermal cycle test;

[0046] (5) De-noising the second high-resolution surface image of each thermal cycle test to obtain a target high-resolution surface image of each thermal cycle test.

[0047] Specifically, the thermal cycle parameters of multiple thermal cycle tests are set, including temperature range, heating and cooling rate, holding time, etc., to ensure that the thermal stress that the chip may suffer in actual operation can be fully simulated. For example, if the chip is expected to experience a temperature change from -40°C to 125°C during use, the parameters of the thermal cycle test should be set within this range, while taking into account the temperature change rate and periodicity to ensure that the test can fully simulate the actual situation. After each thermal cycle test, the surface of the chip stack package is imaged by atomic force microscopy. The atomic force microscope can provide nanometer-level resolution, so that the microstructure of the chip surface can be clearly displayed, and the initial high-resolution image of the chip surface after each thermal cycle test is obtained. After that, each initial high-resolution surface image collected is standardized to eliminate the variation introduced by factors such as illumination and angle that may occur during the image acquisition process, and ensure that all images are under the same standard when compared and analyzed. By adjusting the brightness, contrast and other parameters of the image, the image achieves a consistent visual effect. Then, the first high-resolution surface image of each thermal cycle test is image enhanced to enhance the details of the image and make the microscopic features of the chip surface more obvious. By applying image enhancement techniques, such as sharpening and contrast enhancement, the texture and defects on the chip surface can be better highlighted. The second high-resolution surface image of each thermal cycle test is denoised to remove irrelevant noise and retain valuable signals in the image. Image processing techniques, such as median filtering and wavelet transform denoising, are used to effectively reduce image noise, making the final target high-resolution surface image clearer and more accurate.

[0048] In a specific embodiment, the process of executing step 102 may specifically include the following steps:

[0049] (1) Inputting the target high-resolution surface image of each thermal cycle test into a preset YOLOv7 model, resizing the target high-resolution surface image of each thermal cycle test through the input layer in the YOLOv7 model to obtain a standard high-resolution surface image of each thermal cycle test;

[0050] (2) The convolutional attention layer in the YOLOv7 model is used to extract features from the standard high-resolution surface image of each thermal cycle test to obtain the initial surface feature map of each thermal cycle test;

[0051] (3) The initial surface feature map of each thermal cycle test is enhanced through the receptive field block in the YOLOv7 model to obtain the target surface feature map of each thermal cycle test;

[0052] (4) Using the output layer in the YOLOv7 model, the target surface feature map of each thermal cycle test is used to detect the surface of the chip stack package, and the target surface detection result of each thermal cycle test is obtained;

[0053] (5) Calculate the surface roughness data for each thermal cycle test based on the target surface detection results.

[0054] Specifically, the target high-resolution surface image of each thermal cycle test is input into the YOLOv7 model, and the image is resized to obtain a standard high-resolution surface image. The original high-resolution image size may not match the input requirements of the YOLOv7 model, so the image size needs to be automatically adjusted through the input layer of the model to ensure that each image can be correctly processed by the model. The convolutional attention layer of the YOLOv7 model is used to extract features from each standard high-resolution surface image. The convolutional neural network (CNN) is used to identify various features in the image, such as edges, textures, etc., and the attention mechanism is used to focus on the key parts of the image, such as tiny defects or abnormal areas on the chip surface. The receptive field block of the YOLOv7 model is used to enhance the features of the initial surface feature map. The receptive field block can enhance the key features in the image by integrating feature information from different scales, making tiny defects or abnormal areas more obvious. The enhanced target surface feature map is used for the final chip stacking package surface inspection through the output layer of the YOLOv7 model. The output layer converts the enhanced feature map into specific detection results, such as the location, type and severity of surface defects, through a neural network structure, such as sigmoid or softmax function. Based on this information, the surface roughness data of each thermal cycle test is calculated.

[0055] In a specific embodiment, the process of executing step 103 may specifically include the following steps:

[0056] (1) Obtaining chip stacking packaging parameters of the chip stacking package, and performing three-dimensional thermomechanical finite element analysis modeling on the chip stacking package based on the thermal cycle test parameters of multiple thermal cycle tests, to obtain a chip stacking finite element model for each thermal cycle test;

[0057] (2) Setting boundary conditions and loading for the chip stack finite element model for each thermal cycle test to obtain temperature boundary conditions and thermal loading;

[0058] (3) According to the temperature boundary conditions and thermal loading, the thermal deformation and thermal stress analysis of the chip stack finite element model is performed to obtain the thermal deformation and thermal stress parameters of each thermal cycle test;

[0059] (4) The crack strength analysis is performed using thermal deformation and thermal stress parameters to obtain the crack strength data for each thermal cycle test.

[0060] Specifically, the specific packaging parameters of the chip stack package are obtained, including the chip size, material properties (such as thermal conductivity, thermal expansion coefficient, etc.), stacking level, solder joint location, etc. After obtaining these packaging parameters, the chip stack package is modeled by three-dimensional thermal mechanical finite element analysis combined with the test parameters of multiple thermal cycle tests, such as temperature range, heating and cooling rate, holding time, etc. A three-dimensional model is created based on the actual structure and material properties of the chip through finite element analysis software, such as ANSYS or ABAQUS. The model can simulate the physical behavior of the real chip stack package in the thermal cycle test. The boundary conditions and loading are set for the chip stack finite element model of each thermal cycle test. This includes setting the external temperature conditions of the model to simulate the environment of the thermal cycle test, and applying thermal loading to reflect the impact of temperature changes on the chip. Then, according to the set temperature boundary conditions and thermal loading, the chip stack finite element model is subjected to thermal deformation and thermal stress analysis. The temperature distribution, thermal deformation amount, and thermal stress generated by the model during the entire thermal cycle are calculated. These analysis results reflect the physical state of the chip when it is affected by thermal cycles, including the maximum thermal stress area and thermal deformation that may occur. For example, the analysis may show that a certain area in the chip has a higher concentration of thermal stress due to the mismatch of thermal expansion coefficients, which may be a potential crack formation area. Based on the obtained thermal deformation and thermal stress parameters, a crack strength analysis is performed. The crack formation tendency and crack resistance of the chip stack package under the most unfavorable thermal stress conditions are evaluated. By comparing the thermal stress with the crack strength of the material, the location and strength of cracks that may form during the thermal cycle test are predicted. For example, through analysis, it is found that the thermal stress in a corner of the chip during the thermal cycle exceeds the crack strength threshold of the material, indicating that there is a higher risk of crack formation here.

[0061] In a specific embodiment, the process of executing step 104 may specifically include the following steps:

[0062] (1) Perform curve fitting on the surface roughness data and crack strength data to obtain the target relationship influence curve of the chip stacking package;

[0063] (2) extracting curve features from the target relationship influence curve to obtain a plurality of first curve feature points;

[0064] (3) Calculate the mean value of the target relationship influence curve to obtain the mean value of the curve, and calculate the standard deviation of the target relationship influence curve based on the mean value of the curve to obtain the standard deviation of the curve;

[0065] (4) screening the plurality of first curve feature points according to the curve standard deviation to obtain a plurality of second curve feature points;

[0066] (5) Perform vector encoding on multiple feature points of the second curve to obtain a relationship influence feature vector.

[0067] Specifically, for surface roughness data and crack strength data, a target relationship influence curve that can reflect the relationship between the two data is established by curve fitting technology. Curve fitting finds the best fitting curve by minimizing the difference between experimental data and model prediction data. For example, assuming that there are a series of experimental data points of surface roughness and crack strength, by selecting a suitable mathematical model, such as a polynomial function, an exponential function or a logarithmic function, etc., and using algorithms such as the least squares method to determine the parameters of this function, a curve that can reflect the relationship between surface roughness and crack strength and better fit the experimental data is obtained. Curve feature extraction is performed on the target relationship influence curve to obtain multiple first curve feature points. These feature points may include maximum points, minimum points, inflection points, etc. of the curve, which represent the key change characteristics of the curve. By analyzing these feature points, the intrinsic connection between surface roughness and crack strength is obtained. For example, a minimum point may indicate that the crack strength reaches the lowest at a certain surface roughness level, which helps to optimize the chip stacking packaging process. Then, the curve mean is calculated for the target relationship influence curve, and the curve standard deviation is further calculated based on the curve mean. The mean of the curve represents the overall average level, while the standard deviation of the curve reflects the degree of dispersion of each data point relative to the average level. The consistency and variability of the relationship between surface roughness and crack strength are evaluated by calculating the mean and standard deviation of the entire data set. Based on the obtained standard deviation of the curve, the characteristic points of the first curve are screened to leave the more representative characteristic points of the second curve. Ensure that the subsequent analysis focuses on those data points that best reflect the core characteristics of the relationship between surface roughness and crack strength, thereby improving the prediction accuracy and practicality of the model. The characteristic points of the second curve are vector-encoded to obtain the relationship influence feature vector.

[0068] In a specific embodiment, the process of executing step 105 may specifically include the following steps:

[0069] (1) Inputting the relationship impact feature vector into a preset chip stacking package performance detection model, where the chip stacking package performance detection model includes: an input layer, multiple threshold recurrent networks, and an output layer;

[0070] (2) Perform vector normalization on the relationship influence feature vector through the input layer to obtain the input influence feature vector;

[0071] (3) Extracting features of the input influence feature vectors through multiple threshold recurrent networks respectively, and obtaining the target influence feature vector of each threshold recurrent network;

[0072] (4) The target influence feature vectors of each threshold recurrent network are fused through the output layer to obtain the fused influence feature vector, and the chip stacking packaging performance index is predicted for the fused influence feature vector through the sigmoid function in the output layer to obtain the chip stacking packaging performance index.

[0073] Specifically, the relationship influence feature vector is input into the preset chip stacking package performance detection model. Vector normalization is performed through the input layer of the model to ensure that the range and distribution of the input data are consistent with the data used in model training, thereby avoiding model prediction deviations caused by different data scales. The input influence feature vector is extracted through multiple threshold recurrent networks. The threshold recurrent network can capture the time series characteristics and long-term dependencies in the data. Each network outputs a target influence feature vector, which represents the high-level features extracted from the original input. Then, the target influence feature vectors from different RNN layers are fused through the output layer of the model. Through a series of weighted and nonlinear transformations, the information from different feature extraction networks is integrated to form a fused influence feature vector that comprehensively reflects the factors affecting the performance of the chip stacking package. The fused influence feature vector is processed by the sigmoid function in the output layer to predict the performance indicators of the chip stacking package. The Sigmoid function is a function that maps the input to the (0, 1) interval, which is suitable for completing binary classification tasks or generating probability predictions. The sigmoid function is used to process the fused impact feature vector to obtain a prediction value, which represents the probability that the chip stacking package reaches a certain performance standard based on the current input feature vector.

[0074] In a specific embodiment, the process of executing step 106 may specifically include the following steps:

[0075] (1) obtaining an initial chip stacking packaging process strategy of a chip stacking package, and performing process flow analysis on the initial chip stacking packaging process strategy to obtain a first chip stacking packaging process flow, wherein the first chip stacking packaging process flow includes: inlet pressure, solder bump support height, chip thickness, and aspect ratio;

[0076] (2) performing process flow coding processing on the first chip stacking packaging process flow to obtain process flow coding information;

[0077] (3) defining a process optimization function of a genetic algorithm according to the chip stacking packaging performance index, and initializing a chip stacking packaging process group for the process flow encoding information through the genetic algorithm to generate a plurality of second chip stacking packaging process flows;

[0078] (4) Optimizing the plurality of second chip stacking packaging process flows through a process optimization function to obtain a target chip stacking packaging process flow;

[0079] (5) Optimize the initial chip stacking packaging process strategy according to the target chip stacking packaging process flow, and output the corresponding target chip stacking packaging process strategy.

[0080] Specifically, the initial process strategy of the chip stacking package is obtained. The strategy records the key parameters in the chip production process, such as inlet pressure, solder bump support height, chip thickness and aspect ratio, etc. These parameters directly affect the performance and reliability of the chip. The initial process strategy is analyzed by process flow, and the process strategy is converted into a format that can be processed by the algorithm. During the analysis process, each process parameter and its relationship with each other are clearly recorded to form a first chip stacking package process flow. The first chip stacking package process flow is encoded and converted into process flow encoding information, and the process flow is digitized so that it can be processed by a genetic algorithm. Process flow encoding usually involves assigning a digital identifier to each process parameter and recording the dependency between these parameters. Based on the chip stacking package performance index, a process optimization function of the genetic algorithm is defined. The genetic algorithm is a search algorithm that simulates the natural evolution process and finds the optimal solution in multiple solutions in an iterative manner. In this embodiment, the genetic algorithm is used to find the optimal chip stacking package process flow. The process optimization function evaluates the pros and cons of each process flow based on performance indicators, and these performance indicators may include the electrical performance, thermal performance, mechanical strength, etc. of the chip. The genetic algorithm is used to initialize the chip stacking packaging process group for the process flow encoding information, and multiple candidate second chip stacking packaging process flows are generated. Through continuous iteration, the optimal process flow is gradually approached. After that, the candidate process flow is optimized through the process optimization function, considering the interaction between different process parameters and their impact on the final chip performance, and determining the process flow that can maximize chip performance or minimize cost. The initial process strategy is optimized according to the optimal process flow, and the corresponding target chip stacking packaging process strategy is output. Based on the results obtained by the genetic algorithm, parameters such as the inlet pressure and the height of the solder bump support may need to be adjusted to achieve the goal of performance optimization or cost control.

[0081] The surface detection method of the chip stack package in the embodiment of the present application is described above. The surface detection device of the chip stack package in the embodiment of the present application is described below. Figure 2 , an embodiment of the surface detection device of the chip stack package in the embodiment of the present application includes:

[0082] The acquisition module 201 is used to perform multiple thermal cycle tests on the chip stack package, and to acquire images of the chip stack package through an atomic force microscope to obtain a target high-resolution surface image for each thermal cycle test;

[0083] A detection module 202 is used to input the target high-resolution surface image of each thermal cycle test into a preset YOLOv7 model to perform surface roughness detection of the chip stack package to obtain surface roughness data of each thermal cycle test;

[0084] The analysis module 203 is used to perform three-dimensional thermomechanical finite element analysis modeling on the chip stack package based on multiple thermal cycle tests to obtain a chip stack finite element model for each thermal cycle test, and perform crack strength analysis on the chip stack finite element model to obtain crack strength data for each thermal cycle test;

[0085] A construction module 204 is used to construct a target relationship influence curve of the chip stack package according to the surface roughness data and the crack strength data, and perform curve feature extraction and vector encoding on the target relationship influence curve to obtain a relationship influence feature vector;

[0086] A processing module 205 is used to input the relationship influence feature vector into a preset chip stacking package performance detection model to perform chip stacking package performance detection to obtain a chip stacking package performance index;

[0087] The output module 206 is used to optimize the chip stacking packaging process of the chip stacking package according to the chip stacking packaging performance index, and output a corresponding target chip stacking packaging process strategy.

[0088] Through the synergy of the above components, by combining thermal cycle testing with atomic force microscope image acquisition technology, the microscopic changes of the surface of the chip stack package after temperature cycling can be accurately captured. This not only improves the accuracy of the evaluation of the surface state of the package, but also enables the discovery of potential defects and failure risks at an early stage, thereby greatly improving the reliability and performance stability of the chip. The automatic detection and analysis of surface roughness using the YOLOv7 model greatly improves the detection efficiency and accuracy compared to the traditional manual evaluation method. The introduction of the YOLOv7 model not only reduces human errors, but also enables rapid and large-scale surface defect detection, providing a strong guarantee for high-quality chip packaging production. Through three-dimensional thermal mechanical finite element analysis modeling and crack strength evaluation, combined with the extraction and encoding of relational influence feature vectors, the specific impact of thermal cycles on the performance of chip stack packages and the relationship between surface roughness and crack strength can be deeply analyzed. This in-depth analysis provides a scientific basis for the optimization of the packaging process, enabling targeted adjustment of packaging parameters, further improving packaging quality, and thus improving the surface detection accuracy of chip stack packages.

[0089] The present application also provides a computer device, which includes a memory and a processor. The memory stores computer-readable instructions. When the computer-readable instructions are executed by the processor, the processor executes the steps of the surface detection method of the chip stack package in the above-mentioned embodiments.

[0090] The present application also provides a computer-readable storage medium, which may be a non-volatile computer-readable storage medium or a volatile computer-readable storage medium. Instructions are stored in the computer-readable storage medium. When the instructions are executed on a computer, the computer executes the steps of the surface detection method for the chip stack package.

[0091] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described systems, systems and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0092] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc., various media that can store program codes.

[0093] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A surface detection method for chip stacking package, characterized in that: The surface detection method of the chip stack package comprises: Performing multiple thermal cycle tests on the chip stack package, and collecting images of the chip stack package by atomic force microscopy to obtain a target high-resolution surface image for each thermal cycle test; Inputting the target high-resolution surface image of each thermal cycle test into a preset YOLOv7 model to detect the surface roughness of the chip stacking package, and obtaining the surface roughness data of each thermal cycle test; specifically comprising: inputting the target high-resolution surface image of each thermal cycle test into a preset YOLOv7 model, and performing size processing on the target high-resolution surface image of each thermal cycle test through the input layer in the YOLOv7 model, and obtaining the standard high-resolution surface image of each thermal cycle test; performing feature extraction on the standard high-resolution surface image of each thermal cycle test through the convolutional attention layer in the YOLOv7 model, and obtaining the initial surface feature map of each thermal cycle test; performing feature enhancement on the initial surface feature map of each thermal cycle test through the receptive field block in the YOLOv7 model, and obtaining the target surface feature map of each thermal cycle test; performing chip stacking package surface detection on the target surface feature map of each thermal cycle test through the output layer in the YOLOv7 model, and obtaining the target surface detection result of each thermal cycle test; and calculating the surface roughness data of each thermal cycle test according to the target surface detection result; Based on the multiple thermal cycle tests, three-dimensional thermal mechanical finite element analysis modeling is performed on the chip stack package to obtain a chip stack finite element model for each thermal cycle test, and crack strength analysis is performed on the chip stack finite element model to obtain crack strength data for each thermal cycle test; Constructing a target relationship influence curve of the chip stack package according to the surface roughness data and the crack strength data, and performing curve feature extraction and vector encoding on the target relationship influence curve to obtain a relationship influence feature vector; Inputting the relationship influence feature vector into a preset chip stacking package performance detection model to perform chip stacking package performance detection to obtain a chip stacking package performance index; According to the chip stacking packaging performance index, the chip stacking packaging process is optimized for the chip stacking package, and a corresponding target chip stacking packaging process strategy is output.

2. The surface detection method of chip stacking package according to claim 1, characterized in that: The chip stacking package is subjected to multiple thermal cycle tests, and an image of the chip stacking package is collected by an atomic force microscope to obtain a target high-resolution surface image for each thermal cycle test, including: Setting thermal cycle parameters for multiple thermal cycle tests and performing multiple thermal cycle tests on the chip stack package; After each thermal cycle test is completed, an image of the chip stack package is collected by an atomic force microscope to obtain an initial high-resolution surface image of each thermal cycle test; Performing image standardization processing on the initial high-resolution surface image of each thermal cycle test to obtain a first high-resolution surface image of each thermal cycle test; Performing image enhancement processing on the first high-resolution surface image of each thermal cycle test to obtain a second high-resolution surface image of each thermal cycle test; The second high-resolution surface image of each thermal cycle test is subjected to denoising processing to obtain a target high-resolution surface image of each thermal cycle test.

3. The surface detection method of chip stacking package according to claim 1, characterized in that: The three-dimensional thermomechanical finite element analysis modeling is performed on the chip stack package based on the multiple thermal cycle tests to obtain a chip stack finite element model for each thermal cycle test, and the crack strength analysis is performed on the chip stack finite element model to obtain crack strength data for each thermal cycle test, including: Acquiring chip stacking packaging parameters of the chip stacking package, and performing three-dimensional thermomechanical finite element analysis modeling on the chip stacking package based on the thermal cycle test parameters of the multiple thermal cycle tests to obtain a chip stacking finite element model of each thermal cycle test; The boundary conditions and loading are set for the chip stack finite element model of each thermal cycle test to obtain the temperature boundary conditions and thermal loading; According to the temperature boundary conditions and the thermal loading, thermal deformation and thermal stress analysis are performed on the chip stack finite element model to obtain thermal deformation and thermal stress parameters for each thermal cycle test; The crack strength analysis is performed using the thermal deformation and thermal stress parameters to obtain crack strength data for each thermal cycle test.

4. The surface detection method of chip stacking package according to claim 3, characterized in that: The step of constructing a target relationship influence curve of the chip stack package according to the surface roughness data and the crack strength data, and performing curve feature extraction and vector encoding on the target relationship influence curve to obtain a relationship influence feature vector includes: Performing curve fitting on the surface roughness data and the crack strength data to obtain a target relationship influence curve of the chip stacking package; Extracting curve features from the target relationship influence curve to obtain a plurality of first curve feature points; Performing curve mean calculation on the target relationship influence curve to obtain a curve mean, and performing curve standard deviation calculation on the target relationship influence curve according to the curve mean to obtain a curve standard deviation; Screening the plurality of first curve feature points according to the curve standard deviation to obtain a plurality of second curve feature points; Vector encoding is performed on the plurality of second curve feature points to obtain a relationship influence feature vector.

5. The surface detection method of chip stacking package according to claim 4, characterized in that: The step of inputting the relationship influence feature vector into a preset chip stacking package performance detection model to perform chip stacking package performance detection to obtain a chip stacking package performance index includes: Inputting the relationship impact feature vector into a preset chip stacking package performance detection model, wherein the chip stacking package performance detection model includes: an input layer, a plurality of threshold recurrent networks, and an output layer; Performing vector normalization processing on the relationship impact feature vector through the input layer to obtain an input impact feature vector; Performing feature extraction on the input impact feature vectors respectively through the multiple threshold recurrent networks to obtain a target impact feature vector of each threshold recurrent network; The target influencing feature vectors of each threshold recurrent network are vector-fused through the output layer to obtain a fused influencing feature vector, and the chip stacking packaging performance index is predicted for the fused influencing feature vector through the sigmoid function in the output layer to obtain a chip stacking packaging performance index.

6. The surface detection method of chip stacking package according to claim 5, characterized in that: The step of optimizing the chip stacking packaging process of the chip stacking package according to the chip stacking packaging performance index and outputting a corresponding target chip stacking packaging process strategy comprises: Acquire an initial chip stacking packaging process strategy of the chip stacking package, and perform process flow analysis on the initial chip stacking packaging process strategy to obtain a first chip stacking packaging process flow, wherein the first chip stacking packaging process flow includes: inlet pressure, solder bump support height, chip thickness, and aspect ratio; Performing process flow coding processing on the first chip stacking packaging process flow to obtain process flow coding information; Defining a process optimization function of a genetic algorithm according to the chip stacking packaging performance index, and initializing a chip stacking packaging process flow group for the process flow encoding information through the genetic algorithm to generate a plurality of second chip stacking packaging process flows; Optimizing and solving the plurality of second chip stacking packaging process flows by using the process optimization function to obtain a target chip stacking packaging process flow; The initial chip stacking packaging process strategy is optimized according to the target chip stacking packaging process flow, and the corresponding target chip stacking packaging process strategy is output.

7. A surface detection device for chip stacking package, characterized in that: The surface detection device of the chip stack package comprises: An acquisition module is used to perform multiple thermal cycle tests on the chip stack package, and to acquire images of the chip stack package through an atomic force microscope to obtain a target high-resolution surface image for each thermal cycle test; A detection module is used to input the target high-resolution surface image of each thermal cycle test into a preset YOLOv7 model to perform surface roughness detection of a chip stacking package, and obtain surface roughness data for each thermal cycle test; specifically comprising: inputting the target high-resolution surface image of each thermal cycle test into a preset YOLOv7 model, and performing size processing on the target high-resolution surface image of each thermal cycle test through the input layer in the YOLOv7 model to obtain a standard high-resolution surface image for each thermal cycle test; performing feature extraction on the standard high-resolution surface image of each thermal cycle test through the convolutional attention layer in the YOLOv7 model to obtain an initial surface feature map for each thermal cycle test; performing feature enhancement on the initial surface feature map of each thermal cycle test through the receptive field block in the YOLOv7 model to obtain a target surface feature map for each thermal cycle test; performing chip stacking package surface detection on the target surface feature map of each thermal cycle test through the output layer in the YOLOv7 model to obtain a target surface detection result for each thermal cycle test; and calculating the surface roughness data for each thermal cycle test according to the target surface detection result; An analysis module, configured to perform three-dimensional thermomechanical finite element analysis modeling on the chip stack package based on the multiple thermal cycle tests to obtain a chip stack finite element model for each thermal cycle test, and perform crack strength analysis on the chip stack finite element model to obtain crack strength data for each thermal cycle test; A construction module, used to construct a target relationship influence curve of the chip stack package according to the surface roughness data and the crack strength data, and perform curve feature extraction and vector encoding on the target relationship influence curve to obtain a relationship influence feature vector; A processing module, used for inputting the relationship influence feature vector into a preset chip stacking package performance detection model to perform chip stacking package performance detection to obtain a chip stacking package performance index; An output module is used to optimize the chip stacking packaging process of the chip stacking package according to the chip stacking packaging performance index, and output a corresponding target chip stacking packaging process strategy.

8. A computer device, characterized in that: The computer device comprises: a memory and at least one processor, wherein instructions are stored in the memory; The at least one processor calls the instructions in the memory to enable the computer device to execute the surface detection method for the chip stack package according to any one of claims 1 to 6.

9. A computer-readable storage medium having instructions stored thereon, characterized in that: When the instructions are executed by the processor, the surface detection method for the chip stack package according to any one of claims 1 to 6 is implemented.

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