Single electron transistor radio frequency reflection measurement structure and preparation method thereof

Abstract

The present invention provides a single electron transistor radio frequency reflection measurement structure and a preparation method thereof. The single electron transistor radio frequency reflection measurement structure comprises a substrate, a gate oxide layer, and a split gate component comprising a strip-shaped channel limiting gate; a first gate unit is arranged on a first side of the channel limiting gate, and a first quantum dot is formed on an interface and on one side of a depletion region; a second gate unit is arranged on a second side of the channel limiting gate, and a second quantum dot is formed on an interface and on the other side of the depletion region; a source electrode and a drain electrode are arranged at intervals, and extend from above the gate oxide layer to the interface on the first side, respectively, to form a single electron transistor with the first quantum dot and the first gate unit; the first gate unit comprises a first accumulation gate, which is arranged adjacent to the first quantum dot and is suitable for transmitting a radio frequency signal, so as to utilize the radio frequency signal and the capacitive coupling effect between the single electron transistor and the second quantum dot to realize the measurement of a second electron state in the second quantum dot.

Description

Technical Field

[0001] At least one embodiment of the present invention relates to the fields of quantum technology and semiconductor chip technology, and in particular to a single-electron transistor radio frequency reflection measurement structure for a silicon-based semiconductor quantum chip and a preparation method thereof. Background Art

[0002] Quantum computing has the potential to surpass classical computing. Among the various systems that can realize quantum computing, the confinement of electron spins in semiconductor quantum dots provides an attractive platform for quantum information processing. Specifically, spin qubits in silicon are considered to be strong contenders for the realization of large-scale quantum processors due to their small qubit size, local and global control capabilities, complementary metal oxide semiconductor (CMOS) compatibility, long coherence time, weak hyperfine interactions, and the possibility of operation above 1 Kelvin (K). Among them, single-qubit gates with fidelity exceeding 99.9% and two-qubit gates with fidelity up to 99% have been demonstrated, marking a major progress in the implementation of quantum error correction protocols.

[0003] In the related technology, the single electron transistor is still the most important device in the application of single electron devices. In semiconductor quantum dots, DC measurement is widely used because of its simple circuit, minimal impact on quantum bits, and the ability to use low-pass filters to reduce some high-frequency noise. However, the main disadvantage of single electron transistors is that the measurement bandwidth is limited, usually only a few thousand hertz (can be further reduced using filters), which is attributed to the presence of parasitic capacitance in the DC line (usually in the range of hundreds of picofarads (pF)) and the relatively high input impedance of the amplifier and the output resistance of the single electron transistor (usually in the range of hundreds of kiloohms (KΩ)). Compared with the single quantum bit manipulation rate operating at the nanosecond (ns) level and the exchange coupling between quantum bits (up to tens of megahertz), this measurement rate is significantly slower.

[0004] Radio frequency (RF) reflectometry is an effective and sensitive technique for detecting charge and spin signals in semiconductor quantum dots. For devices operating in accumulation mode, a common approach to facilitate RF measurements is to relocate the ion implantation region to a location approximately 10 microns away from the center of the single-electron transistor and optimize the design of the accumulation gate. This optimization process includes reducing the overlap between the ion implantation region and the accumulation gate, as well as shortening the gate length. These design modifications are intended to mitigate signal leakage due to parasitic capacitance and address dissipative losses due to high impedance in the measurement circuit. Nonetheless, challenges associated with micro-nano manufacturing remain.

[0005] For enhancement mode devices such as silicon-metal oxide semiconductor (Si-MOS), the 2D electron gas below the electrode can act as a leakage path for RF signals when the RF circuit is connected to the ohmic contact (ohmic method). The capacitance between the lead gate and the 2D electron gas allows the RF signal to pass through the low impedance ground capacitance and the line resistance on the printed circuit board, making it challenging to effectively track transient changes in the impedance of the single electron transistor. Summary of the invention

[0006] In view of this, the present invention provides a single electron transistor radio frequency reflection measurement structure and a preparation method thereof, which can reduce the leakage of radio frequency signals.

[0007] As one aspect of an embodiment of the present invention, a single electron transistor radio frequency reflection measurement structure is provided, which is used for a silicon-based semiconductor quantum chip. The single electron transistor radio frequency reflection measurement structure includes a substrate, a gate oxide layer, a split gate assembly, and a source and a drain arranged at intervals. The gate oxide layer is arranged on the above-mentioned substrate, and the split gate assembly is arranged on the above-mentioned gate oxide layer. The above-mentioned split gate assembly includes a strip-shaped channel limiting gate, a first gate unit, and a second gate unit. The strip-shaped channel limiting gate is arranged on the above-mentioned gate oxide layer in a lateral direction, and is suitable for forming a depletion region on the interface between the gate oxide layer and the above-mentioned substrate to prevent electrons from tunneling from one side of the above-mentioned depletion region to the other side. The first gate unit is arranged on the first side of the above-mentioned channel limiting gate, and is suitable for forming a first quantum dot on the above-mentioned interface and on one side of the above-mentioned depletion region. The second gate unit is arranged on the second side of the above-mentioned channel limiting gate opposite to the above-mentioned first side, and is suitable for forming a second quantum dot on the above-mentioned interface and on the other side of the above-mentioned depletion region. The source and the drain are both on the first side and extend from above the gate oxide layer to the interface. The source and the drain form a single electron transistor with the first quantum dot and the first gate unit. The first gate unit includes a first accumulation gate, which is arranged adjacent to the first quantum dot and is suitable for transmitting an external radio frequency signal, so as to utilize the radio frequency signal and the capacitive coupling between the single electron transistor and the second quantum dot to achieve measurement of the second electron state in the second quantum dot.

[0008] According to an embodiment of the present invention, the first gate unit further comprises two lead gates, one of the two lead gates is electrically connected to the source, and the other lead gate is electrically connected to the drain, and each of the lead gates is adapted to form a coupling capacitor with a two-dimensional electron gas located below the lead gate, wherein the two-dimensional electron gas is formed by electrons flowing from the source and the drain converging on the interface under the voltage applied by the lead gates. The radio frequency signal is configured to be applied to the first quantum dot via the coupling capacitor.

[0009] According to an embodiment of the present invention, the first gate unit further includes a first plunger gate, two first barrier gates and a first limiting gate. The first plunger gate is electrically isolated from the channel limiting gate, extends from the channel limiting gate in a direction away from the channel limiting gate, and is suitable for defining the width of the first quantum dot in the lateral direction. The two first barrier gates are electrically isolated from the first plunger gate and the channel limiting gate, extend from the channel limiting gate in a direction away from the channel limiting gate and are arranged on both sides of the first plunger gate, and are suitable for regulating the tunneling rate of the first electron in the first quantum dot. The first limiting gate is spaced apart from the channel limiting gate, extends in a direction away from the channel limiting gate, and is electrically isolated from the first plunger gate and the two first barrier gates. The first limiting gate is arranged below the first plunger gate and the two first barrier gates, and is suitable for defining the length of the first quantum dot in the longitudinal direction.

[0010] According to an embodiment of the present invention, the angle between the turning lines of the first accumulation gate, the lead gate, the first plug gate, the first barrier gate and the first limiting gate extending away from the channel limiting gate and the lateral direction is 45 degrees or 135 degrees.

[0011] According to an embodiment of the present invention, the first accumulation gate extends from a position close to the first quantum dot toward a direction away from the channel limiting gate, and a longitudinal length of the first accumulation gate increases as a lateral length of the first accumulation gate from the first quantum dot increases.

[0012] According to an embodiment of the present invention, the second gate unit includes a second plunger gate, two second barrier gates and a second limiting gate. The second plunger gate is electrically isolated from the channel limiting gate, extends from the channel limiting gate in a direction away from the channel limiting gate, and is suitable for defining the width of the second quantum dot in the lateral direction. The two second barrier gates are electrically isolated from the second plunger gate and the channel limiting gate, and are extended from the channel limiting gate in a direction away from the channel limiting gate and are arranged on both sides of the second plunger gate, and are suitable for regulating the tunneling rate of the second electrons in the second quantum dot. The second limiting gate is spaced from the channel limiting gate, extends in a direction away from the channel limiting gate, is electrically isolated from the second plunger gate and the two second barrier gates, and is arranged below the second plunger gate and the two second barrier gates, and is suitable for defining the length of the second quantum dot in the longitudinal direction. Two second accumulation gates are arranged on both sides of the two second barrier gates that are far away from each other to control the second electrons entering and exiting the second quantum dot.

[0013] According to an embodiment of the present invention, the substrate includes a silicon substrate and a purified silicon layer. The purified silicon layer is disposed between the silicon substrate and the gate oxide layer, wherein the interface is located between the purified silicon layer and the gate oxide layer. The single electron transistor radio frequency reflection measurement structure also includes a magnetic layer, which is disposed around the second quantum dot with a spacing therebetween, and is suitable for providing a transverse gradient magnetic field to the second quantum dot to compensate for the spin-orbit coupling of the second electron in the purified silicon within the second quantum dot, thereby generating a driven rotation of the quantum bit.

[0014] According to an embodiment of the present invention, each of the source and the drain comprises an ion implantation region and an ohmic electrode. The ion implantation region is formed inside the substrate, and the ohmic electrode is electrically connected to the ion implantation region. The two lead gates are electrically connected to the two ion implantation regions in a one-to-one correspondence, and at least one lead gate is electrically contacted with the first accumulation gate to form a first electron reservoir, providing conditions for loading the first electron in the first quantum dot and exchanging the first electron with the first electron reservoir.

[0015] According to an embodiment of the present invention, the contact area between the lead gate and the first accumulation gate on a plane parallel to the substrate is 1 um×1 um.

[0016] As another aspect of an embodiment of the present invention, a method for preparing any of the above-mentioned single-electron transistor radio frequency reflection measurement structures is provided, the preparation method comprising:

[0017] forming a source electrode and a drain electrode on the substrate having a gate oxide layer formed thereon;

[0018] On the substrate formed with the source and the drain, a channel limiting gate, a first limiting gate, two lead gates, and a second limiting gate are formed, one of the two lead gates is electrically connected to the source, the other of the two lead gates is electrically connected to the drain, and the first limiting gate is located on a first side of the channel limiting gate, and the second limiting gate is located on a second side of the channel limiting gate;

[0019] Forming a first oxide layer on the surfaces of the channel limiting gate, the first limiting gate, the two lead gates and the second limiting gate to obtain a first substrate;

[0020] forming a first plug gate, two first accumulation gates, a second plug gate and two second accumulation gates on the first substrate, so that the first plug gate and the two first accumulation gates extend outward from the channel limiting gate in a direction away from the second side and are located on the first limiting gate, and the second plug gate and the two second accumulation gates extend from the channel limiting gate in a direction away from the first side and are located on the second limiting gate;

[0021] forming a second oxide layer on the surfaces of the first plug gate, the two first accumulation gates, the second plug gate and the two second accumulation gates to obtain a second substrate;

[0022] forming two first barrier gates and two second barrier gates on the second substrate, so that the two first barrier gates are respectively located on both sides of the first plug gate and between the two first limiting gates, and the two second barrier gates are respectively located on both sides of the second plug gate and between the two second limiting gates;

[0023] A third oxide layer is formed on the surfaces of the two first barrier gates and the two second barrier gates to obtain the single electron transistor radio frequency reflection measurement structure.

[0024] According to the single electron transistor radio frequency reflection measurement structure of the embodiment of the present invention, by setting the first accumulation gate close to the first quantum dot, the radio frequency signal can be transmitted to the vicinity of the first quantum dot through the first accumulation gate, thereby reducing the leakage of the radio frequency signal. The state of the first electron in the first quantum dot is affected by the radio frequency signal, and the electric field generated by the radio frequency signal affects the state of the second electron in the second quantum dot through the capacitive coupling between the single electron transistor and the first quantum dot. The change in the state of the second electron further affects the state of the first electron through the capacitive coupling, thereby changing the impedance of the single electron transistor, and changing the amplitude, phase, frequency and other parameters of the radio frequency signal, so that the number and position of the first electron in the first quantum dot can be determined according to the parameters such as the amplitude, phase and frequency. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0026] Figure 1 A partial top view of a single electron transistor radio frequency reflection measurement structure according to an embodiment of the present invention is shown;

[0027] Figure 2 Shows Figure 1 A partial enlarged view of the etched area of ​​the split gate assembly shown;

[0028] Figure 3 Schematically shows Figure 2 A partial enlarged view of part A shown;

[0029] Figure 4 Shows Figure 2 The cross-sectional view in the BB direction is shown;

[0030] Figure 5 Shows Figure 3 The cross-sectional view in the CC direction is shown;

[0031] Figure 6 Shows Figure 3 The cross-sectional view in the DD direction is shown;

[0032] Figure 7 A top view of a micromagnet according to an embodiment of the present invention is shown;

[0033] Figure 8 A flow chart showing a method for preparing a single electron transistor radio frequency reflection measurement structure according to an embodiment of the present invention;

[0034] Fig. 9 A top view of an ion implantation region according to an embodiment of the present invention is shown;

[0035] Fig.10 shows a top view of an ohmic electrode according to an embodiment of the present invention;

[0036] Fig.11 shows a top view of a first layer of electrodes according to an embodiment of the present invention;

[0037] Fig.12 shows a top view of a second layer electrode according to an embodiment of the present invention;

[0038] Fig.13 A top view of a third layer electrode according to an embodiment of the present invention is shown.

[0039] The following are the descriptions of the reference numerals:

[0040] 1- substrate;

[0041] 2-gate oxide layer;

[0042] 3- Split the grid assembly;

[0043] 31-channel limiting gate;

[0044] 32-a first gate unit;

[0045] 321-lead grid;

[0046] 322-first accumulation gate;

[0047] 323-first plunger gate;

[0048] 324-first barrier gate;

[0049] 325-first limiting gate;

[0050] 33-a second gate unit;

[0051] 331 - second plunger gate;

[0052] 332-second barrier gate;

[0053] 333-second limiting gate;

[0054] 334 - second accumulation gate;

[0055] 34-First area;

[0056] 35-Second area;

[0057] 4- Source;

[0058] 41- ion implantation region;

[0059] 42-Ohm electrode;

[0060] 5-Magnetic layer;

[0061] 6-field oxide layer;

[0062] 7- first oxide layer;

[0063] 8- second oxide layer;

[0064] 9- third oxide layer;

[0065] 10- Etching area. DETAILED DESCRIPTION

[0066] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0067] The terms used herein are only for describing specific embodiments and are not intended to limit the present invention. The terms "comprise", "include", etc. used herein indicate the existence of the features, steps, operations and / or components, but do not exclude the existence or addition of one or more other features, steps, operations or components.

[0068] All terms used herein, including technical and scientific terms, have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification, and should not be interpreted in an idealized or overly rigid manner.

[0069] When using expressions such as "at least one of A, B, and C, etc.", it should generally be interpreted as the meaning of the expression generally understood by those skilled in the art. For example, "a system having at least one of A, B, and C" should include but not be limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc. When using expressions such as "at least one of A, B, or C, etc.", it should generally be interpreted as the meaning of the expression generally understood by those skilled in the art. For example, "a system having at least one of A, B, or C" should include but not be limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.

[0070] It should also be noted that the directional terms mentioned in the embodiments, such as "upper", "lower", "front", "back", "left", "right", etc., are only reference directions of the drawings and are not intended to limit the scope of protection of the present invention. Throughout the drawings, the same elements are represented by the same or similar reference numerals. Conventional structures or configurations will be omitted when they may cause confusion in the understanding of the present invention.

[0071] In the process of implementing the present invention, it was found that in Si-MOS, the interface of silicon dioxide (SiO2) is only 10 nanometers (nm), and the dielectric constant of SiO2 is about 4. In order to ensure that the single-electron transistor can detect the change of the electronic state in the quantum dot, the single-electron transistor and the quantum dot are placed very close, usually around 30nm. The lead gate usually directly crosses the ion implantation area and goes deep into the quantum dot and the single-electron transistor to provide an electron reservoir. The problem with this structure is that when an RF reflection circuit is added to the source and drain, the signal will leak out through the capacitance formed by the lead gate and the two-dimensional electron gas below. As a result, the single-electron transistor cannot receive enough RF signals, resulting in low reflection sensitivity.

[0072] Figure 1 A partial top view of a single electron transistor radio frequency reflection measurement structure according to an embodiment of the present invention is shown. Figure 2 Shows Figure 1 A partial enlarged view of the etched area of ​​the split gate assembly shown, Figure 3 Schematically shows Figure 2 A partial enlarged view of part A shown, Figure 4 Shows Figure 2 The cross-sectional view along the BB direction is shown. Figure 5 Shows Figure 3 The cross-sectional view along the CC direction is shown. Figure 6 Shows Figure 3 The cross-sectional view along the DD direction is shown.

[0073] It should be noted that Figure 1 The etched area is not shown. Figure 2 The structure shown is located at Figure 1 The etched area of ​​the split gate component, Figures 1 to 3 The magnetic layers are not shown.

[0074] As one aspect of an embodiment of the present invention, a single electron transistor radio frequency reflection measurement structure for a silicon-based semiconductor quantum chip is provided, such as Figures 1 to 6 As shown, the single electron transistor radio frequency reflection measurement structure includes a substrate 1, a gate oxide layer 2, a split gate component 3, and a source and a drain arranged at intervals. The gate oxide layer 2 is arranged on the substrate 1, and the split gate component 3 is arranged on the gate oxide layer 2. The split gate component 3 includes a strip-shaped channel limiting gate 31, a first gate unit 32, and a second gate unit 33. The channel limiting gate 31 is arranged in a lateral direction ( Figures 1 to 6 The channel limiting gate 31 is arranged on the gate oxide layer 2, and the channel limiting gate 31 is used to form a depletion region at the interface between the gate oxide layer 2 and the substrate 1 to prevent electrons from tunneling from one side of the depletion region to the other side. The first gate unit 32 is arranged on the first side of the channel limiting gate 31, and is used to form a first quantum dot (located on the interface and on one side of the depletion region) Figure 3 The second gate unit 33 is disposed on a second side of the channel limiting gate 31 opposite to the first side, and is adapted to form a second quantum dot (located on the other side of the depletion region) on the interface. Figure 3 The source electrode 4 and the drain electrode are both on the first side and extend from the top of the gate oxide layer 2 to the interface, and the source electrode 4 and the drain electrode form a single electron transistor with the first quantum dot and the first gate unit 32. The first gate unit 32 includes a first accumulation gate 322, which is disposed adjacent to the first quantum dot. The first accumulation gate 322 is suitable for transmitting an external radio frequency signal, so as to utilize the radio frequency signal and the capacitive coupling between the single electron transistor and the second quantum dot to achieve the measurement of the second electronic state in the second quantum dot.

[0075] According to the single electron transistor radio frequency reflection measurement structure of the embodiment of the present invention, by setting the first accumulation gate close to the first quantum dot, the radio frequency signal can be transmitted to the vicinity of the first quantum dot through the first accumulation gate, thereby reducing the leakage of the radio frequency signal. The state of the first electron in the first quantum dot is affected by the radio frequency signal, and the electric field generated by the radio frequency signal affects the state of the second electron in the second quantum dot through the capacitive coupling between the single electron transistor and the first quantum dot. The change in the state of the second electron further affects the state of the first electron through the capacitive coupling, thereby changing the impedance of the single electron transistor, and changing the amplitude, phase, frequency and other parameters of the radio frequency signal, so that the number and position of the first electron in the first quantum dot can be determined according to the parameters such as the amplitude, phase and frequency.

[0076] According to an embodiment of the present invention, a negative voltage may be applied to the channel limiting gate 31 to form a depletion region in the interface facing the channel limiting gate 31 , thereby preventing electrons on both sides of the depletion region from tunneling from one side of the depletion region to the other side.

[0077] According to an embodiment of the present invention, the depletion region is located directly below the channel limiting gate 31 in the Y direction.

[0078] In an exemplary embodiment, the gate oxide layer 2 may be made of silicon oxide, and the gate oxide layer 2 and the purified silicon layer form a Si-MOS structure. The thickness of the gate oxide layer 2 may be 10 nm.

[0079] According to an embodiment of the present invention, Figure 1 As shown, the first gate unit 32 further includes two lead gates 321, one lead gate 321 is electrically connected to the source 4, and the other lead gate 321 is electrically connected to the drain, and each lead gate 321 is suitable for forming a coupling capacitor with a two-dimensional electron gas located below the lead gate 321, wherein the two-dimensional electron gas is formed by electrons flowing from the source 4 and the drain and converging on the interface under the voltage applied by the lead gate 321. The radio frequency signal is configured to be applied to the first quantum dot through the coupling capacitor.

[0080] According to an embodiment of the present invention, the two lead gates 321 are respectively a first lead gate 321 and a second lead gate 321. The first lead gate 321 and the two-dimensional electron gas located below the first lead gate 321 form a first coupling capacitor, and the second lead gate 321 and the two-dimensional electron gas located below the second lead gate 321 form a second coupling capacitor.

[0081] According to the embodiment of the present invention, the lead gate 321 is partially located outside the etched region 10 , and a 50 nm field oxide layer under the lead gate 321 prevents the lead gate 321 from leaking electricity.

[0082] According to an embodiment of the present invention, the lead gate 321 and the first accumulation gate 322 not only serve to provide a first electron reservoir for the single-electron transistor, but also need to ensure that the single-electron transistor has sufficient reflection signals when the radio frequency circuit is transmitted to the vicinity of the first quantum dot.

[0083] The single-electron transistor RF reflection measurement structure provided in an embodiment of the present invention moves the RF circuit from the ohmic contact to the first accumulation gate 322, so that the capacitor formed by the lead gate 321 and the two-dimensional electron gas located below the lead gate 321 becomes a coupling capacitor, which can effectively transmit the RF signal to the single-electron transistor through the coupling capacitor, and then the single-electron transistor generates different impedances according to the electronic state in the quantum dot to reflect the RF signal.

[0084] According to an embodiment of the present invention, Figure 1 and Figure 6 As shown, each of the source 4 and the drain includes an ion implantation region 41 and an ohmic electrode 42. The ion implantation region 41 is formed inside the substrate 1, and the ohmic electrode 42 is electrically connected to the ion implantation region 41. Among them, the two lead gates 321 are electrically connected to the two ion implantation regions 41 in a one-to-one correspondence, and at least one lead gate 321 is electrically contacted with the first accumulation gate to form a first electron reservoir, which provides conditions for the loading of the first electron in the first quantum dot and the exchange of the first electron with the first electron reservoir, and is compatible with transport detection and radio frequency detection.

[0085] In an illustrative embodiment, the lead gate 321 penetrates into a position at a first distance (e.g., 8um or 10um) from the center of the quantum dot by overlapping with the ion implantation region 41, so that the single electron transistor can inject the first electron, providing conditions for transport detection.

[0086] In an illustrative embodiment, in the first gate unit 32, the region defining the first quantum dot is formed in the etched region 10 on the substrate 1, and the ion implantation region 41 is isolated from the etched region 10. In the second gate unit 33, the region defining the second quantum dot is formed in the etched region 10. The size of the etched region 10 may be 10um*10um, and it is understood that the size of the etched region 10 may be designed according to actual needs.

[0087] According to an embodiment of the present invention, Figure 6 As shown, the single electron transistor radio frequency reflection measurement structure also includes a field oxide layer 6, which is arranged between the first gate unit 32, the second gate unit 33 and the gate oxide layer 2 at the periphery of the first quantum dot and the second quantum dot (specifically, at the periphery of the etched area 10), and is suitable for electrically isolating the first gate unit 32, the second gate unit 33, the source 4 and the drain.

[0088] According to an embodiment of the present invention, the field oxide layer 6 may be made of aluminum oxide to prevent the first gate unit 32 and the second gate unit 33 from contacting the gate oxide layer 2 and prevent electron accumulation at the interface of the field oxide layer 6 .

[0089] According to an embodiment of the present invention, by forming an etched region 10, noise during quantum chip testing is reduced, and the field oxide layer 6 outside the etched region 10 isolates the contact between the split gate assembly 3 and the gate oxide layer 2, effectively playing a role of electrical insulation.

[0090] It is found in the process of implementing the present invention that if the first accumulation gate 322 is in electrical contact with the ion implantation region 41 , the radio frequency signal will be leaked from the low impedance line in the source 4 and the drain.

[0091] According to an embodiment of the present invention, Figure 2 and Figure 3 As shown, the first accumulation gate 322 extends outward from a position close to the first quantum dot in a direction away from the channel limiting gate 31, and the longitudinal direction ( Figure 2 and Figure 3 The length of the first accumulation gate 322 increases as the distance from the first quantum dot to the lateral direction ( Figure 2 and Figure 3 The first accumulation gate 322 is increased with the increase of the length (in the X direction) so that the first accumulation gate 322 has a larger coupling capacitance, so that the radio frequency signal can enter the first accumulation gate 322 and the two-dimensional electron gas located below the first accumulation gate 322 with a smaller impedance. A sufficiently wide first accumulation gate 322 reduces the resistance of the first accumulation gate 322, thereby reducing the dissipation of the radio frequency signal when entering the single electron transistor.

[0092] According to an embodiment of the present invention, the first accumulation gate 322 avoids overlapping with the ion implantation region 41 to reduce leakage of radio frequency signals.

[0093] According to the embodiment of the present invention, the first accumulation gate 322 has a feature that its width is greater than its length in the etched region 10, which ensures that the radio frequency signal has sufficiently small dissipation when it is transmitted to the first quantum dot. The width of the first accumulation gate 322 refers to the distance in the X direction, and the length refers to the distance in the Y direction.

[0094] According to the embodiment of the present invention, the cooperation between the first accumulation gate 322 and the lead gate 321 optimizes the influence of the leakage capacitance brought by the traditional single lead gate 321 on the radio frequency signal, and converts the capacitance between the lead gate 321 and the two-dimensional electron gas from leakage to coupling.

[0095] According to an embodiment of the present invention, the lead gate 321 crosses the ion implantation region 41 and is electrically connected to the first accumulation gate to ensure that the single electron transistor RF reflection measurement structure can perform current measurement of DC or AC transmission and electron injection processes.

[0096] According to an embodiment of the present invention, the contact area between the lead gate 321 and the first accumulation gate 322 on a plane parallel to the substrate is 1um×1um, so as to avoid leakage of RF signals from the lead gate 321 due to a large contact area. The contact surface between the lead gate 321 and the first accumulation gate 322 is located outside the etching area.

[0097] According to the embodiment of the present invention, the substrate 1 and the first gate unit 32 can form a plurality of single electron transistors, and the substrate 1 and the second gate unit 33 can form a plurality of second quantum dots.

[0098] In an illustrative embodiment, Figure 2 and Figure 3 As shown, the substrate 1 and the first gate unit 32 are on one side of the channel limiting gate 31 ( Figure 2 and Figure 3 The perspective shown is the upper side of the channel limiting gate 31) to form two single electron transistors, the first single electron transistor and the second single electron transistor, which can be symmetrical about the first accumulation gate 322 located between the first single electron transistor and the second single electron transistor to form a structure with low radio frequency impedance to ground. The substrate 1 and the second gate unit 33 are on the other side of the channel limiting gate 31 ( Figure 2 and Figure 3 The perspective shown is the lower side of the channel limiting gate 31) to form four second quantum dots. It can be understood that the number of single electron transistors and the number of second quantum dots can be designed according to actual needs.

[0099] In such an embodiment, the longitudinal lengths of the two first accumulation gates 322 located outside the two single electron transistors increase as the lateral length of the first accumulation gates 322 from the first quantum dot increases, so as to ensure the minimum leakage and dissipation of the radio frequency signal. The first accumulation gate 322 located between the two single electron transistors only needs to have a low impedance value to the ground and does not need to be made very wide.

[0100] The two first accumulation gates 322 located outside the two single electron transistors are electrically connected to the two lead gates in a one-to-one correspondence to provide conditions for the loading of the first electrons in the first quantum dots and the exchange of the first electrons with the first electron reservoir.

[0101] In such an embodiment, the four first barrier gates are respectively used to adjust the coupling between the electrons in each single electron transistor and the electron reservoir. Among the five second barrier gates, the three second barrier gates arranged between the second plunger electrodes are used to adjust the strength of the tunneling and coupling inside the quantum dot group, and the two outer second barrier gates are used to adjust the tunneling rate between the electrons in the quantum dot and the electron reservoir.

[0102] In an exemplary embodiment, the first accumulation gate 322 extends rapidly from the channel limiting gate 31 to a longitudinal length of 5 μm in a direction away from the channel limiting gate 31, forming a multi-trapezoidal structure that gradually expands rapidly. The first accumulation gate 322 overlaps with the lead gate 321 outside the etched area 10, and the overlapping area between the first accumulation gate 322 and the lead gate 321 is 1 μm. 2 The width of the first accumulation gate 322 between the two single electron transistors is kept at 80 um until the bonding pad.

[0103] In an exemplary embodiment, when one single electron transistor is formed, the number of first accumulation gates 322 is two. When three single electron transistors are formed, the number of first accumulation gates 322 is four.

[0104] According to an embodiment of the present invention, Figures 1 to 4 as well as Figure 6 As shown, the first gate unit 32 further includes a first plug gate 323, two first barrier gates 324 and a first limiting gate 325. The first plug gate 323 is electrically isolated from the channel limiting gate 31, and the first plug gate 323 extends from the channel limiting gate 31 in a direction away from the channel limiting gate 31, and is suitable for Figures 1 to 3 The width of the first quantum dot is defined by the X direction in ... Figures 1 to 3 The length of the first quantum dot is defined as the Y direction in the graph.

[0105] According to an embodiment of the present invention, the first plug gate 323 located in the etching area 10 defines the width of the first quantum dot in the lateral direction, and the first plug gate 323, the first limiting gate 325 and the channel limiting gate 31 are electrically isolated from each other. The first plug gate 323 is arranged above the first limiting gate 325. Since there is a spacing space between the first limiting gate 325 and the channel limiting gate 31, the area below the first plug gate 323 located in the spacing space and located on the interface can form a zero-dimensional structure (that is, the first quantum dot), and the first electron will be bound in the potential well formed by applying a voltage to the first plug electrode.

[0106] According to an embodiment of the present invention, Figure 4 As shown, the two first barrier gates 324 are located on both sides of the first plug gate 323, which play a role in rate regulation for the tunneling of the first electron in the first quantum dot and the tunneling between the first quantum dot and the first electron reservoir.

[0107] In an exemplary embodiment, the lateral width of the first plug gate 323 at one end close to the channel limiting gate 31 may be 45 nm, and the longitudinal length of the channel limiting gate 31 may be 40 nm. The distance between the lead gate 321 and the first quantum dot may be 10 um.

[0108] According to an embodiment of the present invention, the turning lines of the first accumulation gate 322, the lead gate 321, the first plug gate 323, the first barrier gate 324 and the first limiting gate 325 extending away from the channel limiting gate 31 have an angle of 45 degrees or 135 degrees with the lateral direction, which can reduce the ringing phenomenon during the transmission of electrical signals.

[0109] According to an embodiment of the present invention, Figures 1 to 3 and Figure 5 As shown, the second gate unit 33 includes a second plunger gate 331, two second barrier gates 332 and a second limiting gate 333. The second plunger gate 331 is electrically isolated from the channel limiting gate 31, extending from the channel limiting gate 31 in a direction away from the channel limiting gate 31, and is suitable for defining the width of the second quantum dot in the lateral direction. The two second barrier gates 332 are electrically isolated from the second plunger gate 331 and the channel limiting gate 31, extending from the channel limiting gate 31 in a direction away from the channel limiting gate 31 and arranged on both sides of the second plunger gate 331, and are suitable for regulating the tunneling rate of the second electrons in the second quantum dot. The second limiting gate 333 is spaced from the channel limiting gate 31, extending in a direction away from the channel limiting gate 31, and is electrically isolated from the second plunger gate 331 and the two second barrier gates 332, and is arranged below the second plunger gate 331 and the two second barrier gates 332, and is suitable for defining the length of the second quantum dot in the longitudinal direction.

[0110] According to an embodiment of the present invention, the second gate unit 33 further includes two second accumulation gates 334. The two second accumulation gates 334 are disposed on two sides away from each other of the two second barrier gates 332 to control the second electrons to enter and exit the second quantum dot.

[0111] According to an embodiment of the present invention, two second barrier gates 332 are located on both sides of the second plug gate 331, which play a role in rate regulation for the tunneling of the second electrons in the second quantum dot and the tunneling between the second quantum dot and the second electron reservoir.

[0112] In an exemplary embodiment, the lateral width of the end of the first barrier gate 324 close to the channel limiting gate 31 may be 45 nm, and the distance between two adjacent first barrier gates 324 may be 35 nm.

[0113] In an exemplary embodiment, the lateral width of the second barrier gate 332 at one end close to the channel limiting gate 31 can be 35 nm, and the distance between two adjacent second barrier gates 332 can be 25 nm. The lateral width of the second barrier gate 332 at one end close to the channel limiting gate 31 can be 35 nm to ensure that the gap between the plug gates is filled. When a voltage is applied to the second plug gate 331 during testing, it is ensured that the electrons under the second plug gate 331 are a zero-dimensional structure confined by a potential well.

[0114] The lateral width of the first barrier gate 324 at one end close to the channel limiting gate 31 may be 45 nm.

[0115] According to an embodiment of the present invention, the substrate 1 includes a silicon substrate and a purified silicon layer (not shown in the figure), the purified silicon layer is arranged between the silicon substrate and the gate oxide layer 2, and the interface is located between the purified silicon layer and the gate oxide layer 2.

[0116] Figure 7 A top view of a micromagnet according to an embodiment of the present invention is shown.

[0117] According to an embodiment of the present invention, Figure 7 As shown, the single electron transistor radio frequency reflection measurement structure also includes a magnetic layer 5, which is arranged on the split gate assembly 3. The magnetic layer 5 is arranged around the second quantum dot with an interval between the magnetic layer 5 and the second quantum dot. The magnetic layer 5 is suitable for providing a transverse gradient magnetic field to the second quantum dot to compensate for the very weak spin-orbit coupling of the second electron in the purified silicon within the second quantum dot, thereby generating a driven rotation of the quantum bit.

[0118] In an illustrative embodiment, the magnetic layer 5 may be a bridge-shaped structure. The material of the magnetic layer 5 may be a non-permanent magnet, such as cobalt, and the thickness of the magnetic layer 5 may be in the range of 200-300 nm, such as 250 nm.

[0119] In an illustrative embodiment, Figure 7 As shown, the bridge-type magnetic layer 5 includes two main body parts arranged opposite to each other in the Y direction and a connecting part connected between the two main body parts. The dimensions of the two main body parts in the X direction are both 1.2um, the dimensions in the Y direction are both 2um, and the spacing between the two main body parts is 0.4um; the dimensions of the connecting part in the X direction are 0.4um, and the dimensions in the Y direction are 0.8um. ​​The second area 35 is located between the two main body parts and the connecting part.

[0120] In an illustrative embodiment, the material of the silicon substrate may be natural silicon.

[0121] In an exemplary embodiment, the material of the purified silicon layer can be isotopically purified. 28 Si is used to minimize decoherence caused by hyperfine interactions in quantum chips.

[0122] According to an embodiment of the present invention, during the measurement process, firstly, a positive voltage is applied to both the lead gate 321 and the first accumulation gate 322 to generate an electron injection process through the source 4 and the drain.

[0123] When measuring the transport current, a positive voltage is applied to the lead gate 321 and the first accumulation gate 322, and the current test is performed by adjusting the voltage of the first plug gate 323 and the first barrier gate 324, so that the Coulomb peak can be measured.

[0124] When measuring radio frequency reflection, the positive voltage of the lead grid 321 is removed, and the first accumulation grid 322 continues to apply a positive voltage, thereby cutting off the leakage channel of the radio frequency signal, so that the radio frequency signal has sufficient reflection sensitivity at the single electron transistor.

[0125] By adjusting the voltage of the second plunger gate 331 and the second barrier gate 332, the second electron trapped inside the second quantum dot is in a different state, which is coupled to the single electron transistor through capacitance. The single electron transistor produces a corresponding impedance change, which is reflected in the RF reflection signal.

[0126] In an illustrative embodiment, the second quantum dot is adjusted to the middle of the two second electron number regions, and the two second electrons can generate a random telegraph signal (RTS), and the frequency of the RTS can be adjusted by the second barrier gate 332 and the second plunger gate 331. Through capacitive coupling, the single electron transistor will detect this random telegraph signal. The DC detection can only detect a frequency bandwidth of hundreds of kilohertz (KHz), while the improved RF detection can detect hundreds of megahertz (MHz), which increases its detection frequency by three orders of magnitude, effectively ensuring the readout speed, reducing the detection time and the frequency of quantum calculation. According to an embodiment of the present invention, an external RF reflection circuit can be bonded to the first accumulation gate 322, and the DC detection and RF detection of the single electron transistor are performed by switching the lead gate 321.

[0127] According to the single electron transistor radio frequency reflection measurement structure of the embodiment of the present invention, the leakage of radio frequency signals can be reduced by setting the first accumulation gate 322 and the lead gate 321, and the requirement for the distance from the ion implantation region 41 to the center of the quantum dot can be relaxed, and a strict small distance is no longer required to weaken the coupling capacitance, and the radio frequency reflection measurement can be read out in a wider range, reducing the processing difficulty. The problem of radio frequency signal leakage through capacitance in the enhancement device is avoided, and the purpose of measuring the quantum bit state by a high-bandwidth single electron transistor is achieved.

[0128] Figure 8 A flow chart of a method for preparing a single electron transistor radio frequency reflection measurement structure according to an embodiment of the present invention is shown.

[0129] As another aspect of the embodiments of the present invention, a method for preparing any of the above-mentioned single electron transistor radio frequency reflection measurement structures is provided, such as Figure 8 As shown, the preparation method includes operations S810 to S870.

[0130] In operation S810, a source electrode and a drain electrode are formed on a substrate having a gate oxide layer formed thereon.

[0131] In operation S820, a channel limiting gate, a first limiting gate, two lead gates, and a second limiting gate are formed on a substrate having a source and a drain, one of the two leads is electrically connected to the source, the other of the two leads is electrically connected to the drain, the first limiting gate is located on a first side of the channel limiting gate, and the second limiting gate is located on a second side of the channel limiting gate.

[0132] In operation S830, a first oxide layer is formed on surfaces of the channel limiting gate, the first limiting gate, the two lead gates, and the second limiting gate to obtain a first substrate.

[0133] In operation S840, a first plug gate, two first accumulation gates, a second plug gate, and two second accumulation gates are formed on the first substrate, so that the first plug gate and the two first accumulation gates extend outward from the channel limiting gate in a direction away from the second side and are located on the first limiting gate, and the second plug gate and the two second accumulation gates extend outward from the channel limiting gate in a direction away from the first side and are located on the second limiting gate.

[0134] In operation S850, a second oxide layer is formed on surfaces of the first plug gate, the two first accumulation gates, the second plug gate, and the two second accumulation gates to obtain a second base.

[0135] In operation S860, two first barrier gates and two second barrier gates are formed on the second substrate, so that the two first barrier gates are respectively located on both sides of the first plug gate and between the two first limiting gates, and the two second barrier gates are respectively located on both sides of the second plug gate and between the two second limiting gates.

[0136] In operation S870 , a third oxide layer is formed on surfaces of the two first barrier gates and the two second barrier gates to obtain a single electron transistor radio frequency reflection measurement structure.

[0137] According to the preparation method of the single electron transistor radio frequency reflection measurement structure provided by the embodiment of the present invention, the split gate component 3 is divided into three layers, and the three layers of electrodes are prepared one by one by overlaying. After each layer is prepared, it is oxidized and covered with a dense oxide layer, which can effectively isolate the interconnection and leakage between the electrodes. The preparation method matches the existing semiconductor industry, does not generate additional layers in semiconductor processing, and the process is relatively simple, and the single electron transistor radio frequency reflection measurement structure can be efficiently prepared in batches.

[0138] Fig. 9 shows a top view of an ion implantation region according to an embodiment of the present invention, Fig.10 A top view of an ohmic electrode according to an embodiment of the present invention is shown.

[0139] According to an embodiment of the present invention, forming a source electrode 4 and a drain electrode on a substrate 1 having a gate oxide layer 2 includes:

[0140] Ion implantation is performed on the Fig. 9 As shown, two ion implantation regions 41 are formed at intervals;

[0141] Depositing a field oxide layer 6 on the substrate 1 where the ion implantation region 41 is formed;

[0142] Etch away the etched area 10 (such as Fig.10 The field oxide layer 6 in the etching area 10 is exposed to the gate oxide layer 2;

[0143] De-patterning and etching the field oxide layer 6 and the gate oxide layer 2 on the two ion implantation regions 41;

[0144] Metal deposition is performed separately to form Fig.10 The ohmic electrode 42 is provided as shown, and the ohmic electrode 42 is in ohmic contact with the ion implantation region 41 to form a source 4 and a drain.

[0145] In an illustrative embodiment, a layer of aluminum oxide with a thickness of 50 nm is grown on the gate oxide layer 2 by physical vapor deposition. A square area with a side length of 10 um in the center of the substrate 1 formed with aluminum oxide is used as an etching area 10, and the aluminum oxide layer in the etching area 10 is etched away by wet etching (for example, by a phosphoric acid oil bath), and the aluminum oxide layer with a thickness of 50 nm on the periphery is retained as a field oxide layer 6.

[0146] In such an embodiment, the etched area 10 is wet-etched by means of a phosphoric acid oil bath, and the slope from the etched area 10 to the non-etched area 10 is very gentle, enough to prevent the first layer from breaking when the thickness is 35 nm.

[0147] In an illustrative embodiment, a layer of aluminum oxide with a thickness of 50 nm is grown on the gate oxide layer 2 by physical vapor deposition, including:

[0148] Trimethylaluminum is reacted with water by atomic layer growth to generate aluminum oxide and methane in an inert gas (e.g., nitrogen) environment, so that the aluminum oxide covers the gate oxide layer 2. In an illustrative embodiment, phosphorus atoms are implanted by high-speed bombardment to form an N-type semiconductor in the ion implantation region 41.

[0149] In an illustrative embodiment, the ohmic electrode 42 is infiltrated into the ion implantation region 41 by thermal annealing to form a source electrode 4 and a drain electrode, respectively, so as to perform electron interaction and electron injection with the outside world through the source electrode 4 and the drain electrode.

[0150] According to an embodiment of the present invention, the split gate assembly 3 is divided into three layers, and the thickness of the gate of each layer can be different. They are sequentially formed on the substrate 1 formed with the source electrode 4 and the drain electrode. The electron beam exposure method with a writing field of 100um is adopted in the etching area 10, and the area outside the etching area 10 is exposed by an electron beam with a writing field of 2000um.

[0151] Fig.11 shows a top view of a first layer electrode according to an embodiment of the present invention, Fig.12 4 shows a top view of the second layer electrode according to an embodiment of the present invention, Fig.13 A top view of a third layer electrode according to an embodiment of the present invention is shown.

[0152] Fig.11 The shape of the first layer of electrodes under the writing field from 100um to 2000um is shown. The outermost bonding pad is 150um×120um. The thickness of the aluminum electrode plated by electron beam evaporation is 35nm.

[0153] Fig.12 The shape of the second layer electrode under the writing field from 100um to 2000um is shown. The outermost bonding pad is 150um×120um. The thickness of the aluminum electrode plated by electron beam evaporation is 55nm.

[0154] Fig.13 The shape design of the third layer electrode under the writing field from 100um to 2000um is shown. The outermost bonding pad is 150um×120um. The thickness of the aluminum electrode plated by electron beam evaporation is 75nm.

[0155] like Fig.11 As shown, the first layer of electrodes (the electrodes formed in operation S820) includes a channel limiting gate 31, a first limiting gate 325, two lead gates 321, and a second limiting gate 333. Fig.12 As shown, the second layer electrode (the electrode formed in operation S840) includes a first plug gate 323, two first accumulation gates 322, a second plug gate 331 and two second accumulation gates 334. Fig.13 As shown, the third electrode (the electrode formed in operation S860) includes two first barrier gates 324 and two second barrier gates 332. The first electrode is electrically isolated from the second electrode and the outside through the first oxide layer 7, the second electrode is electrically isolated from the third electrode and the outside through the second oxide layer 8, and the surface of the third electrode is covered with the third oxide layer and is electrically isolated from the outside.

[0156] The oxide layer of the split gate assembly 3 located at the periphery of the etching area 10 and the oxide layer of the fine electrode located inside the etching area 10 act as an insulating layer. The width of the first accumulation gate 322 of the first quantum dot can be consistent with the lead gate 321, because the first electron reservoir of the first quantum dot needs to be introduced from the ohmic electrode 42 and the ion implantation area 41, and the shape of the first accumulation gate does not need to be copied to the quantum dot, which can reduce the exposure time.

[0157] According to an embodiment of the present invention, the area of ​​the first accumulation gate 322 in the second layer is enlarged, and it penetrates into the first limiting gate 325 near the position of the single-electron transistor, and rapidly expands in the direction away from the channel limiting gate 31. During electron beam exposure, the layout shape of the first accumulation gate 322 can be designed as a trapezoid, so that the first accumulation gate 322 can be rapidly widened to 30um, and then gradually expanded to the same width as the bonding pad (150um) through a rectangular shape. The rapidly widened pattern can generate a sufficiently strong coupling capacitance.

[0158] In an illustrative embodiment, the first electrode layer is developed and fixed after electron beam exposure, and the electron beam evaporation coating machine coats 35nm thick aluminum at a rate of 0.4nm / s, and uses atomic layer deposition (ALD) technology to oxidize, and a dense first oxide layer is produced on the surface of the aluminum electrode. The second electrode layer is developed and fixed after electron beam exposure, and the electron beam evaporation coating machine coats 55nm thick aluminum at a rate of 0.4nm / s, and uses atomic layer deposition (ALD) technology to oxidize, and a dense second oxide layer is produced on the surface of the aluminum electrode. The third electrode layer is developed and fixed after electron beam exposure, and the electron beam evaporation coating machine coats 75nm thick aluminum at a rate of 0.4nm / s, and uses atomic layer deposition (ALD) technology to oxidize, and a dense third oxide layer is produced on the surface of the aluminum electrode.

[0159] According to an embodiment of the present invention, after operation S870, the following may be further included:

[0160] A 10nm layer of titanium is plated in the area around the second quantum dot. The titanium layer is used to ensure the adhesion of the cobalt magnet and prevent it from falling off during the process of peeling the cobalt magnet in the target area. The cobalt magnet located around the second quantum dot is used as the magnetic layer 5, which can provide the optimal transverse magnetic field gradient and the maximum longitudinal magnetic field gradient, thereby ensuring the drivability and addressability of the quantum bit.

[0161] The embodiments of the present invention are described above. However, these embodiments are only for the purpose of illustration, and are not intended to limit the scope of the present invention. Although each embodiment is described above, it does not mean that the measures in each embodiment cannot be used in combination. The scope of the present invention is defined by the attached claims and their equivalents. Without departing from the scope of the present invention, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present invention.

Claims

1. A single electron transistor radio frequency reflection measurement structure, characterized in that: For silicon-based semiconductor quantum chips, the single electron transistor radio frequency reflection measurement structure comprises: substrate; A gate oxide layer is disposed on the substrate, A split gate component is disposed on the gate oxide layer, and the split gate component comprises: A strip-shaped channel limiting gate is arranged on the gate oxide layer in a lateral direction and is suitable for forming a depletion region at the interface between the gate oxide layer and the substrate to prevent electrons from tunneling from one side of the depletion region to the other side; A first gate unit, disposed on a first side of the channel limiting gate, adapted to form a first quantum dot on the interface and on one side of the depletion region; A second gate unit, disposed on a second side of the channel limiting gate opposite to the first side, adapted to form a second quantum dot on the interface and on the other side of the depletion region; A source electrode and a drain electrode are arranged at intervals, both are on the first side, and both extend from above the gate oxide layer to the interface, and the source electrode and the drain electrode form a single electron transistor with the first quantum dot and the first gate unit; Wherein, the first gate unit comprises: The first accumulation gate is arranged adjacent to the first quantum dot and is suitable for transmitting a radio frequency signal from the outside to utilize the radio frequency signal and the capacitive coupling effect between the single electron transistor and the second quantum dot to measure the second electronic state in the second quantum dot.

2. The single electron transistor radio frequency reflection measurement structure according to claim 1, characterized in that: The first gate unit further includes: two lead gates, one lead gate is electrically connected to the source electrode, and the other lead gate is electrically connected to the drain electrode, each of the lead gates is adapted to form a coupling capacitor with a two-dimensional electron gas located below the lead gate, wherein the two-dimensional electron gas is formed by electrons flowing in from the source electrode and the drain electrode and converging on the interface under the voltage applied by the lead gates; Wherein, the radio frequency signal is configured to be applied to the first quantum dot through the coupling capacitor.

3. The single electron transistor radio frequency reflection measurement structure according to claim 2, characterized in that: The first gate unit further includes: A first plug gate is electrically isolated from the channel limiting gate, extends from the channel limiting gate in a direction away from the channel limiting gate, and is suitable for defining a width of the first quantum dot in a lateral direction; Two first barrier gates, which are electrically isolated from the first plug gate and the channel limiting gate, are extended from the channel limiting gate to the direction away from the channel limiting gate and are arranged on both sides of the first plug gate, and are suitable for regulating the tunneling rate of the first electron in the first quantum dot; A first limiting gate is spaced apart from the channel limiting gate, extends in a direction away from the channel limiting gate, and is electrically isolated from the first plug gate and the two first barrier gates. The first limiting gate is arranged below the first plug gate and the two first barrier gates, and is suitable for defining the length of the first quantum dot in the longitudinal direction.

4. The single electron transistor radio frequency reflection measurement structure according to claim 3, characterized in that: The included angle between the turning lines of the first accumulation gate, the lead gate, the first plug gate, the first barrier gate and the first limiting gate extending away from the channel limiting gate and the lateral direction is 45 degrees or 135 degrees.

5. The single electron transistor radio frequency reflection measurement structure according to any one of claims 1 to 4, characterized in that: The first accumulation gate extends from a position close to the first quantum dot toward a direction away from the channel limiting gate, and a longitudinal length of the first accumulation gate increases as a lateral length of the first accumulation gate from the first quantum dot increases.

6. The single electron transistor radio frequency reflection measurement structure according to any one of claims 1 to 4, characterized in that: The second gate unit comprises: A second plug gate is electrically isolated from the channel limiting gate, extends from the channel limiting gate in a direction away from the channel limiting gate, and is suitable for defining a width of the second quantum dot in a lateral direction; Two second barrier gates, which are electrically isolated from the second plug gate and the channel limiting gate, are extended from the channel limiting gate to the direction away from the channel limiting gate and are arranged on both sides of the second plug gate, and are suitable for regulating the tunneling rate of the second electrons in the second quantum dot; A second limiting gate is spaced apart from the channel limiting gate, extends in a direction away from the channel limiting gate, is electrically isolated from the second plunger gate and the two second barrier gates, and is disposed below the second plunger gate and the two second barrier gates, and is suitable for defining the length of the second quantum dot in the longitudinal direction; Two second accumulation gates are arranged on two sides away from each other of the two second barrier gates to control the second electrons to enter and exit the second quantum dot.

7. The single electron transistor radio frequency reflection measurement structure according to claim 1, characterized in that: The substrate comprises: Silicon substrate; A purified silicon layer is disposed between the silicon substrate and the gate oxide layer, wherein the interface is located between the purified silicon layer and the gate oxide layer; The single electron transistor radio frequency reflection measurement structure also includes: The magnetic layer is arranged around the second quantum dot with a spacing therebetween, and is suitable for providing a transverse gradient magnetic field to the second quantum dot to compensate for the spin-orbit coupling of the second electron in the purified silicon within the second quantum dot, thereby generating a driven rotation of the quantum bit.

8. The single electron transistor radio frequency reflection measurement structure according to claim 2, characterized in that: The source electrode and the drain electrode both include: An ion implantation region is formed inside the substrate; an ohmic electrode electrically connected to the ion implantation region; The two lead gates are electrically connected to the two ion injection regions one by one, and at least one lead gate is electrically contacted with the first accumulation gate to form a first electron reservoir, providing conditions for loading the first electron in the first quantum dot and exchanging the first electron with the first electron reservoir.

9. The single electron transistor radio frequency reflection measurement structure according to claim 8, characterized in that: The contact area between the lead gate and the first accumulation gate on a plane parallel to the substrate is 1 um×1 um.

10. A method for preparing a single electron transistor radio frequency reflection measurement structure according to any one of claims 1 to 9, characterized in that: include: forming a source electrode and a drain electrode on the substrate having a gate oxide layer formed thereon; On the substrate formed with the source and the drain, a channel limiting gate, a first limiting gate, two lead gates, and a second limiting gate are formed, one of the two lead gates is electrically connected to the source, the other of the two lead gates is electrically connected to the drain, the first limiting gate is located on a first side of the channel limiting gate, and the second limiting gate is located on a second side of the channel limiting gate; Forming a first oxide layer on the surfaces of the channel limiting gate, the first limiting gate, the two lead gates and the second limiting gate to obtain a first substrate; forming a first plug gate, two first accumulation gates, a second plug gate and two second accumulation gates on the first substrate, so that the first plug gate and the two first accumulation gates extend outward from the channel limiting gate in a direction away from the second side and are located on the first limiting gate, and the second plug gate and the two second accumulation gates extend from the channel limiting gate in a direction away from the first side and are located on the second limiting gate; forming a second oxide layer on the surfaces of the first plunger gate, the two first accumulation gates, the second plunger gate and the two second accumulation gates to obtain a second substrate; forming two first barrier gates and two second barrier gates on the second substrate, so that the two first barrier gates are respectively located on both sides of the first plug gate and between the two first limiting gates, and the two second barrier gates are respectively located on both sides of the second plug gate and between the two second limiting gates; A third oxide layer is formed on the surfaces of the two first barrier gates and the two second barrier gates to obtain the single electron transistor radio frequency reflection measurement structure.

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