Automatic test device and automatic test method for voltage detection chip
The automated testing device and method efficiently test large quantities of voltage detection chips by dividing them into groups and using cascade control units, reducing manual intervention and improving production capacity while ensuring high precision and accuracy.
Patent Information
- Application Number
- CN202311114127.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-30
- Publication Date
- 2024-12-17
AI Technical Summary
Current methods for testing voltage detection chips, particularly for lithium iron phosphate batteries, are inefficient for large quantities due to high labor and time costs, limited chip testing per board, cumbersome processes, and challenges in handling massive test data, which hinder production capacity.
An automated testing device and method that divides chips into groups, using a reference voltage source, cascade control units, and interface conversion modules to streamline testing, enabling automated testing of multiple chips with reduced manual intervention and improved scalability.
The solution significantly reduces testing time and labor, enhances production capacity, and ensures high precision and accuracy in voltage sampling by controlling reference voltages and data processing for large-scale chip testing.
Smart Images
Figure CN119147935A_ABST
Abstract
Description
Technical Field
[0001] The present invention mainly relates to the field of testing of electronic components, and in particular to an automatic testing device for a voltage detection chip and a testing method for performing large-scale automatic testing using the automatic testing device. Background Art
[0002] In recent years, with the rapid rise of my country's new energy vehicle industry, the installed capacity of power battery companies has also led the global market. At the same time, new energy vehicles have higher and higher requirements for batteries and battery management system dedicated chips, especially lithium iron phosphate batteries, whose SOC estimation requires very high voltage sampling precision and accuracy. Therefore, a larger number of tests are needed to support the accuracy and stability of chip sampling results.
[0003] Currently, chip manufacturers usually test their voltage sampling chips based on single-board testing. Although a single board includes multiple chips to be tested, the number of chips on a single board is limited, and the time and labor costs of single-board testing are high, which still cannot meet the testing of large quantities of samples. In addition, the traditional sampling test steps are cumbersome, and the data recording and processing methods are diverse. It is difficult to handle the processing of massive test data, which is not conducive to the improvement of production capacity. Summary of the invention
[0004] The technical problem to be solved by the present application is to provide an automated testing device and method suitable for large quantities of voltage detection chips, which can effectively reduce manual intervention and save testing cycles.
[0005] To solve the above technical problems, the present invention provides an automatic testing device for a voltage detection chip, wherein a plurality of the chips are divided into at least one test group, each of the test groups includes a plurality of the chips, and the device is characterized in that it comprises: a reference voltage source, a cascade control unit, a first interface conversion module and a controller, wherein the reference voltage source is used to provide a reference voltage to the chips in each of the test groups; the cascade control unit corresponds to the test groups one by one, the cascade control unit is used to assign numbers to the corresponding test groups, so that the test groups are tested in the order of the numbers, and the target chips in the test groups are selected according to the selection command of the controller, and the target chips are used as the current test objects; the first interface conversion module is connected between the controller and the cascade control unit, the first interface conversion module is used to send the selection command to the cascade control unit, and obtain the voltage sampling value of the target chip, and send the voltage sampling value to the controller; and the controller is configured to: control the reference voltage source to provide a reference voltage to the plurality of chips in the plurality of test groups, and send the selection command to the cascade control unit according to the test mode.
[0006] In one embodiment of the present application, the first interface conversion module is directly connected to one of the cascade control units, and a plurality of the cascade control units are connected in series to form a multi-stage structure. The voltage sampling value of the target chip in each of the test groups is sent to the cascade control unit of the previous stage through the corresponding cascade control unit, and is finally acquired by the first interface conversion module.
[0007] In one embodiment of the present application, in each test group, the sampling end of each chip is connected to the cascade control unit, the sampling end is used to output the voltage sampling value, and the first interface conversion module obtains the voltage sampling value of the chip through the cascade control unit.
[0008] In one embodiment of the present application, a chip power supply unit is further included. Multiple chips in the test group are connected in series, and chips in adjacent test groups are connected in series. The chip power supply unit is used to supply power to each chip in the test group at the same time.
[0009] In one embodiment of the present application, it also includes a switch unit, which corresponds to the test group one by one, each of the switch units includes a switch controller and a plurality of switch devices, a switch device is connected between the reference voltage source and one of the chips, the cascade control unit is connected to the switch controller, and the cascade control unit is also used to control the switch controller according to the selection command, so that the switch controller controls the switch device connected between the target chip and the reference voltage source to be connected, while disconnecting other switch devices.
[0010] In an embodiment of the present application, the switching device includes a relay.
[0011] In one embodiment of the present application, the switch controller includes a second interface conversion module and a latch, the second interface conversion module and the latch are connected in sequence between the cascade control unit and multiple chips, the second interface conversion module is used to convert the serial selection command into a parallel signal, and send the parallel signal to the latch, the number of bits of the parallel signal is equal to the number of chips in the test group, the latch performs an opening and closing action according to the parallel signal, and closes the latch enable switch after the opening and closing action, until the cascade control unit receives a selection command to test the next target chip, and then opens the latch enable switch.
[0012] In one embodiment of the present application, the second interface conversion module includes a serial port to parallel port circuit.
[0013] In an embodiment of the present application, the reference voltage includes a plurality of different reference voltages, and the range of the reference voltage is within the sampling voltage range of the chip.
[0014] In one embodiment of the present application, a third interface conversion module is further included. The third interface conversion module is arranged between the controller and the reference voltage source, and the third interface conversion module is used for communication protocol conversion between the controller and the reference voltage source.
[0015] In an embodiment of the present application, the controller is further used to evaluate the accuracy of voltage sampling of a single chip and the stability of voltage sampling of multiple chips according to the voltage sampling values.
[0016] In one embodiment of the present application, the voltage detection chip is used to detect the battery voltage.
[0017] In order to solve the above-mentioned technical problems, the present application also proposes an automated testing method for a voltage detection chip, which is characterized in that the automated testing device as described above is used to perform the following steps: initialization, each of the cascade control units assigns a number to each of the test groups, the chip power supply unit supplies power to each chip in the test group, the controller obtains the communication status of each of the chips, and takes the chip with normal communication status as the object to be tested; the controller sets the reference voltage value to be tested, and sends the reference voltage value to the reference voltage source, and the reference voltage source outputs the reference voltage value; the controller sends the enable command to the cascade control units in sequence according to the number, and the cascade control unit enables the target chip in the corresponding test group according to the enable command; and the first interface conversion module obtains the voltage sampling value of the enabled target chip, and sends the voltage sampling value to the controller.
[0018] In an embodiment of the present application, it further includes: recording multiple voltage sampling values of a single chip under the same reference voltage value, so as to evaluate the accuracy of the voltage sampling of the single chip.
[0019] In one embodiment of the present application, it also includes: recording multiple voltage sampling values of multiple chips under the same reference voltage to evaluate the stability of voltage sampling of multiple chips.
[0020] In one embodiment of the present application, the controller further includes: recording a single data as M in a three-dimensional data recording manner. xyz , wherein x represents the sampling times of a single chip at a reference voltage, y represents the number of the single chip, and z represents the number of the reference voltage value provided to the single chip.
[0021] The automated testing method according to claim 16, characterized in that the following formula is used to calculate the first mean and the first variance of multiple voltage sampling values of a single chip at the same reference voltage value:
[0022]
[0023] Wherein, Mx represents the xth voltage sampling value of a single chip under a reference voltage value, and n represents the total number of sampling times. represents the first mean, S1 2 represents the first variance; the method further comprises: using the first mean value and the first variance to evaluate the accuracy of the voltage sampling of the single chip.
[0024] In one embodiment of the present application, the following formula is used to calculate the second mean and the second variance of multiple voltage sampling values of multiple chips at the same reference voltage:
[0025]
[0026] Wherein, My represents the voltage sampling value of the chip numbered y at a reference voltage value, m represents the number of the plurality of chips, represents the second mean, S2 2 represents the second variance; the method further comprises: using the second mean value and the second variance to evaluate the stability of voltage sampling of multiple chips.
[0027] The automated test device and automated test method of the present application control the reference voltage to be provided by the reference voltage source through a controller, cascade multiple test groups by using a cascade control unit, and enable the target chip in the test group to be tested according to the gating command of the controller, thereby realizing automated testing of multiple chips in multiple test groups, greatly reducing manual intervention in testing, saving manpower, and reducing the time required for testing. The use of a cascade control unit makes the automated test device have excellent scalability, which is conducive to further improving chip production capacity. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] The accompanying drawings are included to provide a further understanding of the present application. They are included and constitute a part of the present application. The accompanying drawings illustrate embodiments of the present application and together with the present specification serve to explain the principles of the present invention. In the accompanying drawings:
[0029] Figure 1 is a schematic diagram of an automated testing device according to an embodiment of the present application;
[0030] Figure 2 is a schematic diagram of an automated testing device according to another embodiment of the present application;
[0031] Figure 3 is a schematic diagram of an automated testing device according to another embodiment of the present application;
[0032] Figure 4is a structural schematic diagram of a switch controller in an automated testing device according to an embodiment of the present application;
[0033] Figure 5 is a schematic diagram of an automated testing device according to another embodiment of the present application;
[0034] Figure 6 It is an exemplary flow chart of an automated testing method according to an embodiment of the present application. DETAILED DESCRIPTION
[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for the description of the embodiments. Obviously, the drawings described below are only some examples or embodiments of the present application. For ordinary technicians in this field, the present application can also be applied to other similar scenarios based on these drawings without creative work. Unless it is obvious from the language environment or otherwise explained, the same reference numerals in the figures represent the same structure or operation.
[0036] As shown in this application and claims, unless the context clearly indicates an exception, the words "a", "an", "an" and / or "the" do not refer to the singular and may also include the plural. Generally speaking, the terms "include" and "comprise" only indicate the inclusion of the steps and elements that have been clearly identified, and these steps and elements do not constitute an exclusive list. The method or device may also include other steps or elements.
[0037] Unless otherwise specifically stated, the relative arrangement, numerical expressions and numerical values of the parts and steps set forth in these embodiments do not limit the scope of the present application. At the same time, it should be understood that, for ease of description, the sizes of the various parts shown in the accompanying drawings are not drawn according to the actual proportional relationship. The technology, method and equipment known to those of ordinary skill in the relevant field may not be discussed in detail, but in appropriate cases, the technology, method and equipment should be considered as a part of the authorization specification. In all examples shown and discussed here, any specific value should be interpreted as being merely exemplary, rather than as a limitation. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters represent similar items in the following drawings, so that once a certain item is defined in an accompanying drawing, it does not need to be further discussed in subsequent drawings.
[0038] In addition, it should be noted that the use of words such as "first" and "second" to define components is only for the convenience of distinguishing the corresponding components. If not otherwise stated, the above words have no special meaning and cannot be understood as limiting the scope of protection of this application. In addition, although the terms used in this application are selected from well-known and commonly used terms, some terms mentioned in the specification of this application may be selected by the applicant at his or her discretion, and their detailed meanings are explained in the relevant parts of the description of this article. In addition, it is required to understand this application not only by the actual terms used, but also by the meaning implied by each term.
[0039] Flowcharts are used in the present application to illustrate the operations performed by the system according to the embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed accurately in order. On the contrary, various steps may be processed in reverse order or simultaneously. At the same time, other operations may be added to these processes, or one or more operations may be removed from these processes.
[0040] The automated testing device for the voltage detection chip of the present application can be used to test a large number of voltage detection chips. The voltage detection chip refers to a chip with a voltage detection function. The present application does not limit the specific manufacturer or model of the voltage detection chip. In order to conduct batch testing, the present application divides the multiple chips (the abbreviation for the voltage detection chip) as the test object into at least one test group, and each test group includes multiple chips. The present application does not limit whether the number of chips in each test group is equal, and they can be equal or unequal.
[0041] Figure 1 Schematic diagram of an automated testing device according to an embodiment of the present application. Figure 1 As shown, the automated testing device 100 of this embodiment includes a controller 110 , a reference voltage source 120 , a first interface conversion module 130 and a cascade control unit 140 .
[0042] In this embodiment, multiple chips are divided into multiple test groups. Figure 1 2 test groups 101 and 102 are shown in series. Figure 1 The ellipsis in the figure indicates that multiple test groups 101 can be connected in series after the test group 102. Each test group includes multiple chips. For example, the test group 101 includes n1 chips, and the test group 102 includes n2 chips. n1 and n2 can be equal or unequal. Each test group can be specifically implemented as a test board. At present, when performing chip testing, only one test board can be tested at a time, the number of chips that can be tested is limited, and the data processing method is complicated, which is not conducive to realizing automated testing.
[0043] In some embodiments, the voltage detection chip is a chip for detecting battery voltage. Further, the chip is a chip for detecting the voltage of a power battery on a new energy vehicle.
[0044] like Figure 1 As shown, the automated test device 100 includes a reference voltage source 120 for providing a reference voltage to the chips in each test group. The reference voltage source 120 is connected to each chip in each test group through a power line. Figure 1 As shown, two power lines extend from the reference voltage source 120, one is a positive line, and the other is a negative line, and each chip is connected to the power line. In some embodiments, the reference voltage includes a plurality of different reference voltages, and the range of the reference voltage is within the sampling voltage range of the chip. According to the test mode, different reference voltages can be provided to each target chip. The sampling voltage range of chips with different performances may be different, and the reference voltage source 120 provides the reference voltage according to the sampling voltage range of the chip to be tested. For example, the rated sampling voltage range of the chip is -12V to 12V, and the range of the reference voltage that the reference voltage source 120 can provide is also -12V to 12V. Specifically, a step length can be set to provide different reference voltages to the target chip from low to high in turn to test its accuracy under different reference voltages.
[0045] like Figure 1 As shown, the cascade control unit 140 corresponds to the test group one by one, for example, the test group 101 corresponds to the cascade control unit 141, the test group 102 corresponds to the cascade control unit 142, and so on. The cascade control unit 140 is used to assign numbers to the corresponding test groups so that the test groups are tested in the order of the numbers, and to enable the target chip in the test group to be enabled according to the enable command of the controller 110, and to use the target chip as the current test object.
[0046] The cascade control unit 142 may be specifically implemented as a circuit with an enumeration function, which can count the number of all test groups and automatically assign numbers, thereby distinguishing the test groups by numbers. Each test group number is unique and has a sequence.
[0047] The present application does not limit the number of times to be tested and the number of reference voltages to be provided. The controller 110 sets a series of gating commands according to the test requirements, and the gating commands are used to specify the target chip as the test object, the number of tests, etc. Gating means that the target chip can receive the reference voltage provided to it, and the target chip can work normally, detect the reference voltage, and output the detected voltage sampling value from its sampling terminal. The target chip can be any one of all chips.
[0048] like Figure 1 As shown, the first interface conversion module 130 is connected between the controller 110 and the cascade control unit 140, and the first interface conversion module 130 is used to send a strobe command to the cascade control unit 140, and obtain a voltage sampling value of a target chip, and send the voltage sampling value to the controller 110. Specifically, when there are multiple test groups and their corresponding cascade control units 140, the first interface conversion module 130 can send a strobe command to each cascade control unit 140, and can obtain a voltage sampling value of each chip in each test group.
[0049] In some embodiments, the controller 110 and the first interface conversion module 130 may communicate with each other wirelessly.
[0050] In some embodiments, due to different interface protocols, the controller 110 cannot communicate directly with the cascade control unit 140, so the first interface conversion module 130 also has a protocol conversion function. For example, if the interface of the controller 110 is a USB interface and the interface of the cascade control unit 140 is a serial port, the first interface conversion module 130 needs to have a function of converting the USB protocol into a serial port protocol.
[0051] In some embodiments, multiple cascade control units are connected in series to form a multi-level structure. Figure 1 As shown, the first interface conversion module 130 is directly connected to the cascade control unit 141. Since the cascade control unit 141 is connected in series with the cascade control unit 142, the first interface conversion module 130 can send the selection command to the cascade control unit 142 through the cascade control unit 141. If the target chip is located in the test group 102, the cascade control unit 142 can first send the voltage sampling value of the target chip to the cascade control unit 141 of the previous stage, and then the cascade control unit 141 sends it to the first interface conversion module 130, so that the first interface conversion module 130 obtains the voltage sampling value. According to such a setting, adjacent cascade control units can communicate with each other, so that the test data of each test group is transmitted in one direction and sent to the controller, realizing the cascade of multiple test groups, which is conducive to expanding the number of chip tests.
[0052] In some embodiments, in each test group, the sampling end of each chip is connected to the cascade control unit 140, and the sampling end is used to output the voltage sampling value. The first interface conversion module 130 obtains the voltage sampling value of the chip through the cascade control unit 140. Specifically, Figure 1As shown, each chip is connected to the cascade control unit 140 through two wires. Taking the test group 101 as an example, chip 1 is connected to the cascade control unit 141 through wires 151 and 161, respectively, wherein the cascade control unit 141 controls whether chip 1 is enabled through one wire, such as wire 161, and obtains the voltage sampling value of chip 1 through another wire, such as wire 151. Wherein, wire 151 is connected to the sampling end of chip 1. The same is true for wires 152 and 162 of chip n1, and so on.
[0053] like Figure 1 As shown, the controller 110 is configured to: control the reference voltage source 120 to provide reference voltages to multiple chips in multiple test groups, and send a gating command to the cascade control unit according to the test mode. The test mode can be set according to specific test requirements.
[0054] In some embodiments, in order to test the accuracy of a single chip, the test mode is to obtain multiple voltage sampling values for a certain chip at a fixed reference voltage. For example, under the reference voltage V1, the chip 1 is tested 100 times, and under the reference voltage V2, the chip 1 is tested 100 times. According to the statistical results of the data, the accuracy of the chip 1 under V1 and the accuracy under V2 can be analyzed.
[0055] In some embodiments, in order to test the stability of multiple chips in a batch, the test mode is to obtain multiple voltage sampling values for multiple chips at a fixed reference voltage. For example, under the reference voltage V1, chips 1 to chip n1 are tested 100 times, and under the reference voltage V2, chips 1 to chip n1 are tested 100 times. According to the statistical results of the data, the stability of chips 1 to chip n1 under V1 and the stability under V2 can be analyzed.
[0056] According to the automated testing device 100 of this embodiment, automated testing of multiple chips in multiple test groups can be implemented. After the test mode is set, the test process basically does not require intervention, and the test of a large number of chips can be completed.
[0057] exist Figure 1 In the automated testing device 100 shown, the chip itself has a power supply system to ensure the normal operation of the chip.
[0058] Figure 2 Schematic diagram of an automated testing device according to another embodiment of the present invention. Figure 2 As shown, the automated testing device 200 Figure 1The automated testing device 100 shown further includes a chip power supply unit 210. Multiple chips in a test group are connected in series, and chips in adjacent test groups are connected in series. The chip power supply unit 210 is used to supply power to the chips in each test group simultaneously. Figure 2 Only one test group is shown, and the remaining test groups are omitted, which is not intended to limit the number of test groups in this embodiment. Figure 2 As shown, taking the test group 101 as an example, the chip power supply unit 210 is directly connected to the chip 1 therein through two connecting lines, one of which can be a positive line and the other can be a negative line. At the same time, the chip 1 is connected to the chip on its right through two connecting lines until the chip n1. Figure 2 As shown, the last chip n1 in the test group 101 can also be connected to the first chip in the next test group 102 through two wires, so that the chip power supply unit 210 is also used to power the chips in the test group 102. In this way, the chip power supply unit 210 can power multiple chips in multiple test groups. Although the chip power supply unit 210 can be connected to multiple chips, for a single chip, its power supply method is still independent power supply. For example, the chip power supply unit 210 provides a 5V working voltage, and each chip is subjected to a 5V working voltage.
[0059] Figure 3 Schematic diagram of an automated testing device according to another embodiment of the present invention. Figure 3 As shown, the automated testing device 300 is Figure 2 The automatic test device 200 shown in the figure further includes a switch unit. The switch unit corresponds to the test group one by one, that is, each test group includes a corresponding switch unit. Figure 3 Only one test group is shown, and the remaining test groups are omitted, which is not intended to limit the number of test groups in this embodiment. Figure 3As shown, in this embodiment, each switch unit includes a switch controller 311 and a plurality of switch devices, one switch device is connected between the reference voltage source 120 and a chip, and the cascade control unit 141 is connected to the switch controller 311. The cascade control unit 141 is also used to control the switch controller 311 according to the gating command, so that the switch controller 311 controls the switch device connected between the target chip and the reference voltage source 120 to be connected, and the other switch devices are disconnected. Taking the test group 101 as an example, the test group 101 includes n1 chips, so the corresponding switch unit includes n1 switch devices, each chip has a corresponding switch device, for example, chip 1 corresponds to switch device 1, chip 2 corresponds to switch device 2, and so on. Assuming that the current target chip is chip 1, the cascade control unit 141 controls the switch controller 311, and the switch controller 311 further controls the switch device 1 to be turned on, so that the reference voltage source 120 is connected to chip 1, so that the first interface conversion module 130 can obtain the voltage sampling value of chip 1. At the same time, the switch controller 311 also controls the remaining switch devices 2 to n1 to be turned off, so that the chips 2 to n1 are disconnected from the reference voltage source 120. According to such a setting, it is equivalent to realizing time-division multiplexing of the reference voltage source 120. At a time, the reference voltage source 120 is only connected to one target chip. When testing the target chip, its test result will not be affected by other chips in the circuit, which can improve the detection accuracy of a single chip.
[0060] In some embodiments, the switching device is an electronic switch.
[0061] In some embodiments, the switch device includes a relay. The relay has the function of connecting or disconnecting the element connected thereto. The present application does not limit the type of relay.
[0062] In some embodiments, the switch device is a relay, and accordingly, the switch controller 311 is a relay controller.
[0063] Figure 4 Schematic diagram of the structure of a switch controller in an automated testing device according to an embodiment of the present application. Figure 4 As shown, in this embodiment, the switch controller 310 includes a second interface conversion module 410 and a latch 420, combined with Figure 3 and Figure 4As shown, the second interface conversion module 410 and the latch 420 are sequentially connected between the cascade control unit 140 and the plurality of chips. The second interface conversion module 410 is used to convert the serial strobe command into a parallel signal, and send the parallel signal to the latch 420. The number of bits of the parallel signal is equal to the number of chips in the test group. The latch 420 performs an opening and closing action according to the parallel signal, and closes the latch enable switch WRT_EN after the opening and closing action, until the cascade control unit 140 receives a strobe command for testing the next target chip, and then opens the latch enable switch WRT_EN. In this embodiment, the strobe command issued by the controller 110 is not necessarily a serial signal, but the strobe command received by the cascade control unit 140 and sent to the switch controller 310 is a serial signal.
[0064] In some embodiments, the second interface conversion module 410 includes a serial port to parallel port circuit.
[0065] Combination Figure 4 and Figure 5 In the illustrated embodiment, the switch state of each switch device can be effectively controlled by the switch controller 310 to ensure that when testing the target chip, the reference voltage source 120 is only connected to the target chip and disconnected from other chips, thereby minimizing the impact of other sampling circuits on the target chip.
[0066] Figure 5 Schematic diagram of an automated testing device according to another embodiment of the present invention. Figure 5 As shown, the automated testing device 500 is Figure 3 The automated test device 300 shown further includes a third interface conversion module 510, which is disposed between the controller 110 and the reference voltage source 120. The third interface conversion module 510 is used for communication protocol conversion between the controller 110 and the reference voltage source 120. In some embodiments, due to different interface protocols, the controller 110 cannot communicate directly with the reference voltage source 120, and therefore, the third interface conversion module 510 is added in this embodiment.
[0067] In some embodiments, the controller 110 is specifically implemented as a PC terminal. Assuming that its communication interface is a USB protocol interface, and the interface of the reference voltage source 120 is a serial port, the third interface conversion module 510 is a functional module or device that converts the USB protocol into a serial port protocol. If the interface of the reference voltage source 120 is also a USB interface, the third interface conversion module 510 does not need to be set.
[0068] The present application does not limit the interface type of the controller 110. In some embodiments, the controller 110 and the reference voltage source 120 may also be connected to each other wirelessly, for example, via Ethernet.
[0069] Figure 5 The illustrated embodiment takes into account the problem of interface conversion, so that the automated testing device 500 can run more smoothly and achieve smooth data interaction.
[0070] Based on the automated testing device described above, this application also proposes a method for automated testing of voltage detection chips using the automated testing device. By setting simple steps to perform testing on large quantities of chips and proposing specific processing methods for large amounts of data, the analysis of test data can be accelerated and production capacity can be improved.
[0071] Figure 6 is an exemplary flow chart of an automated testing method according to an embodiment of the present application. Figure 6 As shown, the automated testing method of this embodiment includes the following steps:
[0072] Step S610: Initialization, each cascade control unit assigns a number to each test group, the chip power supply unit supplies power to the chips in each test group, the controller obtains the communication status of each chip, and takes the chips with normal communication status as the tested objects;
[0073] Step S620: the controller sets a reference voltage value to be tested, and sends the reference voltage value to a reference voltage source, and the reference voltage source outputs the reference voltage value;
[0074] Step S630: the controller sends a strobe command to the cascade control unit in sequence according to the number, and the cascade control unit enables the target chip in the corresponding test group according to the strobe command; and
[0075] Step S640: the first interface conversion module obtains the voltage sampling value of the selected target chip, and sends the voltage sampling value to the controller.
[0076] The foregoing description of the automated testing device can be used to illustrate the automated testing method, and the same content will not be expanded. It should be noted that the initial state of all switching devices, such as relays, is the closed state. That is to say, in the initialization step of step S610, all relays are in the closed state. When the chip is in a normal power supply state, if there is a chip with an abnormal communication state, the abnormal chip is recorded, for example, its number in the test group is recorded. In this way, the data of the abnormal chip can be extracted in the data processing so that it does not participate in the subsequent data statistics and analysis. According to the test mode, when the reference voltage value changes, the above steps S620 to S640 are repeated.
[0077] In order to speed up data analysis, the automated testing method proposes different data analysis methods for different test modes.
[0078] In the test mode for evaluating the accuracy of a single chip, the automated test method further includes: recording a plurality of voltage sampling values of the single chip at the same reference voltage value, so as to evaluate the accuracy of the voltage sampling of the single chip.
[0079] In the test mode for evaluating the stability of multiple chips, the automated test method further includes: recording multiple voltage sampling values of the multiple chips at the same reference voltage to evaluate the stability of the voltage sampling of the multiple chips.
[0080] In some embodiments, the present application proposes a data recording method for automated data processing. Specifically, the controller uses a three-dimensional data recording method to record a single data as M xyz , where x represents the number of samples of a single chip under a reference voltage, y represents the number of a single chip, and z represents the reference voltage value provided to the single chip. The reference voltage value is used to represent the discrete value of the reference voltage selected within the chip sampling voltage range. In other embodiments, z can also be the voltage value number corresponding to different reference voltage values. Wherein, xyz can represent three axes in a three-dimensional coordinate system, each coordinate axis is an equivalent coordinate axis, and the parameters represented by them are interchangeable.
[0081] According to the three-dimensional data recording method, in the test mode for evaluating the accuracy of a single chip, the following formula (1) is used to calculate the first mean and first variance of multiple voltage sampling values of a single chip at the same reference voltage value:
[0082]
[0083] Wherein, Mx represents the xth voltage sampling value of a single chip under a reference voltage value, and n represents the total number of sampling times. represents the first mean, S1 2 The test method further includes: using the first mean value and the first variance to evaluate the accuracy of voltage sampling of a single chip.
[0084] In formula (1), the y-axis and z-axis in the three-dimensional data are constants, and the x-axis is a variable. After the test is completed, a distribution diagram of multiple voltage sampling values of a single chip under the same reference voltage value can be generated. If the sample mean is closer to the reference voltage value and the variance is smaller, it means that the accuracy of the chip is higher.
[0085] According to the three-dimensional data recording method, in a test mode for evaluating the stability of multiple chips, the following formula (2) is used to calculate the second mean and the second variance of multiple voltage sampling values of multiple chips at the same reference voltage:
[0086]
[0087] Wherein, My represents the voltage sampling value of the chip numbered y at a reference voltage value, m represents the number of multiple chips, represents the second mean, S2 2 The test method also includes: using the second mean and the second variance to evaluate the stability of voltage sampling of multiple chips.
[0088] In formula (2), the x-axis and z-axis in the three-dimensional data are constants, and the y-axis is a variable. After the test is completed, a distribution diagram of multiple voltage sampling values of multiple chips under the same reference voltage value can be generated. If the sample mean is closer to the reference voltage value and the variance is smaller, it means that the accuracy of the chip is higher.
[0089] In some embodiments, the controller 110 is provided with a processing script for processing data, so as to implement the above-mentioned data processing process.
[0090] According to the automated testing method of the present application, the accuracy of each chip sampling within the entire sampling voltage range and the stability of all chip sampling can be given. The processing speed is fast, and it can also be combined with visual output to provide an intuitive display, which greatly reduces manual intervention in testing, saves manpower, reduces the time required for testing, and is conducive to improving production capacity.
[0091] The basic concepts have been described above. Obviously, for those skilled in the art, the above invention disclosure is only used as an example and does not constitute a limitation of the present application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements and amendments to the present application. Such modifications, improvements and amendments are suggested in the present application, so such modifications, improvements and amendments still belong to the spirit and scope of the exemplary embodiments of the present application.
[0092] At the same time, the present application uses specific words to describe the embodiments of the present application. For example, "one embodiment", "an embodiment", and / or "some embodiments" refer to a certain feature, structure or characteristic related to at least one embodiment of the present application. Therefore, it should be emphasized and noted that "one embodiment" or "an embodiment" or "an alternative embodiment" mentioned twice or more in different positions in this specification does not necessarily refer to the same embodiment. In addition, some features, structures or characteristics in one or more embodiments of the present application can be appropriately combined.
[0093] Similarly, it should be noted that in order to simplify the description of the disclosure of this application and thus help understand one or more embodiments of the invention, in the above description of the embodiments of this application, multiple features are sometimes combined into one embodiment, figure or description thereof. However, this disclosure method does not mean that the features required by the object of this application are more than the features mentioned in the claims. In fact, the features of the embodiments are less than all the features of the single embodiment disclosed above.
[0094] In some embodiments, numbers describing the number of components and attributes are used. It should be understood that such numbers used in the description of the embodiments are modified by the modifiers "about", "approximately" or "substantially" in some examples. Unless otherwise specified, "about", "approximately" or "substantially" indicate that the numbers are allowed to vary by ±20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximate values, which may change according to the required features of individual embodiments. In some embodiments, the numerical parameters should take into account the specified significant digits and adopt the general method of retaining digits. Although the numerical domains and parameters used to confirm the breadth of their range in some embodiments of the present application are approximate values, in specific embodiments, the setting of such numerical values is as accurate as possible within the feasible range.
Claims
1. An automated testing device for a voltage detection chip, wherein a plurality of the chips are divided into at least one test group, each of the test groups includes a plurality of the chips, characterized in that: include: A reference voltage source, a cascade control unit, a first interface conversion module and a controller, wherein: The reference voltage source is used to provide a reference voltage to each chip in the test group; The cascade control unit corresponds to the test group one by one, and is used to assign numbers to the corresponding test groups so that the test groups are tested in the order of the numbers, and to enable the target chip in the test group to be enabled according to the enable command of the controller, so that the target chip is used as the current test object; The first interface conversion module is connected between the controller and the cascade control unit, and the first interface conversion module is used to send the gating command to the cascade control unit, and obtain the voltage sampling value of the target chip, and send the voltage sampling value to the controller; and The controller is configured to: control the reference voltage source to provide reference voltages to the multiple chips in the multiple test groups, and send the strobe command to the cascade control unit according to a test mode.
2. The automated testing device according to claim 1, characterized in that: The first interface conversion module is directly connected to one of the cascade control units, and multiple cascade control units are connected in series to form a multi-level structure. The voltage sampling value of the target chip in each test group is sent to the cascade control unit of the previous level through the corresponding cascade control unit, and is finally acquired by the first interface conversion module.
3. The automated testing device according to claim 1, wherein: In each test group, a sampling end of each chip is connected to the cascade control unit, the sampling end is used to output the voltage sampling value, and the first interface conversion module obtains the voltage sampling value of the chip through the cascade control unit.
4. The automated testing device according to claim 1, wherein: It also includes a chip power supply unit. The multiple chips in the test group are connected in series, and the chips in adjacent test groups are connected in series. The chip power supply unit is used to supply power to each chip in the test group at the same time.
5. The automated testing device according to claim 1, wherein: It also includes switch units, which correspond to the test groups one by one. Each of the switch units includes a switch controller and multiple switch devices. A switch device is connected between the reference voltage source and one of the chips. The cascade control unit is connected to the switch controller. The cascade control unit is also used to control the switch controller according to the selection command, so that the switch controller controls the switch device connected between the target chip and the reference voltage source to be connected, while disconnecting other switch devices.
6. The automated testing device according to claim 5, characterized in that: The switching device includes a relay.
7. The automated testing device according to claim 5, characterized in that: The switch controller includes a second interface conversion module and a latch, which are connected in sequence between the cascade control unit and multiple chips. The second interface conversion module is used to convert the serial selection command into a parallel signal and send the parallel signal to the latch. The number of bits of the parallel signal is equal to the number of chips in the test group. The latch performs an opening and closing action according to the parallel signal and closes the latch enable switch after the opening and closing action until the cascade control unit receives a selection command for testing the next target chip, and then opens the latch enable switch.
8. The automated testing device according to claim 7, wherein: The second interface conversion module includes a serial port to parallel port circuit.
9. The automated testing device according to claim 1, wherein: The reference voltage includes a plurality of different reference voltages, and the range of the reference voltage is within the sampling voltage range of the chip.
10. The automated testing device according to claim 1, wherein: It also includes a third interface conversion module, which is arranged between the controller and the reference voltage source and is used for communication protocol conversion between the controller and the reference voltage source.
11. The automated testing device according to claim 1, wherein: The controller is also used to evaluate the accuracy of voltage sampling of a single chip and the stability of voltage sampling of multiple chips according to the voltage sampling values.
12. The automated testing device according to claim 1, wherein: The voltage detection chip is used to detect the battery voltage.
13. An automated testing method for a voltage detection chip, characterized in that: The following steps are performed using the automated testing device as described in any one of claims 1 to 12: Initialization, each of the cascade control units assigns a number to each of the test groups, the chip power supply unit supplies power to each chip in the test group, the controller obtains the communication status of each chip, and takes the chip with normal communication status as the test object; The controller sets a reference voltage value to be tested, and sends the reference voltage value to the reference voltage source, and the reference voltage source outputs the reference voltage value; The controller sends the strobe command to the cascade control unit in sequence according to the number, and the cascade control unit enables the target chip in the corresponding test group according to the strobe command; and The first interface conversion module obtains a voltage sampling value of the selected target chip, and sends the voltage sampling value to the controller.
14. The automated testing method according to claim 13, wherein: Also includes: Multiple voltage sampling values of a single chip under the same reference voltage value are recorded to evaluate the accuracy of the voltage sampling of the single chip.
15. The automated testing method according to claim 13, wherein: Also includes: Record multiple voltage sampling values of multiple chips at the same reference voltage to evaluate the stability of voltage sampling of multiple chips.
16. The automated testing method according to claim 13, wherein: Also includes: The controller records single data as M in a three-dimensional data recording manner. xyz , wherein x represents the sampling times of a single chip at a reference voltage, y represents the number of the single chip, and z represents the number of the reference voltage value provided to the single chip.
17. The automated testing method according to claim 16, wherein: The following formula is used to calculate the first mean and first variance of multiple voltage sampling values of a single chip at the same reference voltage value: Wherein, Mx represents the xth voltage sampling value of a single chip under a reference voltage value, and n represents the total number of sampling times. represents the first mean, S1 2 represents the first variance; The method further includes: evaluating the accuracy of voltage sampling of the single chip by using the first mean value and the first variance.
18. The automated testing method according to claim 16, wherein: The following formula is used to calculate the second mean and second variance of multiple voltage sampling values of multiple chips at the same reference voltage: Wherein, My represents the voltage sampling value of the chip numbered y at a reference voltage value, m represents the number of the plurality of chips, represents the second mean, S2 2 represents the second variance; The method further includes: evaluating the stability of voltage sampling of multiple chips by using the second mean value and the second variance.
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