Low dropout regulator

Abstract

The invention discloses a low dropout linear regulator. The low dropout regulator includes: a power transistor having a current conduction path coupled between an input voltage and an output voltage; the error amplifier is used for comparing a feedback voltage of the output voltage with a reference voltage and controlling a grid voltage of the power transistor according to a comparison result; and the overshoot protection circuit is used for judging whether overshoot voltage occurs at the output voltage by detecting the gate-source voltage of the power transistor, and conducting a current discharge path of the output voltage to a reference ground under the condition that the overshoot voltage occurs, so that load current of a voltage output end can be absorbed in the LDO, and the output voltage of the LDO is improved. And the overshoot amplitude and the recovery time of the output voltage are reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of power supply, and in particular to a low voltage difference linear regulator. Background Art

[0002] As an important component of the power management module, LDO (Low Dropout Regulator) is widely used in various systems such as data acquisition, battery power supply, low power consumption and industrial control, providing a stable and reliable power supply environment. Whether its output voltage is stable and not affected by power supply and load mutations directly determines the overall performance of the system.

[0003] like Figure 1 As shown, the conventional low voltage drop linear regulator 100 mainly includes a reference circuit 110, an error amplifier AMP, a resistor voltage divider network, a power transistor MP and a load (the load resistor is RL and the output capacitor is CL). The error amplifier AMP is used to amplify the difference between the feedback voltage VFB and the reference voltage VREF, and the gate-source voltage Vgs of the power transistor MP increases or decreases to control the output voltage VOUT, thereby achieving output voltage stability.

[0004] In a low-dropout linear regulator without a fast discharge function, when the load current changes rapidly from a high current to a low current, the output voltage VOUT is raised and an overshoot occurs because a large capacitor CL (generally a few uF to tens of uF) is connected to the output of the LDO. If the overshoot voltage is only discharged slowly through the pull-down current inside the LDO, it will last for a long time, affecting the stability of the circuit.

[0005] Therefore, there is an urgent need for a circuit design that can effectively discharge the output current and enable the output voltage to recover quickly without significantly increasing the power consumption and cost of the low-voltage line linear regulator. Summary of the invention

[0006] In order to solve the above technical problems, the present invention provides a low voltage dropout linear regulator, which can quickly discharge the output current and reduce the output overshoot without affecting the performance of the low voltage dropout linear regulator.

[0007] According to one aspect of the present invention, there is provided a low voltage difference linear regulator, comprising: a power transistor having a current conduction path coupled between an input voltage and an output voltage; an error amplifier, for comparing a feedback voltage of the output voltage with a reference voltage, and controlling a gate voltage of the power transistor according to a comparison result; and an overshoot protection circuit, for determining whether an overshoot voltage occurs at the output voltage by detecting a gate-source voltage of the power transistor, and conducting a current discharge path of the output voltage to a reference ground when the overshoot voltage occurs.

[0008] Optionally, the overshoot protection circuit includes: a current discharge module connected between the output voltage and the reference ground; and a voltage detection module, used to detect the gate-source voltage of the power transistor and turn on the current discharge module when the gate-source voltage is less than a set value.

[0009] Optionally, the voltage detection module includes: a first transistor, a first end of which is connected to the input voltage, and a control end is connected to the gate of the power transistor; a current source, a first end of which is connected to the second end of the first transistor, and a second end is connected to the reference ground; and a second transistor, a first end of which is connected to the input voltage, a control end is connected to an intermediate node between the first transistor and the current source, and a second end is connected to the current discharge module.

[0010] Optionally, the current discharge module includes: a third transistor, whose first end and control end are connected to the second end of the second transistor, and the second end is connected to the reference ground; and a fourth transistor, whose first end is connected to the output voltage, the control end is connected to the control end of the third transistor, and the second end is connected to the reference ground.

[0011] Optionally, a size ratio of the first transistor to the power transistor is 1:N, where N is an integer greater than 1.

[0012] Optionally, the set value is set by an output current of the current source.

[0013] Optionally, the first transistor and the second transistor are PMOS transistors, and the third transistor and the fourth transistor are NMOS transistors.

[0014] In summary, the present invention discloses an overshoot protection circuit with a simple structure for LDO, which can provide a current discharge path of the output voltage to the ground according to the reduction of the gate-source voltage of the power transistor when the load current decreases rapidly, thereby accelerating the discharge speed of the output current, reducing the overshoot amplitude and recovery time of the output voltage, and improving the circuit stability and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings.

[0016] Figure 1 A schematic circuit diagram of a conventional low dropout linear regulator is shown.

[0017] Figure 2 FIG. 4 shows a schematic circuit diagram of a low voltage dropout linear regulator according to an embodiment of the present invention.

[0018] Figure 3 A waveform comparison diagram of a conventional low-dropout linear regulator and a low-dropout linear regulator according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0019] Reference will now be made in detail to the exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings.Where possible, the same reference numerals will be used throughout the drawings to refer to the same or like parts.

[0020] In the specification, it should be noted that similar reference numerals that have been used to represent similar parts in other drawings are used for these elements as much as possible. In the following description, when functions and configurations known to those skilled in the art are not related to the basic configuration of the present disclosure, their detailed description will be omitted. The terms described in the specification should be understood as follows.

[0021] The advantages and features of the present disclosure and their implementation methods will be described through the following embodiments described with reference to the accompanying drawings. However, the present disclosure can be implemented in different forms and should not be interpreted as being limited to the embodiments described herein. Rather, these embodiments are provided to make the present disclosure comprehensive and complete, so as to fully convey the scope of the present disclosure to those skilled in the art. In addition, the present disclosure is limited only by the scope of the claims.

[0022] The shapes, sizes, ratios, angles, and quantities disclosed in the drawings used to describe the embodiments of the present disclosure are merely examples, and the present disclosure is therefore not limited to the illustrated details. Similar reference numerals always represent similar elements. In the following description, when it is determined that a detailed description of a related known function or construction will inevitably obscure the focus of the present disclosure, the detailed description will be omitted.

[0023] As those skilled in the art can fully understand, the features of the various embodiments of the present disclosure can be partially or completely combined or combined with each other, and can interoperate and technically drive each other in various ways. The embodiments of the present disclosure can be performed independently of each other, or can be performed together in a mutually dependent relationship.

[0024] In the present application, a MOS transistor (Metal-Oxide-Semiconductor Field-Effect Transistor) includes a first terminal, a second terminal and a control terminal. When the MOS transistor is in the on state, current flows from the first terminal to the second terminal. The first terminal, the second terminal and the control terminal of a PMOS transistor are the source, the drain and the gate, respectively, and the first terminal, the second terminal and the control terminal of an NMOS transistor are the drain, the source and the gate, respectively.

[0025] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0026] Figure 2 FIG. 2 shows a schematic circuit diagram of a low voltage dropout linear regulator 200 according to an embodiment of the present invention. Figure 2 As shown, the low dropout linear regulator 200 includes a power transistor MP, an error amplifier AMP, a reference circuit 210 , a resistor divider network, a load (the load resistor is RL, the output capacitor is CL), and an overshoot protection circuit 220 .

[0027] The power transistor MP is the main output transistor of the chip, and has a current conduction path and a control terminal coupled between the input voltage VIN and the output voltage VOUT. For example, the power transistor MP is a PMOS transistor, the source of the power transistor MP is coupled to the input voltage VIN, and the drain of the power transistor MP is used to provide the output voltage VOUT to the subsequent load. In other embodiments, the power transistor MP may also be other types of transistors, such as NMOS transistors, NPN Darlington transistors, and NPN bipolar transistors.

[0028] The resistor divider network composed of resistors R1 and R2 is coupled between the output terminal of the output voltage VOUT and the ground, and is used to obtain the feedback voltage VFB after dividing the output voltage VOUT, that is, the node between resistors R1 and R2 provides the feedback voltage VFB. The non-inverting input terminal of the error amplifier AMP is used to receive the feedback voltage VFB, and the inverting input terminal of the error amplifier AMP is connected to the reference circuit 210 for receiving the reference voltage VREF. The output terminal of the error amplifier AMP is connected to the gate of the power transistor MP. The error amplifier AMP is used to compare the feedback voltage VFB with the reference voltage VREF, and to control the gate-source voltage of the power transistor MP by amplifying the difference between the two, so as to stabilize the output voltage VOUT at a set value. Although Figure 2 The embodiment shown in the figure adopts an error amplifier AMP, but those skilled in the art will appreciate that other suitable analog or digital circuits are also applicable as long as the error amplification function can be achieved.

[0029] The overshoot protection circuit 220 is used to determine whether an overshoot voltage occurs in the output voltage VOUT by detecting the gate-source voltage of the power transistor MP, and to turn on the discharge path of the output voltage VOUT to the ground when the overshoot voltage occurs in the circuit, thereby reducing the overshoot voltage amplitude of the output voltage and reducing the time it takes for the output voltage to return to normal.

[0030] Furthermore, the overshoot protection circuit 220 includes a voltage detection module 201 and a current discharge module 202. The voltage detection module 201 is connected to the power transistor MP and is used to detect the gate-source voltage of the power transistor MP. The current discharge module 202 is connected between the output voltage VOUT and the ground GND and is used to provide a charge discharge path of the output voltage VOUT to the ground according to the detection result of the voltage detection module 201. Further, when the gate-source voltage of the power transistor MP is less than the set value, the voltage detection module 201 turns on the current discharge module 202, thereby pulling the output voltage VOUT down to the ground GND to reduce the voltage overshoot at the output voltage VOUT, thereby reducing the overshoot amplitude and recovery time of the output voltage, and improving the stability of the circuit.

[0031] Further, the voltage detection module 201 includes PMOS transistors Mp1 and Mp2 and a current source I1. The first end of the PMOS transistor Mp1 is connected to the input voltage VIN, the control end of the PMOS transistor Mp1 is connected to the gate of the power transistor MP, the second end of the PMOS transistor Mp1 is connected to the first end of the current source I1, the second end of the current source I1 is connected to the reference ground, the first end of the PMOS transistor Mp2 is connected to the input voltage VIN, the control end of the PMOS transistor Mp2 is connected to the middle node of the PMOS transistor Mp1 and the current source I1, and the second end of the PMOS transistor Mp2 is connected to the current discharge module 202. The current discharge module 202 includes NMOS transistors Mn1 and Mn2. Among them, the first end and the control end of the NMOS transistor Mn1 are connected to the second end of the PMOS transistor Mp2, the first end of the NMOS transistor Mn2 is connected to the output voltage VOUT end, the control end of the NMOS transistor Mn2 is connected to the control end and the first end of the NMOS transistor Mn1, and the second ends of the NMOS transistors Mn1 and Mn2 are connected to the reference ground GND.

[0032] Furthermore, the size ratio of the PMOS transistor Mp1 to the power transistor MP is 1:N, where N is an integer greater than 1. Assuming that the load current Iout inside the LDO 200 of this embodiment is 100uA, when N=100, the above-mentioned overshoot protection loop can be established by only setting the output current of the current source I1 to 1uA.

[0033] Among them, when an overshoot voltage appears at the output voltage VOUT, the gate-source voltage Vgs of the power transistor MP will decrease, and then the gate-source voltage Vgs of the PMOS transistor Mp1 will also decrease. Since the PMOS transistor Mp1 is also used to apply a pull-up current at the control end of the PMOS transistor Mp2, as the gate-source voltage Vgs of the PMOS transistor Mp1 decreases, when the pull-up current applied by the PMOS transistor Mp1 is less than the pull-down current (for example, 1uA) provided by the current source I1, the PMOS transistor Mp2 is turned on, and then a larger pull-down current is generated at the output voltage VOUT through the current mirror formed by the NMOS transistors Mn1 and Mn2, so that the output voltage VOUT can be pulled down when an overshoot voltage appears in the circuit, thereby avoiding overshoot of the output voltage VOUT.

[0034] Furthermore, by properly setting the size relationship between the power transistor MP and the NMOS transistors Mn1 and Mn2, it can be ensured that no matter how large the overshoot voltage in the circuit is, it can be absorbed by the NMOS transistor Mn2, thereby enabling the LDO 200 to accelerate the output current discharge and improve the stability and safety of the circuit.

[0035] Figure 3 1 shows a waveform comparison diagram of a conventional low-dropout linear regulator and a low-dropout linear regulator according to an embodiment of the present invention. Among them, Iout represents the waveform of the load current inside the LDO, Vout1 represents the output voltage waveform of the conventional low-dropout linear regulator 100, and Vout2 represents the output voltage waveform of the low-dropout linear regulator 200 according to an embodiment of the present invention. Figure 3 As shown, when the load current inside the LDO decreases from 200mA to 0mA, compared with the traditional low voltage dropout linear regulator, the low voltage dropout linear regulator of the embodiment of the present invention can not only speed up the current discharge of the LDO voltage output end, but also reduce the overshoot of the output voltage.

[0036] In summary, the present invention discloses an overshoot protection circuit with a simple structure for LDO, which can provide a current discharge path of the output voltage to the ground according to the reduction of the gate-source voltage of the power transistor when the load current decreases rapidly, thereby accelerating the discharge speed of the output current, reducing the overshoot amplitude and recovery time of the output voltage, and improving the circuit stability and reliability.

[0037] In addition, the LDO disclosed in the present invention has a simple structure, good performance, requires a small number of transistors, can achieve optimization of layout design, and meets the needs of most occasions in the chip.

[0038] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0039] Finally, it should be noted that: Obviously, the above embodiments are only examples for clearly explaining the present invention, and are not intended to limit the implementation methods. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from this are still within the scope of protection of the present invention.

Claims

1. A low dropout linear regulator, include: a power transistor having a current conduction path coupled between an input voltage and an output voltage; an error amplifier, used for comparing a feedback voltage of the output voltage with a reference voltage, and controlling a gate voltage of the power transistor according to a comparison result; as well as The overshoot protection circuit is used to determine whether an overshoot voltage occurs at the output voltage by detecting the gate-source voltage of the power transistor, and to conduct a current discharge path of the output voltage to a reference ground when the overshoot voltage occurs.

2. The low dropout linear regulator according to claim 1, in, The overshoot protection circuit comprises: a current discharge module, connected between the output voltage and the reference ground; and The voltage detection module is used to detect the gate-source voltage of the power transistor and start the current discharge module when the gate-source voltage is less than a set value.

3. The low dropout linear regulator according to claim 1, in, The voltage detection module comprises: a first transistor, a first terminal of which is connected to the input voltage, and a control terminal of which is connected to the gate of the power transistor; a current source, a first terminal of which is connected to the second terminal of the first transistor, and a second terminal of which is connected to the reference ground; and A second transistor has a first end connected to the input voltage, a control end connected to an intermediate node between the first transistor and the current source, and a second end connected to the current discharge module.

4. The low dropout linear regulator according to claim 3, in, The current discharge module comprises: a third transistor, a first terminal and a control terminal of which are connected to the second terminal of the second transistor, and a second terminal of which is connected to the reference ground; and A fourth transistor has a first terminal connected to the output voltage, a control terminal connected to the control terminal of the third transistor, and a second terminal connected to the reference ground.

5. The low dropout linear regulator according to claim 3, in, The size ratio of the first transistor to the power transistor is 1:N, where N is an integer greater than 1.

6. The low dropout linear regulator according to claim 2, in, The set value is set by the output current of the current source.

7. The low dropout linear regulator according to claim 4, in, The first transistor and the second transistor are PMOS transistors, and the third transistor and the fourth transistor are NMOS transistors.

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