Three-feedback loop quick response low dropout linear regulator

Abstract

The invention discloses a three-feedback loop quick-response low-dropout linear regulator which comprises a first part circuit, a second part circuit, a third part circuit and a fourth part circuit, wherein the first part circuit provides reference voltage VREF; the second part circuit is used for receiving the reference voltage VREF and the feedback voltage VFB, comparing and judging the reference voltage VREF and the feedback voltage VFB, realizing voltage error comparison and feedback regulation control, and outputting voltage VERR and bias current IPB1; the third part circuit is used for receiving the voltage VERR, determining the positions of dominant poles of the second loop and the third loop and improving the phase margin of the loops; the fourth part circuit is used for receiving the bias current IPB1 and outputting bias voltages VB1 and VB2; the fifth part circuit isolates the second part circuit and the sixth part circuit; the sixth part circuit is used for outputting a small-fluctuation stable voltage VOUT and a feedback voltage VFB; the voltage VOUT is used as the output voltage of the low dropout linear regulator; the device has the advantages of high integration level, fast transient response, high stability and simple structure.

Description

Technical Field

[0001] The invention relates to the technical field of power electronic design, and in particular to a three-feedback loop fast response low voltage difference linear regulator. Background Art

[0002] With the continuous development of modern electronic devices, the requirements for power management of modern electronic devices are constantly increasing. Low voltage drop linear regulators can operate at a lower input-output voltage difference, reduce circuit power consumption, improve conversion efficiency, low noise, and maintain a high output voltage stability. This has made them widely used.

[0003] As integrated circuit technology enters the deep submicron and nano era, the frequency of circuits is increasing, and the transient response and stability of traditional low-dropout linear regulators face more stringent challenges. When the load current jumps, the traditional low-dropout linear regulator has a small bandwidth, the transient response of the circuit output voltage is slow, and the output voltage stability is poor, which can easily lead to abnormal function of the subsequent circuit and affect the overall performance of the circuit. Therefore, developing a low-dropout linear regulator with fast transient response, high stability, and simple structure is a hot trend in the future and a practical need. Summary of the invention

[0004] Technical purpose: In view of the problems in the prior art, the present invention discloses a three-feedback loop fast response low voltage drop linear regulator with high integration, fast transient response, high stability and simple structure.

[0005] Technical solution: In order to achieve the above technical objectives, the present invention adopts the following technical solution.

[0006] A three-feedback-loop fast-response low-dropout linear regulator, comprising: The first circuit includes a bandgap reference, which is used to provide a reference voltage V REF ; The second circuit includes an error amplifier for receiving a reference voltage V output by the first circuit. REF And the feedback voltage V output by the sixth circuit FB Compare and judge, realize voltage error comparison and feedback regulation control, and output voltage V ERR and bias current I PB1 ; The third circuit is used for phase compensation low-pass filtering, and its input terminal receives the voltage V output by the second circuit. ERR , used to determine the main pole positions of the second loop and the third loop and improve the loop phase margin; The fourth circuit is used to provide a bias voltage and receive a bias current I output by the second circuit. PB1, and output bias voltage V B1 and V B2 ; The fifth circuit includes a voltage buffer for isolating the second circuit from the sixth circuit. The fifth circuit receives the voltage V output by the second circuit. ERR , the bias voltage V output by the fourth circuit B1 and V B2 , and the output voltage V PG ; The sixth circuit is used to receive the voltage V output by the fifth circuit. PG , and outputs a small fluctuation stable voltage V OUT and feedback voltage V FB , voltage V OUT As the output voltage of a low dropout linear regulator; The fifth circuit and the sixth circuit contain a first loop, which is used as a fast feedback loop for adjusting and controlling the output voltage of the low-dropout linear regulator and improving the transient response speed; The fifth circuit, the sixth circuit, the second circuit, the third circuit, and the fourth circuit contain a second loop and a third loop. The second loop is used as a medium-speed negative feedback loop for adjusting and controlling the output voltage of the low-voltage difference linear regulator, and the third loop is used as a low-speed negative feedback loop for adjusting and controlling the output voltage of the low-voltage difference linear regulator.

[0007] Beneficial effect: In the low voltage drop linear regulator of the present invention, the output voltage V OUT By performing regulation control, the load capacity of the circuit system and the stability of the output voltage are improved, the use of compensation capacitors is eliminated, and the total circuit area is effectively saved. It has high integration, fast transient response, high stability, and a simple circuit structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A schematic diagram of a three-feedback loop fast response low voltage drop linear regulator circuit structure provided in an embodiment of the present application; Figure 2 for Figure 1 Schematic diagram of the structure of the second part of the circuit. DETAILED DESCRIPTION

[0009] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0010] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0011] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0012] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0013] In the description of this application, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "disposed" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0014] The three-feedback loop fast response low voltage drop linear regulator of the present invention is based on the CMOS process platform and is applicable to the following application fields: integrated circuit chips, radio frequency chips and other electronic circuits and systems. Some embodiments of the present application are described in detail below in conjunction with the accompanying drawings. Example

[0015] As attached Figure 1 As shown, a three-feedback loop fast response low voltage drop linear regulator of this embodiment includes: The first circuit 100 includes a bandgap reference for providing a reference voltage V REF; The second circuit 200 includes an error amplifier for receiving a reference voltage V output by the first circuit 100. REF and the feedback voltage V output by the sixth circuit 600 FB Perform comparison and judgment to realize voltage error comparison and feedback regulation control, and output voltage V ERR and bias current I PB1 ; The third circuit 300 is used for phase compensation low-pass filtering, and its input terminal receives the voltage V output by the second circuit 200. ERR , used to determine the main pole positions of the second loop L2 and the third loop L3, and improve the loop phase margin; The fourth circuit 400 is used to provide a bias voltage. The fourth circuit 400 is used to receive the bias current I output by the second circuit 200. PB1 , and output bias voltage V B1 and V B2 ; The fifth circuit 500 includes a voltage buffer for isolating the second circuit 200 from the sixth circuit 600. The fifth circuit 500 receives the voltage V output by the second circuit 200. ERR , the bias voltage V output by the fourth circuit 400 B1 and V B2 , and output voltage V PG ; The sixth circuit 600 is used to receive the voltage V output by the fifth circuit 500. PG , and outputs a small fluctuation stable voltage V OUT and feedback voltage V FB , voltage V OUT As the output voltage of a low dropout linear regulator.

[0016] The fifth circuit 500 and the sixth circuit 600 contain a first loop L1, which is used as a fast feedback loop for regulating and controlling the output voltage of the low-dropout linear regulator and improving the transient response speed; The fifth circuit 500, the sixth circuit 600, the second circuit 200, the third circuit 300, and the fourth circuit 400 contain a second loop L2 and a third loop L3. The second loop L2 is used as a medium-speed negative feedback loop for adjusting and controlling the output voltage of the low-voltage difference linear regulator, and the third loop L3 is used as a low-speed negative feedback loop for adjusting and controlling the output voltage of the low-voltage difference linear regulator.

[0017] like Figure 2As shown, the second circuit 200 in this embodiment is used as an error amplifier circuit, including an error amplifier. The error amplifier in the second circuit 200 uses a folded common-source common-gate amplifier structure, and the circuit structure of the error amplifier includes: a seventh N-type transistor NM7, an eighth N-type transistor NM8, a ninth N-type transistor NM9, a tenth N-type transistor NM10, an eleventh N-type transistor NM11, a twelfth N-type transistor NM12, a thirteenth N-type transistor NM13, a fourteenth N-type transistor NM14, a fifteenth N-type transistor NM15, a sixteenth N-type transistor NM16, a fourth P-type transistor PM4, a fifth P-type transistor PM5, a sixth P-type transistor PM6, a seventh P-type transistor PM7, an eighth P-type transistor PM8, a ninth P-type transistor PM9, a tenth P-type transistor PM10, and an eleventh P-type transistor PM11; The seventh N-type transistor NM7, the eighth N-type transistor NM8, the ninth N-type transistor NM9, the tenth N-type transistor NM10, the eleventh N-type transistor NM11, the twelfth N-type transistor NM12 and the sixth P-type transistor PM6, the seventh P-type transistor PM7, and the eighth P-type transistor PM8 form a current mirror bias structure, and the thirteenth N-type transistor NM13, the fourteenth N-type transistor NM14, the fifteenth N-type transistor NM15, the sixteenth N-type transistor NM16 and the fourth P-type transistor PM4, the fifth P-type transistor PM5, the ninth P-type transistor PM9, the tenth P-type transistor PM10, and the eleventh P-type transistor PM11 form a folded common-source common-gate amplifier structure; The gate of the seventh N-type transistor NM7 and the drain of the seventh N-type transistor NM7 output a bias current I NB1 , the gate of the seventh N-type transistor NM7 is connected to the gate of the eighth N-type transistor NM8, the source of the seventh N-type transistor NM7 is connected to the drain of the ninth N-type transistor NM9, the source of the eighth N-type transistor NM8 is connected to the drain of the tenth N-type transistor NM10, the gate of the ninth N-type transistor NM9 is connected to the drain of the ninth N-type transistor NM9, the source of the ninth N-type transistor NM9 and the source of the tenth N-type transistor NM10 are grounded, and the gate of the ninth N-type transistor NM9 is connected to the gate of the tenth N-type transistor NM10; The gate of the ninth N-type transistor NM9 is connected to the gate of the thirteenth N-type transistor NM13 and the gate of the fourteenth N-type transistor NM14, the gate of the twelfth N-type transistor NM12 is connected to the drain of the twelfth N-type transistor NM12, the gate of the twelfth N-type transistor NM12 is connected to the gate of the eleventh N-type transistor NM11, the source of the twelfth N-type transistor NM12 is connected to the drain of the eleventh N-type transistor NM11, the source of the eleventh N-type transistor NM11, the source of the thirteenth N-type transistor NM13, and the source of the fourteenth N-type transistor NM14 are grounded; The gate of the twelfth N-type transistor NM12 is connected to the gate of the fifteenth N-type transistor NM15 and the gate of the sixteenth N-type transistor NM16, the source of the fifteenth N-type transistor NM15 is connected to the drain of the thirteenth N-type transistor NM13, and the source of the sixteenth N-type transistor NM16 is connected to the drain of the fourteenth N-type transistor NM14; The gate of the fourth P-type transistor PM4 is connected to the reference voltage V output by the first circuit 100. REF The gate of the fifth P-type transistor PM5 is connected to the feedback voltage V output by the sixth circuit 600. FB , the drain of the fourth P-type transistor PM4 is connected to the drain of the thirteenth N-type transistor NM13, and the drain of the fifth P-type transistor PM5 is connected to the drain of the fourteenth N-type transistor NM14; The gate of the seventh P-type transistor PM7 is connected to the drain of the seventh P-type transistor PM7, the gate of the eighth P-type transistor PM8 is connected to the drain of the eighth P-type transistor PM8, the gate of the seventh P-type transistor PM7 is connected to the gate of the eighth P-type transistor PM8, the drain of the seventh P-type transistor PM7 is connected to the gate of the sixth P-type transistor PM6, and the drain of the sixth P-type transistor PM6 outputs a bias current I PB1 , the gate of the eighth P-type transistor PM8 is connected to the gate of the ninth P-type transistor PM9, the drain of the seventh P-type transistor PM7 is connected to the drain of the eighth N-type transistor NM8, the drain of the eighth P-type transistor PM8 is connected to the drain of the twelfth N-type transistor NM12, and the drain of the ninth P-type transistor PM9 is connected to the source of the fourth P-type transistor PM4 and the source of the fifth P-type transistor PM5; The gate of the tenth P-type transistor PM10 is connected to the drain of the tenth P-type transistor PM10, the gate of the eleventh P-type transistor PM11 is connected to the drain of the eleventh P-type transistor PM11, the gate of the eleventh P-type transistor PM11 is connected to the gate of the tenth P-type transistor PM10, the drain of the tenth P-type transistor PM10 is connected to the drain of the fifteenth N-type transistor NM15, the drain of the eleventh P-type transistor PM11 is connected to the drain of the sixteenth N-type transistor NM16, and the drain of the sixteenth N-type transistor NM16 outputs V ERR ; The source of the sixth P-type transistor PM6, the source of the seventh P-type transistor PM7, the source of the eighth P-type transistor PM8, the source of the ninth P-type transistor PM9, the source of the tenth P-type transistor PM10, and the source of the eleventh P-type transistor PM11 are connected to the power supply.

[0018] The third circuit 300 in this embodiment includes a capacitor C1. The capacitor C1 is used as a phase compensation low-pass filter capacitor. The upper plate of the capacitor C1 is connected to the voltage V output by the second circuit 200. ERR The third circuit 300 can be used to determine the main pole position of the second loop L2 and the third loop L3, and improve the loop phase margin. The second circuit 200 has a high output impedance, and the product of the capacitor C1 used as a phase compensation low-pass filter in the third circuit 300 and the output impedance of the second circuit 200 will be much larger than the node RC constant of the fifth circuit 500 and the sixth circuit 600, so the main pole position of the second loop L2 and the third loop L3 is determined by the capacitor C1 in the third circuit 300. The phase compensation of capacitor C1 will move the main pole to low frequency in the frequency domain, and the stability of the loop will be improved as the loop phase margin increases.

[0019] The fourth circuit 400 in this embodiment is a current mirror bias structure, and the fourth circuit 400 includes: a first N-type transistor NM1, a second N-type transistor NM2, a third N-type transistor NM3, a fourth N-type transistor NM4, and a first P-type transistor PM1; The drain of the first N-type transistor NM1 is connected to the bias current I output by the second circuit 200. PB1 The gate of the first N-type transistor NM1 is connected to the drain of the first N-type transistor NM1, and the source of the first N-type transistor NM1 outputs a bias voltage V B1The source of the first N-type transistor NM1 is connected to the drain of the third N-type transistor NM3, the drain of the third N-type transistor NM3 is connected to the gate of the third N-type transistor NM3, the gate of the third N-type transistor NM3 is connected to the gate of the fourth N-type transistor NM4, the source of the fourth N-type transistor NM4 and the source of the third N-type transistor NM3 are grounded; the drain of the fourth N-type transistor NM4 is connected to the source of the second N-type transistor NM2, the gate of the first N-type transistor NM1 is connected to the gate of the second N-type transistor NM2, the drain of the second N-type transistor NM2 is connected to the drain of the first P-type transistor PM1, the drain of the first P-type transistor PM1 is connected to the gate of the first P-type transistor PM1, and the gate of the first P-type transistor PM1 outputs the bias voltage V B2 ; The source of the first P-type transistor PM1 is connected to the power supply; The fifth circuit 500 of this embodiment includes a voltage buffer. The voltage buffer uses a source follower structure to isolate the output terminal V of the error amplifier of the second circuit 200. ERR The high impedance and the third P-type transistor PM3 of the sixth circuit 600 isolate the front and rear circuits to eliminate mutual influence, and the output voltage V PG , the fifth circuit section 500 includes: a fifth N-type transistor NM5, a sixth N-type transistor NM6 and a second P-type transistor PM2; The gate of the fifth N-type transistor NM5 is connected to the bias voltage VB1 output by the fourth part circuit 400; the source of the fifth N-type transistor NM5 is grounded, the drain of the fifth N-type transistor NM5 is connected to the source of the sixth N-type transistor NM6, and the gate of the sixth N-type transistor NM6 is connected to the voltage VERR output by the second part circuit 200; the drain of the sixth N-type transistor NM6 is connected to the drain of the second P-type transistor PM2, the gate of the second P-type transistor PM2 is connected to the bias voltage VB2 output by the fourth part circuit 400, and the source of the second P-type transistor PM2 is connected to the power supply; the drain of the second P-type transistor PM2 outputs the voltage VPG.

[0020] In this embodiment, the fifth part of the circuit 500 and the sixth part of the circuit 600 constitute a super source follower structure, that is, the fifth N-type transistor NM5, the sixth N-type transistor NM6, the second P-type transistor PM2, and the third P-type transistor PM3 constitute a super source follower structure, which reduces the output impedance of the circuit and optimizes the load and driving capabilities of the circuit.

[0021] The sixth circuit 600 in this embodiment is the final output stage of the low voltage drop linear regulator, which is used to output a small fluctuation stable voltage V OUT and feedback voltage V FB The sixth circuit 600 includes a third P-type transistor PM3, a resistor R1, and a resistor R2; The gate of the third P-type transistor PM3 is connected to the voltage V output by the fifth circuit 500. PG The source of the third P-type transistor PM3 is connected to the power supply, the drain of the third P-type transistor PM3 is connected to the source of the sixth N-type transistor NM6 in the fifth circuit 500, and the drain of the third P-type transistor PM3 outputs a voltage V OUT The drain of the third P-type transistor PM3 is connected to the positive electrode of the resistor R1, and the negative electrode of the resistor R1 outputs the feedback voltage V FB , the negative electrode of the resistor R1 is connected to the positive electrode of the resistor R2, and the negative electrode of the resistor R2 is grounded.

[0022] The first loop L1 includes the sixth N-type transistor NM6 in the fifth circuit 500 and the third P-type transistor PM3 in the sixth circuit 600, which is used as a fast feedback loop to adjust and control the output voltage of the low-dropout linear regulator and improve the transient response speed, and can optimize the output voltage V of the low-dropout linear regulator. OUT The transient response speed, specifically, the first loop L1 regulates the output voltage V OUT And improve the transient response speed of the regulator, the first loop L1 can optimize the output voltage V OUT The transient response speed.

[0023] The second loop L2 includes the sixth N-type transistor NM6 in the fifth circuit 500, the resistors R1 and R2 in the sixth circuit 600, the second circuit 200, the third circuit 300, and the fourth circuit 400; it is used as a medium-speed negative feedback loop for adjusting the output voltage of the low-dropout linear regulator, and can provide a feedback voltage to adjust the output voltage V OUT stability, optimizing the bandwidth and stability of the regulator.

[0024] The third loop L3 includes the sixth circuit 600, the sixth N-type transistor NM6 in the fifth circuit 500, the second circuit 200, the third circuit 300, the fourth circuit 400, the third P-type transistor PM3, the sixth N-type transistor NM6, the resistor R1 and the resistor R2, the error amplifier of the second circuit 200, the phase compensation low-pass filter capacitor of the third circuit 300, and the current mirror bias structure of the fourth circuit 400 as the core, which is used as a low-speed negative feedback loop for adjusting and controlling the output voltage of the low-dropout linear regulator, and can provide a low-speed negative feedback path so that V FB With V REF Equal, V ERR The gate voltage of the sixth N-type transistor NM6 is regulated, and the gate voltage of the third P-type transistor PM3 is regulated through voltage transmission, thereby regulating V OUT , so that V OUTThe DC voltage value is at a stable threshold with little fluctuation, which ultimately ensures that V OUT And the stability of the DC operating point of the entire circuit, improving the circuit's sensitivity to external changes.

[0025] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0026] It will be apparent to those skilled in the art that the present application is not limited to the details of the exemplary embodiments described above, and that the present application can be implemented in other specific forms without departing from the spirit or essential features of the present application. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the present application is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims be included in the present application. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A three-feedback loop fast response low voltage dropout linear regulator, characterized in that: include: The first circuit (100) includes a bandgap reference for providing a reference voltage V REF ; The second circuit (200) comprises an error amplifier for receiving a reference voltage V output by the first circuit (100). REF and the feedback voltage V output by the sixth circuit (600) FB Compare and judge, realize voltage error comparison and feedback regulation control, and output voltage V ERR and bias current I PB1 ; The third circuit (300) is used for phase compensation low-pass filtering, and its input end receives the voltage V output by the second circuit (200). ERR , used to determine the main pole positions of the second loop (L2) and the third loop (L3) to improve the loop phase margin; The fourth circuit (400) is used to provide a bias voltage. The fourth circuit (400) is used to receive the bias current I output by the second circuit (200). PB1 , and output bias voltage V B1 and V B2 ; The fifth circuit (500) comprises a voltage buffer for isolating the second circuit (200) and the sixth circuit (600). The fifth circuit (500) receives a voltage V output by the second circuit (200). ERR , the bias voltage V output by the fourth circuit (400) B1 and V B2 , and output voltage V PG ; The sixth circuit (600) is used to receive the voltage V output by the fifth circuit (500) PG , and outputs a small fluctuation stable voltage V OUT and feedback voltage V FB , voltage V OUT As the output voltage of a low dropout linear regulator; The fifth circuit (500) and the sixth circuit (600) contain a first loop (L1) used as a fast feedback loop for regulating and controlling the output voltage of the low-dropout linear regulator and improving the transient response speed; The fifth circuit (500), the sixth circuit (600), the second circuit (200), the third circuit (300), and the fourth circuit (400) contain a second loop (L2) and a third loop (L3); the second loop (L2) is used as a medium-speed negative feedback loop for regulating the output voltage of the low-voltage difference linear regulator, and the third loop (L3) is used as a low-speed negative feedback loop for regulating the output voltage of the low-voltage difference linear regulator.

2. The three-feedback-loop fast-response low-dropout linear regulator according to claim 1, characterized in that: The second circuit part (200) structure comprises: The seventh N-type transistor NM7, the eighth N-type transistor NM8, the ninth N-type transistor NM9, the tenth N-type transistor NM10, the eleventh N-type transistor NM11, the twelfth N-type transistor NM12 and the sixth P-type transistor PM6, the seventh P-type transistor PM7, the eighth P-type transistor PM8 form a current mirror bias structure, and the thirteenth N-type transistor NM13, the fourteenth N-type transistor NM14, the fifteenth N-type transistor NM15, the sixteenth N-type transistor NM16 and the fourth P-type transistor PM4, the fifth P-type transistor PM5, the ninth P-type transistor PM9, the tenth P-type transistor PM10, and the eleventh P-type transistor PM11 form a folded common-source common-gate amplifier structure.

3. The three-feedback-loop fast-response low-dropout linear regulator according to claim 2, characterized in that: The gate of the seventh N-type transistor NM7 and the drain of the seventh N-type transistor NM7 output a bias current I NB1 , the gate of the seventh N-type transistor NM7 is connected to the gate of the eighth N-type transistor NM8, the source of the seventh N-type transistor NM7 is connected to the drain of the ninth N-type transistor NM9, the source of the eighth N-type transistor NM8 is connected to the drain of the tenth N-type transistor NM10, the gate of the ninth N-type transistor NM9 is connected to the drain of the ninth N-type transistor NM9, the source of the ninth N-type transistor NM9 and the source of the tenth N-type transistor NM10 are grounded, and the gate of the ninth N-type transistor NM9 is connected to the gate of the tenth N-type transistor NM10; The gate of the ninth N-type transistor NM9 is connected to the gate of the thirteenth N-type transistor NM13 and the gate of the fourteenth N-type transistor NM14, the gate of the twelfth N-type transistor NM12 is connected to the drain of the twelfth N-type transistor NM12, the gate of the twelfth N-type transistor NM12 is connected to the gate of the eleventh N-type transistor NM11, and the source of the twelfth N-type transistor NM12 is connected to the drain of the eleventh N-type transistor NM11; The gate of the twelfth N-type transistor NM12 is connected to the gate of the fifteenth N-type transistor NM15 and the gate of the sixteenth N-type transistor NM16, the source of the fifteenth N-type transistor NM15 is connected to the drain of the thirteenth N-type transistor NM13, and the source of the sixteenth N-type transistor NM16 is connected to the drain of the fourteenth N-type transistor NM14; The gate of the fourth P-type transistor PM4 is connected to the reference voltage V output by the first circuit (100). REF The gate of the fifth P-type transistor PM5 is connected to the feedback voltage V output by the sixth circuit (600). FB , the drain of the fourth P-type transistor PM4 is connected to the drain of the thirteenth N-type transistor NM13, and the drain of the fifth P-type transistor PM5 is connected to the drain of the fourteenth N-type transistor NM14; The gate of the seventh P-type transistor PM7 is connected to the drain of the seventh P-type transistor PM7, the gate of the eighth P-type transistor PM8 is connected to the drain of the eighth P-type transistor PM8, the gate of the seventh P-type transistor PM7 is connected to the gate of the eighth P-type transistor PM8, the drain of the seventh P-type transistor PM7 is connected to the gate of the sixth P-type transistor PM6, and the drain of the sixth P-type transistor PM6 outputs a bias current I PB1 , the gate of the eighth P-type transistor PM8 is connected to the gate of the ninth P-type transistor PM9, the drain of the seventh P-type transistor PM7 is connected to the drain of the eighth N-type transistor NM8, the drain of the eighth P-type transistor PM8 is connected to the drain of the twelfth N-type transistor NM12, and the drain of the ninth P-type transistor PM9 is connected to the source of the fourth P-type transistor PM4 and the source of the fifth P-type transistor PM5; The gate of the tenth P-type transistor PM10 is connected to the drain of the tenth P-type transistor PM10, the gate of the eleventh P-type transistor PM11 is connected to the drain of the eleventh P-type transistor PM11, the gate of the eleventh P-type transistor PM11 is connected to the gate of the tenth P-type transistor PM10, the drain of the tenth P-type transistor PM10 is connected to the drain of the fifteenth N-type transistor NM15, the drain of the eleventh P-type transistor PM11 is connected to the drain of the sixteenth N-type transistor NM16, and the drain of the sixteenth N-type transistor NM16 outputs V ERR .

4. The three-feedback-loop fast-response low-dropout linear regulator according to claim 1, characterized in that: The third circuit (300) comprises a capacitor C1, the upper plate of the capacitor C1 and the voltage V output by the second circuit (200) ERR The third circuit (300) can be used to determine the main pole positions of the second loop (L2) and the third loop (L3), thereby improving the loop phase margin.

5. The three-feedback-loop fast-response low-dropout linear regulator according to claim 1, characterized in that: The fourth circuit (400) is a current mirror bias structure, and the fourth circuit (400) comprises: a first N-type transistor NM1, a second N-type transistor NM2, a third N-type transistor NM3, a fourth N-type transistor NM4, and a first P-type transistor PM1; The drain of the first N-type transistor NM1 is connected to the bias current I output by the second circuit (200). PB1 The gate of the first N-type transistor NM1 is connected to the drain of the first N-type transistor NM1, and the source of the first N-type transistor NM1 outputs a bias voltage V B1 The source of the first N-type transistor NM1 is connected to the drain of the third N-type transistor NM3, the drain of the third N-type transistor NM3 is connected to the gate of the third N-type transistor NM3, the gate of the third N-type transistor NM3 is connected to the gate of the fourth N-type transistor NM4, the source of the fourth N-type transistor NM4 and the source of the third N-type transistor NM3 are grounded; the drain of the fourth N-type transistor NM4 is connected to the source of the second N-type transistor NM2, the gate of the first N-type transistor NM1 is connected to the gate of the second N-type transistor NM2, the drain of the second N-type transistor NM2 is connected to the drain of the first P-type transistor PM1, the drain of the first P-type transistor PM1 is connected to the gate of the first P-type transistor PM1, and the gate of the first P-type transistor PM1 outputs the bias voltage V B2 ; The source of the first P-type transistor PM1 is connected to the power supply.

6. The three-feedback-loop fast-response low-dropout linear regulator according to claim 1, characterized in that: The fifth circuit (500) comprises a voltage buffer, the voltage buffer adopts a source follower structure, and the fifth circuit (500) comprises: a fifth N-type transistor NM5, a sixth N-type transistor NM6 and a second P-type transistor PM2; The gate of the fifth N-type transistor NM5 is connected to the bias voltage V output by the fourth circuit (400). B1 The source of the fifth N-type transistor NM5 is grounded, the drain of the fifth N-type transistor NM5 is connected to the source of the sixth N-type transistor NM6, and the gate of the sixth N-type transistor NM6 is connected to the voltage V output by the second circuit (200) ERR The drain of the sixth N-type transistor NM6 is connected to the drain of the second P-type transistor PM2, and the gate of the second P-type transistor PM2 is connected to the bias voltage V output by the fourth circuit (400) B2 , the source of the second P-type transistor PM2 is connected to the power supply; the drain of the second P-type transistor PM2 outputs a voltage V PG .

7. The three-feedback-loop fast-response low-dropout linear regulator according to claim 1, characterized in that: The sixth circuit (600) is the final output stage of the low voltage difference linear regulator, and the sixth circuit (600) comprises a third P-type transistor PM3, a resistor R1, and a resistor R2; The gate of the third P-type transistor PM3 is connected to the voltage V output by the fifth circuit (500). PG The source of the third P-type transistor PM3 is connected to the power supply, the drain of the third P-type transistor PM3 is connected to the source of the sixth N-type transistor NM6 in the fifth circuit (500), and the drain of the third P-type transistor PM3 outputs a voltage V OUT The drain of the third P-type transistor PM3 is connected to the positive electrode of the resistor R1, and the negative electrode of the resistor R1 outputs the feedback voltage V FB , the negative electrode of the resistor R1 is connected to the positive electrode of the resistor R2, and the negative electrode of the resistor R2 is grounded.

8. The three-feedback-loop fast-response low-dropout linear regulator according to claim 1, characterized in that: The first loop (L1) includes a sixth N-type transistor NM6 in the fifth circuit section (500) and a third P-type transistor PM3 in the sixth circuit section (600), and optimizes the output voltage V OUT The transient response speed.

9. The three-feedback-loop fast-response low-dropout linear regulator according to claim 1, characterized in that: The second loop (L2) comprises a sixth N-type transistor NM6 in the fifth circuit (500), resistors R1 and R2 in the sixth circuit (600), the second circuit (200), the third circuit (300), and the fourth circuit (400); and is used to provide a feedback voltage to adjust the output voltage V OUT stability, optimizing the bandwidth and stability of the regulator.

10. The three-feedback-loop fast-response low-dropout linear regulator according to claim 1, characterized in that: The third loop (L3) comprises a third P-type transistor PM3 in the sixth circuit (600), resistors R1 and R2, a sixth N-type transistor NM6 in the fifth circuit (500), the second circuit (200), the third circuit (300), and the fourth circuit (400), and the output voltage V is adjusted by the feedback voltage. OUT Guaranteed output voltage V OUT And the stability of the DC operating point of the entire circuit.

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